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author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-13 19:03:33 +0200 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-15 22:27:34 +0200 |
commit | 017667c2dc9843eb5082e991f421c773636dcf36 (patch) | |
tree | 60432008dd3bc012ac60cbfa771305f6d894dd84 /firmware/target/arm/imx233/regs/stmp3700/regs-dram.h | |
parent | 97b9ade63945fd8b8261fb0cf1dd0aa225c1a319 (diff) | |
download | rockbox-017667c2dc9843eb5082e991f421c773636dcf36.tar.gz rockbox-017667c2dc9843eb5082e991f421c773636dcf36.zip |
imx233: generate register headers for stmp3600, stmp3700 and imx233
Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3700/regs-dram.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3700/regs-dram.h | 671 |
1 files changed, 671 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-dram.h b/firmware/target/arm/imx233/regs/stmp3700/regs-dram.h new file mode 100644 index 0000000000..7ec44c41ee --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-dram.h | |||
@@ -0,0 +1,671 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__DRAM__H__ | ||
24 | #define __HEADERGEN__STMP3700__DRAM__H__ | ||
25 | |||
26 | #define REGS_DRAM_BASE (0x800e0000) | ||
27 | |||
28 | #define REGS_DRAM_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DRAM_CTL00 | ||
32 | * Address: 0 | ||
33 | * SCT: no | ||
34 | */ | ||
35 | #define HW_DRAM_CTL00 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x0)) | ||
36 | #define BP_DRAM_CTL00_AHB0_W_PRIORITY 24 | ||
37 | #define BM_DRAM_CTL00_AHB0_W_PRIORITY 0x1000000 | ||
38 | #define BF_DRAM_CTL00_AHB0_W_PRIORITY(v) (((v) << 24) & 0x1000000) | ||
39 | #define BP_DRAM_CTL00_AHB0_R_PRIORITY 16 | ||
40 | #define BM_DRAM_CTL00_AHB0_R_PRIORITY 0x10000 | ||
41 | #define BF_DRAM_CTL00_AHB0_R_PRIORITY(v) (((v) << 16) & 0x10000) | ||
42 | #define BP_DRAM_CTL00_AHB0_FIFO_TYPE_REG 8 | ||
43 | #define BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG 0x100 | ||
44 | #define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v) (((v) << 8) & 0x100) | ||
45 | #define BP_DRAM_CTL00_ADDR_CMP_EN 0 | ||
46 | #define BM_DRAM_CTL00_ADDR_CMP_EN 0x1 | ||
47 | #define BF_DRAM_CTL00_ADDR_CMP_EN(v) (((v) << 0) & 0x1) | ||
48 | |||
49 | /** | ||
50 | * Register: HW_DRAM_CTL01 | ||
51 | * Address: 0x4 | ||
52 | * SCT: no | ||
53 | */ | ||
54 | #define HW_DRAM_CTL01 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4)) | ||
55 | #define BP_DRAM_CTL01_AHB2_FIFO_TYPE_REG 24 | ||
56 | #define BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG 0x1000000 | ||
57 | #define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v) (((v) << 24) & 0x1000000) | ||
58 | #define BP_DRAM_CTL01_AHB1_W_PRIORITY 16 | ||
59 | #define BM_DRAM_CTL01_AHB1_W_PRIORITY 0x10000 | ||
60 | #define BF_DRAM_CTL01_AHB1_W_PRIORITY(v) (((v) << 16) & 0x10000) | ||
61 | #define BP_DRAM_CTL01_AHB1_R_PRIORITY 8 | ||
62 | #define BM_DRAM_CTL01_AHB1_R_PRIORITY 0x100 | ||
63 | #define BF_DRAM_CTL01_AHB1_R_PRIORITY(v) (((v) << 8) & 0x100) | ||
64 | #define BP_DRAM_CTL01_AHB1_FIFO_TYPE_REG 0 | ||
65 | #define BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG 0x1 | ||
66 | #define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v) (((v) << 0) & 0x1) | ||
67 | |||
68 | /** | ||
69 | * Register: HW_DRAM_CTL02 | ||
70 | * Address: 0x8 | ||
71 | * SCT: no | ||
72 | */ | ||
73 | #define HW_DRAM_CTL02 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8)) | ||
74 | #define BP_DRAM_CTL02_AHB3_R_PRIORITY 24 | ||
75 | #define BM_DRAM_CTL02_AHB3_R_PRIORITY 0x1000000 | ||
76 | #define BF_DRAM_CTL02_AHB3_R_PRIORITY(v) (((v) << 24) & 0x1000000) | ||
77 | #define BP_DRAM_CTL02_AHB3_FIFO_TYPE_REG 16 | ||
78 | #define BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG 0x10000 | ||
79 | #define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v) (((v) << 16) & 0x10000) | ||
80 | #define BP_DRAM_CTL02_AHB2_W_PRIORITY 8 | ||
81 | #define BM_DRAM_CTL02_AHB2_W_PRIORITY 0x100 | ||
82 | #define BF_DRAM_CTL02_AHB2_W_PRIORITY(v) (((v) << 8) & 0x100) | ||
83 | #define BP_DRAM_CTL02_AHB2_R_PRIORITY 0 | ||
84 | #define BM_DRAM_CTL02_AHB2_R_PRIORITY 0x1 | ||
85 | #define BF_DRAM_CTL02_AHB2_R_PRIORITY(v) (((v) << 0) & 0x1) | ||
86 | |||
87 | /** | ||
88 | * Register: HW_DRAM_CTL03 | ||
89 | * Address: 0xc | ||
90 | * SCT: no | ||
91 | */ | ||
92 | #define HW_DRAM_CTL03 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xc)) | ||
93 | #define BP_DRAM_CTL03_AUTO_REFRESH_MODE 24 | ||
94 | #define BM_DRAM_CTL03_AUTO_REFRESH_MODE 0x1000000 | ||
95 | #define BF_DRAM_CTL03_AUTO_REFRESH_MODE(v) (((v) << 24) & 0x1000000) | ||
96 | #define BP_DRAM_CTL03_AREFRESH 16 | ||
97 | #define BM_DRAM_CTL03_AREFRESH 0x10000 | ||
98 | #define BF_DRAM_CTL03_AREFRESH(v) (((v) << 16) & 0x10000) | ||
99 | #define BP_DRAM_CTL03_AP 8 | ||
100 | #define BM_DRAM_CTL03_AP 0x100 | ||
101 | #define BF_DRAM_CTL03_AP(v) (((v) << 8) & 0x100) | ||
102 | #define BP_DRAM_CTL03_AHB3_W_PRIORITY 0 | ||
103 | #define BM_DRAM_CTL03_AHB3_W_PRIORITY 0x1 | ||
104 | #define BF_DRAM_CTL03_AHB3_W_PRIORITY(v) (((v) << 0) & 0x1) | ||
105 | |||
106 | /** | ||
107 | * Register: HW_DRAM_CTL04 | ||
108 | * Address: 0x10 | ||
109 | * SCT: no | ||
110 | */ | ||
111 | #define HW_DRAM_CTL04 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x10)) | ||
112 | #define BP_DRAM_CTL04_DLL_BYPASS_MODE 24 | ||
113 | #define BM_DRAM_CTL04_DLL_BYPASS_MODE 0x1000000 | ||
114 | #define BF_DRAM_CTL04_DLL_BYPASS_MODE(v) (((v) << 24) & 0x1000000) | ||
115 | #define BP_DRAM_CTL04_DLLLOCKREG 16 | ||
116 | #define BM_DRAM_CTL04_DLLLOCKREG 0x10000 | ||
117 | #define BF_DRAM_CTL04_DLLLOCKREG(v) (((v) << 16) & 0x10000) | ||
118 | #define BP_DRAM_CTL04_CONCURRENTAP 8 | ||
119 | #define BM_DRAM_CTL04_CONCURRENTAP 0x100 | ||
120 | #define BF_DRAM_CTL04_CONCURRENTAP(v) (((v) << 8) & 0x100) | ||
121 | #define BP_DRAM_CTL04_BANK_SPLIT_EN 0 | ||
122 | #define BM_DRAM_CTL04_BANK_SPLIT_EN 0x1 | ||
123 | #define BF_DRAM_CTL04_BANK_SPLIT_EN(v) (((v) << 0) & 0x1) | ||
124 | |||
125 | /** | ||
126 | * Register: HW_DRAM_CTL05 | ||
127 | * Address: 0x14 | ||
128 | * SCT: no | ||
129 | */ | ||
130 | #define HW_DRAM_CTL05 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x14)) | ||
131 | #define BP_DRAM_CTL05_INTRPTREADA 24 | ||
132 | #define BM_DRAM_CTL05_INTRPTREADA 0x1000000 | ||
133 | #define BF_DRAM_CTL05_INTRPTREADA(v) (((v) << 24) & 0x1000000) | ||
134 | #define BP_DRAM_CTL05_INTRPTAPBURST 16 | ||
135 | #define BM_DRAM_CTL05_INTRPTAPBURST 0x10000 | ||
136 | #define BF_DRAM_CTL05_INTRPTAPBURST(v) (((v) << 16) & 0x10000) | ||
137 | #define BP_DRAM_CTL05_FAST_WRITE 8 | ||
138 | #define BM_DRAM_CTL05_FAST_WRITE 0x100 | ||
139 | #define BF_DRAM_CTL05_FAST_WRITE(v) (((v) << 8) & 0x100) | ||
140 | #define BP_DRAM_CTL05_EN_LOWPOWER_MODE 0 | ||
141 | #define BM_DRAM_CTL05_EN_LOWPOWER_MODE 0x1 | ||
142 | #define BF_DRAM_CTL05_EN_LOWPOWER_MODE(v) (((v) << 0) & 0x1) | ||
143 | |||
144 | /** | ||
145 | * Register: HW_DRAM_CTL06 | ||
146 | * Address: 0x18 | ||
147 | * SCT: no | ||
148 | */ | ||
149 | #define HW_DRAM_CTL06 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x18)) | ||
150 | #define BP_DRAM_CTL06_POWER_DOWN 24 | ||
151 | #define BM_DRAM_CTL06_POWER_DOWN 0x1000000 | ||
152 | #define BF_DRAM_CTL06_POWER_DOWN(v) (((v) << 24) & 0x1000000) | ||
153 | #define BP_DRAM_CTL06_PLACEMENT_EN 16 | ||
154 | #define BM_DRAM_CTL06_PLACEMENT_EN 0x10000 | ||
155 | #define BF_DRAM_CTL06_PLACEMENT_EN(v) (((v) << 16) & 0x10000) | ||
156 | #define BP_DRAM_CTL06_NO_CMD_INIT 8 | ||
157 | #define BM_DRAM_CTL06_NO_CMD_INIT 0x100 | ||
158 | #define BF_DRAM_CTL06_NO_CMD_INIT(v) (((v) << 8) & 0x100) | ||
159 | #define BP_DRAM_CTL06_INTRPTWRITEA 0 | ||
160 | #define BM_DRAM_CTL06_INTRPTWRITEA 0x1 | ||
161 | #define BF_DRAM_CTL06_INTRPTWRITEA(v) (((v) << 0) & 0x1) | ||
162 | |||
163 | /** | ||
164 | * Register: HW_DRAM_CTL07 | ||
165 | * Address: 0x1c | ||
166 | * SCT: no | ||
167 | */ | ||
168 | #define HW_DRAM_CTL07 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x1c)) | ||
169 | #define BP_DRAM_CTL07_RW_SAME_EN 24 | ||
170 | #define BM_DRAM_CTL07_RW_SAME_EN 0x1000000 | ||
171 | #define BF_DRAM_CTL07_RW_SAME_EN(v) (((v) << 24) & 0x1000000) | ||
172 | #define BP_DRAM_CTL07_REG_DIMM_ENABLE 16 | ||
173 | #define BM_DRAM_CTL07_REG_DIMM_ENABLE 0x10000 | ||
174 | #define BF_DRAM_CTL07_REG_DIMM_ENABLE(v) (((v) << 16) & 0x10000) | ||
175 | #define BP_DRAM_CTL07_RD2RD_TURN 8 | ||
176 | #define BM_DRAM_CTL07_RD2RD_TURN 0x100 | ||
177 | #define BF_DRAM_CTL07_RD2RD_TURN(v) (((v) << 8) & 0x100) | ||
178 | #define BP_DRAM_CTL07_PRIORITY_EN 0 | ||
179 | #define BM_DRAM_CTL07_PRIORITY_EN 0x1 | ||
180 | #define BF_DRAM_CTL07_PRIORITY_EN(v) (((v) << 0) & 0x1) | ||
181 | |||
182 | /** | ||
183 | * Register: HW_DRAM_CTL08 | ||
184 | * Address: 0x20 | ||
185 | * SCT: no | ||
186 | */ | ||
187 | #define HW_DRAM_CTL08 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x20)) | ||
188 | #define BP_DRAM_CTL08_TRAS_LOCKOUT 24 | ||
189 | #define BM_DRAM_CTL08_TRAS_LOCKOUT 0x1000000 | ||
190 | #define BF_DRAM_CTL08_TRAS_LOCKOUT(v) (((v) << 24) & 0x1000000) | ||
191 | #define BP_DRAM_CTL08_START 16 | ||
192 | #define BM_DRAM_CTL08_START 0x10000 | ||
193 | #define BF_DRAM_CTL08_START(v) (((v) << 16) & 0x10000) | ||
194 | #define BP_DRAM_CTL08_SREFRESH 8 | ||
195 | #define BM_DRAM_CTL08_SREFRESH 0x100 | ||
196 | #define BF_DRAM_CTL08_SREFRESH(v) (((v) << 8) & 0x100) | ||
197 | #define BP_DRAM_CTL08_SDR_MODE 0 | ||
198 | #define BM_DRAM_CTL08_SDR_MODE 0x1 | ||
199 | #define BF_DRAM_CTL08_SDR_MODE(v) (((v) << 0) & 0x1) | ||
200 | |||
201 | /** | ||
202 | * Register: HW_DRAM_CTL09 | ||
203 | * Address: 0x24 | ||
204 | * SCT: no | ||
205 | */ | ||
206 | #define HW_DRAM_CTL09 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x24)) | ||
207 | #define BP_DRAM_CTL09_OUT_OF_RANGE_TYPE 24 | ||
208 | #define BM_DRAM_CTL09_OUT_OF_RANGE_TYPE 0x3000000 | ||
209 | #define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(v) (((v) << 24) & 0x3000000) | ||
210 | #define BP_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 16 | ||
211 | #define BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 0x30000 | ||
212 | #define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v) (((v) << 16) & 0x30000) | ||
213 | #define BP_DRAM_CTL09_WRITE_MODEREG 8 | ||
214 | #define BM_DRAM_CTL09_WRITE_MODEREG 0x100 | ||
215 | #define BF_DRAM_CTL09_WRITE_MODEREG(v) (((v) << 8) & 0x100) | ||
216 | #define BP_DRAM_CTL09_WRITEINTERP 0 | ||
217 | #define BM_DRAM_CTL09_WRITEINTERP 0x1 | ||
218 | #define BF_DRAM_CTL09_WRITEINTERP(v) (((v) << 0) & 0x1) | ||
219 | |||
220 | /** | ||
221 | * Register: HW_DRAM_CTL10 | ||
222 | * Address: 0x28 | ||
223 | * SCT: no | ||
224 | */ | ||
225 | #define HW_DRAM_CTL10 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x28)) | ||
226 | #define BP_DRAM_CTL10_AGE_COUNT 24 | ||
227 | #define BM_DRAM_CTL10_AGE_COUNT 0x7000000 | ||
228 | #define BF_DRAM_CTL10_AGE_COUNT(v) (((v) << 24) & 0x7000000) | ||
229 | #define BP_DRAM_CTL10_ADDR_PINS 16 | ||
230 | #define BM_DRAM_CTL10_ADDR_PINS 0x70000 | ||
231 | #define BF_DRAM_CTL10_ADDR_PINS(v) (((v) << 16) & 0x70000) | ||
232 | #define BP_DRAM_CTL10_TEMRS 8 | ||
233 | #define BM_DRAM_CTL10_TEMRS 0x300 | ||
234 | #define BF_DRAM_CTL10_TEMRS(v) (((v) << 8) & 0x300) | ||
235 | #define BP_DRAM_CTL10_Q_FULLNESS 0 | ||
236 | #define BM_DRAM_CTL10_Q_FULLNESS 0x3 | ||
237 | #define BF_DRAM_CTL10_Q_FULLNESS(v) (((v) << 0) & 0x3) | ||
238 | |||
239 | /** | ||
240 | * Register: HW_DRAM_CTL11 | ||
241 | * Address: 0x2c | ||
242 | * SCT: no | ||
243 | */ | ||
244 | #define HW_DRAM_CTL11 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x2c)) | ||
245 | #define BP_DRAM_CTL11_MAX_CS_REG 24 | ||
246 | #define BM_DRAM_CTL11_MAX_CS_REG 0x7000000 | ||
247 | #define BF_DRAM_CTL11_MAX_CS_REG(v) (((v) << 24) & 0x7000000) | ||
248 | #define BP_DRAM_CTL11_COMMAND_AGE_COUNT 16 | ||
249 | #define BM_DRAM_CTL11_COMMAND_AGE_COUNT 0x70000 | ||
250 | #define BF_DRAM_CTL11_COMMAND_AGE_COUNT(v) (((v) << 16) & 0x70000) | ||
251 | #define BP_DRAM_CTL11_COLUMN_SIZE 8 | ||
252 | #define BM_DRAM_CTL11_COLUMN_SIZE 0x700 | ||
253 | #define BF_DRAM_CTL11_COLUMN_SIZE(v) (((v) << 8) & 0x700) | ||
254 | #define BP_DRAM_CTL11_CASLAT 0 | ||
255 | #define BM_DRAM_CTL11_CASLAT 0x7 | ||
256 | #define BF_DRAM_CTL11_CASLAT(v) (((v) << 0) & 0x7) | ||
257 | |||
258 | /** | ||
259 | * Register: HW_DRAM_CTL12 | ||
260 | * Address: 0x30 | ||
261 | * SCT: no | ||
262 | */ | ||
263 | #define HW_DRAM_CTL12 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x30)) | ||
264 | #define BP_DRAM_CTL12_TWR_INT 24 | ||
265 | #define BM_DRAM_CTL12_TWR_INT 0x7000000 | ||
266 | #define BF_DRAM_CTL12_TWR_INT(v) (((v) << 24) & 0x7000000) | ||
267 | #define BP_DRAM_CTL12_TRRD 16 | ||
268 | #define BM_DRAM_CTL12_TRRD 0x70000 | ||
269 | #define BF_DRAM_CTL12_TRRD(v) (((v) << 16) & 0x70000) | ||
270 | #define BP_DRAM_CTL12_TCKE 0 | ||
271 | #define BM_DRAM_CTL12_TCKE 0x7 | ||
272 | #define BF_DRAM_CTL12_TCKE(v) (((v) << 0) & 0x7) | ||
273 | |||
274 | /** | ||
275 | * Register: HW_DRAM_CTL13 | ||
276 | * Address: 0x34 | ||
277 | * SCT: no | ||
278 | */ | ||
279 | #define HW_DRAM_CTL13 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x34)) | ||
280 | #define BP_DRAM_CTL13_CASLAT_LIN_GATE 24 | ||
281 | #define BM_DRAM_CTL13_CASLAT_LIN_GATE 0xf000000 | ||
282 | #define BF_DRAM_CTL13_CASLAT_LIN_GATE(v) (((v) << 24) & 0xf000000) | ||
283 | #define BP_DRAM_CTL13_CASLAT_LIN 16 | ||
284 | #define BM_DRAM_CTL13_CASLAT_LIN 0xf0000 | ||
285 | #define BF_DRAM_CTL13_CASLAT_LIN(v) (((v) << 16) & 0xf0000) | ||
286 | #define BP_DRAM_CTL13_APREBIT 8 | ||
287 | #define BM_DRAM_CTL13_APREBIT 0xf00 | ||
288 | #define BF_DRAM_CTL13_APREBIT(v) (((v) << 8) & 0xf00) | ||
289 | #define BP_DRAM_CTL13_TWTR 0 | ||
290 | #define BM_DRAM_CTL13_TWTR 0x7 | ||
291 | #define BF_DRAM_CTL13_TWTR(v) (((v) << 0) & 0x7) | ||
292 | |||
293 | /** | ||
294 | * Register: HW_DRAM_CTL14 | ||
295 | * Address: 0x38 | ||
296 | * SCT: no | ||
297 | */ | ||
298 | #define HW_DRAM_CTL14 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x38)) | ||
299 | #define BP_DRAM_CTL14_MAX_COL_REG 24 | ||
300 | #define BM_DRAM_CTL14_MAX_COL_REG 0xf000000 | ||
301 | #define BF_DRAM_CTL14_MAX_COL_REG(v) (((v) << 24) & 0xf000000) | ||
302 | #define BP_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 16 | ||
303 | #define BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 0xf0000 | ||
304 | #define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v) (((v) << 16) & 0xf0000) | ||
305 | #define BP_DRAM_CTL14_INITAREF 8 | ||
306 | #define BM_DRAM_CTL14_INITAREF 0xf00 | ||
307 | #define BF_DRAM_CTL14_INITAREF(v) (((v) << 8) & 0xf00) | ||
308 | #define BP_DRAM_CTL14_CS_MAP 0 | ||
309 | #define BM_DRAM_CTL14_CS_MAP 0xf | ||
310 | #define BF_DRAM_CTL14_CS_MAP(v) (((v) << 0) & 0xf) | ||
311 | |||
312 | /** | ||
313 | * Register: HW_DRAM_CTL15 | ||
314 | * Address: 0x3c | ||
315 | * SCT: no | ||
316 | */ | ||
317 | #define HW_DRAM_CTL15 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x3c)) | ||
318 | #define BP_DRAM_CTL15_TRP 24 | ||
319 | #define BM_DRAM_CTL15_TRP 0xf000000 | ||
320 | #define BF_DRAM_CTL15_TRP(v) (((v) << 24) & 0xf000000) | ||
321 | #define BP_DRAM_CTL15_TDAL 16 | ||
322 | #define BM_DRAM_CTL15_TDAL 0xf0000 | ||
323 | #define BF_DRAM_CTL15_TDAL(v) (((v) << 16) & 0xf0000) | ||
324 | #define BP_DRAM_CTL15_PORT_BUSY 8 | ||
325 | #define BM_DRAM_CTL15_PORT_BUSY 0xf00 | ||
326 | #define BF_DRAM_CTL15_PORT_BUSY(v) (((v) << 8) & 0xf00) | ||
327 | #define BP_DRAM_CTL15_MAX_ROW_REG 0 | ||
328 | #define BM_DRAM_CTL15_MAX_ROW_REG 0xf | ||
329 | #define BF_DRAM_CTL15_MAX_ROW_REG(v) (((v) << 0) & 0xf) | ||
330 | |||
331 | /** | ||
332 | * Register: HW_DRAM_CTL16 | ||
333 | * Address: 0x40 | ||
334 | * SCT: no | ||
335 | */ | ||
336 | #define HW_DRAM_CTL16 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x40)) | ||
337 | #define BP_DRAM_CTL16_TMRD 24 | ||
338 | #define BM_DRAM_CTL16_TMRD 0x1f000000 | ||
339 | #define BF_DRAM_CTL16_TMRD(v) (((v) << 24) & 0x1f000000) | ||
340 | #define BP_DRAM_CTL16_LOWPOWER_CONTROL 16 | ||
341 | #define BM_DRAM_CTL16_LOWPOWER_CONTROL 0x1f0000 | ||
342 | #define BF_DRAM_CTL16_LOWPOWER_CONTROL(v) (((v) << 16) & 0x1f0000) | ||
343 | #define BP_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 8 | ||
344 | #define BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 0x1f00 | ||
345 | #define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v) (((v) << 8) & 0x1f00) | ||
346 | #define BP_DRAM_CTL16_INT_ACK 0 | ||
347 | #define BM_DRAM_CTL16_INT_ACK 0xf | ||
348 | #define BF_DRAM_CTL16_INT_ACK(v) (((v) << 0) & 0xf) | ||
349 | |||
350 | /** | ||
351 | * Register: HW_DRAM_CTL17 | ||
352 | * Address: 0x44 | ||
353 | * SCT: no | ||
354 | */ | ||
355 | #define HW_DRAM_CTL17 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x44)) | ||
356 | #define BP_DRAM_CTL17_DLL_START_POINT 24 | ||
357 | #define BM_DRAM_CTL17_DLL_START_POINT 0xff000000 | ||
358 | #define BF_DRAM_CTL17_DLL_START_POINT(v) (((v) << 24) & 0xff000000) | ||
359 | #define BP_DRAM_CTL17_DLL_LOCK 16 | ||
360 | #define BM_DRAM_CTL17_DLL_LOCK 0xff0000 | ||
361 | #define BF_DRAM_CTL17_DLL_LOCK(v) (((v) << 16) & 0xff0000) | ||
362 | #define BP_DRAM_CTL17_DLL_INCREMENT 8 | ||
363 | #define BM_DRAM_CTL17_DLL_INCREMENT 0xff00 | ||
364 | #define BF_DRAM_CTL17_DLL_INCREMENT(v) (((v) << 8) & 0xff00) | ||
365 | #define BP_DRAM_CTL17_TRC 0 | ||
366 | #define BM_DRAM_CTL17_TRC 0x1f | ||
367 | #define BF_DRAM_CTL17_TRC(v) (((v) << 0) & 0x1f) | ||
368 | |||
369 | /** | ||
370 | * Register: HW_DRAM_CTL18 | ||
371 | * Address: 0x48 | ||
372 | * SCT: no | ||
373 | */ | ||
374 | #define HW_DRAM_CTL18 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x48)) | ||
375 | #define BP_DRAM_CTL18_DLL_DQS_DELAY_1 24 | ||
376 | #define BM_DRAM_CTL18_DLL_DQS_DELAY_1 0x7f000000 | ||
377 | #define BF_DRAM_CTL18_DLL_DQS_DELAY_1(v) (((v) << 24) & 0x7f000000) | ||
378 | #define BP_DRAM_CTL18_DLL_DQS_DELAY_0 16 | ||
379 | #define BM_DRAM_CTL18_DLL_DQS_DELAY_0 0x7f0000 | ||
380 | #define BF_DRAM_CTL18_DLL_DQS_DELAY_0(v) (((v) << 16) & 0x7f0000) | ||
381 | #define BP_DRAM_CTL18_INT_STATUS 8 | ||
382 | #define BM_DRAM_CTL18_INT_STATUS 0x1f00 | ||
383 | #define BF_DRAM_CTL18_INT_STATUS(v) (((v) << 8) & 0x1f00) | ||
384 | #define BP_DRAM_CTL18_INT_MASK 0 | ||
385 | #define BM_DRAM_CTL18_INT_MASK 0x1f | ||
386 | #define BF_DRAM_CTL18_INT_MASK(v) (((v) << 0) & 0x1f) | ||
387 | |||
388 | /** | ||
389 | * Register: HW_DRAM_CTL19 | ||
390 | * Address: 0x4c | ||
391 | * SCT: no | ||
392 | */ | ||
393 | #define HW_DRAM_CTL19 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4c)) | ||
394 | #define BP_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 24 | ||
395 | #define BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 0xff000000 | ||
396 | #define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v) (((v) << 24) & 0xff000000) | ||
397 | #define BP_DRAM_CTL19_DQS_OUT_SHIFT 16 | ||
398 | #define BM_DRAM_CTL19_DQS_OUT_SHIFT 0x7f0000 | ||
399 | #define BF_DRAM_CTL19_DQS_OUT_SHIFT(v) (((v) << 16) & 0x7f0000) | ||
400 | #define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 8 | ||
401 | #define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 0xff00 | ||
402 | #define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v) (((v) << 8) & 0xff00) | ||
403 | #define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0 | ||
404 | #define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0xff | ||
405 | #define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v) (((v) << 0) & 0xff) | ||
406 | |||
407 | /** | ||
408 | * Register: HW_DRAM_CTL20 | ||
409 | * Address: 0x50 | ||
410 | * SCT: no | ||
411 | */ | ||
412 | #define HW_DRAM_CTL20 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x50)) | ||
413 | #define BP_DRAM_CTL20_TRCD_INT 24 | ||
414 | #define BM_DRAM_CTL20_TRCD_INT 0xff000000 | ||
415 | #define BF_DRAM_CTL20_TRCD_INT(v) (((v) << 24) & 0xff000000) | ||
416 | #define BP_DRAM_CTL20_TRAS_MIN 16 | ||
417 | #define BM_DRAM_CTL20_TRAS_MIN 0xff0000 | ||
418 | #define BF_DRAM_CTL20_TRAS_MIN(v) (((v) << 16) & 0xff0000) | ||
419 | #define BP_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 8 | ||
420 | #define BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 0xff00 | ||
421 | #define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v) (((v) << 8) & 0xff00) | ||
422 | #define BP_DRAM_CTL20_WR_DQS_SHIFT 0 | ||
423 | #define BM_DRAM_CTL20_WR_DQS_SHIFT 0x7f | ||
424 | #define BF_DRAM_CTL20_WR_DQS_SHIFT(v) (((v) << 0) & 0x7f) | ||
425 | |||
426 | /** | ||
427 | * Register: HW_DRAM_CTL21 | ||
428 | * Address: 0x54 | ||
429 | * SCT: no | ||
430 | */ | ||
431 | #define HW_DRAM_CTL21 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x54)) | ||
432 | #define BP_DRAM_CTL21_OUT_OF_RANGE_LENGTH 8 | ||
433 | #define BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH 0x3ff00 | ||
434 | #define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v) (((v) << 8) & 0x3ff00) | ||
435 | #define BP_DRAM_CTL21_TRFC 0 | ||
436 | #define BM_DRAM_CTL21_TRFC 0xff | ||
437 | #define BF_DRAM_CTL21_TRFC(v) (((v) << 0) & 0xff) | ||
438 | |||
439 | /** | ||
440 | * Register: HW_DRAM_CTL22 | ||
441 | * Address: 0x58 | ||
442 | * SCT: no | ||
443 | */ | ||
444 | #define HW_DRAM_CTL22 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x58)) | ||
445 | #define BP_DRAM_CTL22_AHB0_WRCNT 16 | ||
446 | #define BM_DRAM_CTL22_AHB0_WRCNT 0x7ff0000 | ||
447 | #define BF_DRAM_CTL22_AHB0_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
448 | #define BP_DRAM_CTL22_AHB0_RDCNT 0 | ||
449 | #define BM_DRAM_CTL22_AHB0_RDCNT 0x7ff | ||
450 | #define BF_DRAM_CTL22_AHB0_RDCNT(v) (((v) << 0) & 0x7ff) | ||
451 | |||
452 | /** | ||
453 | * Register: HW_DRAM_CTL23 | ||
454 | * Address: 0x5c | ||
455 | * SCT: no | ||
456 | */ | ||
457 | #define HW_DRAM_CTL23 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x5c)) | ||
458 | #define BP_DRAM_CTL23_AHB1_WRCNT 16 | ||
459 | #define BM_DRAM_CTL23_AHB1_WRCNT 0x7ff0000 | ||
460 | #define BF_DRAM_CTL23_AHB1_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
461 | #define BP_DRAM_CTL23_AHB1_RDCNT 0 | ||
462 | #define BM_DRAM_CTL23_AHB1_RDCNT 0x7ff | ||
463 | #define BF_DRAM_CTL23_AHB1_RDCNT(v) (((v) << 0) & 0x7ff) | ||
464 | |||
465 | /** | ||
466 | * Register: HW_DRAM_CTL24 | ||
467 | * Address: 0x60 | ||
468 | * SCT: no | ||
469 | */ | ||
470 | #define HW_DRAM_CTL24 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x60)) | ||
471 | #define BP_DRAM_CTL24_AHB2_WRCNT 16 | ||
472 | #define BM_DRAM_CTL24_AHB2_WRCNT 0x7ff0000 | ||
473 | #define BF_DRAM_CTL24_AHB2_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
474 | #define BP_DRAM_CTL24_AHB2_RDCNT 0 | ||
475 | #define BM_DRAM_CTL24_AHB2_RDCNT 0x7ff | ||
476 | #define BF_DRAM_CTL24_AHB2_RDCNT(v) (((v) << 0) & 0x7ff) | ||
477 | |||
478 | /** | ||
479 | * Register: HW_DRAM_CTL25 | ||
480 | * Address: 0x64 | ||
481 | * SCT: no | ||
482 | */ | ||
483 | #define HW_DRAM_CTL25 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x64)) | ||
484 | #define BP_DRAM_CTL25_AHB3_WRCNT 16 | ||
485 | #define BM_DRAM_CTL25_AHB3_WRCNT 0x7ff0000 | ||
486 | #define BF_DRAM_CTL25_AHB3_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
487 | #define BP_DRAM_CTL25_AHB3_RDCNT 0 | ||
488 | #define BM_DRAM_CTL25_AHB3_RDCNT 0x7ff | ||
489 | #define BF_DRAM_CTL25_AHB3_RDCNT(v) (((v) << 0) & 0x7ff) | ||
490 | |||
491 | /** | ||
492 | * Register: HW_DRAM_CTL26 | ||
493 | * Address: 0x68 | ||
494 | * SCT: no | ||
495 | */ | ||
496 | #define HW_DRAM_CTL26 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x68)) | ||
497 | #define BP_DRAM_CTL26_TREF 0 | ||
498 | #define BM_DRAM_CTL26_TREF 0xfff | ||
499 | #define BF_DRAM_CTL26_TREF(v) (((v) << 0) & 0xfff) | ||
500 | |||
501 | /** | ||
502 | * Register: HW_DRAM_CTL27 | ||
503 | * Address: 0x6c | ||
504 | * SCT: no | ||
505 | */ | ||
506 | #define HW_DRAM_CTL27 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x6c)) | ||
507 | |||
508 | /** | ||
509 | * Register: HW_DRAM_CTL28 | ||
510 | * Address: 0x70 | ||
511 | * SCT: no | ||
512 | */ | ||
513 | #define HW_DRAM_CTL28 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x70)) | ||
514 | |||
515 | /** | ||
516 | * Register: HW_DRAM_CTL29 | ||
517 | * Address: 0x74 | ||
518 | * SCT: no | ||
519 | */ | ||
520 | #define HW_DRAM_CTL29 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x74)) | ||
521 | #define BP_DRAM_CTL29_LOWPOWER_INTERNAL_CNT 16 | ||
522 | #define BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT 0xffff0000 | ||
523 | #define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v) (((v) << 16) & 0xffff0000) | ||
524 | #define BP_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT 0 | ||
525 | #define BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT 0xffff | ||
526 | #define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v) (((v) << 0) & 0xffff) | ||
527 | |||
528 | /** | ||
529 | * Register: HW_DRAM_CTL30 | ||
530 | * Address: 0x78 | ||
531 | * SCT: no | ||
532 | */ | ||
533 | #define HW_DRAM_CTL30 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x78)) | ||
534 | #define BP_DRAM_CTL30_LOWPOWER_REFRESH_HOLD 16 | ||
535 | #define BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD 0xffff0000 | ||
536 | #define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v) (((v) << 16) & 0xffff0000) | ||
537 | #define BP_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT 0 | ||
538 | #define BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT 0xffff | ||
539 | #define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v) (((v) << 0) & 0xffff) | ||
540 | |||
541 | /** | ||
542 | * Register: HW_DRAM_CTL31 | ||
543 | * Address: 0x7c | ||
544 | * SCT: no | ||
545 | */ | ||
546 | #define HW_DRAM_CTL31 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x7c)) | ||
547 | #define BP_DRAM_CTL31_TDLL 16 | ||
548 | #define BM_DRAM_CTL31_TDLL 0xffff0000 | ||
549 | #define BF_DRAM_CTL31_TDLL(v) (((v) << 16) & 0xffff0000) | ||
550 | #define BP_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT 0 | ||
551 | #define BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT 0xffff | ||
552 | #define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v) (((v) << 0) & 0xffff) | ||
553 | |||
554 | /** | ||
555 | * Register: HW_DRAM_CTL32 | ||
556 | * Address: 0x80 | ||
557 | * SCT: no | ||
558 | */ | ||
559 | #define HW_DRAM_CTL32 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x80)) | ||
560 | #define BP_DRAM_CTL32_TXSNR 16 | ||
561 | #define BM_DRAM_CTL32_TXSNR 0xffff0000 | ||
562 | #define BF_DRAM_CTL32_TXSNR(v) (((v) << 16) & 0xffff0000) | ||
563 | #define BP_DRAM_CTL32_TRAS_MAX 0 | ||
564 | #define BM_DRAM_CTL32_TRAS_MAX 0xffff | ||
565 | #define BF_DRAM_CTL32_TRAS_MAX(v) (((v) << 0) & 0xffff) | ||
566 | |||
567 | /** | ||
568 | * Register: HW_DRAM_CTL33 | ||
569 | * Address: 0x84 | ||
570 | * SCT: no | ||
571 | */ | ||
572 | #define HW_DRAM_CTL33 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x84)) | ||
573 | #define BP_DRAM_CTL33_VERSION 16 | ||
574 | #define BM_DRAM_CTL33_VERSION 0xffff0000 | ||
575 | #define BF_DRAM_CTL33_VERSION(v) (((v) << 16) & 0xffff0000) | ||
576 | #define BP_DRAM_CTL33_TXSR 0 | ||
577 | #define BM_DRAM_CTL33_TXSR 0xffff | ||
578 | #define BF_DRAM_CTL33_TXSR(v) (((v) << 0) & 0xffff) | ||
579 | |||
580 | /** | ||
581 | * Register: HW_DRAM_CTL34 | ||
582 | * Address: 0x88 | ||
583 | * SCT: no | ||
584 | */ | ||
585 | #define HW_DRAM_CTL34 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x88)) | ||
586 | #define BP_DRAM_CTL34_TINIT 0 | ||
587 | #define BM_DRAM_CTL34_TINIT 0xffffff | ||
588 | #define BF_DRAM_CTL34_TINIT(v) (((v) << 0) & 0xffffff) | ||
589 | |||
590 | /** | ||
591 | * Register: HW_DRAM_CTL35 | ||
592 | * Address: 0x8c | ||
593 | * SCT: no | ||
594 | */ | ||
595 | #define HW_DRAM_CTL35 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8c)) | ||
596 | #define BP_DRAM_CTL35_OUT_OF_RANGE_ADDR 0 | ||
597 | #define BM_DRAM_CTL35_OUT_OF_RANGE_ADDR 0x7fffffff | ||
598 | #define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(v) (((v) << 0) & 0x7fffffff) | ||
599 | |||
600 | /** | ||
601 | * Register: HW_DRAM_CTL36 | ||
602 | * Address: 0x90 | ||
603 | * SCT: no | ||
604 | */ | ||
605 | #define HW_DRAM_CTL36 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x90)) | ||
606 | #define BP_DRAM_CTL36_PWRUP_SREFRESH_EXIT 24 | ||
607 | #define BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT 0x1000000 | ||
608 | #define BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT(v) (((v) << 24) & 0x1000000) | ||
609 | #define BP_DRAM_CTL36_ENABLE_QUICK_SREFRESH 16 | ||
610 | #define BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH 0x10000 | ||
611 | #define BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH(v) (((v) << 16) & 0x10000) | ||
612 | #define BP_DRAM_CTL36_BUS_SHARE_ENABLE 8 | ||
613 | #define BM_DRAM_CTL36_BUS_SHARE_ENABLE 0x100 | ||
614 | #define BF_DRAM_CTL36_BUS_SHARE_ENABLE(v) (((v) << 8) & 0x100) | ||
615 | #define BP_DRAM_CTL36_ACTIVE_AGING 0 | ||
616 | #define BM_DRAM_CTL36_ACTIVE_AGING 0x1 | ||
617 | #define BF_DRAM_CTL36_ACTIVE_AGING(v) (((v) << 0) & 0x1) | ||
618 | |||
619 | /** | ||
620 | * Register: HW_DRAM_CTL37 | ||
621 | * Address: 0x94 | ||
622 | * SCT: no | ||
623 | */ | ||
624 | #define HW_DRAM_CTL37 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x94)) | ||
625 | #define BP_DRAM_CTL37_BUS_SHARE_TIMEOUT 8 | ||
626 | #define BM_DRAM_CTL37_BUS_SHARE_TIMEOUT 0x3ff00 | ||
627 | #define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(v) (((v) << 8) & 0x3ff00) | ||
628 | #define BP_DRAM_CTL37_TREF_ENABLE 0 | ||
629 | #define BM_DRAM_CTL37_TREF_ENABLE 0x1 | ||
630 | #define BF_DRAM_CTL37_TREF_ENABLE(v) (((v) << 0) & 0x1) | ||
631 | |||
632 | /** | ||
633 | * Register: HW_DRAM_CTL38 | ||
634 | * Address: 0x98 | ||
635 | * SCT: no | ||
636 | */ | ||
637 | #define HW_DRAM_CTL38 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x98)) | ||
638 | #define BP_DRAM_CTL38_EMRS2_DATA_0 16 | ||
639 | #define BM_DRAM_CTL38_EMRS2_DATA_0 0x1fff0000 | ||
640 | #define BF_DRAM_CTL38_EMRS2_DATA_0(v) (((v) << 16) & 0x1fff0000) | ||
641 | #define BP_DRAM_CTL38_EMRS1_DATA 0 | ||
642 | #define BM_DRAM_CTL38_EMRS1_DATA 0x1fff | ||
643 | #define BF_DRAM_CTL38_EMRS1_DATA(v) (((v) << 0) & 0x1fff) | ||
644 | |||
645 | /** | ||
646 | * Register: HW_DRAM_CTL39 | ||
647 | * Address: 0x9c | ||
648 | * SCT: no | ||
649 | */ | ||
650 | #define HW_DRAM_CTL39 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x9c)) | ||
651 | #define BP_DRAM_CTL39_EMRS2_DATA_2 16 | ||
652 | #define BM_DRAM_CTL39_EMRS2_DATA_2 0x1fff0000 | ||
653 | #define BF_DRAM_CTL39_EMRS2_DATA_2(v) (((v) << 16) & 0x1fff0000) | ||
654 | #define BP_DRAM_CTL39_EMRS2_DATA_1 0 | ||
655 | #define BM_DRAM_CTL39_EMRS2_DATA_1 0x1fff | ||
656 | #define BF_DRAM_CTL39_EMRS2_DATA_1(v) (((v) << 0) & 0x1fff) | ||
657 | |||
658 | /** | ||
659 | * Register: HW_DRAM_CTL40 | ||
660 | * Address: 0xa0 | ||
661 | * SCT: no | ||
662 | */ | ||
663 | #define HW_DRAM_CTL40 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xa0)) | ||
664 | #define BP_DRAM_CTL40_TPDEX 16 | ||
665 | #define BM_DRAM_CTL40_TPDEX 0xffff0000 | ||
666 | #define BF_DRAM_CTL40_TPDEX(v) (((v) << 16) & 0xffff0000) | ||
667 | #define BP_DRAM_CTL40_EMRS2_DATA_3 0 | ||
668 | #define BM_DRAM_CTL40_EMRS2_DATA_3 0x1fff | ||
669 | #define BF_DRAM_CTL40_EMRS2_DATA_3(v) (((v) << 0) & 0x1fff) | ||
670 | |||
671 | #endif /* __HEADERGEN__STMP3700__DRAM__H__ */ | ||