imx233: generate register headers for stmp3600, stmp3700 and imx233

Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934

1 files changed, 759 insertions, 0 deletions

diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h
new file mode 100644
index 0000000000..69d4e7128f
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h
@@ -0,0 +1,759 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__DIGCTL__H__
+#define __HEADERGEN__STMP3700__DIGCTL__H__
+
+#define REGS_DIGCTL_BASE (0x8001c000)
+
+#define REGS_DIGCTL_VERSION "3.2.0"
+
+/**
+ * Register: HW_DIGCTL_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_DIGCTL_CTRL                                      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x0))
+#define HW_DIGCTL_CTRL_SET                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x4))
+#define HW_DIGCTL_CTRL_CLR                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x8))
+#define HW_DIGCTL_CTRL_TOG                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0xc))
+#define BP_DIGCTL_CTRL_TRAP_IRQ                             29
+#define BM_DIGCTL_CTRL_TRAP_IRQ                             0x20000000
+#define BF_DIGCTL_CTRL_TRAP_IRQ(v)                          (((v) << 29) & 0x20000000)
+#define BP_DIGCTL_CTRL_DCP_BIST_CLKEN                       23
+#define BM_DIGCTL_CTRL_DCP_BIST_CLKEN                       0x800000
+#define BF_DIGCTL_CTRL_DCP_BIST_CLKEN(v)                    (((v) << 23) & 0x800000)
+#define BP_DIGCTL_CTRL_DCP_BIST_START                       22
+#define BM_DIGCTL_CTRL_DCP_BIST_START                       0x400000
+#define BF_DIGCTL_CTRL_DCP_BIST_START(v)                    (((v) << 22) & 0x400000)
+#define BP_DIGCTL_CTRL_ARM_BIST_CLKEN                       21
+#define BM_DIGCTL_CTRL_ARM_BIST_CLKEN                       0x200000
+#define BF_DIGCTL_CTRL_ARM_BIST_CLKEN(v)                    (((v) << 21) & 0x200000)
+#define BP_DIGCTL_CTRL_USB_TESTMODE                         20
+#define BM_DIGCTL_CTRL_USB_TESTMODE                         0x100000
+#define BF_DIGCTL_CTRL_USB_TESTMODE(v)                      (((v) << 20) & 0x100000)
+#define BP_DIGCTL_CTRL_ANALOG_TESTMODE                      19
+#define BM_DIGCTL_CTRL_ANALOG_TESTMODE                      0x80000
+#define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v)                   (((v) << 19) & 0x80000)
+#define BP_DIGCTL_CTRL_DIGITAL_TESTMODE                     18
+#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE                     0x40000
+#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v)                  (((v) << 18) & 0x40000)
+#define BP_DIGCTL_CTRL_ARM_BIST_START                       17
+#define BM_DIGCTL_CTRL_ARM_BIST_START                       0x20000
+#define BF_DIGCTL_CTRL_ARM_BIST_START(v)                    (((v) << 17) & 0x20000)
+#define BP_DIGCTL_CTRL_UART_LOOPBACK                        16
+#define BM_DIGCTL_CTRL_UART_LOOPBACK                        0x10000
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL                0x0
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT                0x1
+#define BF_DIGCTL_CTRL_UART_LOOPBACK(v)                     (((v) << 16) & 0x10000)
+#define BF_DIGCTL_CTRL_UART_LOOPBACK_V(v)                   ((BV_DIGCTL_CTRL_UART_LOOPBACK__##v << 16) & 0x10000)
+#define BP_DIGCTL_CTRL_SAIF_LOOPBACK                        15
+#define BM_DIGCTL_CTRL_SAIF_LOOPBACK                        0x8000
+#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL                0x0
+#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT                0x1
+#define BF_DIGCTL_CTRL_SAIF_LOOPBACK(v)                     (((v) << 15) & 0x8000)
+#define BF_DIGCTL_CTRL_SAIF_LOOPBACK_V(v)                   ((BV_DIGCTL_CTRL_SAIF_LOOPBACK__##v << 15) & 0x8000)
+#define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL                      13
+#define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL                      0x6000
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT         0x0
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT          0x1
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN           0x3
+#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v)                   (((v) << 13) & 0x6000)
+#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(v)                 ((BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__##v << 13) & 0x6000)
+#define BP_DIGCTL_CTRL_SAIF_CLKMST_SEL                      12
+#define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL                      0x1000
+#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST           0x0
+#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST           0x1
+#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(v)                   (((v) << 12) & 0x1000)
+#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(v)                 ((BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__##v << 12) & 0x1000)
+#define BP_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL                  11
+#define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL                  0x800
+#define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v)               (((v) << 11) & 0x800)
+#define BP_DIGCTL_CTRL_USE_SERIAL_JTAG                      6
+#define BM_DIGCTL_CTRL_USE_SERIAL_JTAG                      0x40
+#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG            0x0
+#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG         0x1
+#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG(v)                   (((v) << 6) & 0x40)
+#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG_V(v)                 ((BV_DIGCTL_CTRL_USE_SERIAL_JTAG__##v << 6) & 0x40)
+#define BP_DIGCTL_CTRL_TRAP_IN_RANGE                        5
+#define BM_DIGCTL_CTRL_TRAP_IN_RANGE                        0x20
+#define BF_DIGCTL_CTRL_TRAP_IN_RANGE(v)                     (((v) << 5) & 0x20)
+#define BP_DIGCTL_CTRL_TRAP_ENABLE                          4
+#define BM_DIGCTL_CTRL_TRAP_ENABLE                          0x10
+#define BF_DIGCTL_CTRL_TRAP_ENABLE(v)                       (((v) << 4) & 0x10)
+#define BP_DIGCTL_CTRL_DEBUG_DISABLE                        3
+#define BM_DIGCTL_CTRL_DEBUG_DISABLE                        0x8
+#define BF_DIGCTL_CTRL_DEBUG_DISABLE(v)                     (((v) << 3) & 0x8)
+#define BP_DIGCTL_CTRL_USB_CLKGATE                          2
+#define BM_DIGCTL_CTRL_USB_CLKGATE                          0x4
+#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN                     0x0
+#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS                 0x1
+#define BF_DIGCTL_CTRL_USB_CLKGATE(v)                       (((v) << 2) & 0x4)
+#define BF_DIGCTL_CTRL_USB_CLKGATE_V(v)                     ((BV_DIGCTL_CTRL_USB_CLKGATE__##v << 2) & 0x4)
+#define BP_DIGCTL_CTRL_JTAG_SHIELD                          1
+#define BM_DIGCTL_CTRL_JTAG_SHIELD                          0x2
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL                  0x0
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP              0x1
+#define BF_DIGCTL_CTRL_JTAG_SHIELD(v)                       (((v) << 1) & 0x2)
+#define BF_DIGCTL_CTRL_JTAG_SHIELD_V(v)                     ((BV_DIGCTL_CTRL_JTAG_SHIELD__##v << 1) & 0x2)
+#define BP_DIGCTL_CTRL_LATCH_ENTROPY                        0
+#define BM_DIGCTL_CTRL_LATCH_ENTROPY                        0x1
+#define BF_DIGCTL_CTRL_LATCH_ENTROPY(v)                     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_STATUS
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_DIGCTL_STATUS                        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10))
+#define BP_DIGCTL_STATUS_USB_HS_PRESENT         31
+#define BM_DIGCTL_STATUS_USB_HS_PRESENT         0x80000000
+#define BF_DIGCTL_STATUS_USB_HS_PRESENT(v)      (((v) << 31) & 0x80000000)
+#define BP_DIGCTL_STATUS_USB_OTG_PRESENT        30
+#define BM_DIGCTL_STATUS_USB_OTG_PRESENT        0x40000000
+#define BF_DIGCTL_STATUS_USB_OTG_PRESENT(v)     (((v) << 30) & 0x40000000)
+#define BP_DIGCTL_STATUS_USB_HOST_PRESENT       29
+#define BM_DIGCTL_STATUS_USB_HOST_PRESENT       0x20000000
+#define BF_DIGCTL_STATUS_USB_HOST_PRESENT(v)    (((v) << 29) & 0x20000000)
+#define BP_DIGCTL_STATUS_USB_DEVICE_PRESENT     28
+#define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT     0x10000000
+#define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(v)  (((v) << 28) & 0x10000000)
+#define BP_DIGCTL_STATUS_DCP_BIST_FAIL          10
+#define BM_DIGCTL_STATUS_DCP_BIST_FAIL          0x400
+#define BF_DIGCTL_STATUS_DCP_BIST_FAIL(v)       (((v) << 10) & 0x400)
+#define BP_DIGCTL_STATUS_DCP_BIST_PASS          9
+#define BM_DIGCTL_STATUS_DCP_BIST_PASS          0x200
+#define BF_DIGCTL_STATUS_DCP_BIST_PASS(v)       (((v) << 9) & 0x200)
+#define BP_DIGCTL_STATUS_DCP_BIST_DONE          8
+#define BM_DIGCTL_STATUS_DCP_BIST_DONE          0x100
+#define BF_DIGCTL_STATUS_DCP_BIST_DONE(v)       (((v) << 8) & 0x100)
+#define BP_DIGCTL_STATUS_JTAG_IN_USE            4
+#define BM_DIGCTL_STATUS_JTAG_IN_USE            0x10
+#define BF_DIGCTL_STATUS_JTAG_IN_USE(v)         (((v) << 4) & 0x10)
+#define BP_DIGCTL_STATUS_PACKAGE_TYPE           1
+#define BM_DIGCTL_STATUS_PACKAGE_TYPE           0xe
+#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v)        (((v) << 1) & 0xe)
+#define BP_DIGCTL_STATUS_WRITTEN                0
+#define BM_DIGCTL_STATUS_WRITTEN                0x1
+#define BF_DIGCTL_STATUS_WRITTEN(v)             (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_HCLKCOUNT
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_DIGCTL_HCLKCOUNT             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20))
+#define BP_DIGCTL_HCLKCOUNT_COUNT       0
+#define BM_DIGCTL_HCLKCOUNT_COUNT       0xffffffff
+#define BF_DIGCTL_HCLKCOUNT_COUNT(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_RAMCTRL
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_DIGCTL_RAMCTRL                   (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x0))
+#define HW_DIGCTL_RAMCTRL_SET               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x4))
+#define HW_DIGCTL_RAMCTRL_CLR               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x8))
+#define HW_DIGCTL_RAMCTRL_TOG               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0xc))
+#define BP_DIGCTL_RAMCTRL_SPEED_SELECT      8
+#define BM_DIGCTL_RAMCTRL_SPEED_SELECT      0xf00
+#define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v)   (((v) << 8) & 0xf00)
+#define BP_DIGCTL_RAMCTRL_RAM_REPAIR_EN     0
+#define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN     0x1
+#define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v)  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_RAMREPAIR
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_DIGCTL_RAMREPAIR         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x0))
+#define HW_DIGCTL_RAMREPAIR_SET     (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x4))
+#define HW_DIGCTL_RAMREPAIR_CLR     (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x8))
+#define HW_DIGCTL_RAMREPAIR_TOG     (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0xc))
+#define BP_DIGCTL_RAMREPAIR_ADDR    0
+#define BM_DIGCTL_RAMREPAIR_ADDR    0xffff
+#define BF_DIGCTL_RAMREPAIR_ADDR(v) (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DIGCTL_ROMCTRL
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_DIGCTL_ROMCTRL               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x0))
+#define HW_DIGCTL_ROMCTRL_SET           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x4))
+#define HW_DIGCTL_ROMCTRL_CLR           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x8))
+#define HW_DIGCTL_ROMCTRL_TOG           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0xc))
+#define BP_DIGCTL_ROMCTRL_RD_MARGIN     0
+#define BM_DIGCTL_ROMCTRL_RD_MARGIN     0xf
+#define BF_DIGCTL_ROMCTRL_RD_MARGIN(v)  (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_DIGCTL_WRITEONCE
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_DIGCTL_WRITEONCE         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x60))
+#define BP_DIGCTL_WRITEONCE_BITS    0
+#define BM_DIGCTL_WRITEONCE_BITS    0xffffffff
+#define BF_DIGCTL_WRITEONCE_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_ENTROPY
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_DIGCTL_ENTROPY           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x90))
+#define BP_DIGCTL_ENTROPY_VALUE     0
+#define BM_DIGCTL_ENTROPY_VALUE     0xffffffff
+#define BF_DIGCTL_ENTROPY_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_ENTROPY_LATCHED
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_DIGCTL_ENTROPY_LATCHED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xa0))
+#define BP_DIGCTL_ENTROPY_LATCHED_VALUE     0
+#define BM_DIGCTL_ENTROPY_LATCHED_VALUE     0xffffffff
+#define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_SJTAGDBG
+ * Address: 0xb0
+ * SCT: yes
+*/
+#define HW_DIGCTL_SJTAGDBG                      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x0))
+#define HW_DIGCTL_SJTAGDBG_SET                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x4))
+#define HW_DIGCTL_SJTAGDBG_CLR                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x8))
+#define HW_DIGCTL_SJTAGDBG_TOG                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0xc))
+#define BP_DIGCTL_SJTAGDBG_SJTAG_STATE          16
+#define BM_DIGCTL_SJTAGDBG_SJTAG_STATE          0x7ff0000
+#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v)       (((v) << 16) & 0x7ff0000)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_TDO            10
+#define BM_DIGCTL_SJTAGDBG_SJTAG_TDO            0x400
+#define BF_DIGCTL_SJTAGDBG_SJTAG_TDO(v)         (((v) << 10) & 0x400)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_TDI            9
+#define BM_DIGCTL_SJTAGDBG_SJTAG_TDI            0x200
+#define BF_DIGCTL_SJTAGDBG_SJTAG_TDI(v)         (((v) << 9) & 0x200)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_MODE           8
+#define BM_DIGCTL_SJTAGDBG_SJTAG_MODE           0x100
+#define BF_DIGCTL_SJTAGDBG_SJTAG_MODE(v)        (((v) << 8) & 0x100)
+#define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE       4
+#define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE       0xf0
+#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v)    (((v) << 4) & 0xf0)
+#define BP_DIGCTL_SJTAGDBG_ACTIVE               3
+#define BM_DIGCTL_SJTAGDBG_ACTIVE               0x8
+#define BF_DIGCTL_SJTAGDBG_ACTIVE(v)            (((v) << 3) & 0x8)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE      2
+#define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE      0x4
+#define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v)   (((v) << 2) & 0x4)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA     1
+#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA     0x2
+#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v)  (((v) << 1) & 0x2)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE       0
+#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE       0x1
+#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_MICROSECONDS
+ * Address: 0xc0
+ * SCT: yes
+*/
+#define HW_DIGCTL_MICROSECONDS          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x0))
+#define HW_DIGCTL_MICROSECONDS_SET      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x4))
+#define HW_DIGCTL_MICROSECONDS_CLR      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x8))
+#define HW_DIGCTL_MICROSECONDS_TOG      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0xc))
+#define BP_DIGCTL_MICROSECONDS_VALUE    0
+#define BM_DIGCTL_MICROSECONDS_VALUE    0xffffffff
+#define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_DBGRD
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_DIGCTL_DBGRD                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xd0))
+#define BP_DIGCTL_DBGRD_COMPLEMENT      0
+#define BM_DIGCTL_DBGRD_COMPLEMENT      0xffffffff
+#define BF_DIGCTL_DBGRD_COMPLEMENT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_DBG
+ * Address: 0xe0
+ * SCT: no
+*/
+#define HW_DIGCTL_DBG           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0))
+#define BP_DIGCTL_DBG_VALUE     0
+#define BM_DIGCTL_DBG_VALUE     0xffffffff
+#define BF_DIGCTL_DBG_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_BIST_CSR
+ * Address: 0xf0
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_BIST_CSR                        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x0))
+#define HW_DIGCTL_OCRAM_BIST_CSR_SET                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x4))
+#define HW_DIGCTL_OCRAM_BIST_CSR_CLR                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x8))
+#define HW_DIGCTL_OCRAM_BIST_CSR_TOG                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0xc))
+#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE       9
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE       0x200
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v)    (((v) << 9) & 0x200)
+#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN             8
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN             0x100
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v)          (((v) << 8) & 0x100)
+#define BP_DIGCTL_OCRAM_BIST_CSR_FAIL                   3
+#define BM_DIGCTL_OCRAM_BIST_CSR_FAIL                   0x8
+#define BF_DIGCTL_OCRAM_BIST_CSR_FAIL(v)                (((v) << 3) & 0x8)
+#define BP_DIGCTL_OCRAM_BIST_CSR_PASS                   2
+#define BM_DIGCTL_OCRAM_BIST_CSR_PASS                   0x4
+#define BF_DIGCTL_OCRAM_BIST_CSR_PASS(v)                (((v) << 2) & 0x4)
+#define BP_DIGCTL_OCRAM_BIST_CSR_DONE                   1
+#define BM_DIGCTL_OCRAM_BIST_CSR_DONE                   0x2
+#define BF_DIGCTL_OCRAM_BIST_CSR_DONE(v)                (((v) << 1) & 0x2)
+#define BP_DIGCTL_OCRAM_BIST_CSR_START                  0
+#define BM_DIGCTL_OCRAM_BIST_CSR_START                  0x1
+#define BF_DIGCTL_OCRAM_BIST_CSR_START(v)               (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS0
+ * Address: 0x110
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS0                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110))
+#define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00      0
+#define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS1
+ * Address: 0x120
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS1                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120))
+#define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01      0
+#define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS2
+ * Address: 0x130
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS2                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130))
+#define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10      0
+#define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS3
+ * Address: 0x140
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS3                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140))
+#define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11      0
+#define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS4
+ * Address: 0x150
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS4                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150))
+#define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20      0
+#define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS5
+ * Address: 0x160
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS5                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160))
+#define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21      0
+#define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS6
+ * Address: 0x170
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS6                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170))
+#define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30      0
+#define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS7
+ * Address: 0x180
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS7                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180))
+#define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31      0
+#define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS8
+ * Address: 0x190
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS8                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190))
+#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01      16
+#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01      0xffff0000
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v)   (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00      0
+#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00      0xffff
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS9
+ * Address: 0x1a0
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS9                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0))
+#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11      16
+#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11      0xffff0000
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v)   (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10      0
+#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10      0xffff
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS10
+ * Address: 0x1b0
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS10                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0))
+#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21     16
+#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21     0xffff0000
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v)  (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20     0
+#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20     0xffff
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS11
+ * Address: 0x1c0
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS11                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0))
+#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31     16
+#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31     0xffff0000
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v)  (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30     0
+#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30     0xffff
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS12
+ * Address: 0x1d0
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS12                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0))
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11    24
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11    0x1f000000
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) (((v) << 24) & 0x1f000000)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10    16
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10    0x1f0000
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) (((v) << 16) & 0x1f0000)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01    8
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01    0x1f00
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) (((v) << 8) & 0x1f00)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00    0
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00    0x1f
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS13
+ * Address: 0x1e0
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS13                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0))
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31    24
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31    0x1f000000
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) (((v) << 24) & 0x1f000000)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30    16
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30    0x1f0000
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) (((v) << 16) & 0x1f0000)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21    8
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21    0x1f00
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) (((v) << 8) & 0x1f00)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20    0
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20    0x1f
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_DIGCTL_SCRATCH0
+ * Address: 0x290
+ * SCT: no
+*/
+#define HW_DIGCTL_SCRATCH0          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x290))
+#define BP_DIGCTL_SCRATCH0_PTR      0
+#define BM_DIGCTL_SCRATCH0_PTR      0xffffffff
+#define BF_DIGCTL_SCRATCH0_PTR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_SCRATCH1
+ * Address: 0x2a0
+ * SCT: no
+*/
+#define HW_DIGCTL_SCRATCH1          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2a0))
+#define BP_DIGCTL_SCRATCH1_PTR      0
+#define BM_DIGCTL_SCRATCH1_PTR      0xffffffff
+#define BF_DIGCTL_SCRATCH1_PTR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_ARMCACHE
+ * Address: 0x2b0
+ * SCT: no
+*/
+#define HW_DIGCTL_ARMCACHE              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2b0))
+#define BP_DIGCTL_ARMCACHE_CACHE_SS     8
+#define BM_DIGCTL_ARMCACHE_CACHE_SS     0x300
+#define BF_DIGCTL_ARMCACHE_CACHE_SS(v)  (((v) << 8) & 0x300)
+#define BP_DIGCTL_ARMCACHE_DTAG_SS      4
+#define BM_DIGCTL_ARMCACHE_DTAG_SS      0x30
+#define BF_DIGCTL_ARMCACHE_DTAG_SS(v)   (((v) << 4) & 0x30)
+#define BP_DIGCTL_ARMCACHE_ITAG_SS      0
+#define BM_DIGCTL_ARMCACHE_ITAG_SS      0x3
+#define BF_DIGCTL_ARMCACHE_ITAG_SS(v)   (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_LOW
+ * Address: 0x2c0
+ * SCT: no
+*/
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2c0))
+#define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR      0
+#define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR      0xffffffff
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH
+ * Address: 0x2d0
+ * SCT: no
+*/
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2d0))
+#define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR     0
+#define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR     0xffffffff
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_SGTL
+ * Address: 0x300
+ * SCT: no
+*/
+#define HW_DIGCTL_SGTL              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x300))
+#define BP_DIGCTL_SGTL_COPYRIGHT    0
+#define BM_DIGCTL_SGTL_COPYRIGHT    0xffffffff
+#define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_CHIPID
+ * Address: 0x310
+ * SCT: no
+*/
+#define HW_DIGCTL_CHIPID                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x310))
+#define BP_DIGCTL_CHIPID_PRODUCT_CODE       16
+#define BM_DIGCTL_CHIPID_PRODUCT_CODE       0xffff0000
+#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v)    (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_CHIPID_REVISION           0
+#define BM_DIGCTL_CHIPID_REVISION           0xff
+#define BF_DIGCTL_CHIPID_REVISION(v)        (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DIGCTL_AHB_STATS_SELECT
+ * Address: 0x330
+ * SCT: no
+*/
+#define HW_DIGCTL_AHB_STATS_SELECT                          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x330))
+#define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT         24
+#define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT         0xf000000
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH   0x1
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX   0x2
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB    0x4
+#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v)      (((v) << 24) & 0xf000000)
+#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__##v << 24) & 0xf000000)
+#define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT         16
+#define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT         0xf0000
+#define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D  0x1
+#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v)      (((v) << 16) & 0xf0000)
+#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__##v << 16) & 0xf0000)
+#define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT         8
+#define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT         0xf00
+#define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I  0x1
+#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v)      (((v) << 8) & 0xf00)
+#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__##v << 8) & 0xf00)
+#define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT         0
+#define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT         0xf
+#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8   0x1
+#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2
+#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v)      (((v) << 0) & 0xf)
+#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__##v << 0) & 0xf)
+
+/**
+ * Register: HW_DIGCTL_L0_AHB_ACTIVE_CYCLES
+ * Address: 0x340
+ * SCT: no
+*/
+#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x340))
+#define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT    0
+#define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
+#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L0_AHB_DATA_STALLED
+ * Address: 0x350
+ * SCT: no
+*/
+#define HW_DIGCTL_L0_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x350))
+#define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT     0
+#define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT     0xffffffff
+#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L0_AHB_DATA_CYCLES
+ * Address: 0x360
+ * SCT: no
+*/
+#define HW_DIGCTL_L0_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x360))
+#define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT      0
+#define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT      0xffffffff
+#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L1_AHB_ACTIVE_CYCLES
+ * Address: 0x370
+ * SCT: no
+*/
+#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x370))
+#define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT    0
+#define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
+#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L1_AHB_DATA_STALLED
+ * Address: 0x380
+ * SCT: no
+*/
+#define HW_DIGCTL_L1_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x380))
+#define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT     0
+#define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT     0xffffffff
+#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L1_AHB_DATA_CYCLES
+ * Address: 0x390
+ * SCT: no
+*/
+#define HW_DIGCTL_L1_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x390))
+#define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT      0
+#define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT      0xffffffff
+#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L2_AHB_ACTIVE_CYCLES
+ * Address: 0x3a0
+ * SCT: no
+*/
+#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3a0))
+#define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT    0
+#define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
+#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L2_AHB_DATA_STALLED
+ * Address: 0x3b0
+ * SCT: no
+*/
+#define HW_DIGCTL_L2_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3b0))
+#define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT     0
+#define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT     0xffffffff
+#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L2_AHB_DATA_CYCLES
+ * Address: 0x3c0
+ * SCT: no
+*/
+#define HW_DIGCTL_L2_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3c0))
+#define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT      0
+#define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT      0xffffffff
+#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L3_AHB_ACTIVE_CYCLES
+ * Address: 0x3d0
+ * SCT: no
+*/
+#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3d0))
+#define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT    0
+#define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
+#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L3_AHB_DATA_STALLED
+ * Address: 0x3e0
+ * SCT: no
+*/
+#define HW_DIGCTL_L3_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3e0))
+#define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT     0
+#define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT     0xffffffff
+#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L3_AHB_DATA_CYCLES
+ * Address: 0x3f0
+ * SCT: no
+*/
+#define HW_DIGCTL_L3_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3f0))
+#define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT      0
+#define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT      0xffffffff
+#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_MPTEn_LOC
+ * Address: 0x400+n*0x10
+ * SCT: no
+*/
+#define HW_DIGCTL_MPTEn_LOC(n)      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x400+(n)*0x10))
+#define BP_DIGCTL_MPTEn_LOC_LOC     0
+#define BM_DIGCTL_MPTEn_LOC_LOC     0xfff
+#define BF_DIGCTL_MPTEn_LOC_LOC(v)  (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_DIGCTL_EMICLK_DELAY
+ * Address: 0x480
+ * SCT: no
+*/
+#define HW_DIGCTL_EMICLK_DELAY              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x480))
+#define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS     0
+#define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS     0x1f
+#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v)  (((v) << 0) & 0x1f)
+
+#endif /* __HEADERGEN__STMP3700__DIGCTL__H__ */