diff options
author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-13 19:03:33 +0200 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-15 22:27:34 +0200 |
commit | 017667c2dc9843eb5082e991f421c773636dcf36 (patch) | |
tree | 60432008dd3bc012ac60cbfa771305f6d894dd84 /firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h | |
parent | 97b9ade63945fd8b8261fb0cf1dd0aa225c1a319 (diff) | |
download | rockbox-017667c2dc9843eb5082e991f421c773636dcf36.tar.gz rockbox-017667c2dc9843eb5082e991f421c773636dcf36.zip |
imx233: generate register headers for stmp3600, stmp3700 and imx233
Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h | 459 |
1 files changed, 459 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h new file mode 100644 index 0000000000..0449161d11 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h | |||
@@ -0,0 +1,459 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__CLKCTRL__H__ | ||
24 | #define __HEADERGEN__STMP3700__CLKCTRL__H__ | ||
25 | |||
26 | #define REGS_CLKCTRL_BASE (0x80040000) | ||
27 | |||
28 | #define REGS_CLKCTRL_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_CLKCTRL_PLLCTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_CLKCTRL_PLLCTRL0 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_CLKCTRL_PLLCTRL0_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_CLKCTRL_PLLCTRL0_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_CLKCTRL_PLLCTRL0_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 | ||
40 | #define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 | ||
41 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0 | ||
42 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 | ||
43 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 | ||
44 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 | ||
45 | #define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) (((v) << 28) & 0x30000000) | ||
46 | #define BF_CLKCTRL_PLLCTRL0_LFR_SEL_V(v) ((BV_CLKCTRL_PLLCTRL0_LFR_SEL__##v << 28) & 0x30000000) | ||
47 | #define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 | ||
48 | #define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x3000000 | ||
49 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0 | ||
50 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 | ||
51 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 | ||
52 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 | ||
53 | #define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) (((v) << 24) & 0x3000000) | ||
54 | #define BF_CLKCTRL_PLLCTRL0_CP_SEL_V(v) ((BV_CLKCTRL_PLLCTRL0_CP_SEL__##v << 24) & 0x3000000) | ||
55 | #define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 | ||
56 | #define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x300000 | ||
57 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0 | ||
58 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 | ||
59 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 | ||
60 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 | ||
61 | #define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) (((v) << 20) & 0x300000) | ||
62 | #define BF_CLKCTRL_PLLCTRL0_DIV_SEL_V(v) ((BV_CLKCTRL_PLLCTRL0_DIV_SEL__##v << 20) & 0x300000) | ||
63 | #define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS 18 | ||
64 | #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x40000 | ||
65 | #define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v) (((v) << 18) & 0x40000) | ||
66 | #define BP_CLKCTRL_PLLCTRL0_POWER 16 | ||
67 | #define BM_CLKCTRL_PLLCTRL0_POWER 0x10000 | ||
68 | #define BF_CLKCTRL_PLLCTRL0_POWER(v) (((v) << 16) & 0x10000) | ||
69 | |||
70 | /** | ||
71 | * Register: HW_CLKCTRL_PLLCTRL1 | ||
72 | * Address: 0x10 | ||
73 | * SCT: no | ||
74 | */ | ||
75 | #define HW_CLKCTRL_PLLCTRL1 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10)) | ||
76 | #define BP_CLKCTRL_PLLCTRL1_LOCK 31 | ||
77 | #define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 | ||
78 | #define BF_CLKCTRL_PLLCTRL1_LOCK(v) (((v) << 31) & 0x80000000) | ||
79 | #define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK 30 | ||
80 | #define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 | ||
81 | #define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v) (((v) << 30) & 0x40000000) | ||
82 | #define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 | ||
83 | #define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0xffff | ||
84 | #define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) (((v) << 0) & 0xffff) | ||
85 | |||
86 | /** | ||
87 | * Register: HW_CLKCTRL_CPU | ||
88 | * Address: 0x20 | ||
89 | * SCT: yes | ||
90 | */ | ||
91 | #define HW_CLKCTRL_CPU (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x0)) | ||
92 | #define HW_CLKCTRL_CPU_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x4)) | ||
93 | #define HW_CLKCTRL_CPU_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x8)) | ||
94 | #define HW_CLKCTRL_CPU_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0xc)) | ||
95 | #define BP_CLKCTRL_CPU_BUSY_REF_XTAL 29 | ||
96 | #define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 | ||
97 | #define BF_CLKCTRL_CPU_BUSY_REF_XTAL(v) (((v) << 29) & 0x20000000) | ||
98 | #define BP_CLKCTRL_CPU_BUSY_REF_CPU 28 | ||
99 | #define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 | ||
100 | #define BF_CLKCTRL_CPU_BUSY_REF_CPU(v) (((v) << 28) & 0x10000000) | ||
101 | #define BP_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 26 | ||
102 | #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x4000000 | ||
103 | #define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v) (((v) << 26) & 0x4000000) | ||
104 | #define BP_CLKCTRL_CPU_DIV_XTAL 16 | ||
105 | #define BM_CLKCTRL_CPU_DIV_XTAL 0x3ff0000 | ||
106 | #define BF_CLKCTRL_CPU_DIV_XTAL(v) (((v) << 16) & 0x3ff0000) | ||
107 | #define BP_CLKCTRL_CPU_INTERRUPT_WAIT 12 | ||
108 | #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x1000 | ||
109 | #define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v) (((v) << 12) & 0x1000) | ||
110 | #define BP_CLKCTRL_CPU_DIV_CPU_FRAC_EN 10 | ||
111 | #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x400 | ||
112 | #define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v) (((v) << 10) & 0x400) | ||
113 | #define BP_CLKCTRL_CPU_DIV_CPU 0 | ||
114 | #define BM_CLKCTRL_CPU_DIV_CPU 0x3ff | ||
115 | #define BF_CLKCTRL_CPU_DIV_CPU(v) (((v) << 0) & 0x3ff) | ||
116 | |||
117 | /** | ||
118 | * Register: HW_CLKCTRL_HBUS | ||
119 | * Address: 0x30 | ||
120 | * SCT: yes | ||
121 | */ | ||
122 | #define HW_CLKCTRL_HBUS (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x0)) | ||
123 | #define HW_CLKCTRL_HBUS_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x4)) | ||
124 | #define HW_CLKCTRL_HBUS_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x8)) | ||
125 | #define HW_CLKCTRL_HBUS_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0xc)) | ||
126 | #define BP_CLKCTRL_HBUS_BUSY 29 | ||
127 | #define BM_CLKCTRL_HBUS_BUSY 0x20000000 | ||
128 | #define BF_CLKCTRL_HBUS_BUSY(v) (((v) << 29) & 0x20000000) | ||
129 | #define BP_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 26 | ||
130 | #define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x4000000 | ||
131 | #define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v) (((v) << 26) & 0x4000000) | ||
132 | #define BP_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 25 | ||
133 | #define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x2000000 | ||
134 | #define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v) (((v) << 25) & 0x2000000) | ||
135 | #define BP_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 24 | ||
136 | #define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x1000000 | ||
137 | #define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v) (((v) << 24) & 0x1000000) | ||
138 | #define BP_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 23 | ||
139 | #define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x800000 | ||
140 | #define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v) (((v) << 23) & 0x800000) | ||
141 | #define BP_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 22 | ||
142 | #define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x400000 | ||
143 | #define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v) (((v) << 22) & 0x400000) | ||
144 | #define BP_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 21 | ||
145 | #define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x200000 | ||
146 | #define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v) (((v) << 21) & 0x200000) | ||
147 | #define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE 20 | ||
148 | #define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x100000 | ||
149 | #define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v) (((v) << 20) & 0x100000) | ||
150 | #define BP_CLKCTRL_HBUS_SLOW_DIV 16 | ||
151 | #define BM_CLKCTRL_HBUS_SLOW_DIV 0x70000 | ||
152 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 | ||
153 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 | ||
154 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 | ||
155 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 | ||
156 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 | ||
157 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 | ||
158 | #define BF_CLKCTRL_HBUS_SLOW_DIV(v) (((v) << 16) & 0x70000) | ||
159 | #define BF_CLKCTRL_HBUS_SLOW_DIV_V(v) ((BV_CLKCTRL_HBUS_SLOW_DIV__##v << 16) & 0x70000) | ||
160 | #define BP_CLKCTRL_HBUS_DIV_FRAC_EN 5 | ||
161 | #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x20 | ||
162 | #define BF_CLKCTRL_HBUS_DIV_FRAC_EN(v) (((v) << 5) & 0x20) | ||
163 | #define BP_CLKCTRL_HBUS_DIV 0 | ||
164 | #define BM_CLKCTRL_HBUS_DIV 0x1f | ||
165 | #define BF_CLKCTRL_HBUS_DIV(v) (((v) << 0) & 0x1f) | ||
166 | |||
167 | /** | ||
168 | * Register: HW_CLKCTRL_XBUS | ||
169 | * Address: 0x40 | ||
170 | * SCT: no | ||
171 | */ | ||
172 | #define HW_CLKCTRL_XBUS (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x40)) | ||
173 | #define BP_CLKCTRL_XBUS_BUSY 31 | ||
174 | #define BM_CLKCTRL_XBUS_BUSY 0x80000000 | ||
175 | #define BF_CLKCTRL_XBUS_BUSY(v) (((v) << 31) & 0x80000000) | ||
176 | #define BP_CLKCTRL_XBUS_DIV_FRAC_EN 10 | ||
177 | #define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x400 | ||
178 | #define BF_CLKCTRL_XBUS_DIV_FRAC_EN(v) (((v) << 10) & 0x400) | ||
179 | #define BP_CLKCTRL_XBUS_DIV 0 | ||
180 | #define BM_CLKCTRL_XBUS_DIV 0x3ff | ||
181 | #define BF_CLKCTRL_XBUS_DIV(v) (((v) << 0) & 0x3ff) | ||
182 | |||
183 | /** | ||
184 | * Register: HW_CLKCTRL_XTAL | ||
185 | * Address: 0x50 | ||
186 | * SCT: yes | ||
187 | */ | ||
188 | #define HW_CLKCTRL_XTAL (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x0)) | ||
189 | #define HW_CLKCTRL_XTAL_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x4)) | ||
190 | #define HW_CLKCTRL_XTAL_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x8)) | ||
191 | #define HW_CLKCTRL_XTAL_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0xc)) | ||
192 | #define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 | ||
193 | #define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 | ||
194 | #define BF_CLKCTRL_XTAL_UART_CLK_GATE(v) (((v) << 31) & 0x80000000) | ||
195 | #define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30 | ||
196 | #define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 | ||
197 | #define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v) (((v) << 30) & 0x40000000) | ||
198 | #define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 | ||
199 | #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 | ||
200 | #define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v) (((v) << 29) & 0x20000000) | ||
201 | #define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE 28 | ||
202 | #define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 | ||
203 | #define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v) (((v) << 28) & 0x10000000) | ||
204 | #define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 27 | ||
205 | #define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x8000000 | ||
206 | #define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v) (((v) << 27) & 0x8000000) | ||
207 | #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 | ||
208 | #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x4000000 | ||
209 | #define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v) (((v) << 26) & 0x4000000) | ||
210 | #define BP_CLKCTRL_XTAL_DIV_UART 0 | ||
211 | #define BM_CLKCTRL_XTAL_DIV_UART 0x3 | ||
212 | #define BF_CLKCTRL_XTAL_DIV_UART(v) (((v) << 0) & 0x3) | ||
213 | |||
214 | /** | ||
215 | * Register: HW_CLKCTRL_PIX | ||
216 | * Address: 0x60 | ||
217 | * SCT: no | ||
218 | */ | ||
219 | #define HW_CLKCTRL_PIX (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x60)) | ||
220 | #define BP_CLKCTRL_PIX_CLKGATE 31 | ||
221 | #define BM_CLKCTRL_PIX_CLKGATE 0x80000000 | ||
222 | #define BF_CLKCTRL_PIX_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
223 | #define BP_CLKCTRL_PIX_BUSY 29 | ||
224 | #define BM_CLKCTRL_PIX_BUSY 0x20000000 | ||
225 | #define BF_CLKCTRL_PIX_BUSY(v) (((v) << 29) & 0x20000000) | ||
226 | #define BP_CLKCTRL_PIX_DIV_FRAC_EN 15 | ||
227 | #define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x8000 | ||
228 | #define BF_CLKCTRL_PIX_DIV_FRAC_EN(v) (((v) << 15) & 0x8000) | ||
229 | #define BP_CLKCTRL_PIX_DIV 0 | ||
230 | #define BM_CLKCTRL_PIX_DIV 0x7fff | ||
231 | #define BF_CLKCTRL_PIX_DIV(v) (((v) << 0) & 0x7fff) | ||
232 | |||
233 | /** | ||
234 | * Register: HW_CLKCTRL_SSP | ||
235 | * Address: 0x70 | ||
236 | * SCT: no | ||
237 | */ | ||
238 | #define HW_CLKCTRL_SSP (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x70)) | ||
239 | #define BP_CLKCTRL_SSP_CLKGATE 31 | ||
240 | #define BM_CLKCTRL_SSP_CLKGATE 0x80000000 | ||
241 | #define BF_CLKCTRL_SSP_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
242 | #define BP_CLKCTRL_SSP_BUSY 29 | ||
243 | #define BM_CLKCTRL_SSP_BUSY 0x20000000 | ||
244 | #define BF_CLKCTRL_SSP_BUSY(v) (((v) << 29) & 0x20000000) | ||
245 | #define BP_CLKCTRL_SSP_DIV_FRAC_EN 9 | ||
246 | #define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x200 | ||
247 | #define BF_CLKCTRL_SSP_DIV_FRAC_EN(v) (((v) << 9) & 0x200) | ||
248 | #define BP_CLKCTRL_SSP_DIV 0 | ||
249 | #define BM_CLKCTRL_SSP_DIV 0x1ff | ||
250 | #define BF_CLKCTRL_SSP_DIV(v) (((v) << 0) & 0x1ff) | ||
251 | |||
252 | /** | ||
253 | * Register: HW_CLKCTRL_GPMI | ||
254 | * Address: 0x80 | ||
255 | * SCT: no | ||
256 | */ | ||
257 | #define HW_CLKCTRL_GPMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x80)) | ||
258 | #define BP_CLKCTRL_GPMI_CLKGATE 31 | ||
259 | #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 | ||
260 | #define BF_CLKCTRL_GPMI_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
261 | #define BP_CLKCTRL_GPMI_BUSY 29 | ||
262 | #define BM_CLKCTRL_GPMI_BUSY 0x20000000 | ||
263 | #define BF_CLKCTRL_GPMI_BUSY(v) (((v) << 29) & 0x20000000) | ||
264 | #define BP_CLKCTRL_GPMI_DIV_FRAC_EN 10 | ||
265 | #define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x400 | ||
266 | #define BF_CLKCTRL_GPMI_DIV_FRAC_EN(v) (((v) << 10) & 0x400) | ||
267 | #define BP_CLKCTRL_GPMI_DIV 0 | ||
268 | #define BM_CLKCTRL_GPMI_DIV 0x3ff | ||
269 | #define BF_CLKCTRL_GPMI_DIV(v) (((v) << 0) & 0x3ff) | ||
270 | |||
271 | /** | ||
272 | * Register: HW_CLKCTRL_SPDIF | ||
273 | * Address: 0x90 | ||
274 | * SCT: no | ||
275 | */ | ||
276 | #define HW_CLKCTRL_SPDIF (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x90)) | ||
277 | #define BP_CLKCTRL_SPDIF_CLKGATE 31 | ||
278 | #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 | ||
279 | #define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
280 | |||
281 | /** | ||
282 | * Register: HW_CLKCTRL_EMI | ||
283 | * Address: 0xa0 | ||
284 | * SCT: no | ||
285 | */ | ||
286 | #define HW_CLKCTRL_EMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xa0)) | ||
287 | #define BP_CLKCTRL_EMI_CLKGATE 31 | ||
288 | #define BM_CLKCTRL_EMI_CLKGATE 0x80000000 | ||
289 | #define BF_CLKCTRL_EMI_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
290 | #define BP_CLKCTRL_EMI_BUSY_REF_XTAL 29 | ||
291 | #define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 | ||
292 | #define BF_CLKCTRL_EMI_BUSY_REF_XTAL(v) (((v) << 29) & 0x20000000) | ||
293 | #define BP_CLKCTRL_EMI_BUSY_REF_EMI 28 | ||
294 | #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 | ||
295 | #define BF_CLKCTRL_EMI_BUSY_REF_EMI(v) (((v) << 28) & 0x10000000) | ||
296 | #define BP_CLKCTRL_EMI_BUSY_DCC_RESYNC 17 | ||
297 | #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x20000 | ||
298 | #define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(v) (((v) << 17) & 0x20000) | ||
299 | #define BP_CLKCTRL_EMI_DCC_RESYNC_ENABLE 16 | ||
300 | #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x10000 | ||
301 | #define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v) (((v) << 16) & 0x10000) | ||
302 | #define BP_CLKCTRL_EMI_DIV_XTAL 8 | ||
303 | #define BM_CLKCTRL_EMI_DIV_XTAL 0xf00 | ||
304 | #define BF_CLKCTRL_EMI_DIV_XTAL(v) (((v) << 8) & 0xf00) | ||
305 | #define BP_CLKCTRL_EMI_DIV_EMI 0 | ||
306 | #define BM_CLKCTRL_EMI_DIV_EMI 0x3f | ||
307 | #define BF_CLKCTRL_EMI_DIV_EMI(v) (((v) << 0) & 0x3f) | ||
308 | |||
309 | /** | ||
310 | * Register: HW_CLKCTRL_IR | ||
311 | * Address: 0xb0 | ||
312 | * SCT: no | ||
313 | */ | ||
314 | #define HW_CLKCTRL_IR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xb0)) | ||
315 | #define BP_CLKCTRL_IR_CLKGATE 31 | ||
316 | #define BM_CLKCTRL_IR_CLKGATE 0x80000000 | ||
317 | #define BF_CLKCTRL_IR_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
318 | #define BP_CLKCTRL_IR_AUTO_DIV 29 | ||
319 | #define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 | ||
320 | #define BF_CLKCTRL_IR_AUTO_DIV(v) (((v) << 29) & 0x20000000) | ||
321 | #define BP_CLKCTRL_IR_IR_BUSY 28 | ||
322 | #define BM_CLKCTRL_IR_IR_BUSY 0x10000000 | ||
323 | #define BF_CLKCTRL_IR_IR_BUSY(v) (((v) << 28) & 0x10000000) | ||
324 | #define BP_CLKCTRL_IR_IROV_BUSY 27 | ||
325 | #define BM_CLKCTRL_IR_IROV_BUSY 0x8000000 | ||
326 | #define BF_CLKCTRL_IR_IROV_BUSY(v) (((v) << 27) & 0x8000000) | ||
327 | #define BP_CLKCTRL_IR_IROV_DIV 16 | ||
328 | #define BM_CLKCTRL_IR_IROV_DIV 0x1ff0000 | ||
329 | #define BF_CLKCTRL_IR_IROV_DIV(v) (((v) << 16) & 0x1ff0000) | ||
330 | #define BP_CLKCTRL_IR_IR_DIV 0 | ||
331 | #define BM_CLKCTRL_IR_IR_DIV 0x3ff | ||
332 | #define BF_CLKCTRL_IR_IR_DIV(v) (((v) << 0) & 0x3ff) | ||
333 | |||
334 | /** | ||
335 | * Register: HW_CLKCTRL_SAIF | ||
336 | * Address: 0xc0 | ||
337 | * SCT: no | ||
338 | */ | ||
339 | #define HW_CLKCTRL_SAIF (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xc0)) | ||
340 | #define BP_CLKCTRL_SAIF_CLKGATE 31 | ||
341 | #define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 | ||
342 | #define BF_CLKCTRL_SAIF_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
343 | #define BP_CLKCTRL_SAIF_BUSY 29 | ||
344 | #define BM_CLKCTRL_SAIF_BUSY 0x20000000 | ||
345 | #define BF_CLKCTRL_SAIF_BUSY(v) (((v) << 29) & 0x20000000) | ||
346 | #define BP_CLKCTRL_SAIF_DIV_FRAC_EN 16 | ||
347 | #define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x10000 | ||
348 | #define BF_CLKCTRL_SAIF_DIV_FRAC_EN(v) (((v) << 16) & 0x10000) | ||
349 | #define BP_CLKCTRL_SAIF_DIV 0 | ||
350 | #define BM_CLKCTRL_SAIF_DIV 0xffff | ||
351 | #define BF_CLKCTRL_SAIF_DIV(v) (((v) << 0) & 0xffff) | ||
352 | |||
353 | /** | ||
354 | * Register: HW_CLKCTRL_FRAC | ||
355 | * Address: 0xd0 | ||
356 | * SCT: yes | ||
357 | */ | ||
358 | #define HW_CLKCTRL_FRAC (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0x0)) | ||
359 | #define HW_CLKCTRL_FRAC_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0x4)) | ||
360 | #define HW_CLKCTRL_FRAC_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0x8)) | ||
361 | #define HW_CLKCTRL_FRAC_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0xc)) | ||
362 | #define BP_CLKCTRL_FRAC_CLKGATEIO 31 | ||
363 | #define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000 | ||
364 | #define BF_CLKCTRL_FRAC_CLKGATEIO(v) (((v) << 31) & 0x80000000) | ||
365 | #define BP_CLKCTRL_FRAC_IO_STABLE 30 | ||
366 | #define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000 | ||
367 | #define BF_CLKCTRL_FRAC_IO_STABLE(v) (((v) << 30) & 0x40000000) | ||
368 | #define BP_CLKCTRL_FRAC_IOFRAC 24 | ||
369 | #define BM_CLKCTRL_FRAC_IOFRAC 0x3f000000 | ||
370 | #define BF_CLKCTRL_FRAC_IOFRAC(v) (((v) << 24) & 0x3f000000) | ||
371 | #define BP_CLKCTRL_FRAC_CLKGATEPIX 23 | ||
372 | #define BM_CLKCTRL_FRAC_CLKGATEPIX 0x800000 | ||
373 | #define BF_CLKCTRL_FRAC_CLKGATEPIX(v) (((v) << 23) & 0x800000) | ||
374 | #define BP_CLKCTRL_FRAC_PIX_STABLE 22 | ||
375 | #define BM_CLKCTRL_FRAC_PIX_STABLE 0x400000 | ||
376 | #define BF_CLKCTRL_FRAC_PIX_STABLE(v) (((v) << 22) & 0x400000) | ||
377 | #define BP_CLKCTRL_FRAC_PIXFRAC 16 | ||
378 | #define BM_CLKCTRL_FRAC_PIXFRAC 0x3f0000 | ||
379 | #define BF_CLKCTRL_FRAC_PIXFRAC(v) (((v) << 16) & 0x3f0000) | ||
380 | #define BP_CLKCTRL_FRAC_CLKGATEEMI 15 | ||
381 | #define BM_CLKCTRL_FRAC_CLKGATEEMI 0x8000 | ||
382 | #define BF_CLKCTRL_FRAC_CLKGATEEMI(v) (((v) << 15) & 0x8000) | ||
383 | #define BP_CLKCTRL_FRAC_EMI_STABLE 14 | ||
384 | #define BM_CLKCTRL_FRAC_EMI_STABLE 0x4000 | ||
385 | #define BF_CLKCTRL_FRAC_EMI_STABLE(v) (((v) << 14) & 0x4000) | ||
386 | #define BP_CLKCTRL_FRAC_EMIFRAC 8 | ||
387 | #define BM_CLKCTRL_FRAC_EMIFRAC 0x3f00 | ||
388 | #define BF_CLKCTRL_FRAC_EMIFRAC(v) (((v) << 8) & 0x3f00) | ||
389 | #define BP_CLKCTRL_FRAC_CLKGATECPU 7 | ||
390 | #define BM_CLKCTRL_FRAC_CLKGATECPU 0x80 | ||
391 | #define BF_CLKCTRL_FRAC_CLKGATECPU(v) (((v) << 7) & 0x80) | ||
392 | #define BP_CLKCTRL_FRAC_CPU_STABLE 6 | ||
393 | #define BM_CLKCTRL_FRAC_CPU_STABLE 0x40 | ||
394 | #define BF_CLKCTRL_FRAC_CPU_STABLE(v) (((v) << 6) & 0x40) | ||
395 | #define BP_CLKCTRL_FRAC_CPUFRAC 0 | ||
396 | #define BM_CLKCTRL_FRAC_CPUFRAC 0x3f | ||
397 | #define BF_CLKCTRL_FRAC_CPUFRAC(v) (((v) << 0) & 0x3f) | ||
398 | |||
399 | /** | ||
400 | * Register: HW_CLKCTRL_CLKSEQ | ||
401 | * Address: 0xe0 | ||
402 | * SCT: yes | ||
403 | */ | ||
404 | #define HW_CLKCTRL_CLKSEQ (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0x0)) | ||
405 | #define HW_CLKCTRL_CLKSEQ_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0x4)) | ||
406 | #define HW_CLKCTRL_CLKSEQ_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0x8)) | ||
407 | #define HW_CLKCTRL_CLKSEQ_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0xc)) | ||
408 | #define BP_CLKCTRL_CLKSEQ_BYPASS_CPU 7 | ||
409 | #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x80 | ||
410 | #define BF_CLKCTRL_CLKSEQ_BYPASS_CPU(v) (((v) << 7) & 0x80) | ||
411 | #define BP_CLKCTRL_CLKSEQ_BYPASS_EMI 6 | ||
412 | #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x40 | ||
413 | #define BF_CLKCTRL_CLKSEQ_BYPASS_EMI(v) (((v) << 6) & 0x40) | ||
414 | #define BP_CLKCTRL_CLKSEQ_BYPASS_SSP 5 | ||
415 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x20 | ||
416 | #define BF_CLKCTRL_CLKSEQ_BYPASS_SSP(v) (((v) << 5) & 0x20) | ||
417 | #define BP_CLKCTRL_CLKSEQ_BYPASS_GPMI 4 | ||
418 | #define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x10 | ||
419 | #define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(v) (((v) << 4) & 0x10) | ||
420 | #define BP_CLKCTRL_CLKSEQ_BYPASS_IR 3 | ||
421 | #define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x8 | ||
422 | #define BF_CLKCTRL_CLKSEQ_BYPASS_IR(v) (((v) << 3) & 0x8) | ||
423 | #define BP_CLKCTRL_CLKSEQ_BYPASS_PIX 1 | ||
424 | #define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x2 | ||
425 | #define BF_CLKCTRL_CLKSEQ_BYPASS_PIX(v) (((v) << 1) & 0x2) | ||
426 | #define BP_CLKCTRL_CLKSEQ_BYPASS_SAIF 0 | ||
427 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x1 | ||
428 | #define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(v) (((v) << 0) & 0x1) | ||
429 | |||
430 | /** | ||
431 | * Register: HW_CLKCTRL_RESET | ||
432 | * Address: 0xf0 | ||
433 | * SCT: no | ||
434 | */ | ||
435 | #define HW_CLKCTRL_RESET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0)) | ||
436 | #define BP_CLKCTRL_RESET_CHIP 1 | ||
437 | #define BM_CLKCTRL_RESET_CHIP 0x2 | ||
438 | #define BF_CLKCTRL_RESET_CHIP(v) (((v) << 1) & 0x2) | ||
439 | #define BP_CLKCTRL_RESET_DIG 0 | ||
440 | #define BM_CLKCTRL_RESET_DIG 0x1 | ||
441 | #define BF_CLKCTRL_RESET_DIG(v) (((v) << 0) & 0x1) | ||
442 | |||
443 | /** | ||
444 | * Register: HW_CLKCTRL_VERSION | ||
445 | * Address: 0x100 | ||
446 | * SCT: no | ||
447 | */ | ||
448 | #define HW_CLKCTRL_VERSION (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100)) | ||
449 | #define BP_CLKCTRL_VERSION_MAJOR 24 | ||
450 | #define BM_CLKCTRL_VERSION_MAJOR 0xff000000 | ||
451 | #define BF_CLKCTRL_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
452 | #define BP_CLKCTRL_VERSION_MINOR 16 | ||
453 | #define BM_CLKCTRL_VERSION_MINOR 0xff0000 | ||
454 | #define BF_CLKCTRL_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
455 | #define BP_CLKCTRL_VERSION_STEP 0 | ||
456 | #define BM_CLKCTRL_VERSION_STEP 0xffff | ||
457 | #define BF_CLKCTRL_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
458 | |||
459 | #endif /* __HEADERGEN__STMP3700__CLKCTRL__H__ */ | ||