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authorAmaury Pouly <amaury.pouly@gmail.com>2013-06-13 19:03:33 +0200
committerAmaury Pouly <amaury.pouly@gmail.com>2013-06-15 22:27:34 +0200
commit017667c2dc9843eb5082e991f421c773636dcf36 (patch)
tree60432008dd3bc012ac60cbfa771305f6d894dd84 /firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h
parent97b9ade63945fd8b8261fb0cf1dd0aa225c1a319 (diff)
downloadrockbox-017667c2dc9843eb5082e991f421c773636dcf36.tar.gz
rockbox-017667c2dc9843eb5082e991f421c773636dcf36.zip
imx233: generate register headers for stmp3600, stmp3700 and imx233
Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h')
-rw-r--r--firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h294
1 files changed, 294 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h b/firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h
new file mode 100644
index 0000000000..5f93e5de3c
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h
@@ -0,0 +1,294 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * This file was automatically generated by headergen, DO NOT EDIT it.
9 * headergen version: 2.1.7
10 * XML versions: stmp3700:3.2.0
11 *
12 * Copyright (C) 2013 by Amaury Pouly
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version 2
17 * of the License, or (at your option) any later version.
18 *
19 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
20 * KIND, either express or implied.
21 *
22 ****************************************************************************/
23#ifndef __HEADERGEN__STMP3700__APBX__H__
24#define __HEADERGEN__STMP3700__APBX__H__
25
26#define REGS_APBX_BASE (0x80024000)
27
28#define REGS_APBX_VERSION "3.2.0"
29
30/**
31 * Register: HW_APBX_CTRL0
32 * Address: 0
33 * SCT: yes
34*/
35#define HW_APBX_CTRL0 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x0))
36#define HW_APBX_CTRL0_SET (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x4))
37#define HW_APBX_CTRL0_CLR (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x8))
38#define HW_APBX_CTRL0_TOG (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0xc))
39#define BP_APBX_CTRL0_SFTRST 31
40#define BM_APBX_CTRL0_SFTRST 0x80000000
41#define BF_APBX_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000)
42#define BP_APBX_CTRL0_CLKGATE 30
43#define BM_APBX_CTRL0_CLKGATE 0x40000000
44#define BF_APBX_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000)
45#define BP_APBX_CTRL0_RESET_CHANNEL 16
46#define BM_APBX_CTRL0_RESET_CHANNEL 0xff0000
47#define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOIN 0x1
48#define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOOUT 0x2
49#define BV_APBX_CTRL0_RESET_CHANNEL__SPDIF_TX 0x4
50#define BV_APBX_CTRL0_RESET_CHANNEL__SAIF2 0x4
51#define BV_APBX_CTRL0_RESET_CHANNEL__I2C 0x8
52#define BV_APBX_CTRL0_RESET_CHANNEL__SAIF1 0x10
53#define BV_APBX_CTRL0_RESET_CHANNEL__DRI 0x20
54#define BV_APBX_CTRL0_RESET_CHANNEL__UART_RX 0x40
55#define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_RX 0x40
56#define BV_APBX_CTRL0_RESET_CHANNEL__UART_TX 0x80
57#define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_TX 0x80
58#define BF_APBX_CTRL0_RESET_CHANNEL(v) (((v) << 16) & 0xff0000)
59#define BF_APBX_CTRL0_RESET_CHANNEL_V(v) ((BV_APBX_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000)
60#define BP_APBX_CTRL0_FREEZE_CHANNEL 0
61#define BM_APBX_CTRL0_FREEZE_CHANNEL 0xff
62#define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOIN 0x1
63#define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOOUT 0x2
64#define BV_APBX_CTRL0_FREEZE_CHANNEL__SPDIF_TX 0x4
65#define BV_APBX_CTRL0_FREEZE_CHANNEL__SAIF2 0x4
66#define BV_APBX_CTRL0_FREEZE_CHANNEL__I2C 0x8
67#define BV_APBX_CTRL0_FREEZE_CHANNEL__SAIF1 0x10
68#define BV_APBX_CTRL0_FREEZE_CHANNEL__DRI 0x20
69#define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_RX 0x40
70#define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_RX 0x40
71#define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_TX 0x80
72#define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_TX 0x80
73#define BF_APBX_CTRL0_FREEZE_CHANNEL(v) (((v) << 0) & 0xff)
74#define BF_APBX_CTRL0_FREEZE_CHANNEL_V(v) ((BV_APBX_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff)
75
76/**
77 * Register: HW_APBX_CTRL1
78 * Address: 0x10
79 * SCT: yes
80*/
81#define HW_APBX_CTRL1 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x0))
82#define HW_APBX_CTRL1_SET (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x4))
83#define HW_APBX_CTRL1_CLR (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x8))
84#define HW_APBX_CTRL1_TOG (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0xc))
85#define BP_APBX_CTRL1_CH_AHB_ERROR_IRQ 16
86#define BM_APBX_CTRL1_CH_AHB_ERROR_IRQ 0xff0000
87#define BF_APBX_CTRL1_CH_AHB_ERROR_IRQ(v) (((v) << 16) & 0xff0000)
88#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN 8
89#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN 0xff00
90#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 8) & 0xff00)
91#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ 0
92#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ 0xff
93#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v) (((v) << 0) & 0xff)
94
95/**
96 * Register: HW_APBX_DEVSEL
97 * Address: 0x20
98 * SCT: no
99*/
100#define HW_APBX_DEVSEL (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20))
101#define BP_APBX_DEVSEL_CH7 28
102#define BM_APBX_DEVSEL_CH7 0xf0000000
103#define BV_APBX_DEVSEL_CH7__USE_UART 0x0
104#define BV_APBX_DEVSEL_CH7__USE_IRDA 0x1
105#define BF_APBX_DEVSEL_CH7(v) (((v) << 28) & 0xf0000000)
106#define BF_APBX_DEVSEL_CH7_V(v) ((BV_APBX_DEVSEL_CH7__##v << 28) & 0xf0000000)
107#define BP_APBX_DEVSEL_CH6 24
108#define BM_APBX_DEVSEL_CH6 0xf000000
109#define BV_APBX_DEVSEL_CH6__USE_UART 0x0
110#define BV_APBX_DEVSEL_CH6__USE_IRDA 0x1
111#define BF_APBX_DEVSEL_CH6(v) (((v) << 24) & 0xf000000)
112#define BF_APBX_DEVSEL_CH6_V(v) ((BV_APBX_DEVSEL_CH6__##v << 24) & 0xf000000)
113#define BP_APBX_DEVSEL_CH5 20
114#define BM_APBX_DEVSEL_CH5 0xf00000
115#define BF_APBX_DEVSEL_CH5(v) (((v) << 20) & 0xf00000)
116#define BP_APBX_DEVSEL_CH4 16
117#define BM_APBX_DEVSEL_CH4 0xf0000
118#define BF_APBX_DEVSEL_CH4(v) (((v) << 16) & 0xf0000)
119#define BP_APBX_DEVSEL_CH3 12
120#define BM_APBX_DEVSEL_CH3 0xf000
121#define BF_APBX_DEVSEL_CH3(v) (((v) << 12) & 0xf000)
122#define BP_APBX_DEVSEL_CH2 8
123#define BM_APBX_DEVSEL_CH2 0xf00
124#define BV_APBX_DEVSEL_CH2__USE_SPDIF 0x0
125#define BV_APBX_DEVSEL_CH2__USE_SAIF2 0x1
126#define BF_APBX_DEVSEL_CH2(v) (((v) << 8) & 0xf00)
127#define BF_APBX_DEVSEL_CH2_V(v) ((BV_APBX_DEVSEL_CH2__##v << 8) & 0xf00)
128#define BP_APBX_DEVSEL_CH1 4
129#define BM_APBX_DEVSEL_CH1 0xf0
130#define BF_APBX_DEVSEL_CH1(v) (((v) << 4) & 0xf0)
131#define BP_APBX_DEVSEL_CH0 0
132#define BM_APBX_DEVSEL_CH0 0xf
133#define BF_APBX_DEVSEL_CH0(v) (((v) << 0) & 0xf)
134
135/**
136 * Register: HW_APBX_CHn_CURCMDAR
137 * Address: 0x40+n*0x70
138 * SCT: no
139*/
140#define HW_APBX_CHn_CURCMDAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x40+(n)*0x70))
141#define BP_APBX_CHn_CURCMDAR_CMD_ADDR 0
142#define BM_APBX_CHn_CURCMDAR_CMD_ADDR 0xffffffff
143#define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff)
144
145/**
146 * Register: HW_APBX_CHn_NXTCMDAR
147 * Address: 0x50+n*0x70
148 * SCT: no
149*/
150#define HW_APBX_CHn_NXTCMDAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x50+(n)*0x70))
151#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0
152#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xffffffff
153#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff)
154
155/**
156 * Register: HW_APBX_CHn_CMD
157 * Address: 0x60+n*0x70
158 * SCT: no
159*/
160#define HW_APBX_CHn_CMD(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x60+(n)*0x70))
161#define BP_APBX_CHn_CMD_XFER_COUNT 16
162#define BM_APBX_CHn_CMD_XFER_COUNT 0xffff0000
163#define BF_APBX_CHn_CMD_XFER_COUNT(v) (((v) << 16) & 0xffff0000)
164#define BP_APBX_CHn_CMD_CMDWORDS 12
165#define BM_APBX_CHn_CMD_CMDWORDS 0xf000
166#define BF_APBX_CHn_CMD_CMDWORDS(v) (((v) << 12) & 0xf000)
167#define BP_APBX_CHn_CMD_WAIT4ENDCMD 7
168#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x80
169#define BF_APBX_CHn_CMD_WAIT4ENDCMD(v) (((v) << 7) & 0x80)
170#define BP_APBX_CHn_CMD_SEMAPHORE 6
171#define BM_APBX_CHn_CMD_SEMAPHORE 0x40
172#define BF_APBX_CHn_CMD_SEMAPHORE(v) (((v) << 6) & 0x40)
173#define BP_APBX_CHn_CMD_IRQONCMPLT 3
174#define BM_APBX_CHn_CMD_IRQONCMPLT 0x8
175#define BF_APBX_CHn_CMD_IRQONCMPLT(v) (((v) << 3) & 0x8)
176#define BP_APBX_CHn_CMD_CHAIN 2
177#define BM_APBX_CHn_CMD_CHAIN 0x4
178#define BF_APBX_CHn_CMD_CHAIN(v) (((v) << 2) & 0x4)
179#define BP_APBX_CHn_CMD_COMMAND 0
180#define BM_APBX_CHn_CMD_COMMAND 0x3
181#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
182#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1
183#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2
184#define BF_APBX_CHn_CMD_COMMAND(v) (((v) << 0) & 0x3)
185#define BF_APBX_CHn_CMD_COMMAND_V(v) ((BV_APBX_CHn_CMD_COMMAND__##v << 0) & 0x3)
186
187/**
188 * Register: HW_APBX_CHn_BAR
189 * Address: 0x70+n*0x70
190 * SCT: no
191*/
192#define HW_APBX_CHn_BAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x70+(n)*0x70))
193#define BP_APBX_CHn_BAR_ADDRESS 0
194#define BM_APBX_CHn_BAR_ADDRESS 0xffffffff
195#define BF_APBX_CHn_BAR_ADDRESS(v) (((v) << 0) & 0xffffffff)
196
197/**
198 * Register: HW_APBX_CHn_SEMA
199 * Address: 0x80+n*0x70
200 * SCT: no
201*/
202#define HW_APBX_CHn_SEMA(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x80+(n)*0x70))
203#define BP_APBX_CHn_SEMA_PHORE 16
204#define BM_APBX_CHn_SEMA_PHORE 0xff0000
205#define BF_APBX_CHn_SEMA_PHORE(v) (((v) << 16) & 0xff0000)
206#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
207#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0xff
208#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) (((v) << 0) & 0xff)
209
210/**
211 * Register: HW_APBX_CHn_DEBUG1
212 * Address: 0x90+n*0x70
213 * SCT: no
214*/
215#define HW_APBX_CHn_DEBUG1(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x90+(n)*0x70))
216#define BP_APBX_CHn_DEBUG1_REQ 31
217#define BM_APBX_CHn_DEBUG1_REQ 0x80000000
218#define BF_APBX_CHn_DEBUG1_REQ(v) (((v) << 31) & 0x80000000)
219#define BP_APBX_CHn_DEBUG1_BURST 30
220#define BM_APBX_CHn_DEBUG1_BURST 0x40000000
221#define BF_APBX_CHn_DEBUG1_BURST(v) (((v) << 30) & 0x40000000)
222#define BP_APBX_CHn_DEBUG1_KICK 29
223#define BM_APBX_CHn_DEBUG1_KICK 0x20000000
224#define BF_APBX_CHn_DEBUG1_KICK(v) (((v) << 29) & 0x20000000)
225#define BP_APBX_CHn_DEBUG1_END 28
226#define BM_APBX_CHn_DEBUG1_END 0x10000000
227#define BF_APBX_CHn_DEBUG1_END(v) (((v) << 28) & 0x10000000)
228#define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 24
229#define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 0x1000000
230#define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v) (((v) << 24) & 0x1000000)
231#define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 23
232#define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 0x800000
233#define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v) (((v) << 23) & 0x800000)
234#define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL 22
235#define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL 0x400000
236#define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v) (((v) << 22) & 0x400000)
237#define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 21
238#define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 0x200000
239#define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v) (((v) << 21) & 0x200000)
240#define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL 20
241#define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL 0x100000
242#define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v) (((v) << 20) & 0x100000)
243#define BP_APBX_CHn_DEBUG1_STATEMACHINE 0
244#define BM_APBX_CHn_DEBUG1_STATEMACHINE 0x1f
245#define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE 0x0
246#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x1
247#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x2
248#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x3
249#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x4
250#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x5
251#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x6
252#define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x7
253#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x8
254#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x9
255#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE 0xc
256#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ 0xd
257#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0xe
258#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0xf
259#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15
260#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1c
261#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1e
262#define BF_APBX_CHn_DEBUG1_STATEMACHINE(v) (((v) << 0) & 0x1f)
263#define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(v) ((BV_APBX_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f)
264
265/**
266 * Register: HW_APBX_CHn_DEBUG2
267 * Address: 0xa0+n*0x70
268 * SCT: no
269*/
270#define HW_APBX_CHn_DEBUG2(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0xa0+(n)*0x70))
271#define BP_APBX_CHn_DEBUG2_APB_BYTES 16
272#define BM_APBX_CHn_DEBUG2_APB_BYTES 0xffff0000
273#define BF_APBX_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000)
274#define BP_APBX_CHn_DEBUG2_AHB_BYTES 0
275#define BM_APBX_CHn_DEBUG2_AHB_BYTES 0xffff
276#define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff)
277
278/**
279 * Register: HW_APBX_VERSION
280 * Address: 0x3f0
281 * SCT: no
282*/
283#define HW_APBX_VERSION (*(volatile unsigned long *)(REGS_APBX_BASE + 0x3f0))
284#define BP_APBX_VERSION_MAJOR 24
285#define BM_APBX_VERSION_MAJOR 0xff000000
286#define BF_APBX_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
287#define BP_APBX_VERSION_MINOR 16
288#define BM_APBX_VERSION_MINOR 0xff0000
289#define BF_APBX_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
290#define BP_APBX_VERSION_STEP 0
291#define BM_APBX_VERSION_STEP 0xffff
292#define BF_APBX_VERSION_STEP(v) (((v) << 0) & 0xffff)
293
294#endif /* __HEADERGEN__STMP3700__APBX__H__ */