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author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-13 19:03:33 +0200 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-15 22:27:34 +0200 |
commit | 017667c2dc9843eb5082e991f421c773636dcf36 (patch) | |
tree | 60432008dd3bc012ac60cbfa771305f6d894dd84 /firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h | |
parent | 97b9ade63945fd8b8261fb0cf1dd0aa225c1a319 (diff) | |
download | rockbox-017667c2dc9843eb5082e991f421c773636dcf36.tar.gz rockbox-017667c2dc9843eb5082e991f421c773636dcf36.zip |
imx233: generate register headers for stmp3600, stmp3700 and imx233
Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h | 223 |
1 files changed, 223 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h new file mode 100644 index 0000000000..b6e5ead2ba --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h | |||
@@ -0,0 +1,223 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__HWECC__H__ | ||
24 | #define __HEADERGEN__STMP3600__HWECC__H__ | ||
25 | |||
26 | #define REGS_HWECC_BASE (0x80008000) | ||
27 | |||
28 | #define REGS_HWECC_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_HWECC_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_HWECC_CTRL (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x0)) | ||
36 | #define HW_HWECC_CTRL_SET (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x4)) | ||
37 | #define HW_HWECC_CTRL_CLR (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x8)) | ||
38 | #define HW_HWECC_CTRL_TOG (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0xc)) | ||
39 | #define BP_HWECC_CTRL_SFTRST 31 | ||
40 | #define BM_HWECC_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_HWECC_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_HWECC_CTRL_CLKGATE 30 | ||
43 | #define BM_HWECC_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_HWECC_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_HWECC_CTRL_NUM_SYMBOLS 16 | ||
46 | #define BM_HWECC_CTRL_NUM_SYMBOLS 0x1ff0000 | ||
47 | #define BF_HWECC_CTRL_NUM_SYMBOLS(v) (((v) << 16) & 0x1ff0000) | ||
48 | #define BP_HWECC_CTRL_DMAWAIT_COUNT 8 | ||
49 | #define BM_HWECC_CTRL_DMAWAIT_COUNT 0x1f00 | ||
50 | #define BF_HWECC_CTRL_DMAWAIT_COUNT(v) (((v) << 8) & 0x1f00) | ||
51 | #define BP_HWECC_CTRL_BYTE_ENABLE 6 | ||
52 | #define BM_HWECC_CTRL_BYTE_ENABLE 0x40 | ||
53 | #define BF_HWECC_CTRL_BYTE_ENABLE(v) (((v) << 6) & 0x40) | ||
54 | #define BP_HWECC_CTRL_ECC_SEL 5 | ||
55 | #define BM_HWECC_CTRL_ECC_SEL 0x20 | ||
56 | #define BF_HWECC_CTRL_ECC_SEL(v) (((v) << 5) & 0x20) | ||
57 | #define BP_HWECC_CTRL_ENC_SEL 4 | ||
58 | #define BM_HWECC_CTRL_ENC_SEL 0x10 | ||
59 | #define BF_HWECC_CTRL_ENC_SEL(v) (((v) << 4) & 0x10) | ||
60 | #define BP_HWECC_CTRL_UNCORR_IRQ 2 | ||
61 | #define BM_HWECC_CTRL_UNCORR_IRQ 0x4 | ||
62 | #define BF_HWECC_CTRL_UNCORR_IRQ(v) (((v) << 2) & 0x4) | ||
63 | #define BP_HWECC_CTRL_UNCORR_IRQ_EN 1 | ||
64 | #define BM_HWECC_CTRL_UNCORR_IRQ_EN 0x2 | ||
65 | #define BF_HWECC_CTRL_UNCORR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
66 | #define BP_HWECC_CTRL_RUN 0 | ||
67 | #define BM_HWECC_CTRL_RUN 0x1 | ||
68 | #define BF_HWECC_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
69 | |||
70 | /** | ||
71 | * Register: HW_HWECC_STAT | ||
72 | * Address: 0x10 | ||
73 | * SCT: no | ||
74 | */ | ||
75 | #define HW_HWECC_STAT (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x10)) | ||
76 | #define BP_HWECC_STAT_RSDEC_PRESENT 31 | ||
77 | #define BM_HWECC_STAT_RSDEC_PRESENT 0x80000000 | ||
78 | #define BF_HWECC_STAT_RSDEC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
79 | #define BP_HWECC_STAT_RSENC_PRESENT 30 | ||
80 | #define BM_HWECC_STAT_RSENC_PRESENT 0x40000000 | ||
81 | #define BF_HWECC_STAT_RSENC_PRESENT(v) (((v) << 30) & 0x40000000) | ||
82 | #define BP_HWECC_STAT_SSDEC_PRESENT 29 | ||
83 | #define BM_HWECC_STAT_SSDEC_PRESENT 0x20000000 | ||
84 | #define BF_HWECC_STAT_SSDEC_PRESENT(v) (((v) << 29) & 0x20000000) | ||
85 | #define BP_HWECC_STAT_SSENC_PRESENT 28 | ||
86 | #define BM_HWECC_STAT_SSENC_PRESENT 0x10000000 | ||
87 | #define BF_HWECC_STAT_SSENC_PRESENT(v) (((v) << 28) & 0x10000000) | ||
88 | |||
89 | /** | ||
90 | * Register: HW_HWECC_DEBUG0 | ||
91 | * Address: 0x20 | ||
92 | * SCT: no | ||
93 | */ | ||
94 | #define HW_HWECC_DEBUG0 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x20)) | ||
95 | #define BP_HWECC_DEBUG0_DMA_PENDCMD 29 | ||
96 | #define BM_HWECC_DEBUG0_DMA_PENDCMD 0x20000000 | ||
97 | #define BF_HWECC_DEBUG0_DMA_PENDCMD(v) (((v) << 29) & 0x20000000) | ||
98 | #define BP_HWECC_DEBUG0_DMA_PREQ 28 | ||
99 | #define BM_HWECC_DEBUG0_DMA_PREQ 0x10000000 | ||
100 | #define BF_HWECC_DEBUG0_DMA_PREQ(v) (((v) << 28) & 0x10000000) | ||
101 | #define BP_HWECC_DEBUG0_SYMBOL_STATE 24 | ||
102 | #define BM_HWECC_DEBUG0_SYMBOL_STATE 0xf000000 | ||
103 | #define BF_HWECC_DEBUG0_SYMBOL_STATE(v) (((v) << 24) & 0xf000000) | ||
104 | #define BP_HWECC_DEBUG0_CTRL_STATE 16 | ||
105 | #define BM_HWECC_DEBUG0_CTRL_STATE 0x3f0000 | ||
106 | #define BF_HWECC_DEBUG0_CTRL_STATE(v) (((v) << 16) & 0x3f0000) | ||
107 | #define BP_HWECC_DEBUG0_ECC_EXCEPTION 12 | ||
108 | #define BM_HWECC_DEBUG0_ECC_EXCEPTION 0xf000 | ||
109 | #define BF_HWECC_DEBUG0_ECC_EXCEPTION(v) (((v) << 12) & 0xf000) | ||
110 | #define BP_HWECC_DEBUG0_NUM_BIT_ERRORS 4 | ||
111 | #define BM_HWECC_DEBUG0_NUM_BIT_ERRORS 0x3f0 | ||
112 | #define BF_HWECC_DEBUG0_NUM_BIT_ERRORS(v) (((v) << 4) & 0x3f0) | ||
113 | #define BP_HWECC_DEBUG0_NUM_SYMBOL_ERRORS 0 | ||
114 | #define BM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS 0x7 | ||
115 | #define BF_HWECC_DEBUG0_NUM_SYMBOL_ERRORS(v) (((v) << 0) & 0x7) | ||
116 | |||
117 | /** | ||
118 | * Register: HW_HWECC_DEBUG1 | ||
119 | * Address: 0x30 | ||
120 | * SCT: no | ||
121 | */ | ||
122 | #define HW_HWECC_DEBUG1 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x30)) | ||
123 | #define BP_HWECC_DEBUG1_SYNDROME2 18 | ||
124 | #define BM_HWECC_DEBUG1_SYNDROME2 0x7fc0000 | ||
125 | #define BF_HWECC_DEBUG1_SYNDROME2(v) (((v) << 18) & 0x7fc0000) | ||
126 | #define BP_HWECC_DEBUG1_SYNDROME1 9 | ||
127 | #define BM_HWECC_DEBUG1_SYNDROME1 0x3fe00 | ||
128 | #define BF_HWECC_DEBUG1_SYNDROME1(v) (((v) << 9) & 0x3fe00) | ||
129 | #define BP_HWECC_DEBUG1_SYNDROME0 0 | ||
130 | #define BM_HWECC_DEBUG1_SYNDROME0 0x1ff | ||
131 | #define BF_HWECC_DEBUG1_SYNDROME0(v) (((v) << 0) & 0x1ff) | ||
132 | |||
133 | /** | ||
134 | * Register: HW_HWECC_DEBUG2 | ||
135 | * Address: 0x40 | ||
136 | * SCT: no | ||
137 | */ | ||
138 | #define HW_HWECC_DEBUG2 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x40)) | ||
139 | #define BP_HWECC_DEBUG2_SYNDROME5 18 | ||
140 | #define BM_HWECC_DEBUG2_SYNDROME5 0x7fc0000 | ||
141 | #define BF_HWECC_DEBUG2_SYNDROME5(v) (((v) << 18) & 0x7fc0000) | ||
142 | #define BP_HWECC_DEBUG2_SYNDROME4 9 | ||
143 | #define BM_HWECC_DEBUG2_SYNDROME4 0x3fe00 | ||
144 | #define BF_HWECC_DEBUG2_SYNDROME4(v) (((v) << 9) & 0x3fe00) | ||
145 | #define BP_HWECC_DEBUG2_SYNDROME3 0 | ||
146 | #define BM_HWECC_DEBUG2_SYNDROME3 0x1ff | ||
147 | #define BF_HWECC_DEBUG2_SYNDROME3(v) (((v) << 0) & 0x1ff) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_HWECC_DEBUG3 | ||
151 | * Address: 0x50 | ||
152 | * SCT: no | ||
153 | */ | ||
154 | #define HW_HWECC_DEBUG3 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x50)) | ||
155 | #define BP_HWECC_DEBUG3_OMEGA0 18 | ||
156 | #define BM_HWECC_DEBUG3_OMEGA0 0x7fc0000 | ||
157 | #define BF_HWECC_DEBUG3_OMEGA0(v) (((v) << 18) & 0x7fc0000) | ||
158 | #define BP_HWECC_DEBUG3_SYNDROME7 9 | ||
159 | #define BM_HWECC_DEBUG3_SYNDROME7 0x3fe00 | ||
160 | #define BF_HWECC_DEBUG3_SYNDROME7(v) (((v) << 9) & 0x3fe00) | ||
161 | #define BP_HWECC_DEBUG3_SYNDROME6 0 | ||
162 | #define BM_HWECC_DEBUG3_SYNDROME6 0x1ff | ||
163 | #define BF_HWECC_DEBUG3_SYNDROME6(v) (((v) << 0) & 0x1ff) | ||
164 | |||
165 | /** | ||
166 | * Register: HW_HWECC_DEBUG4 | ||
167 | * Address: 0x60 | ||
168 | * SCT: no | ||
169 | */ | ||
170 | #define HW_HWECC_DEBUG4 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x60)) | ||
171 | #define BP_HWECC_DEBUG4_OMEGA3 18 | ||
172 | #define BM_HWECC_DEBUG4_OMEGA3 0x7fc0000 | ||
173 | #define BF_HWECC_DEBUG4_OMEGA3(v) (((v) << 18) & 0x7fc0000) | ||
174 | #define BP_HWECC_DEBUG4_OMEGA2 9 | ||
175 | #define BM_HWECC_DEBUG4_OMEGA2 0x3fe00 | ||
176 | #define BF_HWECC_DEBUG4_OMEGA2(v) (((v) << 9) & 0x3fe00) | ||
177 | #define BP_HWECC_DEBUG4_OMEGA1 0 | ||
178 | #define BM_HWECC_DEBUG4_OMEGA1 0x1ff | ||
179 | #define BF_HWECC_DEBUG4_OMEGA1(v) (((v) << 0) & 0x1ff) | ||
180 | |||
181 | /** | ||
182 | * Register: HW_HWECC_DEBUG5 | ||
183 | * Address: 0x70 | ||
184 | * SCT: no | ||
185 | */ | ||
186 | #define HW_HWECC_DEBUG5 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x70)) | ||
187 | #define BP_HWECC_DEBUG5_LAMBDA2 18 | ||
188 | #define BM_HWECC_DEBUG5_LAMBDA2 0x7fc0000 | ||
189 | #define BF_HWECC_DEBUG5_LAMBDA2(v) (((v) << 18) & 0x7fc0000) | ||
190 | #define BP_HWECC_DEBUG5_LAMBDA1 9 | ||
191 | #define BM_HWECC_DEBUG5_LAMBDA1 0x3fe00 | ||
192 | #define BF_HWECC_DEBUG5_LAMBDA1(v) (((v) << 9) & 0x3fe00) | ||
193 | #define BP_HWECC_DEBUG5_LAMBDA0 0 | ||
194 | #define BM_HWECC_DEBUG5_LAMBDA0 0x1ff | ||
195 | #define BF_HWECC_DEBUG5_LAMBDA0(v) (((v) << 0) & 0x1ff) | ||
196 | |||
197 | /** | ||
198 | * Register: HW_HWECC_DEBUG6 | ||
199 | * Address: 0x80 | ||
200 | * SCT: no | ||
201 | */ | ||
202 | #define HW_HWECC_DEBUG6 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x80)) | ||
203 | #define BP_HWECC_DEBUG6_LAMBDA4 9 | ||
204 | #define BM_HWECC_DEBUG6_LAMBDA4 0x3fe00 | ||
205 | #define BF_HWECC_DEBUG6_LAMBDA4(v) (((v) << 9) & 0x3fe00) | ||
206 | #define BP_HWECC_DEBUG6_LAMBDA3 0 | ||
207 | #define BM_HWECC_DEBUG6_LAMBDA3 0x1ff | ||
208 | #define BF_HWECC_DEBUG6_LAMBDA3(v) (((v) << 0) & 0x1ff) | ||
209 | |||
210 | /** | ||
211 | * Register: HW_HWECC_DATA | ||
212 | * Address: 0x90 | ||
213 | * SCT: yes | ||
214 | */ | ||
215 | #define HW_HWECC_DATA (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x0)) | ||
216 | #define HW_HWECC_DATA_SET (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x4)) | ||
217 | #define HW_HWECC_DATA_CLR (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x8)) | ||
218 | #define HW_HWECC_DATA_TOG (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0xc)) | ||
219 | #define BP_HWECC_DATA_DATA 0 | ||
220 | #define BM_HWECC_DATA_DATA 0xffffffff | ||
221 | #define BF_HWECC_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
222 | |||
223 | #endif /* __HEADERGEN__STMP3600__HWECC__H__ */ | ||