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author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-13 19:03:33 +0200 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-15 22:27:34 +0200 |
commit | 017667c2dc9843eb5082e991f421c773636dcf36 (patch) | |
tree | 60432008dd3bc012ac60cbfa771305f6d894dd84 /firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h | |
parent | 97b9ade63945fd8b8261fb0cf1dd0aa225c1a319 (diff) | |
download | rockbox-017667c2dc9843eb5082e991f421c773636dcf36.tar.gz rockbox-017667c2dc9843eb5082e991f421c773636dcf36.zip |
imx233: generate register headers for stmp3600, stmp3700 and imx233
Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h | 595 |
1 files changed, 595 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h new file mode 100644 index 0000000000..a7b45a7ca9 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h | |||
@@ -0,0 +1,595 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__DIGCTL__H__ | ||
24 | #define __HEADERGEN__STMP3600__DIGCTL__H__ | ||
25 | |||
26 | #define REGS_DIGCTL_BASE (0x8001c000) | ||
27 | |||
28 | #define REGS_DIGCTL_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DIGCTL_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_DIGCTL_CTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_DIGCTL_CTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_DIGCTL_CTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_DIGCTL_CTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_DIGCTL_CTRL_MASTER_SELECT 24 | ||
40 | #define BM_DIGCTL_CTRL_MASTER_SELECT 0x1f000000 | ||
41 | #define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_I 0x1 | ||
42 | #define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_D 0x2 | ||
43 | #define BV_DIGCTL_CTRL_MASTER_SELECT__USB 0x4 | ||
44 | #define BV_DIGCTL_CTRL_MASTER_SELECT__APBH 0x8 | ||
45 | #define BV_DIGCTL_CTRL_MASTER_SELECT__APBX 0x10 | ||
46 | #define BF_DIGCTL_CTRL_MASTER_SELECT(v) (((v) << 24) & 0x1f000000) | ||
47 | #define BF_DIGCTL_CTRL_MASTER_SELECT_V(v) ((BV_DIGCTL_CTRL_MASTER_SELECT__##v << 24) & 0x1f000000) | ||
48 | #define BP_DIGCTL_CTRL_USB_TESTMODE 20 | ||
49 | #define BM_DIGCTL_CTRL_USB_TESTMODE 0x100000 | ||
50 | #define BF_DIGCTL_CTRL_USB_TESTMODE(v) (((v) << 20) & 0x100000) | ||
51 | #define BP_DIGCTL_CTRL_ANALOG_TESTMODE 19 | ||
52 | #define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x80000 | ||
53 | #define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v) (((v) << 19) & 0x80000) | ||
54 | #define BP_DIGCTL_CTRL_DIGITAL_TESTMODE 18 | ||
55 | #define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x40000 | ||
56 | #define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v) (((v) << 18) & 0x40000) | ||
57 | #define BP_DIGCTL_CTRL_UTMI_TESTMODE 17 | ||
58 | #define BM_DIGCTL_CTRL_UTMI_TESTMODE 0x20000 | ||
59 | #define BF_DIGCTL_CTRL_UTMI_TESTMODE(v) (((v) << 17) & 0x20000) | ||
60 | #define BP_DIGCTL_CTRL_UART_LOOPBACK 16 | ||
61 | #define BM_DIGCTL_CTRL_UART_LOOPBACK 0x10000 | ||
62 | #define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0 | ||
63 | #define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1 | ||
64 | #define BF_DIGCTL_CTRL_UART_LOOPBACK(v) (((v) << 16) & 0x10000) | ||
65 | #define BF_DIGCTL_CTRL_UART_LOOPBACK_V(v) ((BV_DIGCTL_CTRL_UART_LOOPBACK__##v << 16) & 0x10000) | ||
66 | #define BP_DIGCTL_CTRL_DEBUG_DISABLE 3 | ||
67 | #define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x8 | ||
68 | #define BF_DIGCTL_CTRL_DEBUG_DISABLE(v) (((v) << 3) & 0x8) | ||
69 | #define BP_DIGCTL_CTRL_USB_CLKGATE 2 | ||
70 | #define BM_DIGCTL_CTRL_USB_CLKGATE 0x4 | ||
71 | #define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0 | ||
72 | #define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1 | ||
73 | #define BF_DIGCTL_CTRL_USB_CLKGATE(v) (((v) << 2) & 0x4) | ||
74 | #define BF_DIGCTL_CTRL_USB_CLKGATE_V(v) ((BV_DIGCTL_CTRL_USB_CLKGATE__##v << 2) & 0x4) | ||
75 | #define BP_DIGCTL_CTRL_JTAG_SHIELD 1 | ||
76 | #define BM_DIGCTL_CTRL_JTAG_SHIELD 0x2 | ||
77 | #define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 | ||
78 | #define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 | ||
79 | #define BF_DIGCTL_CTRL_JTAG_SHIELD(v) (((v) << 1) & 0x2) | ||
80 | #define BF_DIGCTL_CTRL_JTAG_SHIELD_V(v) ((BV_DIGCTL_CTRL_JTAG_SHIELD__##v << 1) & 0x2) | ||
81 | #define BP_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE 0 | ||
82 | #define BM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE 0x1 | ||
83 | #define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__DISABLE 0x0 | ||
84 | #define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__ENABLE 0x1 | ||
85 | #define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE(v) (((v) << 0) & 0x1) | ||
86 | #define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE_V(v) ((BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__##v << 0) & 0x1) | ||
87 | |||
88 | /** | ||
89 | * Register: HW_DIGCTL_STATUS | ||
90 | * Address: 0x10 | ||
91 | * SCT: no | ||
92 | */ | ||
93 | #define HW_DIGCTL_STATUS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10)) | ||
94 | #define BP_DIGCTL_STATUS_ROM_KEYS_PRESENT 31 | ||
95 | #define BM_DIGCTL_STATUS_ROM_KEYS_PRESENT 0x80000000 | ||
96 | #define BF_DIGCTL_STATUS_ROM_KEYS_PRESENT(v) (((v) << 31) & 0x80000000) | ||
97 | #define BP_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT 6 | ||
98 | #define BM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT 0x40 | ||
99 | #define BF_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT(v) (((v) << 6) & 0x40) | ||
100 | #define BP_DIGCTL_STATUS_ROM_SHIELDED 5 | ||
101 | #define BM_DIGCTL_STATUS_ROM_SHIELDED 0x20 | ||
102 | #define BF_DIGCTL_STATUS_ROM_SHIELDED(v) (((v) << 5) & 0x20) | ||
103 | #define BP_DIGCTL_STATUS_JTAG_IN_USE 4 | ||
104 | #define BM_DIGCTL_STATUS_JTAG_IN_USE 0x10 | ||
105 | #define BF_DIGCTL_STATUS_JTAG_IN_USE(v) (((v) << 4) & 0x10) | ||
106 | #define BP_DIGCTL_STATUS_PSWITCH 2 | ||
107 | #define BM_DIGCTL_STATUS_PSWITCH 0xc | ||
108 | #define BF_DIGCTL_STATUS_PSWITCH(v) (((v) << 2) & 0xc) | ||
109 | #define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 | ||
110 | #define BM_DIGCTL_STATUS_PACKAGE_TYPE 0x2 | ||
111 | #define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) (((v) << 1) & 0x2) | ||
112 | #define BP_DIGCTL_STATUS_WRITTEN 0 | ||
113 | #define BM_DIGCTL_STATUS_WRITTEN 0x1 | ||
114 | #define BF_DIGCTL_STATUS_WRITTEN(v) (((v) << 0) & 0x1) | ||
115 | |||
116 | /** | ||
117 | * Register: HW_DIGCTL_HCLKCOUNT | ||
118 | * Address: 0x20 | ||
119 | * SCT: no | ||
120 | */ | ||
121 | #define HW_DIGCTL_HCLKCOUNT (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20)) | ||
122 | #define BP_DIGCTL_HCLKCOUNT_COUNT 0 | ||
123 | #define BM_DIGCTL_HCLKCOUNT_COUNT 0xffffffff | ||
124 | #define BF_DIGCTL_HCLKCOUNT_COUNT(v) (((v) << 0) & 0xffffffff) | ||
125 | |||
126 | /** | ||
127 | * Register: HW_DIGCTL_RAMCTRL | ||
128 | * Address: 0x30 | ||
129 | * SCT: yes | ||
130 | */ | ||
131 | #define HW_DIGCTL_RAMCTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x0)) | ||
132 | #define HW_DIGCTL_RAMCTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x4)) | ||
133 | #define HW_DIGCTL_RAMCTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x8)) | ||
134 | #define HW_DIGCTL_RAMCTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0xc)) | ||
135 | #define BP_DIGCTL_RAMCTRL_TEST_MARGIN 28 | ||
136 | #define BM_DIGCTL_RAMCTRL_TEST_MARGIN 0x70000000 | ||
137 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__NORMAL 0x0 | ||
138 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL1 0x1 | ||
139 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL2 0x2 | ||
140 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL3 0x3 | ||
141 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL4 0x4 | ||
142 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL5 0x5 | ||
143 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL6 0x6 | ||
144 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL7 0x7 | ||
145 | #define BF_DIGCTL_RAMCTRL_TEST_MARGIN(v) (((v) << 28) & 0x70000000) | ||
146 | #define BF_DIGCTL_RAMCTRL_TEST_MARGIN_V(v) ((BV_DIGCTL_RAMCTRL_TEST_MARGIN__##v << 28) & 0x70000000) | ||
147 | #define BP_DIGCTL_RAMCTRL_PWDN_BANKS 24 | ||
148 | #define BM_DIGCTL_RAMCTRL_PWDN_BANKS 0xf000000 | ||
149 | #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK3 0x8 | ||
150 | #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK2 0x4 | ||
151 | #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK1 0x2 | ||
152 | #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK0 0x1 | ||
153 | #define BF_DIGCTL_RAMCTRL_PWDN_BANKS(v) (((v) << 24) & 0xf000000) | ||
154 | #define BF_DIGCTL_RAMCTRL_PWDN_BANKS_V(v) ((BV_DIGCTL_RAMCTRL_PWDN_BANKS__##v << 24) & 0xf000000) | ||
155 | #define BP_DIGCTL_RAMCTRL_TEMP_SENSOR 20 | ||
156 | #define BM_DIGCTL_RAMCTRL_TEMP_SENSOR 0x700000 | ||
157 | #define BF_DIGCTL_RAMCTRL_TEMP_SENSOR(v) (((v) << 20) & 0x700000) | ||
158 | #define BP_DIGCTL_RAMCTRL_TEST_TEMP_COMP 16 | ||
159 | #define BM_DIGCTL_RAMCTRL_TEST_TEMP_COMP 0x70000 | ||
160 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__LOW_TEMP 0x1 | ||
161 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_A 0x2 | ||
162 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_B 0x3 | ||
163 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_C 0x4 | ||
164 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_D 0x5 | ||
165 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_E 0x6 | ||
166 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_F 0x7 | ||
167 | #define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP(v) (((v) << 16) & 0x70000) | ||
168 | #define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP_V(v) ((BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__##v << 16) & 0x70000) | ||
169 | #define BP_DIGCTL_RAMCTRL_SHIFT_COUNT 8 | ||
170 | #define BM_DIGCTL_RAMCTRL_SHIFT_COUNT 0x7f00 | ||
171 | #define BF_DIGCTL_RAMCTRL_SHIFT_COUNT(v) (((v) << 8) & 0x7f00) | ||
172 | #define BP_DIGCTL_RAMCTRL_FLIP_CLK 7 | ||
173 | #define BM_DIGCTL_RAMCTRL_FLIP_CLK 0x80 | ||
174 | #define BV_DIGCTL_RAMCTRL_FLIP_CLK__NORMAL 0x0 | ||
175 | #define BV_DIGCTL_RAMCTRL_FLIP_CLK__INVERT 0x1 | ||
176 | #define BF_DIGCTL_RAMCTRL_FLIP_CLK(v) (((v) << 7) & 0x80) | ||
177 | #define BF_DIGCTL_RAMCTRL_FLIP_CLK_V(v) ((BV_DIGCTL_RAMCTRL_FLIP_CLK__##v << 7) & 0x80) | ||
178 | #define BP_DIGCTL_RAMCTRL_OVER_RIDE_TEMP 3 | ||
179 | #define BM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP 0x8 | ||
180 | #define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__NORMAL 0x0 | ||
181 | #define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__OVER_RIDE 0x1 | ||
182 | #define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP(v) (((v) << 3) & 0x8) | ||
183 | #define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP_V(v) ((BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__##v << 3) & 0x8) | ||
184 | #define BP_DIGCTL_RAMCTRL_REF_CLK_GATE 2 | ||
185 | #define BM_DIGCTL_RAMCTRL_REF_CLK_GATE 0x4 | ||
186 | #define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__NORMAL 0x0 | ||
187 | #define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__OFF 0x1 | ||
188 | #define BF_DIGCTL_RAMCTRL_REF_CLK_GATE(v) (((v) << 2) & 0x4) | ||
189 | #define BF_DIGCTL_RAMCTRL_REF_CLK_GATE_V(v) ((BV_DIGCTL_RAMCTRL_REF_CLK_GATE__##v << 2) & 0x4) | ||
190 | #define BP_DIGCTL_RAMCTRL_REPAIR_STATUS 1 | ||
191 | #define BM_DIGCTL_RAMCTRL_REPAIR_STATUS 0x2 | ||
192 | #define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__IDLE 0x0 | ||
193 | #define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__BUSY 0x1 | ||
194 | #define BF_DIGCTL_RAMCTRL_REPAIR_STATUS(v) (((v) << 1) & 0x2) | ||
195 | #define BF_DIGCTL_RAMCTRL_REPAIR_STATUS_V(v) ((BV_DIGCTL_RAMCTRL_REPAIR_STATUS__##v << 1) & 0x2) | ||
196 | #define BP_DIGCTL_RAMCTRL_REPAIR_TRANSMIT 0 | ||
197 | #define BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT 0x1 | ||
198 | #define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__IDLE 0x0 | ||
199 | #define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__SEND 0x1 | ||
200 | #define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT(v) (((v) << 0) & 0x1) | ||
201 | #define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT_V(v) ((BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__##v << 0) & 0x1) | ||
202 | |||
203 | /** | ||
204 | * Register: HW_DIGCTL_RAMREPAIR0 | ||
205 | * Address: 0x40 | ||
206 | * SCT: yes | ||
207 | */ | ||
208 | #define HW_DIGCTL_RAMREPAIR0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x0)) | ||
209 | #define HW_DIGCTL_RAMREPAIR0_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x4)) | ||
210 | #define HW_DIGCTL_RAMREPAIR0_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x8)) | ||
211 | #define HW_DIGCTL_RAMREPAIR0_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0xc)) | ||
212 | #define BP_DIGCTL_RAMREPAIR0_EFUSE3 24 | ||
213 | #define BM_DIGCTL_RAMREPAIR0_EFUSE3 0x7f000000 | ||
214 | #define BF_DIGCTL_RAMREPAIR0_EFUSE3(v) (((v) << 24) & 0x7f000000) | ||
215 | #define BP_DIGCTL_RAMREPAIR0_EFUSE2 16 | ||
216 | #define BM_DIGCTL_RAMREPAIR0_EFUSE2 0x7f0000 | ||
217 | #define BF_DIGCTL_RAMREPAIR0_EFUSE2(v) (((v) << 16) & 0x7f0000) | ||
218 | #define BP_DIGCTL_RAMREPAIR0_EFUSE1 8 | ||
219 | #define BM_DIGCTL_RAMREPAIR0_EFUSE1 0x7f00 | ||
220 | #define BF_DIGCTL_RAMREPAIR0_EFUSE1(v) (((v) << 8) & 0x7f00) | ||
221 | #define BP_DIGCTL_RAMREPAIR0_EFUSE0 0 | ||
222 | #define BM_DIGCTL_RAMREPAIR0_EFUSE0 0x7f | ||
223 | #define BF_DIGCTL_RAMREPAIR0_EFUSE0(v) (((v) << 0) & 0x7f) | ||
224 | |||
225 | /** | ||
226 | * Register: HW_DIGCTL_RAMREPAIR1 | ||
227 | * Address: 0x50 | ||
228 | * SCT: yes | ||
229 | */ | ||
230 | #define HW_DIGCTL_RAMREPAIR1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x0)) | ||
231 | #define HW_DIGCTL_RAMREPAIR1_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x4)) | ||
232 | #define HW_DIGCTL_RAMREPAIR1_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x8)) | ||
233 | #define HW_DIGCTL_RAMREPAIR1_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0xc)) | ||
234 | #define BP_DIGCTL_RAMREPAIR1_EFUSE3 24 | ||
235 | #define BM_DIGCTL_RAMREPAIR1_EFUSE3 0x7f000000 | ||
236 | #define BF_DIGCTL_RAMREPAIR1_EFUSE3(v) (((v) << 24) & 0x7f000000) | ||
237 | #define BP_DIGCTL_RAMREPAIR1_EFUSE2 16 | ||
238 | #define BM_DIGCTL_RAMREPAIR1_EFUSE2 0x7f0000 | ||
239 | #define BF_DIGCTL_RAMREPAIR1_EFUSE2(v) (((v) << 16) & 0x7f0000) | ||
240 | #define BP_DIGCTL_RAMREPAIR1_EFUSE1 8 | ||
241 | #define BM_DIGCTL_RAMREPAIR1_EFUSE1 0x7f00 | ||
242 | #define BF_DIGCTL_RAMREPAIR1_EFUSE1(v) (((v) << 8) & 0x7f00) | ||
243 | #define BP_DIGCTL_RAMREPAIR1_EFUSE0 0 | ||
244 | #define BM_DIGCTL_RAMREPAIR1_EFUSE0 0x7f | ||
245 | #define BF_DIGCTL_RAMREPAIR1_EFUSE0(v) (((v) << 0) & 0x7f) | ||
246 | |||
247 | /** | ||
248 | * Register: HW_DIGCTL_WRITEONCE | ||
249 | * Address: 0x60 | ||
250 | * SCT: no | ||
251 | */ | ||
252 | #define HW_DIGCTL_WRITEONCE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x60)) | ||
253 | #define BP_DIGCTL_WRITEONCE_BITS 0 | ||
254 | #define BM_DIGCTL_WRITEONCE_BITS 0xffffffff | ||
255 | #define BF_DIGCTL_WRITEONCE_BITS(v) (((v) << 0) & 0xffffffff) | ||
256 | |||
257 | /** | ||
258 | * Register: HW_DIGCTL_AHBCYCLES | ||
259 | * Address: 0x70 | ||
260 | * SCT: no | ||
261 | */ | ||
262 | #define HW_DIGCTL_AHBCYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x70)) | ||
263 | #define BP_DIGCTL_AHBCYCLES_COUNT 0 | ||
264 | #define BM_DIGCTL_AHBCYCLES_COUNT 0xffffffff | ||
265 | #define BF_DIGCTL_AHBCYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
266 | |||
267 | /** | ||
268 | * Register: HW_DIGCTL_AHBSTALLED | ||
269 | * Address: 0x80 | ||
270 | * SCT: no | ||
271 | */ | ||
272 | #define HW_DIGCTL_AHBSTALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x80)) | ||
273 | #define BP_DIGCTL_AHBSTALLED_COUNT 0 | ||
274 | #define BM_DIGCTL_AHBSTALLED_COUNT 0xffffffff | ||
275 | #define BF_DIGCTL_AHBSTALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
276 | |||
277 | /** | ||
278 | * Register: HW_DIGCTL_ENTROPY | ||
279 | * Address: 0x90 | ||
280 | * SCT: no | ||
281 | */ | ||
282 | #define HW_DIGCTL_ENTROPY (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x90)) | ||
283 | #define BP_DIGCTL_ENTROPY_VALUE 0 | ||
284 | #define BM_DIGCTL_ENTROPY_VALUE 0xffffffff | ||
285 | #define BF_DIGCTL_ENTROPY_VALUE(v) (((v) << 0) & 0xffffffff) | ||
286 | |||
287 | /** | ||
288 | * Register: HW_DIGCTL_ROMSHIELD | ||
289 | * Address: 0xa0 | ||
290 | * SCT: no | ||
291 | */ | ||
292 | #define HW_DIGCTL_ROMSHIELD (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xa0)) | ||
293 | #define BP_DIGCTL_ROMSHIELD_WRITE_ONCE 0 | ||
294 | #define BM_DIGCTL_ROMSHIELD_WRITE_ONCE 0x1 | ||
295 | #define BF_DIGCTL_ROMSHIELD_WRITE_ONCE(v) (((v) << 0) & 0x1) | ||
296 | |||
297 | /** | ||
298 | * Register: HW_DIGCTL_MICROSECONDS | ||
299 | * Address: 0xb0 | ||
300 | * SCT: yes | ||
301 | */ | ||
302 | #define HW_DIGCTL_MICROSECONDS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x0)) | ||
303 | #define HW_DIGCTL_MICROSECONDS_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x4)) | ||
304 | #define HW_DIGCTL_MICROSECONDS_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x8)) | ||
305 | #define HW_DIGCTL_MICROSECONDS_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0xc)) | ||
306 | #define BP_DIGCTL_MICROSECONDS_VALUE 0 | ||
307 | #define BM_DIGCTL_MICROSECONDS_VALUE 0xffffffff | ||
308 | #define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) << 0) & 0xffffffff) | ||
309 | |||
310 | /** | ||
311 | * Register: HW_DIGCTL_DBGRD | ||
312 | * Address: 0xc0 | ||
313 | * SCT: no | ||
314 | */ | ||
315 | #define HW_DIGCTL_DBGRD (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0)) | ||
316 | #define BP_DIGCTL_DBGRD_COMPLEMENT 0 | ||
317 | #define BM_DIGCTL_DBGRD_COMPLEMENT 0xffffffff | ||
318 | #define BF_DIGCTL_DBGRD_COMPLEMENT(v) (((v) << 0) & 0xffffffff) | ||
319 | |||
320 | /** | ||
321 | * Register: HW_DIGCTL_DBG | ||
322 | * Address: 0xd0 | ||
323 | * SCT: no | ||
324 | */ | ||
325 | #define HW_DIGCTL_DBG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xd0)) | ||
326 | #define BP_DIGCTL_DBG_VALUE 0 | ||
327 | #define BM_DIGCTL_DBG_VALUE 0xffffffff | ||
328 | #define BF_DIGCTL_DBG_VALUE(v) (((v) << 0) & 0xffffffff) | ||
329 | |||
330 | /** | ||
331 | * Register: HW_DIGCTL_1TRAM_BIST_CSR | ||
332 | * Address: 0xe0 | ||
333 | * SCT: yes | ||
334 | */ | ||
335 | #define HW_DIGCTL_1TRAM_BIST_CSR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x0)) | ||
336 | #define HW_DIGCTL_1TRAM_BIST_CSR_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x4)) | ||
337 | #define HW_DIGCTL_1TRAM_BIST_CSR_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x8)) | ||
338 | #define HW_DIGCTL_1TRAM_BIST_CSR_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0xc)) | ||
339 | #define BP_DIGCTL_1TRAM_BIST_CSR_FAIL 3 | ||
340 | #define BM_DIGCTL_1TRAM_BIST_CSR_FAIL 0x8 | ||
341 | #define BF_DIGCTL_1TRAM_BIST_CSR_FAIL(v) (((v) << 3) & 0x8) | ||
342 | #define BP_DIGCTL_1TRAM_BIST_CSR_PASS 2 | ||
343 | #define BM_DIGCTL_1TRAM_BIST_CSR_PASS 0x4 | ||
344 | #define BF_DIGCTL_1TRAM_BIST_CSR_PASS(v) (((v) << 2) & 0x4) | ||
345 | #define BP_DIGCTL_1TRAM_BIST_CSR_DONE 1 | ||
346 | #define BM_DIGCTL_1TRAM_BIST_CSR_DONE 0x2 | ||
347 | #define BF_DIGCTL_1TRAM_BIST_CSR_DONE(v) (((v) << 1) & 0x2) | ||
348 | #define BP_DIGCTL_1TRAM_BIST_CSR_START 0 | ||
349 | #define BM_DIGCTL_1TRAM_BIST_CSR_START 0x1 | ||
350 | #define BF_DIGCTL_1TRAM_BIST_CSR_START(v) (((v) << 0) & 0x1) | ||
351 | |||
352 | /** | ||
353 | * Register: HW_DIGCTL_1TRAM_BIST_REPAIR0 | ||
354 | * Address: 0xf0 | ||
355 | * SCT: no | ||
356 | */ | ||
357 | #define HW_DIGCTL_1TRAM_BIST_REPAIR0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0)) | ||
358 | |||
359 | /** | ||
360 | * Register: HW_DIGCTL_1TRAM_BIST_REPAIR1 | ||
361 | * Address: 0x100 | ||
362 | * SCT: no | ||
363 | */ | ||
364 | #define HW_DIGCTL_1TRAM_BIST_REPAIR1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x100)) | ||
365 | |||
366 | /** | ||
367 | * Register: HW_DIGCTL_1TRAM_STATUS0 | ||
368 | * Address: 0x110 | ||
369 | * SCT: no | ||
370 | */ | ||
371 | #define HW_DIGCTL_1TRAM_STATUS0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110)) | ||
372 | #define BP_DIGCTL_1TRAM_STATUS0_FAILDATA00 0 | ||
373 | #define BM_DIGCTL_1TRAM_STATUS0_FAILDATA00 0xffffffff | ||
374 | #define BF_DIGCTL_1TRAM_STATUS0_FAILDATA00(v) (((v) << 0) & 0xffffffff) | ||
375 | |||
376 | /** | ||
377 | * Register: HW_DIGCTL_1TRAM_STATUS1 | ||
378 | * Address: 0x120 | ||
379 | * SCT: no | ||
380 | */ | ||
381 | #define HW_DIGCTL_1TRAM_STATUS1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120)) | ||
382 | #define BP_DIGCTL_1TRAM_STATUS1_FAILDATA01 0 | ||
383 | #define BM_DIGCTL_1TRAM_STATUS1_FAILDATA01 0xffffffff | ||
384 | #define BF_DIGCTL_1TRAM_STATUS1_FAILDATA01(v) (((v) << 0) & 0xffffffff) | ||
385 | |||
386 | /** | ||
387 | * Register: HW_DIGCTL_1TRAM_STATUS2 | ||
388 | * Address: 0x130 | ||
389 | * SCT: no | ||
390 | */ | ||
391 | #define HW_DIGCTL_1TRAM_STATUS2 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130)) | ||
392 | #define BP_DIGCTL_1TRAM_STATUS2_FAILDATA10 0 | ||
393 | #define BM_DIGCTL_1TRAM_STATUS2_FAILDATA10 0xffffffff | ||
394 | #define BF_DIGCTL_1TRAM_STATUS2_FAILDATA10(v) (((v) << 0) & 0xffffffff) | ||
395 | |||
396 | /** | ||
397 | * Register: HW_DIGCTL_1TRAM_STATUS3 | ||
398 | * Address: 0x140 | ||
399 | * SCT: no | ||
400 | */ | ||
401 | #define HW_DIGCTL_1TRAM_STATUS3 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140)) | ||
402 | #define BP_DIGCTL_1TRAM_STATUS3_FAILDATA11 0 | ||
403 | #define BM_DIGCTL_1TRAM_STATUS3_FAILDATA11 0xffffffff | ||
404 | #define BF_DIGCTL_1TRAM_STATUS3_FAILDATA11(v) (((v) << 0) & 0xffffffff) | ||
405 | |||
406 | /** | ||
407 | * Register: HW_DIGCTL_1TRAM_STATUS4 | ||
408 | * Address: 0x150 | ||
409 | * SCT: no | ||
410 | */ | ||
411 | #define HW_DIGCTL_1TRAM_STATUS4 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150)) | ||
412 | #define BP_DIGCTL_1TRAM_STATUS4_FAILDATA20 0 | ||
413 | #define BM_DIGCTL_1TRAM_STATUS4_FAILDATA20 0xffffffff | ||
414 | #define BF_DIGCTL_1TRAM_STATUS4_FAILDATA20(v) (((v) << 0) & 0xffffffff) | ||
415 | |||
416 | /** | ||
417 | * Register: HW_DIGCTL_1TRAM_STATUS5 | ||
418 | * Address: 0x160 | ||
419 | * SCT: no | ||
420 | */ | ||
421 | #define HW_DIGCTL_1TRAM_STATUS5 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160)) | ||
422 | #define BP_DIGCTL_1TRAM_STATUS5_FAILDATA21 0 | ||
423 | #define BM_DIGCTL_1TRAM_STATUS5_FAILDATA21 0xffffffff | ||
424 | #define BF_DIGCTL_1TRAM_STATUS5_FAILDATA21(v) (((v) << 0) & 0xffffffff) | ||
425 | |||
426 | /** | ||
427 | * Register: HW_DIGCTL_1TRAM_STATUS6 | ||
428 | * Address: 0x170 | ||
429 | * SCT: no | ||
430 | */ | ||
431 | #define HW_DIGCTL_1TRAM_STATUS6 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170)) | ||
432 | #define BP_DIGCTL_1TRAM_STATUS6_FAILDATA30 0 | ||
433 | #define BM_DIGCTL_1TRAM_STATUS6_FAILDATA30 0xffffffff | ||
434 | #define BF_DIGCTL_1TRAM_STATUS6_FAILDATA30(v) (((v) << 0) & 0xffffffff) | ||
435 | |||
436 | /** | ||
437 | * Register: HW_DIGCTL_1TRAM_STATUS7 | ||
438 | * Address: 0x180 | ||
439 | * SCT: no | ||
440 | */ | ||
441 | #define HW_DIGCTL_1TRAM_STATUS7 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180)) | ||
442 | #define BP_DIGCTL_1TRAM_STATUS7_FAILDATA31 0 | ||
443 | #define BM_DIGCTL_1TRAM_STATUS7_FAILDATA31 0xffffffff | ||
444 | #define BF_DIGCTL_1TRAM_STATUS7_FAILDATA31(v) (((v) << 0) & 0xffffffff) | ||
445 | |||
446 | /** | ||
447 | * Register: HW_DIGCTL_1TRAM_STATUS8 | ||
448 | * Address: 0x190 | ||
449 | * SCT: no | ||
450 | */ | ||
451 | #define HW_DIGCTL_1TRAM_STATUS8 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190)) | ||
452 | #define BP_DIGCTL_1TRAM_STATUS8_FAILADDR01 16 | ||
453 | #define BM_DIGCTL_1TRAM_STATUS8_FAILADDR01 0xffff0000 | ||
454 | #define BF_DIGCTL_1TRAM_STATUS8_FAILADDR01(v) (((v) << 16) & 0xffff0000) | ||
455 | #define BP_DIGCTL_1TRAM_STATUS8_FAILADDR00 0 | ||
456 | #define BM_DIGCTL_1TRAM_STATUS8_FAILADDR00 0xffff | ||
457 | #define BF_DIGCTL_1TRAM_STATUS8_FAILADDR00(v) (((v) << 0) & 0xffff) | ||
458 | |||
459 | /** | ||
460 | * Register: HW_DIGCTL_1TRAM_STATUS9 | ||
461 | * Address: 0x1a0 | ||
462 | * SCT: no | ||
463 | */ | ||
464 | #define HW_DIGCTL_1TRAM_STATUS9 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0)) | ||
465 | #define BP_DIGCTL_1TRAM_STATUS9_FAILADDR11 16 | ||
466 | #define BM_DIGCTL_1TRAM_STATUS9_FAILADDR11 0xffff0000 | ||
467 | #define BF_DIGCTL_1TRAM_STATUS9_FAILADDR11(v) (((v) << 16) & 0xffff0000) | ||
468 | #define BP_DIGCTL_1TRAM_STATUS9_FAILADDR10 0 | ||
469 | #define BM_DIGCTL_1TRAM_STATUS9_FAILADDR10 0xffff | ||
470 | #define BF_DIGCTL_1TRAM_STATUS9_FAILADDR10(v) (((v) << 0) & 0xffff) | ||
471 | |||
472 | /** | ||
473 | * Register: HW_DIGCTL_1TRAM_STATUS10 | ||
474 | * Address: 0x1b0 | ||
475 | * SCT: no | ||
476 | */ | ||
477 | #define HW_DIGCTL_1TRAM_STATUS10 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0)) | ||
478 | #define BP_DIGCTL_1TRAM_STATUS10_FAILADDR21 16 | ||
479 | #define BM_DIGCTL_1TRAM_STATUS10_FAILADDR21 0xffff0000 | ||
480 | #define BF_DIGCTL_1TRAM_STATUS10_FAILADDR21(v) (((v) << 16) & 0xffff0000) | ||
481 | #define BP_DIGCTL_1TRAM_STATUS10_FAILADDR20 0 | ||
482 | #define BM_DIGCTL_1TRAM_STATUS10_FAILADDR20 0xffff | ||
483 | #define BF_DIGCTL_1TRAM_STATUS10_FAILADDR20(v) (((v) << 0) & 0xffff) | ||
484 | |||
485 | /** | ||
486 | * Register: HW_DIGCTL_1TRAM_STATUS11 | ||
487 | * Address: 0x1c0 | ||
488 | * SCT: no | ||
489 | */ | ||
490 | #define HW_DIGCTL_1TRAM_STATUS11 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0)) | ||
491 | #define BP_DIGCTL_1TRAM_STATUS11_FAILADDR31 16 | ||
492 | #define BM_DIGCTL_1TRAM_STATUS11_FAILADDR31 0xffff0000 | ||
493 | #define BF_DIGCTL_1TRAM_STATUS11_FAILADDR31(v) (((v) << 16) & 0xffff0000) | ||
494 | #define BP_DIGCTL_1TRAM_STATUS11_FAILADDR30 0 | ||
495 | #define BM_DIGCTL_1TRAM_STATUS11_FAILADDR30 0xffff | ||
496 | #define BF_DIGCTL_1TRAM_STATUS11_FAILADDR30(v) (((v) << 0) & 0xffff) | ||
497 | |||
498 | /** | ||
499 | * Register: HW_DIGCTL_1TRAM_STATUS12 | ||
500 | * Address: 0x1d0 | ||
501 | * SCT: no | ||
502 | */ | ||
503 | #define HW_DIGCTL_1TRAM_STATUS12 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0)) | ||
504 | #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE11 24 | ||
505 | #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE11 0x1f000000 | ||
506 | #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE11(v) (((v) << 24) & 0x1f000000) | ||
507 | #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE10 16 | ||
508 | #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE10 0x1f0000 | ||
509 | #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE10(v) (((v) << 16) & 0x1f0000) | ||
510 | #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE01 8 | ||
511 | #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE01 0x1f00 | ||
512 | #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE01(v) (((v) << 8) & 0x1f00) | ||
513 | #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE00 0 | ||
514 | #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE00 0x1f | ||
515 | #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE00(v) (((v) << 0) & 0x1f) | ||
516 | |||
517 | /** | ||
518 | * Register: HW_DIGCTL_1TRAM_STATUS13 | ||
519 | * Address: 0x1e0 | ||
520 | * SCT: no | ||
521 | */ | ||
522 | #define HW_DIGCTL_1TRAM_STATUS13 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0)) | ||
523 | #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE31 24 | ||
524 | #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE31 0x1f000000 | ||
525 | #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE31(v) (((v) << 24) & 0x1f000000) | ||
526 | #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE30 16 | ||
527 | #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE30 0x1f0000 | ||
528 | #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE30(v) (((v) << 16) & 0x1f0000) | ||
529 | #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE21 8 | ||
530 | #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE21 0x1f00 | ||
531 | #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE21(v) (((v) << 8) & 0x1f00) | ||
532 | #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE20 0 | ||
533 | #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE20 0x1f | ||
534 | #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE20(v) (((v) << 0) & 0x1f) | ||
535 | |||
536 | /** | ||
537 | * Register: HW_DIGCTL_SCRATCH0 | ||
538 | * Address: 0x290 | ||
539 | * SCT: no | ||
540 | */ | ||
541 | #define HW_DIGCTL_SCRATCH0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x290)) | ||
542 | #define BP_DIGCTL_SCRATCH0_PTR 0 | ||
543 | #define BM_DIGCTL_SCRATCH0_PTR 0xffffffff | ||
544 | #define BF_DIGCTL_SCRATCH0_PTR(v) (((v) << 0) & 0xffffffff) | ||
545 | |||
546 | /** | ||
547 | * Register: HW_DIGCTL_SCRATCH1 | ||
548 | * Address: 0x2a0 | ||
549 | * SCT: no | ||
550 | */ | ||
551 | #define HW_DIGCTL_SCRATCH1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2a0)) | ||
552 | #define BP_DIGCTL_SCRATCH1_PTR 0 | ||
553 | #define BM_DIGCTL_SCRATCH1_PTR 0xffffffff | ||
554 | #define BF_DIGCTL_SCRATCH1_PTR(v) (((v) << 0) & 0xffffffff) | ||
555 | |||
556 | /** | ||
557 | * Register: HW_DIGCTL_ARMCACHE | ||
558 | * Address: 0x2b0 | ||
559 | * SCT: no | ||
560 | */ | ||
561 | #define HW_DIGCTL_ARMCACHE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2b0)) | ||
562 | #define BP_DIGCTL_ARMCACHE_CACHE_SS 8 | ||
563 | #define BM_DIGCTL_ARMCACHE_CACHE_SS 0x300 | ||
564 | #define BF_DIGCTL_ARMCACHE_CACHE_SS(v) (((v) << 8) & 0x300) | ||
565 | #define BP_DIGCTL_ARMCACHE_DTAG_SS 4 | ||
566 | #define BM_DIGCTL_ARMCACHE_DTAG_SS 0x30 | ||
567 | #define BF_DIGCTL_ARMCACHE_DTAG_SS(v) (((v) << 4) & 0x30) | ||
568 | #define BP_DIGCTL_ARMCACHE_ITAG_SS 0 | ||
569 | #define BM_DIGCTL_ARMCACHE_ITAG_SS 0x3 | ||
570 | #define BF_DIGCTL_ARMCACHE_ITAG_SS(v) (((v) << 0) & 0x3) | ||
571 | |||
572 | /** | ||
573 | * Register: HW_DIGCTL_SGTL | ||
574 | * Address: 0x300 | ||
575 | * SCT: no | ||
576 | */ | ||
577 | #define HW_DIGCTL_SGTL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x300)) | ||
578 | #define BP_DIGCTL_SGTL_COPYRIGHT 0 | ||
579 | #define BM_DIGCTL_SGTL_COPYRIGHT 0xffffffff | ||
580 | #define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) << 0) & 0xffffffff) | ||
581 | |||
582 | /** | ||
583 | * Register: HW_DIGCTL_CHIPID | ||
584 | * Address: 0x310 | ||
585 | * SCT: no | ||
586 | */ | ||
587 | #define HW_DIGCTL_CHIPID (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x310)) | ||
588 | #define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 | ||
589 | #define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xffff0000 | ||
590 | #define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) (((v) << 16) & 0xffff0000) | ||
591 | #define BP_DIGCTL_CHIPID_REVISION 0 | ||
592 | #define BM_DIGCTL_CHIPID_REVISION 0xff | ||
593 | #define BF_DIGCTL_CHIPID_REVISION(v) (((v) << 0) & 0xff) | ||
594 | |||
595 | #endif /* __HEADERGEN__STMP3600__DIGCTL__H__ */ | ||