From 017667c2dc9843eb5082e991f421c773636dcf36 Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Thu, 13 Jun 2013 19:03:33 +0200 Subject: imx233: generate register headers for stmp3600, stmp3700 and imx233 Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934 --- .../target/arm/imx233/regs/stmp3600/regs-digctl.h | 595 +++++++++++++++++++++ 1 file changed, 595 insertions(+) create mode 100644 firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h (limited to 'firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h') diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h new file mode 100644 index 0000000000..a7b45a7ca9 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h @@ -0,0 +1,595 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 2.1.7 + * XML versions: stmp3600:2.3.0 + * + * Copyright (C) 2013 by Amaury Pouly + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN__STMP3600__DIGCTL__H__ +#define __HEADERGEN__STMP3600__DIGCTL__H__ + +#define REGS_DIGCTL_BASE (0x8001c000) + +#define REGS_DIGCTL_VERSION "2.3.0" + +/** + * Register: HW_DIGCTL_CTRL + * Address: 0 + * SCT: yes +*/ +#define HW_DIGCTL_CTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x0)) +#define HW_DIGCTL_CTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x4)) +#define HW_DIGCTL_CTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x8)) +#define HW_DIGCTL_CTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0xc)) +#define BP_DIGCTL_CTRL_MASTER_SELECT 24 +#define BM_DIGCTL_CTRL_MASTER_SELECT 0x1f000000 +#define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_I 0x1 +#define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_D 0x2 +#define BV_DIGCTL_CTRL_MASTER_SELECT__USB 0x4 +#define BV_DIGCTL_CTRL_MASTER_SELECT__APBH 0x8 +#define BV_DIGCTL_CTRL_MASTER_SELECT__APBX 0x10 +#define BF_DIGCTL_CTRL_MASTER_SELECT(v) (((v) << 24) & 0x1f000000) +#define BF_DIGCTL_CTRL_MASTER_SELECT_V(v) ((BV_DIGCTL_CTRL_MASTER_SELECT__##v << 24) & 0x1f000000) +#define BP_DIGCTL_CTRL_USB_TESTMODE 20 +#define BM_DIGCTL_CTRL_USB_TESTMODE 0x100000 +#define BF_DIGCTL_CTRL_USB_TESTMODE(v) (((v) << 20) & 0x100000) +#define BP_DIGCTL_CTRL_ANALOG_TESTMODE 19 +#define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x80000 +#define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v) (((v) << 19) & 0x80000) +#define BP_DIGCTL_CTRL_DIGITAL_TESTMODE 18 +#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x40000 +#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v) (((v) << 18) & 0x40000) +#define BP_DIGCTL_CTRL_UTMI_TESTMODE 17 +#define BM_DIGCTL_CTRL_UTMI_TESTMODE 0x20000 +#define BF_DIGCTL_CTRL_UTMI_TESTMODE(v) (((v) << 17) & 0x20000) +#define BP_DIGCTL_CTRL_UART_LOOPBACK 16 +#define BM_DIGCTL_CTRL_UART_LOOPBACK 0x10000 +#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0 +#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1 +#define BF_DIGCTL_CTRL_UART_LOOPBACK(v) (((v) << 16) & 0x10000) +#define BF_DIGCTL_CTRL_UART_LOOPBACK_V(v) ((BV_DIGCTL_CTRL_UART_LOOPBACK__##v << 16) & 0x10000) +#define BP_DIGCTL_CTRL_DEBUG_DISABLE 3 +#define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x8 +#define BF_DIGCTL_CTRL_DEBUG_DISABLE(v) (((v) << 3) & 0x8) +#define BP_DIGCTL_CTRL_USB_CLKGATE 2 +#define BM_DIGCTL_CTRL_USB_CLKGATE 0x4 +#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0 +#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1 +#define BF_DIGCTL_CTRL_USB_CLKGATE(v) (((v) << 2) & 0x4) +#define BF_DIGCTL_CTRL_USB_CLKGATE_V(v) ((BV_DIGCTL_CTRL_USB_CLKGATE__##v << 2) & 0x4) +#define BP_DIGCTL_CTRL_JTAG_SHIELD 1 +#define BM_DIGCTL_CTRL_JTAG_SHIELD 0x2 +#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 +#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 +#define BF_DIGCTL_CTRL_JTAG_SHIELD(v) (((v) << 1) & 0x2) +#define BF_DIGCTL_CTRL_JTAG_SHIELD_V(v) ((BV_DIGCTL_CTRL_JTAG_SHIELD__##v << 1) & 0x2) +#define BP_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE 0 +#define BM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE 0x1 +#define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__DISABLE 0x0 +#define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__ENABLE 0x1 +#define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE(v) (((v) << 0) & 0x1) +#define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE_V(v) ((BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__##v << 0) & 0x1) + +/** + * Register: HW_DIGCTL_STATUS + * Address: 0x10 + * SCT: no +*/ +#define HW_DIGCTL_STATUS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10)) +#define BP_DIGCTL_STATUS_ROM_KEYS_PRESENT 31 +#define BM_DIGCTL_STATUS_ROM_KEYS_PRESENT 0x80000000 +#define BF_DIGCTL_STATUS_ROM_KEYS_PRESENT(v) (((v) << 31) & 0x80000000) +#define BP_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT 6 +#define BM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT 0x40 +#define BF_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT(v) (((v) << 6) & 0x40) +#define BP_DIGCTL_STATUS_ROM_SHIELDED 5 +#define BM_DIGCTL_STATUS_ROM_SHIELDED 0x20 +#define BF_DIGCTL_STATUS_ROM_SHIELDED(v) (((v) << 5) & 0x20) +#define BP_DIGCTL_STATUS_JTAG_IN_USE 4 +#define BM_DIGCTL_STATUS_JTAG_IN_USE 0x10 +#define BF_DIGCTL_STATUS_JTAG_IN_USE(v) (((v) << 4) & 0x10) +#define BP_DIGCTL_STATUS_PSWITCH 2 +#define BM_DIGCTL_STATUS_PSWITCH 0xc +#define BF_DIGCTL_STATUS_PSWITCH(v) (((v) << 2) & 0xc) +#define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 +#define BM_DIGCTL_STATUS_PACKAGE_TYPE 0x2 +#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) (((v) << 1) & 0x2) +#define BP_DIGCTL_STATUS_WRITTEN 0 +#define BM_DIGCTL_STATUS_WRITTEN 0x1 +#define BF_DIGCTL_STATUS_WRITTEN(v) (((v) << 0) & 0x1) + +/** + * Register: HW_DIGCTL_HCLKCOUNT + * Address: 0x20 + * SCT: no +*/ +#define HW_DIGCTL_HCLKCOUNT (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20)) +#define BP_DIGCTL_HCLKCOUNT_COUNT 0 +#define BM_DIGCTL_HCLKCOUNT_COUNT 0xffffffff +#define BF_DIGCTL_HCLKCOUNT_COUNT(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_RAMCTRL + * Address: 0x30 + * SCT: yes +*/ +#define HW_DIGCTL_RAMCTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x0)) +#define HW_DIGCTL_RAMCTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x4)) +#define HW_DIGCTL_RAMCTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x8)) +#define HW_DIGCTL_RAMCTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0xc)) +#define BP_DIGCTL_RAMCTRL_TEST_MARGIN 28 +#define BM_DIGCTL_RAMCTRL_TEST_MARGIN 0x70000000 +#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__NORMAL 0x0 +#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL1 0x1 +#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL2 0x2 +#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL3 0x3 +#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL4 0x4 +#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL5 0x5 +#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL6 0x6 +#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL7 0x7 +#define BF_DIGCTL_RAMCTRL_TEST_MARGIN(v) (((v) << 28) & 0x70000000) +#define BF_DIGCTL_RAMCTRL_TEST_MARGIN_V(v) ((BV_DIGCTL_RAMCTRL_TEST_MARGIN__##v << 28) & 0x70000000) +#define BP_DIGCTL_RAMCTRL_PWDN_BANKS 24 +#define BM_DIGCTL_RAMCTRL_PWDN_BANKS 0xf000000 +#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK3 0x8 +#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK2 0x4 +#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK1 0x2 +#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK0 0x1 +#define BF_DIGCTL_RAMCTRL_PWDN_BANKS(v) (((v) << 24) & 0xf000000) +#define BF_DIGCTL_RAMCTRL_PWDN_BANKS_V(v) ((BV_DIGCTL_RAMCTRL_PWDN_BANKS__##v << 24) & 0xf000000) +#define BP_DIGCTL_RAMCTRL_TEMP_SENSOR 20 +#define BM_DIGCTL_RAMCTRL_TEMP_SENSOR 0x700000 +#define BF_DIGCTL_RAMCTRL_TEMP_SENSOR(v) (((v) << 20) & 0x700000) +#define BP_DIGCTL_RAMCTRL_TEST_TEMP_COMP 16 +#define BM_DIGCTL_RAMCTRL_TEST_TEMP_COMP 0x70000 +#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__LOW_TEMP 0x1 +#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_A 0x2 +#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_B 0x3 +#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_C 0x4 +#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_D 0x5 +#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_E 0x6 +#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_F 0x7 +#define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP(v) (((v) << 16) & 0x70000) +#define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP_V(v) ((BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__##v << 16) & 0x70000) +#define BP_DIGCTL_RAMCTRL_SHIFT_COUNT 8 +#define BM_DIGCTL_RAMCTRL_SHIFT_COUNT 0x7f00 +#define BF_DIGCTL_RAMCTRL_SHIFT_COUNT(v) (((v) << 8) & 0x7f00) +#define BP_DIGCTL_RAMCTRL_FLIP_CLK 7 +#define BM_DIGCTL_RAMCTRL_FLIP_CLK 0x80 +#define BV_DIGCTL_RAMCTRL_FLIP_CLK__NORMAL 0x0 +#define BV_DIGCTL_RAMCTRL_FLIP_CLK__INVERT 0x1 +#define BF_DIGCTL_RAMCTRL_FLIP_CLK(v) (((v) << 7) & 0x80) +#define BF_DIGCTL_RAMCTRL_FLIP_CLK_V(v) ((BV_DIGCTL_RAMCTRL_FLIP_CLK__##v << 7) & 0x80) +#define BP_DIGCTL_RAMCTRL_OVER_RIDE_TEMP 3 +#define BM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP 0x8 +#define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__NORMAL 0x0 +#define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__OVER_RIDE 0x1 +#define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP(v) (((v) << 3) & 0x8) +#define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP_V(v) ((BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__##v << 3) & 0x8) +#define BP_DIGCTL_RAMCTRL_REF_CLK_GATE 2 +#define BM_DIGCTL_RAMCTRL_REF_CLK_GATE 0x4 +#define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__NORMAL 0x0 +#define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__OFF 0x1 +#define BF_DIGCTL_RAMCTRL_REF_CLK_GATE(v) (((v) << 2) & 0x4) +#define BF_DIGCTL_RAMCTRL_REF_CLK_GATE_V(v) ((BV_DIGCTL_RAMCTRL_REF_CLK_GATE__##v << 2) & 0x4) +#define BP_DIGCTL_RAMCTRL_REPAIR_STATUS 1 +#define BM_DIGCTL_RAMCTRL_REPAIR_STATUS 0x2 +#define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__IDLE 0x0 +#define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__BUSY 0x1 +#define BF_DIGCTL_RAMCTRL_REPAIR_STATUS(v) (((v) << 1) & 0x2) +#define BF_DIGCTL_RAMCTRL_REPAIR_STATUS_V(v) ((BV_DIGCTL_RAMCTRL_REPAIR_STATUS__##v << 1) & 0x2) +#define BP_DIGCTL_RAMCTRL_REPAIR_TRANSMIT 0 +#define BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT 0x1 +#define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__IDLE 0x0 +#define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__SEND 0x1 +#define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT(v) (((v) << 0) & 0x1) +#define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT_V(v) ((BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__##v << 0) & 0x1) + +/** + * Register: HW_DIGCTL_RAMREPAIR0 + * Address: 0x40 + * SCT: yes +*/ +#define HW_DIGCTL_RAMREPAIR0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x0)) +#define HW_DIGCTL_RAMREPAIR0_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x4)) +#define HW_DIGCTL_RAMREPAIR0_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x8)) +#define HW_DIGCTL_RAMREPAIR0_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0xc)) +#define BP_DIGCTL_RAMREPAIR0_EFUSE3 24 +#define BM_DIGCTL_RAMREPAIR0_EFUSE3 0x7f000000 +#define BF_DIGCTL_RAMREPAIR0_EFUSE3(v) (((v) << 24) & 0x7f000000) +#define BP_DIGCTL_RAMREPAIR0_EFUSE2 16 +#define BM_DIGCTL_RAMREPAIR0_EFUSE2 0x7f0000 +#define BF_DIGCTL_RAMREPAIR0_EFUSE2(v) (((v) << 16) & 0x7f0000) +#define BP_DIGCTL_RAMREPAIR0_EFUSE1 8 +#define BM_DIGCTL_RAMREPAIR0_EFUSE1 0x7f00 +#define BF_DIGCTL_RAMREPAIR0_EFUSE1(v) (((v) << 8) & 0x7f00) +#define BP_DIGCTL_RAMREPAIR0_EFUSE0 0 +#define BM_DIGCTL_RAMREPAIR0_EFUSE0 0x7f +#define BF_DIGCTL_RAMREPAIR0_EFUSE0(v) (((v) << 0) & 0x7f) + +/** + * Register: HW_DIGCTL_RAMREPAIR1 + * Address: 0x50 + * SCT: yes +*/ +#define HW_DIGCTL_RAMREPAIR1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x0)) +#define HW_DIGCTL_RAMREPAIR1_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x4)) +#define HW_DIGCTL_RAMREPAIR1_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x8)) +#define HW_DIGCTL_RAMREPAIR1_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0xc)) +#define BP_DIGCTL_RAMREPAIR1_EFUSE3 24 +#define BM_DIGCTL_RAMREPAIR1_EFUSE3 0x7f000000 +#define BF_DIGCTL_RAMREPAIR1_EFUSE3(v) (((v) << 24) & 0x7f000000) +#define BP_DIGCTL_RAMREPAIR1_EFUSE2 16 +#define BM_DIGCTL_RAMREPAIR1_EFUSE2 0x7f0000 +#define BF_DIGCTL_RAMREPAIR1_EFUSE2(v) (((v) << 16) & 0x7f0000) +#define BP_DIGCTL_RAMREPAIR1_EFUSE1 8 +#define BM_DIGCTL_RAMREPAIR1_EFUSE1 0x7f00 +#define BF_DIGCTL_RAMREPAIR1_EFUSE1(v) (((v) << 8) & 0x7f00) +#define BP_DIGCTL_RAMREPAIR1_EFUSE0 0 +#define BM_DIGCTL_RAMREPAIR1_EFUSE0 0x7f +#define BF_DIGCTL_RAMREPAIR1_EFUSE0(v) (((v) << 0) & 0x7f) + +/** + * Register: HW_DIGCTL_WRITEONCE + * Address: 0x60 + * SCT: no +*/ +#define HW_DIGCTL_WRITEONCE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x60)) +#define BP_DIGCTL_WRITEONCE_BITS 0 +#define BM_DIGCTL_WRITEONCE_BITS 0xffffffff +#define BF_DIGCTL_WRITEONCE_BITS(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_AHBCYCLES + * Address: 0x70 + * SCT: no +*/ +#define HW_DIGCTL_AHBCYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x70)) +#define BP_DIGCTL_AHBCYCLES_COUNT 0 +#define BM_DIGCTL_AHBCYCLES_COUNT 0xffffffff +#define BF_DIGCTL_AHBCYCLES_COUNT(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_AHBSTALLED + * Address: 0x80 + * SCT: no +*/ +#define HW_DIGCTL_AHBSTALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x80)) +#define BP_DIGCTL_AHBSTALLED_COUNT 0 +#define BM_DIGCTL_AHBSTALLED_COUNT 0xffffffff +#define BF_DIGCTL_AHBSTALLED_COUNT(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_ENTROPY + * Address: 0x90 + * SCT: no +*/ +#define HW_DIGCTL_ENTROPY (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x90)) +#define BP_DIGCTL_ENTROPY_VALUE 0 +#define BM_DIGCTL_ENTROPY_VALUE 0xffffffff +#define BF_DIGCTL_ENTROPY_VALUE(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_ROMSHIELD + * Address: 0xa0 + * SCT: no +*/ +#define HW_DIGCTL_ROMSHIELD (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xa0)) +#define BP_DIGCTL_ROMSHIELD_WRITE_ONCE 0 +#define BM_DIGCTL_ROMSHIELD_WRITE_ONCE 0x1 +#define BF_DIGCTL_ROMSHIELD_WRITE_ONCE(v) (((v) << 0) & 0x1) + +/** + * Register: HW_DIGCTL_MICROSECONDS + * Address: 0xb0 + * SCT: yes +*/ +#define HW_DIGCTL_MICROSECONDS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x0)) +#define HW_DIGCTL_MICROSECONDS_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x4)) +#define HW_DIGCTL_MICROSECONDS_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x8)) +#define HW_DIGCTL_MICROSECONDS_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0xc)) +#define BP_DIGCTL_MICROSECONDS_VALUE 0 +#define BM_DIGCTL_MICROSECONDS_VALUE 0xffffffff +#define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_DBGRD + * Address: 0xc0 + * SCT: no +*/ +#define HW_DIGCTL_DBGRD (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0)) +#define BP_DIGCTL_DBGRD_COMPLEMENT 0 +#define BM_DIGCTL_DBGRD_COMPLEMENT 0xffffffff +#define BF_DIGCTL_DBGRD_COMPLEMENT(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_DBG + * Address: 0xd0 + * SCT: no +*/ +#define HW_DIGCTL_DBG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xd0)) +#define BP_DIGCTL_DBG_VALUE 0 +#define BM_DIGCTL_DBG_VALUE 0xffffffff +#define BF_DIGCTL_DBG_VALUE(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_1TRAM_BIST_CSR + * Address: 0xe0 + * SCT: yes +*/ +#define HW_DIGCTL_1TRAM_BIST_CSR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x0)) +#define HW_DIGCTL_1TRAM_BIST_CSR_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x4)) +#define HW_DIGCTL_1TRAM_BIST_CSR_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x8)) +#define HW_DIGCTL_1TRAM_BIST_CSR_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0xc)) +#define BP_DIGCTL_1TRAM_BIST_CSR_FAIL 3 +#define BM_DIGCTL_1TRAM_BIST_CSR_FAIL 0x8 +#define BF_DIGCTL_1TRAM_BIST_CSR_FAIL(v) (((v) << 3) & 0x8) +#define BP_DIGCTL_1TRAM_BIST_CSR_PASS 2 +#define BM_DIGCTL_1TRAM_BIST_CSR_PASS 0x4 +#define BF_DIGCTL_1TRAM_BIST_CSR_PASS(v) (((v) << 2) & 0x4) +#define BP_DIGCTL_1TRAM_BIST_CSR_DONE 1 +#define BM_DIGCTL_1TRAM_BIST_CSR_DONE 0x2 +#define BF_DIGCTL_1TRAM_BIST_CSR_DONE(v) (((v) << 1) & 0x2) +#define BP_DIGCTL_1TRAM_BIST_CSR_START 0 +#define BM_DIGCTL_1TRAM_BIST_CSR_START 0x1 +#define BF_DIGCTL_1TRAM_BIST_CSR_START(v) (((v) << 0) & 0x1) + +/** + * Register: HW_DIGCTL_1TRAM_BIST_REPAIR0 + * Address: 0xf0 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_BIST_REPAIR0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0)) + +/** + * Register: HW_DIGCTL_1TRAM_BIST_REPAIR1 + * Address: 0x100 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_BIST_REPAIR1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x100)) + +/** + * Register: HW_DIGCTL_1TRAM_STATUS0 + * Address: 0x110 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_STATUS0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110)) +#define BP_DIGCTL_1TRAM_STATUS0_FAILDATA00 0 +#define BM_DIGCTL_1TRAM_STATUS0_FAILDATA00 0xffffffff +#define BF_DIGCTL_1TRAM_STATUS0_FAILDATA00(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_1TRAM_STATUS1 + * Address: 0x120 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_STATUS1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120)) +#define BP_DIGCTL_1TRAM_STATUS1_FAILDATA01 0 +#define BM_DIGCTL_1TRAM_STATUS1_FAILDATA01 0xffffffff +#define BF_DIGCTL_1TRAM_STATUS1_FAILDATA01(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_1TRAM_STATUS2 + * Address: 0x130 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_STATUS2 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130)) +#define BP_DIGCTL_1TRAM_STATUS2_FAILDATA10 0 +#define BM_DIGCTL_1TRAM_STATUS2_FAILDATA10 0xffffffff +#define BF_DIGCTL_1TRAM_STATUS2_FAILDATA10(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_1TRAM_STATUS3 + * Address: 0x140 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_STATUS3 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140)) +#define BP_DIGCTL_1TRAM_STATUS3_FAILDATA11 0 +#define BM_DIGCTL_1TRAM_STATUS3_FAILDATA11 0xffffffff +#define BF_DIGCTL_1TRAM_STATUS3_FAILDATA11(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_1TRAM_STATUS4 + * Address: 0x150 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_STATUS4 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150)) +#define BP_DIGCTL_1TRAM_STATUS4_FAILDATA20 0 +#define BM_DIGCTL_1TRAM_STATUS4_FAILDATA20 0xffffffff +#define BF_DIGCTL_1TRAM_STATUS4_FAILDATA20(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_1TRAM_STATUS5 + * Address: 0x160 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_STATUS5 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160)) +#define BP_DIGCTL_1TRAM_STATUS5_FAILDATA21 0 +#define BM_DIGCTL_1TRAM_STATUS5_FAILDATA21 0xffffffff +#define BF_DIGCTL_1TRAM_STATUS5_FAILDATA21(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_1TRAM_STATUS6 + * Address: 0x170 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_STATUS6 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170)) +#define BP_DIGCTL_1TRAM_STATUS6_FAILDATA30 0 +#define BM_DIGCTL_1TRAM_STATUS6_FAILDATA30 0xffffffff +#define BF_DIGCTL_1TRAM_STATUS6_FAILDATA30(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_1TRAM_STATUS7 + * Address: 0x180 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_STATUS7 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180)) +#define BP_DIGCTL_1TRAM_STATUS7_FAILDATA31 0 +#define BM_DIGCTL_1TRAM_STATUS7_FAILDATA31 0xffffffff +#define BF_DIGCTL_1TRAM_STATUS7_FAILDATA31(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_1TRAM_STATUS8 + * Address: 0x190 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_STATUS8 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190)) +#define BP_DIGCTL_1TRAM_STATUS8_FAILADDR01 16 +#define BM_DIGCTL_1TRAM_STATUS8_FAILADDR01 0xffff0000 +#define BF_DIGCTL_1TRAM_STATUS8_FAILADDR01(v) (((v) << 16) & 0xffff0000) +#define BP_DIGCTL_1TRAM_STATUS8_FAILADDR00 0 +#define BM_DIGCTL_1TRAM_STATUS8_FAILADDR00 0xffff +#define BF_DIGCTL_1TRAM_STATUS8_FAILADDR00(v) (((v) << 0) & 0xffff) + +/** + * Register: HW_DIGCTL_1TRAM_STATUS9 + * Address: 0x1a0 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_STATUS9 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0)) +#define BP_DIGCTL_1TRAM_STATUS9_FAILADDR11 16 +#define BM_DIGCTL_1TRAM_STATUS9_FAILADDR11 0xffff0000 +#define BF_DIGCTL_1TRAM_STATUS9_FAILADDR11(v) (((v) << 16) & 0xffff0000) +#define BP_DIGCTL_1TRAM_STATUS9_FAILADDR10 0 +#define BM_DIGCTL_1TRAM_STATUS9_FAILADDR10 0xffff +#define BF_DIGCTL_1TRAM_STATUS9_FAILADDR10(v) (((v) << 0) & 0xffff) + +/** + * Register: HW_DIGCTL_1TRAM_STATUS10 + * Address: 0x1b0 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_STATUS10 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0)) +#define BP_DIGCTL_1TRAM_STATUS10_FAILADDR21 16 +#define BM_DIGCTL_1TRAM_STATUS10_FAILADDR21 0xffff0000 +#define BF_DIGCTL_1TRAM_STATUS10_FAILADDR21(v) (((v) << 16) & 0xffff0000) +#define BP_DIGCTL_1TRAM_STATUS10_FAILADDR20 0 +#define BM_DIGCTL_1TRAM_STATUS10_FAILADDR20 0xffff +#define BF_DIGCTL_1TRAM_STATUS10_FAILADDR20(v) (((v) << 0) & 0xffff) + +/** + * Register: HW_DIGCTL_1TRAM_STATUS11 + * Address: 0x1c0 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_STATUS11 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0)) +#define BP_DIGCTL_1TRAM_STATUS11_FAILADDR31 16 +#define BM_DIGCTL_1TRAM_STATUS11_FAILADDR31 0xffff0000 +#define BF_DIGCTL_1TRAM_STATUS11_FAILADDR31(v) (((v) << 16) & 0xffff0000) +#define BP_DIGCTL_1TRAM_STATUS11_FAILADDR30 0 +#define BM_DIGCTL_1TRAM_STATUS11_FAILADDR30 0xffff +#define BF_DIGCTL_1TRAM_STATUS11_FAILADDR30(v) (((v) << 0) & 0xffff) + +/** + * Register: HW_DIGCTL_1TRAM_STATUS12 + * Address: 0x1d0 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_STATUS12 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0)) +#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE11 24 +#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE11 0x1f000000 +#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE11(v) (((v) << 24) & 0x1f000000) +#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE10 16 +#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE10 0x1f0000 +#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE10(v) (((v) << 16) & 0x1f0000) +#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE01 8 +#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE01 0x1f00 +#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE01(v) (((v) << 8) & 0x1f00) +#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE00 0 +#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE00 0x1f +#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE00(v) (((v) << 0) & 0x1f) + +/** + * Register: HW_DIGCTL_1TRAM_STATUS13 + * Address: 0x1e0 + * SCT: no +*/ +#define HW_DIGCTL_1TRAM_STATUS13 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0)) +#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE31 24 +#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE31 0x1f000000 +#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE31(v) (((v) << 24) & 0x1f000000) +#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE30 16 +#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE30 0x1f0000 +#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE30(v) (((v) << 16) & 0x1f0000) +#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE21 8 +#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE21 0x1f00 +#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE21(v) (((v) << 8) & 0x1f00) +#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE20 0 +#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE20 0x1f +#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE20(v) (((v) << 0) & 0x1f) + +/** + * Register: HW_DIGCTL_SCRATCH0 + * Address: 0x290 + * SCT: no +*/ +#define HW_DIGCTL_SCRATCH0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x290)) +#define BP_DIGCTL_SCRATCH0_PTR 0 +#define BM_DIGCTL_SCRATCH0_PTR 0xffffffff +#define BF_DIGCTL_SCRATCH0_PTR(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_SCRATCH1 + * Address: 0x2a0 + * SCT: no +*/ +#define HW_DIGCTL_SCRATCH1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2a0)) +#define BP_DIGCTL_SCRATCH1_PTR 0 +#define BM_DIGCTL_SCRATCH1_PTR 0xffffffff +#define BF_DIGCTL_SCRATCH1_PTR(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_ARMCACHE + * Address: 0x2b0 + * SCT: no +*/ +#define HW_DIGCTL_ARMCACHE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2b0)) +#define BP_DIGCTL_ARMCACHE_CACHE_SS 8 +#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x300 +#define BF_DIGCTL_ARMCACHE_CACHE_SS(v) (((v) << 8) & 0x300) +#define BP_DIGCTL_ARMCACHE_DTAG_SS 4 +#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x30 +#define BF_DIGCTL_ARMCACHE_DTAG_SS(v) (((v) << 4) & 0x30) +#define BP_DIGCTL_ARMCACHE_ITAG_SS 0 +#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x3 +#define BF_DIGCTL_ARMCACHE_ITAG_SS(v) (((v) << 0) & 0x3) + +/** + * Register: HW_DIGCTL_SGTL + * Address: 0x300 + * SCT: no +*/ +#define HW_DIGCTL_SGTL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x300)) +#define BP_DIGCTL_SGTL_COPYRIGHT 0 +#define BM_DIGCTL_SGTL_COPYRIGHT 0xffffffff +#define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_DIGCTL_CHIPID + * Address: 0x310 + * SCT: no +*/ +#define HW_DIGCTL_CHIPID (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x310)) +#define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 +#define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xffff0000 +#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) (((v) << 16) & 0xffff0000) +#define BP_DIGCTL_CHIPID_REVISION 0 +#define BM_DIGCTL_CHIPID_REVISION 0xff +#define BF_DIGCTL_CHIPID_REVISION(v) (((v) << 0) & 0xff) + +#endif /* __HEADERGEN__STMP3600__DIGCTL__H__ */ -- cgit v1.2.3