Gigabeat S: Reclaim about 800K of memory that was laying unused. Get rid of DEVBSS_ATTR for this target and implement as NOCACHEBSS_ATTR. Plugin and codec buffers move so all that is now incompatible (do full update). No version increase for plugins/codecs because the loader will reject them.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25895 a1c6a512-1295-4272-9138-f99709370657

9 files changed, 119 insertions, 69 deletions

diff --git a/apps/plugins/plugin.lds b/apps/plugins/plugin.lds
index 11038109e1..fa8333ce9b 100644
--- a/apps/plugins/plugin.lds
+++ b/apps/plugins/plugin.lds
@@ -30,17 +30,16 @@ OUTPUT_FORMAT(elf32-littlemips)
 #define CACHEALIGN_SIZE 16
 #endif /* CPU_PP */
 
-#ifndef NOCACHE_BASE
-/* Default to no offset if target doesn't define this */
-#define NOCACHE_BASE 0x00000000
-#endif
+#if CONFIG_CPU==IMX31L
+/* No fudges! */
+#include "imx31l.h"
+#define DRAMSIZE ((MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGIN_BUFFER_SIZE \
+                  - CODEC_SIZE - QHARRAY_SIZE - FRAME_SIZE - TTB_SIZE)
 
-#if CONFIG_CPU==DM320 || CONFIG_CPU==IMX31L
+#elif CONFIG_CPU==DM320
 /* Give this 1 meg to allow it to align to the MMU boundary */
-#if CONFIG_CPU==DM320
 #ifndef LCD_NATIVE_WIDTH
 #define LCD_NATIVE_WIDTH LCD_WIDTH
-#endif
 
 #ifndef LCD_NATIVE_HEIGHT
 #define LCD_NATIVE_HEIGHT LCD_HEIGHT
@@ -156,6 +155,11 @@ OUTPUT_FORMAT(elf32-littlemips)
 #define DRAMORIG 0x09000000 + STUBOFFSET
 #endif
 
+#ifndef NOCACHE_BASE
+/* Default to no offset if target doesn't define this */
+#define NOCACHE_BASE 0x00000000
+#endif
+
 #define PLUGIN_LENGTH PLUGIN_BUFFER_SIZE
 
 
diff --git a/firmware/export/config.h b/firmware/export/config.h
index c3dd4fde93..070bd959b7 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -826,6 +826,11 @@ Lyre prototype 1 */
 
 #endif /* CPU_PP */
 
+#if CONFIG_CPU == IMX31L
+#define NOCACHEBSS_ATTR     __attribute__((section(".ncbss"),nocommon))
+#define NOCACHEDATA_ATTR    __attribute__((section(".ncdata"),nocommon))
+#endif
+
 #ifndef CONFIG_CORELOCK
 #define CONFIG_CORELOCK CORELOCK_NONE
 #endif
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h
index 66ae0acc4d..ea92d059cc 100644
--- a/firmware/export/imx31l.h
+++ b/firmware/export/imx31l.h
@@ -35,14 +35,18 @@
 #define FRAME_SIZE    (240*320*2)
 /* Rockbox framebuffer address, not retail OS */
 #define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE)
-#define FRAME         ((void *)(FRAME_PHYS_ADDR-CSD0_BASE_ADDR))
+#define FRAME         ((void *)(FRAME_PHYS_ADDR+0x100000-CSD0_BASE_ADDR))
+
+#define CACHEALIGN_SIZE     32
+#define NOCACHE_BASE        CSD0_BASE_ADDR
 
-#define DEVBSS_ATTR   __attribute__((section(".devbss"),nocommon))
 /* USBOTG */
 #define USB_QHARRAY_ATTR    __attribute__((section(".qharray"),nocommon,aligned(2048)))
 #define USB_NUM_ENDPOINTS   8
-#define USB_DEVBSS_ATTR     DEVBSS_ATTR
+#define USB_DEVBSS_ATTR     NOCACHEBSS_ATTR
 #define USB_BASE            OTG_BASE_ADDR
+#define QHARRAY_SIZE        ((64*USB_NUM_ENDPOINTS*2 + 2047) & (0xffffffff - 2047))
+#define QHARRAY_PHYS_ADDR   ((FRAME_PHYS_ADDR - QHARRAY_SIZE) & (0xffffffff - 2047))
 
 /*
  * AIPS 1
diff --git a/firmware/target/arm/imx31/app.lds b/firmware/target/arm/imx31/app.lds
index 4ee7ac45d4..7043a55526 100644
--- a/firmware/target/arm/imx31/app.lds
+++ b/firmware/target/arm/imx31/app.lds
@@ -17,7 +17,8 @@ STARTUP(target/arm/imx31/crt0.o)
 
 #include "imx31l.h"
 /* Subtract 1MB for the FRAME/TTB section */
-#define DRAMSIZE (MEMORYSIZE * 0x100000 - 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE
+#define DRAMSIZE ((MEMORYSIZE * 0x100000) - STUBOFFSET - CODECSIZE - \
+                  PLUGINSIZE - QHARRAY_SIZE - FRAME_SIZE - TTB_SIZE)
 
 #define DRAMORIG (0x0 + STUBOFFSET)
 /* #define IRAMORIG 0x1FFFC000 */
@@ -34,8 +35,7 @@ STARTUP(target/arm/imx31/crt0.o)
 MEMORY
 {
     DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
-    DEVBSS : ORIGIN = CSD0_BASE_ADDR + (MEMORYSIZE * 0x100000 - 0x100000), \
-             LENGTH = 0x100000 - FRAME_SIZE - TTB_SIZE
+    QHARRAY : ORIGIN = QHARRAY_PHYS_ADDR, LENGTH = QHARRAY_SIZE
 }
 
 SECTIONS
@@ -78,6 +78,17 @@ SECTIONS
         _dataend  = .;
     } > DRAM
 
+#if 0 /* Unneeded at the moment */
+    /* .ncdata section is placed at uncached physical alias address and is
+     * loaded at the proper cached virtual address - no copying is
+     * performed in the init code */
+    .ncdata . + NOCACHE_BASE :
+    {
+        . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
+        *(.ncdata*)
+        . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
+    } AT> DRAM
+#endif
     /DISCARD/ :
     {
         *(.eh_frame)
@@ -109,12 +120,22 @@ SECTIONS
         *(.ibss)
         *(COMMON)
         . = ALIGN(0x4);
-       _end = .;
+    } > DRAM
+    
+    .ncbss . + NOCACHE_BASE (NOLOAD) :
+    {
+        . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
+        *(.ncbss*)
+        . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
+    } AT> DRAM
+    
+    .endaddr . - NOCACHE_BASE (NOLOAD) :
+    {
+        _end = .;
     } > DRAM
 
     .audiobuf (NOLOAD) :
     {
-        . = ALIGN(0x4);
         _audiobuffer = .;
         audiobuffer = .;
     } > DRAM
@@ -144,12 +165,11 @@ SECTIONS
         _sdmacodeend = .;
     }
     
-    .devbss (NOLOAD) :
+    .qharray (NOLOAD) :
     {
-        _devbssdata = .;
-        *(.qharray)
-        *(.devbss*)
-        _devbssend = .;
-    } > DEVBSS
+        _qharray = .;
+        *(.qharray)
+        _qharrayend = .;
+    } > QHARRAY
 }
 
diff --git a/firmware/target/arm/imx31/ata-imx31.c b/firmware/target/arm/imx31/ata-imx31.c
index 5ce7ad0a03..4c6bebd168 100644
--- a/firmware/target/arm/imx31/ata-imx31.c
+++ b/firmware/target/arm/imx31/ata-imx31.c
@@ -249,17 +249,17 @@ static struct wakeup ata_dma_wakeup;
 
 /** SDMA **/
 /* Array of buffer descriptors for large transfers and alignnment */
-static struct buffer_descriptor ata_bda[ATA_BD_COUNT] DEVBSS_ATTR;
+static struct buffer_descriptor ata_bda[ATA_BD_COUNT] NOCACHEBSS_ATTR;
 /* ATA channel descriptors */
-static struct channel_descriptor ata_cd_rd DEVBSS_ATTR; /* read channel */
-static struct channel_descriptor ata_cd_wr DEVBSS_ATTR; /* write channel */
+static struct channel_descriptor ata_cd_rd NOCACHEBSS_ATTR; /* read channel */
+static struct channel_descriptor ata_cd_wr NOCACHEBSS_ATTR; /* write channel */
 /* DMA channel to be started for transfer */
 static unsigned int current_channel = 0;
 
 /** Buffers **/
 /* Scatter buffer for first and last 32 bytes of a non cache-aligned transfer
  * to cached RAM. */
-static uint32_t scatter_buffer[32/4*2] DEVBSS_ATTR;
+static uint32_t scatter_buffer[32/4*2] NOCACHEBSS_ATTR;
 /* Address of ends in destination buffer for unaligned reads - copied after
  * DMA completes. */
 static void *sb_dst[2] = { NULL, NULL };
diff --git a/firmware/target/arm/imx31/boot.lds b/firmware/target/arm/imx31/boot.lds
index e08b4bfb7a..6030044c85 100644
--- a/firmware/target/arm/imx31/boot.lds
+++ b/firmware/target/arm/imx31/boot.lds
@@ -19,8 +19,7 @@ STARTUP(target/arm/imx31/crt0.o)
 MEMORY
 {
    DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
-   DEVBSS : ORIGIN = CSD0_BASE_ADDR + (MEMORYSIZE*0x100000 - 0x100000), \
-            LENGTH = 0x100000 - FRAME_SIZE - TTB_SIZE
+   QHARRAY : ORIGIN = QHARRAY_PHYS_ADDR, LENGTH = QHARRAY_SIZE
 }
 
 SECTIONS
@@ -59,6 +58,18 @@ SECTIONS
         . = ALIGN(0x4);
         _dataend = . ;
     } > DRAM
+
+#if 0 /* Unneeded at the moment */
+    /* .ncdata section is placed at uncached physical alias address and is
+     * loaded at the proper cached virtual address - no copying is
+     * performed in the init code */
+    .ncdata . + NOCACHE_BASE :
+    {
+        . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
+        *(.ncdata*)
+        . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
+    } AT> DRAM
+#endif
     
     .vectors 0x0 :
     {
@@ -79,20 +90,33 @@ SECTIONS
         stackend = .;
     } > IRAM
 
+    /* .bss and .ncbss are treated as a single section to use one init loop to
+     * zero it - note "_edata" and "_end" */
     .bss (NOLOAD) :
     {
          _edata = .;
          *(.bss*);
          *(.ibss);
          *(COMMON)
-         _end = .;
+         . = ALIGN(0x4);
+    } > DRAM
+    
+    .ncbss . + NOCACHE_BASE (NOLOAD) :
+    {
+        . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
+        *(.ncbss*)
+        . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
+    } AT> DRAM
+
+    .endaddr . - NOCACHE_BASE (NOLOAD) :
+    {
+        _end = .;
     } > DRAM
-   
-    .devbss (NOLOAD) :
+
+    .qharray (NOLOAD) :
     {
-        _devbssdata = .;
-        *(.qharray)
-        *(.devbss*)
-        _devbssend = .;
-    } > DEVBSS
+        _qharray = .;
+        *(.qharray)
+        _qharrayend = .;
+    } > QHARRAY
 }
diff --git a/firmware/target/arm/imx31/crt0.S b/firmware/target/arm/imx31/crt0.S
index 3a0a0041d4..979306e264 100644
--- a/firmware/target/arm/imx31/crt0.S
+++ b/firmware/target/arm/imx31/crt0.S
@@ -134,7 +134,8 @@ remap_start:
 
     /* Set page tables */
 
-    /* Map each memory loc to itself, no cache */
+    /* Map each memory loc to itself
+     * not cached, not buffered */
                                    /* Physical address = 0x0 */
     mov     r1,      #(1 << 10)    /* superuser - r/w, user - no access */
     orr     r1, r1, #((0 <<  5)  | /* domain 0th */ \
@@ -148,27 +149,28 @@ remap_start:
     cmp     r2, r3
     blo     1b
 
-    bic     r1, r1, #0x0ff00000 /* Back up */
+    /* Bits 31:20 of r1 will be 0 due to wraparound in previous loop */
 
-    /* Map 0x80000000 -> 0x0, cached */
-    mov     r2, r5               /* TTB pointer */
-    add     r3, r5, #64*4        /* End position */
-    orr     r1, r1, #0x80000000  /* Physical address */
-    orr     r1, r1, #((1 << 3) | /* cache flag */ \
-                      (1 << 2))  /* buffer flag */
+    /* Map PA:0x80000000-0x83ffffff to VA:0x00000000-0x03f00000
+     * cached, buffered */
+    mov     r2, r5                 /* TTB pointer */
+    add     r3, r5, #64*4          /* End position */
+    orr     r1, r1, #(0x80000000 | /* Physical address */ \
+                      (1 << 3) |   /* cache flag */ \
+                      (1 << 2))    /* buffer flag */
 1:
     str     r1, [r2], #4
     add     r1, r1, #(1 << 20)
     cmp     r2, r3
     blo     1b
 
-    /* Map device section 0x83f00000 to 0x03f00000 - buffered, not cached */
-    bic     r1, r1, #0x0ff00000
-    orr     r1, r1, #0x03f00000
-    bic     r1, r1, #(1 << 3)
-    add     r2, r5, #63*4
-    str     r1, [r2]
-    
+    /* Map TTB, FRAME and QHARRAY section PA:0x83f00000-0x83ffffff to
+     * VA:0x04000000-0x040fffff
+     * not cache, buffered */
+    sub     r1, r1, #0x00100000
+    bic     r1, r1, #(1 << 3)     /* clear cache flag */
+    str     r1, [r5, #64*4]
+
     /* Enable MMU */
     mov     r0, #0
     mcr     p15, 0, r0, c8, c7, 0 /* Invalidate TLB */
@@ -249,7 +251,7 @@ remap_end:
     bl      clean_dcache_range
 #endif /* BOOTLOADER */
 
-    /* Initialise bss section to zero */
+    /* Initialise bss and ncbss sections to zero */
     ldr     r2, =_edata
     ldr     r3, =_end
     mov     r4, #0
@@ -257,15 +259,6 @@ remap_end:
     cmp     r3, r2
     strhi   r4, [r2], #4
     bhi     1b
-    
-    /* Initialise the device bss section to zero */
-    ldr     r2, =_devbssdata
-    ldr     r3, =_devbssend
-    mov     r4, #0
-1:
-    cmp     r3, r2
-    strhi   r4, [r2], #4
-    bhi     1b
 
     /* Set up some stack and munge it with 0xdeadbeef */
     ldr     sp, =stackend
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c
index 6cec3ecdd3..c0651caf51 100644
--- a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c
@@ -32,8 +32,8 @@
 #define DMA_PLAY_CH_PRIORITY 6
 #define DMA_REC_CH_PRIORITY 6
 
-static struct buffer_descriptor dma_play_bd DEVBSS_ATTR;
-static struct channel_descriptor dma_play_cd DEVBSS_ATTR;
+static struct buffer_descriptor dma_play_bd NOCACHEBSS_ATTR;
+static struct channel_descriptor dma_play_cd NOCACHEBSS_ATTR;
 
 struct dma_data
 {
@@ -315,7 +315,7 @@ void pcm_play_dma_pause(bool pause)
 /* Return the number of bytes waiting - full L-R sample pairs only */
 size_t pcm_get_bytes_waiting(void)
 {
-    static unsigned long dsa DEVBSS_ATTR;
+    static unsigned long dsa NOCACHEBSS_ATTR;
     long offs, size;
     int oldstatus;
 
@@ -339,7 +339,7 @@ size_t pcm_get_bytes_waiting(void)
 /* Return a pointer to the samples and the number of them in *count */
 const void * pcm_play_dma_get_peak_buffer(int *count)
 {
-    static unsigned long dsa DEVBSS_ATTR;
+    static unsigned long dsa NOCACHEBSS_ATTR;
     unsigned long addr;
     long offs, size;
     int oldstatus;
@@ -370,8 +370,8 @@ void * pcm_dma_addr(void *addr)
 }
 
 #ifdef HAVE_RECORDING
-static struct buffer_descriptor dma_rec_bd DEVBSS_ATTR;
-static struct channel_descriptor dma_rec_cd DEVBSS_ATTR;
+static struct buffer_descriptor dma_rec_bd NOCACHEBSS_ATTR;
+static struct channel_descriptor dma_rec_cd NOCACHEBSS_ATTR;
 
 static struct dma_data dma_rec_data =
 {
@@ -526,7 +526,7 @@ void pcm_rec_dma_init(void)
 
 const void * pcm_rec_dma_get_peak_buffer(int *count)
 {
-    static unsigned long pda DEVBSS_ATTR;
+    static unsigned long pda NOCACHEBSS_ATTR;
     unsigned long buf, addr, end, bufend;
     int oldstatus;
 
diff --git a/firmware/target/arm/imx31/sdma-imx31.c b/firmware/target/arm/imx31/sdma-imx31.c
index 40a43f8121..a877d5824b 100644
--- a/firmware/target/arm/imx31/sdma-imx31.c
+++ b/firmware/target/arm/imx31/sdma-imx31.c
@@ -40,9 +40,9 @@ static struct sdma_script_start_addrs script_info;
 /* Mask of channels with callback enabled */
 static unsigned long sdma_enabled_ints = 0;
 /* One channel control block per channel in physically mapped device RAM */
-static struct channel_control_block ccb_array[CH_NUM] DEVBSS_ATTR;
+static struct channel_control_block ccb_array[CH_NUM] NOCACHEBSS_ATTR;
 /* Channel 0 (command channel) data */
-static struct buffer_descriptor_extd c0_buffer_desc DEVBSS_ATTR;
+static struct buffer_descriptor_extd c0_buffer_desc NOCACHEBSS_ATTR;
 
 /* All SDMA channel interrupts are handled here.
  * Dispatches lower channel numbers first (prioritized by SDMA API callers