Add cleaned-up xDuoo X3 support

Cleaned up, rebased, and forward-ported from the xvortex fork.

(original credit to vsoftster@gmail.com)

Change-Id: Ibcc023a0271ea81e901450a88317708c2683236d
Signed-off-by: Solomon Peachy <pizza@shaftnet.org>

114 files changed, 17349 insertions, 102 deletions

diff --git a/apps/SOURCES b/apps/SOURCES
index de633880f6..a84c01977f 100644
--- a/apps/SOURCES
+++ b/apps/SOURCES
@@ -317,4 +317,6 @@ keymaps/keymap-ypr1.c
 keymaps/keymap-dx50.c
 #elif CONFIG_KEYPAD == AGPTEK_ROCKER_PAD
 keymaps/keymap-agptekrocker.c
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+keymaps/keymap-xduoox3.c
 #endif
diff --git a/apps/keymaps/keymap-xduoox3.c b/apps/keymaps/keymap-xduoox3.c
new file mode 100644
index 0000000000..abe8507cd8
--- /dev/null
+++ b/apps/keymaps/keymap-xduoox3.c
@@ -0,0 +1,212 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/* Button Code Definitions for xDuoo X3 target */
+
+#include "config.h"
+#include "action.h"
+#include "button.h"
+#include "settings.h"
+
+/* {Action Code,    Button code,    Prereq button code } */
+
+/*
+ * The format of the list is as follows
+ * { Action Code,   Button code,    Prereq button code }
+ * if there's no need to check the previous button's value, use BUTTON_NONE
+ * Insert LAST_ITEM_IN_LIST at the end of each mapping
+ */
+static const struct button_mapping button_context_standard[] = {
+    { ACTION_STD_PREV,        BUTTON_PREV,                      BUTTON_NONE },
+    { ACTION_STD_PREVREPEAT,  BUTTON_PREV|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_STD_NEXT,        BUTTON_NEXT,                      BUTTON_NONE },
+    { ACTION_STD_NEXTREPEAT,  BUTTON_NEXT|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_STD_CONTEXT,     BUTTON_PLAY|BUTTON_REPEAT,        BUTTON_PLAY },
+    { ACTION_STD_CANCEL,      BUTTON_OPTION|BUTTON_REL,         BUTTON_OPTION },
+    { ACTION_STD_OK,          BUTTON_PLAY|BUTTON_REL,           BUTTON_PLAY },
+    { ACTION_STD_MENU,        BUTTON_HOME|BUTTON_REL,           BUTTON_HOME },
+
+    LAST_ITEM_IN_LIST
+}; /* button_context_standard */
+
+static const struct button_mapping button_context_wps[] = {
+    { ACTION_WPS_PLAY,        BUTTON_PLAY|BUTTON_REL,           BUTTON_PLAY },
+    { ACTION_WPS_STOP,        BUTTON_POWER|BUTTON_REL,          BUTTON_POWER },
+    { ACTION_WPS_SKIPPREV,    BUTTON_PREV|BUTTON_REL,           BUTTON_PREV },
+    { ACTION_WPS_SEEKBACK,    BUTTON_PREV|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_WPS_STOPSEEK,    BUTTON_PREV|BUTTON_REL,           BUTTON_PREV|BUTTON_REPEAT },
+    { ACTION_WPS_SKIPNEXT,    BUTTON_NEXT|BUTTON_REL,           BUTTON_NEXT },
+    { ACTION_WPS_SEEKFWD,     BUTTON_NEXT|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_WPS_STOPSEEK,    BUTTON_NEXT|BUTTON_REL,           BUTTON_NEXT|BUTTON_REPEAT },
+    { ACTION_WPS_VOLUP,       BUTTON_VOL_UP,                    BUTTON_NONE },
+    { ACTION_WPS_VOLUP,       BUTTON_VOL_UP|BUTTON_REPEAT,      BUTTON_NONE },
+    { ACTION_WPS_VOLDOWN,     BUTTON_VOL_DOWN,                  BUTTON_NONE },
+    { ACTION_WPS_VOLDOWN,     BUTTON_VOL_DOWN|BUTTON_REPEAT,    BUTTON_NONE },
+    { ACTION_WPS_BROWSE,      BUTTON_OPTION|BUTTON_REL,         BUTTON_OPTION },
+    { ACTION_WPS_CONTEXT,     BUTTON_PLAY|BUTTON_REPEAT,        BUTTON_PLAY },
+    { ACTION_WPS_MENU,        BUTTON_HOME|BUTTON_REL,           BUTTON_HOME },
+    { ACTION_WPS_QUICKSCREEN, BUTTON_HOME|BUTTON_REPEAT,        BUTTON_HOME },
+    { ACTION_WPS_HOTKEY,      BUTTON_OPTION|BUTTON_REPEAT,      BUTTON_OPTION },
+
+    LAST_ITEM_IN_LIST
+}; /* button_context_wps */
+
+static const struct button_mapping button_context_list[] = {
+    { ACTION_LIST_VOLUP,      BUTTON_VOL_UP,                    BUTTON_NONE },
+    { ACTION_LIST_VOLUP,      BUTTON_VOL_UP|BUTTON_REPEAT,      BUTTON_NONE },
+    { ACTION_LIST_VOLDOWN,    BUTTON_VOL_DOWN,                  BUTTON_NONE },
+    { ACTION_LIST_VOLDOWN,    BUTTON_VOL_DOWN|BUTTON_REPEAT,    BUTTON_NONE },
+
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_list */
+
+/** Bookmark Screen **/
+static const struct button_mapping button_context_bmark[] = {
+    { ACTION_BMS_DELETE,      BUTTON_PLAY|BUTTON_REPEAT,        BUTTON_PLAY },
+
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_LIST)
+}; /* button_context_bmark */
+
+/** Keyboard **/
+static const struct button_mapping button_context_keyboard[] = {
+    { ACTION_KBD_LEFT,        BUTTON_PREV,                      BUTTON_NONE },
+    { ACTION_KBD_LEFT,        BUTTON_PREV|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_KBD_RIGHT,       BUTTON_NEXT,                      BUTTON_NONE },
+    { ACTION_KBD_RIGHT,       BUTTON_NEXT|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_KBD_DOWN,        BUTTON_OPTION,                    BUTTON_NONE },
+    { ACTION_KBD_DOWN,        BUTTON_OPTION|BUTTON_REPEAT,      BUTTON_NONE },
+    { ACTION_KBD_CURSOR_LEFT, BUTTON_VOL_UP,                    BUTTON_NONE },
+    { ACTION_KBD_CURSOR_LEFT, BUTTON_VOL_UP|BUTTON_REPEAT,      BUTTON_NONE },
+    { ACTION_KBD_CURSOR_RIGHT, BUTTON_VOL_DOWN,                 BUTTON_NONE },
+    { ACTION_KBD_CURSOR_RIGHT, BUTTON_VOL_DOWN|BUTTON_REPEAT,   BUTTON_NONE },
+    { ACTION_KBD_BACKSPACE,   BUTTON_HOME,                      BUTTON_NONE },
+    { ACTION_KBD_BACKSPACE,   BUTTON_HOME|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_KBD_SELECT,      BUTTON_PLAY|BUTTON_REL,           BUTTON_PLAY },
+    { ACTION_KBD_DONE,        BUTTON_PLAY|BUTTON_REPEAT,        BUTTON_PLAY },
+    { ACTION_KBD_ABORT,       BUTTON_POWER|BUTTON_REL,          BUTTON_POWER },
+
+    LAST_ITEM_IN_LIST
+}; /* button_context_keyboard */
+
+/** Pitchscreen **/
+static const struct button_mapping button_context_pitchscreen[] = {
+    { ACTION_PS_INC_SMALL,    BUTTON_VOL_UP,                    BUTTON_NONE },
+    { ACTION_PS_INC_BIG,      BUTTON_VOL_UP|BUTTON_REPEAT,      BUTTON_NONE },
+    { ACTION_PS_DEC_SMALL,    BUTTON_VOL_DOWN,                  BUTTON_NONE },
+    { ACTION_PS_DEC_BIG,      BUTTON_VOL_DOWN|BUTTON_REPEAT,    BUTTON_NONE },   
+    { ACTION_PS_NUDGE_LEFT,   BUTTON_PREV,                      BUTTON_NONE },
+    { ACTION_PS_NUDGE_LEFTOFF, BUTTON_PREV|BUTTON_REL,          BUTTON_NONE },
+    { ACTION_PS_NUDGE_RIGHT,  BUTTON_NEXT,                      BUTTON_NONE },
+    { ACTION_PS_NUDGE_RIGHTOFF, BUTTON_NEXT|BUTTON_REL,         BUTTON_NONE },
+    { ACTION_PS_TOGGLE_MODE,  BUTTON_PLAY|BUTTON_REL,           BUTTON_NONE },
+    { ACTION_PS_RESET,        BUTTON_POWER|BUTTON_REL,          BUTTON_POWER },
+    { ACTION_PS_EXIT,         BUTTON_OPTION|BUTTON_REL,         BUTTON_OPTION },
+
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_pitchscreen */
+
+/** Quickscreen **/
+static const struct button_mapping button_context_quickscreen[] = {
+    { ACTION_QS_TOP,          BUTTON_VOL_UP,                    BUTTON_NONE },
+    { ACTION_QS_TOP,          BUTTON_VOL_UP|BUTTON_REPEAT,      BUTTON_NONE },
+    { ACTION_QS_DOWN,         BUTTON_VOL_DOWN,                  BUTTON_NONE },
+    { ACTION_QS_DOWN,         BUTTON_VOL_DOWN|BUTTON_REPEAT,    BUTTON_NONE },
+    { ACTION_QS_LEFT,         BUTTON_PREV,                      BUTTON_NONE },
+    { ACTION_QS_LEFT,         BUTTON_PREV|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_QS_RIGHT,        BUTTON_NEXT,                      BUTTON_NONE },
+    { ACTION_QS_RIGHT,        BUTTON_NEXT|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_STD_CANCEL,      BUTTON_HOME|BUTTON_REL,           BUTTON_HOME },
+
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_quickscreen */
+
+/** Settings - General Mappings **/
+static const struct button_mapping button_context_settings[] = {
+    { ACTION_SETTINGS_RESET,  BUTTON_POWER|BUTTON_REL,          BUTTON_POWER },
+    { ACTION_STD_PREV,        BUTTON_PREV,                      BUTTON_NONE },
+    { ACTION_STD_PREVREPEAT,  BUTTON_PREV|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_STD_NEXT,        BUTTON_NEXT,                      BUTTON_NONE },
+    { ACTION_STD_NEXTREPEAT,  BUTTON_NEXT|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_STD_OK,          BUTTON_PLAY|BUTTON_REL,           BUTTON_PLAY },
+    { ACTION_STD_CANCEL,      BUTTON_OPTION|BUTTON_REL,         BUTTON_OPTION },
+
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_settings */
+
+static const struct button_mapping button_context_settings_vol_is_inc[] = {
+    { ACTION_SETTINGS_INC,    BUTTON_VOL_UP,                    BUTTON_NONE },
+    { ACTION_SETTINGS_INCREPEAT,BUTTON_VOL_UP|BUTTON_REPEAT,    BUTTON_NONE },
+    { ACTION_SETTINGS_DEC,    BUTTON_VOL_DOWN,                  BUTTON_NONE },
+    { ACTION_SETTINGS_DECREPEAT,BUTTON_VOL_DOWN|BUTTON_REPEAT,  BUTTON_NONE },
+
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_settings_right_is_inc */
+
+/** Tree **/
+static const struct button_mapping button_context_tree[] = {
+    { ACTION_TREE_WPS,        BUTTON_HOME|BUTTON_REL,           BUTTON_HOME },
+    { ACTION_TREE_STOP,       BUTTON_POWER|BUTTON_REL,          BUTTON_POWER },
+    { ACTION_TREE_HOTKEY,     BUTTON_OPTION|BUTTON_REPEAT,      BUTTON_OPTION },
+
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_LIST)
+}; /* button_context_tree */
+
+/** Yes/No Screen **/
+static const struct button_mapping button_context_yesnoscreen[] = {
+    { ACTION_YESNO_ACCEPT,    BUTTON_PLAY,                      BUTTON_NONE },
+
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_settings_yesnoscreen */
+
+/* get_context_mapping returns a pointer to one of the above defined arrays depending on the context */
+const struct button_mapping* get_context_mapping(int context)
+{
+    switch (context)
+    {
+        case CONTEXT_LIST:
+            return button_context_list;
+        case CONTEXT_STD:
+            return button_context_standard;
+        case CONTEXT_BOOKMARKSCREEN:
+            return button_context_bmark;
+        case CONTEXT_KEYBOARD:
+            return button_context_keyboard;
+        case CONTEXT_PITCHSCREEN:
+            return button_context_pitchscreen;
+        case CONTEXT_QUICKSCREEN:
+            return button_context_quickscreen;
+        case CONTEXT_SETTINGS:
+            return button_context_settings;
+        case CONTEXT_SETTINGS_TIME:
+        case CONTEXT_SETTINGS_COLOURCHOOSER:
+        case CONTEXT_SETTINGS_EQ:
+        case CONTEXT_SETTINGS_RECTRIGGER:
+            return button_context_settings_vol_is_inc;
+        case CONTEXT_TREE:
+        case CONTEXT_MAINMENU:
+            return button_context_tree;
+        case CONTEXT_WPS:
+            return button_context_wps;
+        case CONTEXT_YESNOSCREEN:
+            return button_context_yesnoscreen;
+    }
+    return button_context_standard;
+}
diff --git a/apps/menus/sound_menu.c b/apps/menus/sound_menu.c
index 69e8e3676a..489d03bf4d 100644
--- a/apps/menus/sound_menu.c
+++ b/apps/menus/sound_menu.c
@@ -132,6 +132,10 @@ MENUITEM_SETTING(depth_3d, &global_settings.depth_3d, NULL);
 MENUITEM_SETTING(roll_off, &global_settings.roll_off, NULL);
 #endif
 
+#ifdef AUDIOHW_HAVE_FUNCTIONAL_MODE
+MENUITEM_SETTING(func_mode, &global_settings.func_mode, NULL);
+#endif
+
 #if CONFIG_CODEC == SWCODEC
     /* Crossfeed Submenu */
     MENUITEM_SETTING(crossfeed, &global_settings.crossfeed, lowlatency_callback);
@@ -256,6 +260,9 @@ MAKE_MENU(sound_settings, ID2P(LANG_SOUND_SETTINGS), NULL, Icon_Audio,
 #ifdef AUDIOHW_HAVE_FILTER_ROLL_OFF
           ,&roll_off
 #endif
+#ifdef AUDIOHW_HAVE_FUNCTIONAL_MODE
+          ,&func_mode
+#endif
 #if CONFIG_CODEC == SWCODEC
           ,&crossfeed_menu, &equalizer_menu, &dithering_enabled
           ,&surround_menu, &pbe_menu, &afr_enabled
diff --git a/apps/plugins/battery_bench.c b/apps/plugins/battery_bench.c
index bb9c3b0e6f..9a48ef2fdb 100644
--- a/apps/plugins/battery_bench.c
+++ b/apps/plugins/battery_bench.c
@@ -279,6 +279,12 @@
 #define BATTERY_OFF_TXT "Right"
 #define BATTERY_ON_TXT  "Left - start"
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define BATTERY_ON      BUTTON_PLAY
+#define BATTERY_OFF     BUTTON_POWER
+#define BATTERY_ON_TXT  "PLAY - start"
+#define BATTERY_OFF_TXT "POWER"
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/blackjack.c b/apps/plugins/blackjack.c
index 411ff3970b..6c3e487bf2 100644
--- a/apps/plugins/blackjack.c
+++ b/apps/plugins/blackjack.c
@@ -573,6 +573,22 @@ enum {
 #define BJACK_QUIT_NAME     "Volume up"
 #define BJACK_DOUBLE_NAME   "Option+Down"
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define BJACK_SELECT_NAME   "PLAY"
+#define BJACK_STAY_NAME     "NEXT"
+#define BJACK_QUIT_NAME     "POWER"
+#define BJACK_DOUBLE_NAME   "PREV"
+#define BJACK_SELECT        BUTTON_PLAY
+#define BJACK_QUIT          BUTTON_POWER
+#define BJACK_MAX           BUTTON_VOL_UP
+#define BJACK_MIN           BUTTON_VOL_DOWN
+#define BJACK_STAY          BUTTON_NEXT
+#define BJACK_DOUBLEDOWN    BUTTON_PREV
+#define BJACK_UP            BUTTON_HOME
+#define BJACK_DOWN          BUTTON_OPTION
+#define BJACK_RIGHT         BUTTON_NEXT
+#define BJACK_LEFT          BUTTON_PREV
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/brickmania.c b/apps/plugins/brickmania.c
index 3fc30819b9..24c6fab613 100644
--- a/apps/plugins/brickmania.c
+++ b/apps/plugins/brickmania.c
@@ -332,6 +332,16 @@ CONFIG_KEYPAD == SANSA_CONNECT_PAD
 #define UP        BUTTON_UP
 #define DOWN      BUTTON_DOWN
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define QUIT      BUTTON_POWER
+#define LEFT      BUTTON_PREV
+#define RIGHT     BUTTON_NEXT
+#define ALTLEFT   BUTTON_VOL_DOWN
+#define ALTRIGHT  BUTTON_VOL_UP
+#define SELECT    BUTTON_PLAY
+#define UP        BUTTON_HOME
+#define DOWN      BUTTON_OPTION
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/calculator.c b/apps/plugins/calculator.c
index a30ccdc83d..f10bca66ec 100644
--- a/apps/plugins/calculator.c
+++ b/apps/plugins/calculator.c
@@ -525,6 +525,17 @@ F3: equal to "="
 #define CALCULATOR_CALC    BUTTON_VOLUP
 #define CALCULATOR_CLEAR   (BUTTON_SELECT|BUTTON_REPEAT)
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define CALCULATOR_LEFT      BUTTON_PREV
+#define CALCULATOR_RIGHT     BUTTON_NEXT
+#define CALCULATOR_UP        BUTTON_HOME
+#define CALCULATOR_DOWN      BUTTON_OPTION
+#define CALCULATOR_QUIT      BUTTON_POWER
+#define CALCULATOR_INPUT_CALC_PRE (BUTTON_OPTION|BUTTON_REPEAT)
+#define CALCULATOR_INPUT     (BUTTON_PLAY|BUTTON_REL)
+#define CALCULATOR_CALC      (BUTTON_PLAY|BUTTON_REPEAT)
+#define CALCULATOR_CLEAR     (BUTTON_POWER|BUTTON_REPEAT)
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/calendar.c b/apps/plugins/calendar.c
index 23446beb40..74ee49904b 100644
--- a/apps/plugins/calendar.c
+++ b/apps/plugins/calendar.c
@@ -413,6 +413,16 @@
 #define CALENDAR_NEXT_MONTH  (BUTTON_VOLDOWN)
 #define CALENDAR_PREV_MONTH  (BUTTON_VOLUP)
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define CALENDAR_QUIT       BUTTON_POWER
+#define CALENDAR_SELECT     BUTTON_PLAY
+#define CALENDAR_NEXT_WEEK  BUTTON_OPTION
+#define CALENDAR_PREV_WEEK  BUTTON_HOME
+#define CALENDAR_NEXT_DAY   BUTTON_NEXT
+#define CALENDAR_PREV_DAY   BUTTON_PREV
+#define CALENDAR_NEXT_MONTH BUTTON_VOL_UP
+#define CALENDAR_PREV_MONTH BUTTON_VOL_DOWN
+
 #else
 #error "No keypad setting."
 #endif
diff --git a/apps/plugins/chessbox/chessbox_pgn.h b/apps/plugins/chessbox/chessbox_pgn.h
index fe50297732..1f44d1b712 100644
--- a/apps/plugins/chessbox/chessbox_pgn.h
+++ b/apps/plugins/chessbox/chessbox_pgn.h
@@ -558,6 +558,20 @@
 #define CB_SCROLL_LEFT   (BUTTON_LEFT|BUTTON_REPEAT)
 #define CB_SCROLL_RIGHT  (BUTTON_RIGHT|BUTTON_REPEAT)
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define CB_SELECT  BUTTON_PLAY
+#define CB_UP      BUTTON_HOME
+#define CB_DOWN    BUTTON_OPTION
+#define CB_LEFT    BUTTON_PREV
+#define CB_RIGHT   BUTTON_NEXT
+#define CB_PLAY    BUTTON_VOL_UP
+#define CB_LEVEL   (BUTTON_PLAY|BUTTON_REPEAT)
+#define CB_MENU    BUTTON_POWER
+#define CB_SCROLL_UP     (BUTTON_HOME|BUTTON_REPEAT)
+#define CB_SCROLL_DOWN   (BUTTON_OPTION|BUTTON_REPEAT)
+#define CB_SCROLL_LEFT   (BUTTON_PREV|BUTTON_REPEAT)
+#define CB_SCROLL_RIGHT  (BUTTON_NEXT|BUTTON_REPEAT)
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/chessclock.c b/apps/plugins/chessclock.c
index bc907feec3..ae7889ed95 100644
--- a/apps/plugins/chessclock.c
+++ b/apps/plugins/chessclock.c
@@ -412,6 +412,16 @@
 #define CHC_SETTINGS_CANCEL BUTTON_RIGHT
 #define CHC_SETTINGS_OK     (BUTTON_SELECT|BUTTON_REPEAT)
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define CHC_QUIT            BUTTON_POWER
+#define CHC_STARTSTOP       BUTTON_PLAY
+#define CHC_RESET           BUTTON_OPTION
+#define CHC_MENU            BUTTON_HOME
+#define CHC_SETTINGS_INC    BUTTON_NEXT
+#define CHC_SETTINGS_DEC    BUTTON_PREV
+#define CHC_SETTINGS_OK     BUTTON_PLAY
+#define CHC_SETTINGS_CANCEL BUTTON_POWER
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/chip8.c b/apps/plugins/chip8.c
index 5fb55ae011..153558667e 100644
--- a/apps/plugins/chip8.c
+++ b/apps/plugins/chip8.c
@@ -1283,6 +1283,14 @@ CONFIG_KEYPAD == MROBE500_PAD
 #define CHIP8_KEY6    BUTTON_RIGHT
 #define CHIP8_KEY8    BUTTON_LEFT
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define CHIP8_OFF  BUTTON_POWER
+#define CHIP8_KEY2 BUTTON_HOME
+#define CHIP8_KEY4 BUTTON_PREV
+#define CHIP8_KEY5 BUTTON_PLAY
+#define CHIP8_KEY6 BUTTON_NEXT
+#define CHIP8_KEY8 BUTTON_OPTION
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/chopper.c b/apps/plugins/chopper.c
index 4a838c44ae..1732a16ecb 100644
--- a/apps/plugins/chopper.c
+++ b/apps/plugins/chopper.c
@@ -209,6 +209,10 @@ CONFIG_KEYPAD == MROBE500_PAD
 #define ACTION     BUTTON_SELECT
 #define ACTIONTEXT "Select"
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define QUIT       BUTTON_POWER
+#define ACTION     BUTTON_PLAY
+#define ACTIONTEXT "PLAY"
 
 #elif !defined(HAVE_TOUCHSCREEN)
 #error No keymap defined!
diff --git a/apps/plugins/clix.c b/apps/plugins/clix.c
index b47fe69952..b2580a1630 100644
--- a/apps/plugins/clix.c
+++ b/apps/plugins/clix.c
@@ -276,6 +276,14 @@
 #define CLIX_BUTTON_RIGHT         BUTTON_RIGHT
 #define CLIX_BUTTON_CLICK         BUTTON_SELECT
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define CLIX_BUTTON_QUIT          BUTTON_POWER
+#define CLIX_BUTTON_UP            BUTTON_HOME
+#define CLIX_BUTTON_DOWN          BUTTON_OPTION
+#define CLIX_BUTTON_LEFT          BUTTON_PREV
+#define CLIX_BUTTON_RIGHT         BUTTON_NEXT
+#define CLIX_BUTTON_CLICK         BUTTON_PLAY
+
 #else
 #error "no keymap"
 #endif
diff --git a/apps/plugins/cube.c b/apps/plugins/cube.c
index 04cb013f26..9a67c337d1 100644
--- a/apps/plugins/cube.c
+++ b/apps/plugins/cube.c
@@ -413,6 +413,16 @@
 #define CUBE_HIGHSPEED     (BUTTON_SELECT | BUTTON_REPEAT)
 #define CUBE_PAUSE         (BUTTON_LEFT | BUTTON_REPEAT)
 
+#elif (CONFIG_KEYPAD == XDUOO_X3_PAD)
+#define CUBE_QUIT          BUTTON_POWER
+#define CUBE_NEXT          BUTTON_NEXT
+#define CUBE_PREV          BUTTON_PREV
+#define CUBE_INC           BUTTON_VOL_UP
+#define CUBE_DEC           BUTTON_VOL_DOWN
+#define CUBE_MODE          BUTTON_OPTION
+#define CUBE_PAUSE         BUTTON_HOME
+#define CUBE_HIGHSPEED     BUTTON_PLAY
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/doom/i_video.c b/apps/plugins/doom/i_video.c
index 5535f08b6e..d734e1e12b 100644
--- a/apps/plugins/doom/i_video.c
+++ b/apps/plugins/doom/i_video.c
@@ -555,6 +555,17 @@ void I_ShutdownGraphics(void)
 #define DOOMBUTTON_WEAPON  BUTTON_VOLUP
 #define DOOMBUTTON_MAP     (BUTTON_VOLUP|BUTTON_REPEAT)
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define DOOMBUTTON_UP      BUTTON_HOME
+#define DOOMBUTTON_DOWN    BUTTON_OPTION
+#define DOOMBUTTON_LEFT    BUTTON_PREV
+#define DOOMBUTTON_RIGHT   BUTTON_NEXT
+#define DOOMBUTTON_SHOOT   BUTTON_PLAY
+#define DOOMBUTTON_OPEN    (BUTTON_HOME | BUTTON_POWER)
+#define DOOMBUTTON_ESC     BUTTON_POWER
+#define DOOMBUTTON_ENTER   BUTTON_PLAY
+#define DOOMBUTTON_WEAPON  BUTTON_VOL_UP
+
 #else
 #error Keymap not defined!
 #endif
diff --git a/apps/plugins/fft/fft.c b/apps/plugins/fft/fft.c
index a83bd36557..e5750c109a 100644
--- a/apps/plugins/fft/fft.c
+++ b/apps/plugins/fft/fft.c
@@ -334,6 +334,15 @@ GREY_INFO_STRUCT
 #   define FFT_ORIENTATION  BUTTON_SELECT
 #   define FFT_WINDOW       BUTTON_VOLDOWN
 
+#elif (CONFIG_KEYPAD == XDUOO_X3_PAD)
+#   define FFT_PREV_GRAPH   BUTTON_PREV
+#   define FFT_NEXT_GRAPH   BUTTON_NEXT
+#   define FFT_ORIENTATION  BUTTON_HOME
+#   define FFT_FREQ_SCALE   BUTTON_OPTION
+#   define FFT_WINDOW       (BUTTON_HOME|BUTTON_POWER)
+#   define FFT_AMP_SCALE    BUTTON_PLAY
+#   define FFT_QUIT         BUTTON_POWER
+
 #elif !defined(HAVE_TOUCHSCREEN)
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/flipit.c b/apps/plugins/flipit.c
index fafc1f9c08..b089974aef 100644
--- a/apps/plugins/flipit.c
+++ b/apps/plugins/flipit.c
@@ -482,6 +482,18 @@
 #define FLIPIT_STEP_BY_STEP (BUTTON_LEFT|BUTTON_VOLUP)
 #define FLIPIT_TOGGLE       BUTTON_SELECT
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+
+#define FLIPIT_LEFT         BUTTON_PREV
+#define FLIPIT_RIGHT        BUTTON_NEXT
+#define FLIPIT_UP           BUTTON_HOME
+#define FLIPIT_DOWN         BUTTON_OPTION
+#define FLIPIT_QUIT         BUTTON_POWER
+#define FLIPIT_SHUFFLE      (BUTTON_HOME | BUTTON_PREV)
+#define FLIPIT_SOLVE        (BUTTON_HOME | BUTTON_NEXT)
+#define FLIPIT_STEP_BY_STEP (BUTTON_HOME | BUTTON_PLAY)
+#define FLIPIT_TOGGLE       BUTTON_PLAY
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/fractals/fractal.h b/apps/plugins/fractals/fractal.h
index aa8c31f093..ed6be31695 100644
--- a/apps/plugins/fractals/fractal.h
+++ b/apps/plugins/fractals/fractal.h
@@ -484,6 +484,18 @@
 #define FRACTAL_PRECISION_DEC   (BUTTON_VOLUP|BUTTON_LEFT)
 #define FRACTAL_RESET           BUTTON_SELECT
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define FRACTAL_QUIT            BUTTON_POWER
+#define FRACTAL_UP              BUTTON_HOME
+#define FRACTAL_DOWN            BUTTON_OPTION
+#define FRACTAL_LEFT            BUTTON_PREV
+#define FRACTAL_RIGHT           BUTTON_NEXT
+#define FRACTAL_ZOOM_IN         BUTTON_VOL_UP
+#define FRACTAL_ZOOM_OUT        BUTTON_VOL_DOWN
+#define FRACTAL_PRECISION_INC   (BUTTON_PLAY | BUTTON_NEXT)
+#define FRACTAL_PRECISION_DEC   (BUTTON_PLAY | BUTTON_PREV)
+#define FRACTAL_RESET           (BUTTON_HOME | BUTTON_POWER)
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/goban/goban.h b/apps/plugins/goban/goban.h
index 135b9dbe95..d1d66e3535 100644
--- a/apps/plugins/goban/goban.h
+++ b/apps/plugins/goban/goban.h
@@ -452,6 +452,18 @@
 #define  GBN_BUTTON_PLAY               (BUTTON_SELECT | BUTTON_REL)
 #define  GBN_BUTTON_NAV_MODE           BUTTON_VOLUP
 
+#elif (CONFIG_KEYPAD == XDUOO_X3_PAD)
+#define  GBN_BUTTON_UP                 BUTTON_HOME
+#define  GBN_BUTTON_DOWN               BUTTON_OPTION
+#define  GBN_BUTTON_LEFT               BUTTON_PREV
+#define  GBN_BUTTON_RIGHT              BUTTON_NEXT
+#define  GBN_BUTTON_RETREAT            BUTTON_VOL_DOWN
+#define  GBN_BUTTON_ADVANCE            BUTTON_VOL_UP
+#define  GBN_BUTTON_MENU               BUTTON_POWER
+#define  GBN_BUTTON_PLAY               BUTTON_PLAY | BUTTON_REL
+#define  GBN_BUTTON_CONTEXT            BUTTON_PLAY | BUTTON_REPEAT
+#define  GBN_BUTTON_NEXT_VAR           BUTTON_HOME | BUTTON_POWER
+
 #else
 #error Unsupported keypad
 #endif
diff --git a/apps/plugins/greyscale.c b/apps/plugins/greyscale.c
index 4dd29cee0b..ae873a06ac 100644
--- a/apps/plugins/greyscale.c
+++ b/apps/plugins/greyscale.c
@@ -108,6 +108,14 @@
 #define GREYSCALE_RIGHT BUTTON_RIGHT
 #define GREYSCALE_OFF   BUTTON_PLAY
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define GREYSCALE_SHIFT BUTTON_PLAY
+#define GREYSCALE_UP    BUTTON_HOME
+#define GREYSCALE_DOWN  BUTTON_OPTION
+#define GREYSCALE_LEFT  BUTTON_PREV
+#define GREYSCALE_RIGHT BUTTON_NEXT
+#define GREYSCALE_OFF   BUTTON_POWER
+
 #endif
 
 #define GFX_HEIGHT (LCD_HEIGHT-8)
diff --git a/apps/plugins/imageviewer/imageviewer_button.h b/apps/plugins/imageviewer/imageviewer_button.h
index abd84f1710..2f349b1a24 100644
--- a/apps/plugins/imageviewer/imageviewer_button.h
+++ b/apps/plugins/imageviewer/imageviewer_button.h
@@ -495,6 +495,21 @@
 #define IMGVIEW_QUIT        (BUTTON_POWER|BUTTON_REL)
 #define IMGVIEW_MENU        (BUTTON_SELECT|BUTTON_REL)
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define IMGVIEW_ZOOM_PRE    BUTTON_PLAY
+#define IMGVIEW_ZOOM_IN     (BUTTON_PLAY | BUTTON_REL)
+#define IMGVIEW_ZOOM_OUT    (BUTTON_PLAY | BUTTON_REPEAT)
+#define IMGVIEW_UP          BUTTON_HOME
+#define IMGVIEW_DOWN        BUTTON_OPTION
+#define IMGVIEW_LEFT        BUTTON_PREV
+#define IMGVIEW_RIGHT       BUTTON_NEXT
+#define IMGVIEW_NEXT        BUTTON_VOL_UP
+#define IMGVIEW_NEXT_REPEAT (BUTTON_VOL_UP|BUTTON_REPEAT)
+#define IMGVIEW_PREVIOUS    BUTTON_VOL_DOWN
+#define IMGVIEW_PREVIOUS_REPEAT (BUTTON_VOL_DOWN|BUTTON_REPEAT)
+#define IMGVIEW_MENU        BUTTON_POWER
+#define IMGVIEW_SLIDE_SHOW  (BUTTON_HOME|BUTTON_POWER)
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/jewels.c b/apps/plugins/jewels.c
index 97531a001c..e4a22830a1 100644
--- a/apps/plugins/jewels.c
+++ b/apps/plugins/jewels.c
@@ -377,6 +377,16 @@ CONFIG_KEYPAD == MROBE500_PAD
 #define JEWELS_CANCEL BUTTON_POWER
 #define HK_CANCEL "Power"
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define JEWELS_UP     BUTTON_HOME
+#define JEWELS_DOWN   BUTTON_OPTION
+#define JEWELS_LEFT   BUTTON_PREV
+#define JEWELS_RIGHT  BUTTON_NEXT
+#define JEWELS_SELECT BUTTON_PLAY
+#define JEWELS_CANCEL BUTTON_POWER
+#define HK_SELECT "PLAY"
+#define HK_CANCEL "POWER"
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/lib/keymaps.h b/apps/plugins/lib/keymaps.h
index 64deccf513..5fab361620 100644
--- a/apps/plugins/lib/keymaps.h
+++ b/apps/plugins/lib/keymaps.h
@@ -215,6 +215,14 @@
 #define BTN_FIRE       BUTTON_MENU
 #define BTN_PAUSE      BUTTON_POWER
 
+#elif (CONFIG_KEYPAD == XDUOO_X3_PAD)
+#define BTN_UP         BUTTON_VOL_UP
+#define BTN_DOWN       BUTTON_VOL_DOWN
+#define BTN_LEFT       BUTTON_PREV
+#define BTN_RIGHT      BUTTON_NEXT
+#define BTN_FIRE       BUTTON_PLAY
+#define BTN_PAUSE      BUTTON_OPTION
+
 #else
 #error Unsupported keypad
 #endif
diff --git a/apps/plugins/lib/pluginlib_actions.c b/apps/plugins/lib/pluginlib_actions.c
index f9addb32f4..2c5fb773ba 100644
--- a/apps/plugins/lib/pluginlib_actions.c
+++ b/apps/plugins/lib/pluginlib_actions.c
@@ -228,6 +228,15 @@ const struct button_mapping pla_main_ctx[] =
     { PLA_DOWN_REPEAT,       BUTTON_FF|BUTTON_REPEAT,           BUTTON_NONE},
     { PLA_LEFT_REPEAT,       BUTTON_REW|BUTTON_M|BUTTON_REPEAT, BUTTON_NONE},
     { PLA_RIGHT_REPEAT,      BUTTON_FF|BUTTON_M|BUTTON_REPEAT,  BUTTON_NONE},
+#elif (CONFIG_KEYPAD == XDUOO_X3_PAD)
+    { PLA_UP,               BUTTON_HOME,                        BUTTON_NONE },
+    { PLA_DOWN,             BUTTON_OPTION,                      BUTTON_NONE },
+    { PLA_LEFT,             BUTTON_PREV,                        BUTTON_NONE },
+    { PLA_RIGHT,            BUTTON_NEXT,                        BUTTON_NONE },
+    { PLA_UP_REPEAT,        BUTTON_HOME|BUTTON_REPEAT,          BUTTON_NONE },
+    { PLA_DOWN_REPEAT,      BUTTON_OPTION|BUTTON_REPEAT,        BUTTON_NONE },
+    { PLA_LEFT_REPEAT,      BUTTON_PREV|BUTTON_REPEAT,          BUTTON_NONE },
+    { PLA_RIGHT_REPEAT,     BUTTON_NEXT|BUTTON_REPEAT,          BUTTON_NONE },
 #else
 #   ifndef HAVE_TOUCHSCREEN
 #       error pluginlib_actions: No directions defined
@@ -447,6 +456,12 @@ const struct button_mapping pla_main_ctx[] =
     {PLA_SELECT,            BUTTON_PLAY,                        BUTTON_NONE},
     {PLA_SELECT_REL,        BUTTON_PLAY|BUTTON_REL,             BUTTON_NONE},
     {PLA_SELECT_REPEAT,     BUTTON_PLAY|BUTTON_REPEAT,          BUTTON_NONE},
+#elif (CONFIG_KEYPAD == XDUOO_X3_PAD)
+    {PLA_CANCEL,            BUTTON_POWER|BUTTON_REL,            BUTTON_POWER},
+    {PLA_EXIT,              BUTTON_POWER|BUTTON_REPEAT,         BUTTON_NONE},
+    {PLA_SELECT,            BUTTON_PLAY,                        BUTTON_NONE},
+    {PLA_SELECT_REL,        BUTTON_PLAY|BUTTON_REL,             BUTTON_PLAY},
+    {PLA_SELECT_REPEAT,     BUTTON_PLAY|BUTTON_REPEAT,          BUTTON_NONE},
 
 #else
 #   ifndef HAVE_TOUCHSCREEN
diff --git a/apps/plugins/midi/midiplay.c b/apps/plugins/midi/midiplay.c
index 418f72b6a5..de6310dcd8 100644
--- a/apps/plugins/midi/midiplay.c
+++ b/apps/plugins/midi/midiplay.c
@@ -293,6 +293,14 @@
 #define MIDI_VOL_DOWN   BUTTON_VOLDOWN
 #define MIDI_PLAYPAUSE  BUTTON_SELECT
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define MIDI_QUIT         BUTTON_POWER
+#define MIDI_FFWD         BUTTON_NEXT
+#define MIDI_REWIND       BUTTON_PREV
+#define MIDI_VOL_UP       BUTTON_VOL_UP
+#define MIDI_VOL_DOWN     BUTTON_VOL_DOWN
+#define MIDI_PLAYPAUSE    BUTTON_PLAY
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/minesweeper.c b/apps/plugins/minesweeper.c
index 98eb8d9e7a..2a3b5f78e9 100644
--- a/apps/plugins/minesweeper.c
+++ b/apps/plugins/minesweeper.c
@@ -404,6 +404,19 @@ CONFIG_KEYPAD == MROBE500_PAD
 #elif CONFIG_KEYPAD == CREATIVE_ZENXFI2_PAD
 #   define MINESWP_QUIT     BUTTON_POWER
 
+#elif (CONFIG_KEYPAD == XDUOO_X3_PAD)
+#   define MINESWP_LEFT       BUTTON_PREV
+#   define MINESWP_RIGHT      BUTTON_NEXT
+#   define MINESWP_UP         BUTTON_HOME
+#   define MINESWP_DOWN       BUTTON_OPTION
+#   define MINESWP_QUIT       BUTTON_POWER
+#   define MINESWP_TOGGLE_PRE BUTTON_PLAY
+#   define MINESWP_TOGGLE     (BUTTON_PLAY | BUTTON_REL)
+#   define MINESWP_TOGGLE2    BUTTON_VOL_DOWN
+#   define MINESWP_DISCOVER   (BUTTON_PLAY | BUTTON_REPEAT)
+#   define MINESWP_DISCOVER2  BUTTON_VOL_UP
+#   define MINESWP_INFO       (BUTTON_PLAY | BUTTON_OPTION)
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/mp3_encoder.c b/apps/plugins/mp3_encoder.c
index e86e74f408..9e09135385 100644
--- a/apps/plugins/mp3_encoder.c
+++ b/apps/plugins/mp3_encoder.c
@@ -2556,6 +2556,12 @@ CONFIG_KEYPAD == MROBE500_PAD
 #define MP3ENC_DONE    BUTTON_POWER
 #define MP3ENC_SELECT  BUTTON_SELECT
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define MP3ENC_PREV    BUTTON_HOME
+#define MP3ENC_NEXT    BUTTON_OPTION
+#define MP3ENC_DONE    BUTTON_POWER
+#define MP3ENC_SELECT  BUTTON_PLAY
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/mpegplayer/mpeg_settings.c b/apps/plugins/mpegplayer/mpeg_settings.c
index dadfccf291..7976f5f542 100644
--- a/apps/plugins/mpegplayer/mpeg_settings.c
+++ b/apps/plugins/mpegplayer/mpeg_settings.c
@@ -306,6 +306,16 @@ struct mpeg_settings settings;
 #define MPEG_START_TIME_DOWN        BUTTON_DOWN
 #define MPEG_START_TIME_EXIT        BUTTON_POWER
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define MPEG_START_TIME_SELECT      BUTTON_PLAY
+#define MPEG_START_TIME_LEFT        BUTTON_PREV
+#define MPEG_START_TIME_RIGHT       BUTTON_NEXT
+#define MPEG_START_TIME_UP          BUTTON_HOME
+#define MPEG_START_TIME_DOWN        BUTTON_OPTION
+#define MPEG_START_TIME_LEFT2       BUTTON_VOL_UP
+#define MPEG_START_TIME_RIGHT2      BUTTON_VOL_DOWN
+#define MPEG_START_TIME_EXIT        BUTTON_POWER
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/mpegplayer/mpegplayer.c b/apps/plugins/mpegplayer/mpegplayer.c
index 07cf8ba8e2..fd3e8d8cd5 100644
--- a/apps/plugins/mpegplayer/mpegplayer.c
+++ b/apps/plugins/mpegplayer/mpegplayer.c
@@ -441,6 +441,15 @@ CONFIG_KEYPAD == SANSA_M200_PAD
 #define MPEG_RW         BUTTON_LEFT
 #define MPEG_FF         BUTTON_RIGHT
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define MPEG_MENU       BUTTON_PLAY
+#define MPEG_STOP       BUTTON_POWER
+#define MPEG_PAUSE      BUTTON_HOME
+#define MPEG_VOLDOWN    BUTTON_VOL_DOWN
+#define MPEG_VOLUP      BUTTON_VOL_UP
+#define MPEG_RW         BUTTON_PREV
+#define MPEG_FF         BUTTON_NEXT
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/oscilloscope.c b/apps/plugins/oscilloscope.c
index 85cbf2bfb2..4534684293 100644
--- a/apps/plugins/oscilloscope.c
+++ b/apps/plugins/oscilloscope.c
@@ -504,6 +504,20 @@
 #define OSCILLOSCOPE_VOL_UP         BUTTON_VOLUP
 #define OSCILLOSCOPE_VOL_DOWN       BUTTON_VOLDOWN
 
+#elif (CONFIG_KEYPAD == XDUOO_X3_PAD)
+#define OSCILLOSCOPE_QUIT            BUTTON_POWER
+#define OSCILLOSCOPE_DRAWMODE_PRE    BUTTON_PLAY
+#define OSCILLOSCOPE_DRAWMODE        (BUTTON_PLAY | BUTTON_REL)
+#define OSCILLOSCOPE_ORIENTATION_PRE BUTTON_PLAY
+#define OSCILLOSCOPE_ORIENTATION     (BUTTON_PLAY | BUTTON_REPEAT)
+#define OSCILLOSCOPE_ADVMODE         BUTTON_HOME
+#define OSCILLOSCOPE_PAUSE           BUTTON_OPTION
+#define OSCILLOSCOPE_SPEED_UP        BUTTON_NEXT
+#define OSCILLOSCOPE_SPEED_DOWN      BUTTON_PREV
+#define OSCILLOSCOPE_VOL_UP          BUTTON_VOL_UP
+#define OSCILLOSCOPE_VOL_DOWN        BUTTON_VOL_DOWN
+#define NEED_LASTBUTTON
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/pegbox.c b/apps/plugins/pegbox.c
index dcc6176d2b..922359cd32 100644
--- a/apps/plugins/pegbox.c
+++ b/apps/plugins/pegbox.c
@@ -643,6 +643,23 @@ CONFIG_KEYPAD == MROBE500_PAD
 #define QUIT_TEXT       "POWER"
 #define SELECT_TEXT     "MENU"
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define PEGBOX_SELECT   BUTTON_PLAY
+#define PEGBOX_QUIT     BUTTON_POWER
+#define PEGBOX_RESTART  (BUTTON_POWER | BUTTON_HOME)
+#define PEGBOX_LVL_UP   BUTTON_VOL_UP
+#define PEGBOX_LVL_DOWN BUTTON_VOL_DOWN
+#define PEGBOX_UP       BUTTON_HOME
+#define PEGBOX_DOWN     BUTTON_OPTION
+#define PEGBOX_RIGHT    BUTTON_NEXT
+#define PEGBOX_LEFT     BUTTON_PREV
+
+#define SELECT_TEXT "PLAY"
+#define QUIT_TEXT "POWER"
+#define RESTART_TEXT "HOME"
+#define LVL_UP_TEXT "VOL+"
+#define LVL_DOWN_TEXT "VOL-"
+
 #else
 #error Unsupported keymap!
 #endif
diff --git a/apps/plugins/pictureflow/pictureflow.c b/apps/plugins/pictureflow/pictureflow.c
index 6e47418e93..84a4315141 100644
--- a/apps/plugins/pictureflow/pictureflow.c
+++ b/apps/plugins/pictureflow/pictureflow.c
@@ -118,7 +118,8 @@ const struct button_mapping pf_context_buttons[] =
     CONFIG_KEYPAD == GIGABEAT_PAD || CONFIG_KEYPAD == GIGABEAT_S_PAD || \
     CONFIG_KEYPAD == MROBE100_PAD || CONFIG_KEYPAD == MROBE500_PAD || \
     CONFIG_KEYPAD == PHILIPS_SA9200_PAD || CONFIG_KEYPAD == SANSA_CLIP_PAD || \
-    CONFIG_KEYPAD == SANSA_FUZEPLUS_PAD || CONFIG_KEYPAD == CREATIVE_ZENXFI3_PAD
+    CONFIG_KEYPAD == SANSA_FUZEPLUS_PAD || CONFIG_KEYPAD == CREATIVE_ZENXFI3_PAD || \
+    CONFIG_KEYPAD == XDUOO_X3_PAD
     {PF_QUIT,         BUTTON_POWER,               BUTTON_NONE},
 #if CONFIG_KEYPAD == SANSA_FUZEPLUS_PAD
     {PF_MENU,         BUTTON_SELECT|BUTTON_REPEAT,  BUTTON_SELECT},
diff --git a/apps/plugins/plugin.lds b/apps/plugins/plugin.lds
index 831cb59b81..aea44e7d40 100644
--- a/apps/plugins/plugin.lds
+++ b/apps/plugins/plugin.lds
@@ -163,8 +163,14 @@ OUTPUT_FORMAT(elf32-littlemips)
 #define IRAMORIG (0x00000000 + (56*1024))
 #define IRAMSIZE (200*1024)
 
-#elif CONFIG_CPU == JZ4732
-#define DRAMORIG 0x80004000 + STUBOFFSET
+#elif CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B
+#undef STUBOFFSET
+#ifdef DEBUG
+#define STUBOFFSET 0x14000
+#else
+#define STUBOFFSET 0x4000
+#endif
+#define DRAMORIG 0x80000000 + STUBOFFSET
 #define IRAM DRAM
 #define IRAMSIZE 0
 /* The bit of IRAM that is available is used in the core */
diff --git a/apps/plugins/pong.c b/apps/plugins/pong.c
index 016d548675..d65134e5d2 100644
--- a/apps/plugins/pong.c
+++ b/apps/plugins/pong.c
@@ -309,6 +309,14 @@ CONFIG_KEYPAD == MROBE500_PAD
 #define PONG_QUIT        BUTTON_POWER
 #define PONG_PAUSE       BUTTON_MENU
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define PONG_QUIT        BUTTON_POWER
+#define PONG_PAUSE       BUTTON_PLAY
+#define PONG_LEFT_UP     BUTTON_PREV
+#define PONG_LEFT_DOWN   BUTTON_OPTION
+#define PONG_RIGHT_UP    BUTTON_HOME
+#define PONG_RIGHT_DOWN  BUTTON_NEXT
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/reversi/reversi-gui.h b/apps/plugins/reversi/reversi-gui.h
index 67897a9772..1dc1dedbed 100644
--- a/apps/plugins/reversi/reversi-gui.h
+++ b/apps/plugins/reversi/reversi-gui.h
@@ -328,6 +328,17 @@
 #define REVERSI_BUTTON_MAKE_MOVE   BUTTON_SELECT
 #define REVERSI_BUTTON_MENU        BUTTON_POWER
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define REVERSI_BUTTON_QUIT        BUTTON_POWER
+#define REVERSI_BUTTON_UP          BUTTON_HOME
+#define REVERSI_BUTTON_DOWN        BUTTON_OPTION
+#define REVERSI_BUTTON_LEFT        BUTTON_PREV
+#define REVERSI_BUTTON_RIGHT       BUTTON_NEXT
+#define REVERSI_BUTTON_MAKE_MOVE   BUTTON_PLAY
+#define REVERSI_BUTTON_MAKE_MOVE_SHORTPRESS
+#define REVERSI_BUTTON_MENU        BUTTON_PLAY
+#define REVERSI_BUTTON_MENU_LONGPRESS
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/rockblox.c b/apps/plugins/rockblox.c
index a0814beda1..b204ed87da 100644
--- a/apps/plugins/rockblox.c
+++ b/apps/plugins/rockblox.c
@@ -480,6 +480,18 @@
 #define ROCKBLOX_ROTATE_CCW    BUTTON_VOLDOWN
 #define ROCKBLOX_DOWN          BUTTON_DOWN
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+
+#define ROCKBLOX_OFF           BUTTON_POWER
+#define ROCKBLOX_ROTATE_CCW    BUTTON_HOME
+#define ROCKBLOX_ROTATE_CCW2   BUTTON_VOL_DOWN
+#define ROCKBLOX_ROTATE_CW     BUTTON_VOL_UP
+#define ROCKBLOX_DOWN          BUTTON_OPTION
+#define ROCKBLOX_LEFT          BUTTON_PREV
+#define ROCKBLOX_RIGHT         BUTTON_NEXT
+#define ROCKBLOX_DROP          (BUTTON_PLAY|BUTTON_REL)
+#define ROCKBLOX_RESTART       (BUTTON_PLAY|BUTTON_REPEAT)
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/rockboy/rockboy.c b/apps/plugins/rockboy/rockboy.c
index 38536d1375..7425fc2550 100644
--- a/apps/plugins/rockboy/rockboy.c
+++ b/apps/plugins/rockboy/rockboy.c
@@ -423,6 +423,16 @@ static void setoptions (void)
         options.A      = BUTTON_VOLDOWN;
         options.B      = BUTTON_VOLUP;
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+        options.UP      = BUTTON_PREV;
+        options.DOWN    = BUTTON_NEXT;
+
+        options.A       = BUTTON_HOME;
+        options.B       = BUTTON_OPTION;
+        options.START   = BUTTON_VOL_DOWN;
+        options.SELECT  = BUTTON_VOL_UP;
+        options.MENU    = BUTTON_POWER;
+
 #else
 #error No Keymap Defined!
 #endif
diff --git a/apps/plugins/rockpaint.c b/apps/plugins/rockpaint.c
index d2534f4aa6..d0f9f7235c 100644
--- a/apps/plugins/rockpaint.c
+++ b/apps/plugins/rockpaint.c
@@ -327,6 +327,17 @@
 #define ROCKPAINT_QUIT        BUTTON_POWER
 #define ROCKPAINT_MENU        BUTTON_MENU
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define ROCKPAINT_QUIT        BUTTON_POWER
+#define ROCKPAINT_DRAW        BUTTON_PLAY
+#define ROCKPAINT_MENU        (BUTTON_HOME | BUTTON_POWER)
+#define ROCKPAINT_TOOLBAR     BUTTON_VOL_UP
+#define ROCKPAINT_TOOLBAR2    BUTTON_VOL_DOWN
+#define ROCKPAINT_UP          BUTTON_HOME
+#define ROCKPAINT_DOWN        BUTTON_OPTION
+#define ROCKPAINT_LEFT        BUTTON_PREV
+#define ROCKPAINT_RIGHT       BUTTON_NEXT
+
 #else
 #error "Please define keys for this keypad"
 #endif
diff --git a/apps/plugins/sliding_puzzle.c b/apps/plugins/sliding_puzzle.c
index d43c3d527f..a3f84e32ae 100644
--- a/apps/plugins/sliding_puzzle.c
+++ b/apps/plugins/sliding_puzzle.c
@@ -331,6 +331,15 @@ CONFIG_KEYPAD == MROBE500_PAD
 #define PUZZLE_SHUFFLE BUTTON_POWER
 #define PUZZLE_PICTURE BUTTON_SELECT
 
+#elif (CONFIG_KEYPAD == XDUOO_X3_PAD)
+#define PUZZLE_QUIT    BUTTON_POWER
+#define PUZZLE_LEFT    BUTTON_PREV
+#define PUZZLE_RIGHT   BUTTON_NEXT
+#define PUZZLE_UP      BUTTON_HOME
+#define PUZZLE_DOWN    BUTTON_OPTION
+#define PUZZLE_SHUFFLE (BUTTON_HOME | BUTTON_POWER)
+#define PUZZLE_PICTURE BUTTON_PLAY
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/snake.c b/apps/plugins/snake.c
index a73e61d9ec..9144edf062 100644
--- a/apps/plugins/snake.c
+++ b/apps/plugins/snake.c
@@ -289,6 +289,14 @@ dir is the current direction of the snake - 0=up, 1=right, 2=down, 3=left;
 #define SNAKE_DOWN      BUTTON_DOWN
 #define SNAKE_PLAYPAUSE BUTTON_SELECT
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define SNAKE_QUIT      BUTTON_POWER
+#define SNAKE_LEFT      BUTTON_PREV
+#define SNAKE_RIGHT     BUTTON_NEXT
+#define SNAKE_UP        BUTTON_HOME
+#define SNAKE_DOWN      BUTTON_OPTION
+#define SNAKE_PLAYPAUSE BUTTON_PLAY
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/snake2.c b/apps/plugins/snake2.c
index f32012e029..13d2c57b24 100644
--- a/apps/plugins/snake2.c
+++ b/apps/plugins/snake2.c
@@ -419,6 +419,15 @@ CONFIG_KEYPAD == MROBE500_PAD
 #define SNAKE2_PLAYPAUSE    BUTTON_SELECT
 #define SNAKE2_PLAYPAUSE_TEXT    "Select"
 
+#elif (CONFIG_KEYPAD == XDUOO_X3_PAD)
+#define SNAKE2_LEFT         BUTTON_PREV
+#define SNAKE2_RIGHT        BUTTON_NEXT
+#define SNAKE2_UP           BUTTON_HOME
+#define SNAKE2_DOWN         BUTTON_OPTION
+#define SNAKE2_QUIT         BUTTON_POWER
+#define SNAKE2_PLAYPAUSE    BUTTON_PLAY
+#define SNAKE2_PLAYPAUSE_TEXT    "PLAY"
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/sokoban.c b/apps/plugins/sokoban.c
index af369f82a6..98d295eb1a 100644
--- a/apps/plugins/sokoban.c
+++ b/apps/plugins/sokoban.c
@@ -651,6 +651,22 @@
 #define SOKOBAN_MENU    BUTTON_MENU
 #define SOKOBAN_MENU_NAME     "[MENU]"
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define SOKOBAN_LEFT BUTTON_PREV
+#define SOKOBAN_RIGHT BUTTON_NEXT
+#define SOKOBAN_UP BUTTON_HOME
+#define SOKOBAN_DOWN BUTTON_OPTION
+#define SOKOBAN_MENU BUTTON_POWER
+#define SOKOBAN_UNDO_PRE BUTTON_PLAY
+#define SOKOBAN_UNDO (BUTTON_PLAY | BUTTON_REL)
+#define SOKOBAN_REDO (BUTTON_POWER | BUTTON_PLAY)
+#define SOKOBAN_LEVEL_DOWN BUTTON_VOL_DOWN
+#define SOKOBAN_LEVEL_REPEAT (BUTTON_PLAY | BUTTON_NEXT)
+#define SOKOBAN_LEVEL_UP BUTTON_VOL_UP
+#define SOKOBAN_PAUSE BUTTON_PLAY
+#define BUTTON_SAVE BUTTON_PLAY
+#define BUTTON_SAVE_NAME "PLAY"
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/solitaire.c b/apps/plugins/solitaire.c
index ee3742472b..fe7da2788e 100644
--- a/apps/plugins/solitaire.c
+++ b/apps/plugins/solitaire.c
@@ -687,6 +687,25 @@ CONFIG_KEYPAD == MROBE500_PAD
 #elif CONFIG_KEYPAD == CREATIVE_ZENXFI2_PAD
 #   define SOL_QUIT         BUTTON_POWER
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#   define SOL_QUIT          BUTTON_POWER
+#   define SOL_UP            BUTTON_HOME
+#   define SOL_DOWN          BUTTON_OPTION
+#   define SOL_LEFT          BUTTON_PREV
+#   define SOL_RIGHT         BUTTON_NEXT
+#   define SOL_MOVE_PRE      BUTTON_PLAY
+#   define SOL_MOVE          (BUTTON_PLAY | BUTTON_REL)
+#   define SOL_DRAW          (BUTTON_POWER | BUTTON_REPEAT)
+#   define SOL_REM2CUR       BUTTON_VOL_DOWN
+#   define SOL_CUR2STACK_PRE BUTTON_PLAY
+#   define SOL_CUR2STACK     (BUTTON_PLAY | BUTTON_REPEAT)
+#   define SOL_REM2STACK     BUTTON_VOL_UP
+#   define HK_MOVE           "PLAY"
+#   define HK_DRAW           "DBL HOME"
+#   define HK_REM2CUR        "PREV"
+#   define HK_CUR2STACK      "DBL PLAY"
+#   define HK_REM2STACK      "NEXT"
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/spacerocks.c b/apps/plugins/spacerocks.c
index 7a22de814b..ad03919861 100644
--- a/apps/plugins/spacerocks.c
+++ b/apps/plugins/spacerocks.c
@@ -354,6 +354,15 @@
 #define AST_RIGHT       BUTTON_RIGHT
 #define AST_FIRE        BUTTON_SELECT
 
+#elif (CONFIG_KEYPAD == XDUOO_X3_PAD)
+#define AST_PAUSE       BUTTON_VOL_UP
+#define AST_QUIT        BUTTON_POWER
+#define AST_THRUST      BUTTON_HOME
+#define AST_HYPERSPACE  BUTTON_OPTION
+#define AST_LEFT        BUTTON_PREV
+#define AST_RIGHT       BUTTON_NEXT
+#define AST_FIRE        BUTTON_PLAY
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/star.c b/apps/plugins/star.c
index 6d0cd65e20..bcddab8f20 100644
--- a/apps/plugins/star.c
+++ b/apps/plugins/star.c
@@ -623,6 +623,22 @@
 #define STAR_TOGGLE_CONTROL_NAME "Play"
 #define STAR_QUIT_NAME           "Back"
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define STAR_QUIT           BUTTON_POWER
+#define STAR_LEFT           BUTTON_PREV
+#define STAR_RIGHT          BUTTON_NEXT
+#define STAR_UP             BUTTON_HOME
+#define STAR_DOWN           BUTTON_OPTION
+#define STAR_TOGGLE_CONTROL BUTTON_PLAY
+#define STAR_LEVEL_UP      (BUTTON_PLAY | BUTTON_NEXT)
+#define STAR_LEVEL_DOWN    (BUTTON_PLAY | BUTTON_PREV)
+#define STAR_LEVEL_REPEAT  (BUTTON_PLAY | BUTTON_OPTION)
+#define STAR_TOGGLE_CONTROL_NAME "PLAY"
+#define STAR_QUIT_NAME      "POWER"
+#define STAR_LEVEL_UP_NAME  "PLAY + NEXT"
+#define STAR_LEVEL_DOWN_NAME "PLAY + PREV"
+#define STAR_LEVEL_REPEAT_NAME "PLAY + OPTION"
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/stopwatch.c b/apps/plugins/stopwatch.c
index 8d99178e48..69f14a20ef 100644
--- a/apps/plugins/stopwatch.c
+++ b/apps/plugins/stopwatch.c
@@ -313,6 +313,14 @@
 #define STOPWATCH_SCROLL_UP      BUTTON_UP
 #define STOPWATCH_SCROLL_DOWN    BUTTON_DOWN
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define STOPWATCH_QUIT           BUTTON_POWER
+#define STOPWATCH_START_STOP     BUTTON_NEXT
+#define STOPWATCH_RESET_TIMER    BUTTON_PREV
+#define STOPWATCH_LAP_TIMER      BUTTON_PLAY
+#define STOPWATCH_SCROLL_UP      BUTTON_HOME
+#define STOPWATCH_SCROLL_DOWN    BUTTON_OPTION
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/sudoku/sudoku.h b/apps/plugins/sudoku/sudoku.h
index 8d871c7b2d..e26644a2d8 100644
--- a/apps/plugins/sudoku/sudoku.h
+++ b/apps/plugins/sudoku/sudoku.h
@@ -423,6 +423,20 @@
 #define SUDOKU_BUTTON_TOGGLE     BUTTON_SELECT
 #define SUDOKU_BUTTON_POSSIBLE   BUTTON_VOLUP
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define SUDOKU_BUTTON_QUIT_PRE   BUTTON_POWER
+#define SUDOKU_BUTTON_QUIT       (BUTTON_POWER | BUTTON_REPEAT)
+#define SUDOKU_BUTTON_UP         BUTTON_HOME
+#define SUDOKU_BUTTON_DOWN       BUTTON_OPTION
+#define SUDOKU_BUTTON_LEFT       BUTTON_PREV
+#define SUDOKU_BUTTON_RIGHT      BUTTON_NEXT
+#define SUDOKU_BUTTON_TOGGLEBACK BUTTON_VOL_DOWN
+#define SUDOKU_BUTTON_TOGGLE     BUTTON_VOL_UP
+#define SUDOKU_BUTTON_ALTTOGGLE  BUTTON_PLAY
+#define SUDOKU_BUTTON_MENU_PRE   BUTTON_POWER
+#define SUDOKU_BUTTON_MENU       (BUTTON_POWER | BUTTON_REL)
+#define SUDOKU_BUTTON_POSSIBLE   (BUTTON_HOME | BUTTON_POWER)
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/text_viewer/tv_button.h b/apps/plugins/text_viewer/tv_button.h
index 9d1b5afa88..58bce80eaf 100644
--- a/apps/plugins/text_viewer/tv_button.h
+++ b/apps/plugins/text_viewer/tv_button.h
@@ -550,6 +550,18 @@
 #define TV_AUTOSCROLL   BUTTON_VOLDOWN
 #define TV_BOOKMARK     BUTTON_VOLUP
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define TV_QUIT         BUTTON_POWER
+#define TV_SCROLL_UP    BUTTON_VOL_UP
+#define TV_SCROLL_DOWN  BUTTON_VOL_DOWN
+#define TV_SCREEN_LEFT  BUTTON_PREV
+#define TV_SCREEN_RIGHT BUTTON_NEXT
+#define TV_MENU         BUTTON_PLAY
+#define TV_AUTOSCROLL   (BUTTON_POWER | BUTTON_HOME)
+#define TV_LINE_UP      BUTTON_HOME
+#define TV_LINE_DOWN    BUTTON_OPTION
+#define TV_BOOKMARK     (BUTTON_OPTION | BUTTON_PLAY)
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/vu_meter.c b/apps/plugins/vu_meter.c
index 8c80066c67..04876ba198 100644
--- a/apps/plugins/vu_meter.c
+++ b/apps/plugins/vu_meter.c
@@ -421,6 +421,17 @@
 #define LABEL_VOLUME    "Vol Up/Down"
 #define LABEL_MENU      "Select"
 
+#elif (CONFIG_KEYPAD == XDUOO_X3_PAD)
+#define VUMETER_QUIT    BUTTON_POWER
+#define VUMETER_HELP    BUTTON_HOME
+#define VUMETER_MENU    BUTTON_PLAY
+#define VUMETER_UP      BUTTON_VOL_UP
+#define VUMETER_DOWN    BUTTON_VOL_DOWN
+#define LABEL_HELP      "HOME"
+#define LABEL_QUIT      "POWER"
+#define LABEL_MENU      "PLAY"
+#define LABEL_VOLUME    "VOL UP/DN"
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/wormlet.c b/apps/plugins/wormlet.c
index f1ccaec782..83cfadc338 100644
--- a/apps/plugins/wormlet.c
+++ b/apps/plugins/wormlet.c
@@ -393,6 +393,15 @@ CONFIG_KEYPAD == MROBE500_PAD
 #define BTN_QUIT          BUTTON_POWER
 #define BTN_STOPRESET     (BUTTON_SELECT|BUTTON_REPEAT)
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define BTN_DIR_UP        BUTTON_HOME
+#define BTN_DIR_DOWN      BUTTON_OPTION
+#define BTN_DIR_LEFT      BUTTON_PREV
+#define BTN_DIR_RIGHT     BUTTON_NEXT
+#define BTN_STARTPAUSE    BUTTON_PLAY
+#define BTN_QUIT          BUTTON_POWER
+#define BTN_STOPRESET     (BUTTON_HOME | BUTTON_POWER)
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/xobox.c b/apps/plugins/xobox.c
index f5c4a29bdf..9b41e2d1ac 100644
--- a/apps/plugins/xobox.c
+++ b/apps/plugins/xobox.c
@@ -342,6 +342,15 @@ CONFIG_KEYPAD == MROBE500_PAD
 #define DOWN     BUTTON_DOWN
 #define PAUSE    BUTTON_SELECT
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+
+#define QUIT     BUTTON_POWER
+#define LEFT     BUTTON_PREV
+#define RIGHT    BUTTON_NEXT
+#define UP       BUTTON_HOME
+#define DOWN     BUTTON_OPTION
+#define PAUSE    BUTTON_PLAY
+
 #else
 #error No keymap defined!
 #endif
diff --git a/apps/plugins/zxbox/keymaps.h b/apps/plugins/zxbox/keymaps.h
index d10eeb67e7..ebdd41734e 100644
--- a/apps/plugins/zxbox/keymaps.h
+++ b/apps/plugins/zxbox/keymaps.h
@@ -282,6 +282,14 @@
 #define ZX_RIGHT        BUTTON_RIGHT
 #define ZX_SELECT       BUTTON_SELECT
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+#define ZX_SELECT       BUTTON_PLAY
+#define ZX_MENU         BUTTON_POWER
+#define ZX_LEFT         BUTTON_PREV
+#define ZX_RIGHT        BUTTON_NEXT
+#define ZX_UP           BUTTON_HOME
+#define ZX_DOWN         BUTTON_OPTION
+
 #else
 #error Keymap not defined!
 
diff --git a/apps/plugins/zxbox/zxbox_keyb.c b/apps/plugins/zxbox/zxbox_keyb.c
index 2931c8ea32..f38712d8d1 100644
--- a/apps/plugins/zxbox/zxbox_keyb.c
+++ b/apps/plugins/zxbox/zxbox_keyb.c
@@ -278,6 +278,15 @@
 #define KBD_UP     BUTTON_UP
 #define KBD_DOWN   BUTTON_DOWN
 
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+
+#define KBD_SELECT BUTTON_PLAY
+#define KBD_ABORT  BUTTON_POWER
+#define KBD_LEFT   BUTTON_PREV
+#define KBD_RIGHT  BUTTON_NEXT
+#define KBD_UP     BUTTON_HOME
+#define KBD_DOWN   BUTTON_OPTION
+
 #endif
 
 #ifdef HAVE_TOUCHSCREEN
diff --git a/apps/settings.h b/apps/settings.h
index 411675153a..8d8c766d45 100644
--- a/apps/settings.h
+++ b/apps/settings.h
@@ -811,6 +811,10 @@ struct user_settings
     int roll_off;
 #endif
 
+#ifdef AUDIOHW_HAVE_FUNCTIONAL_MODE
+    int func_mode;
+#endif
+
 #ifdef AUDIOHW_HAVE_EQ
     /** Hardware EQ tone controls **/
     struct hw_eq_band
diff --git a/bootloader/SOURCES b/bootloader/SOURCES
index 359e2ba700..0b39da153a 100644
--- a/bootloader/SOURCES
+++ b/bootloader/SOURCES
@@ -53,6 +53,9 @@ samsung_yps3.c
 #elif defined(ONDA_VX747) || defined(ONDA_VX747P) || defined(ONDA_VX767) || defined(ONDA_VX777)
 ondavx747.c
 show_logo.c
+#elif defined(XDUOO_X3)
+xduoox3.c
+show_logo.c
 #elif defined(CREATIVE_ZVx)
 creativezvm.c
 #elif CONFIG_CPU==AS3525 || CONFIG_CPU==AS3525v2
diff --git a/bootloader/common.c b/bootloader/common.c
index 4969d92b40..5c5647ac64 100644
--- a/bootloader/common.c
+++ b/bootloader/common.c
@@ -54,7 +54,7 @@
  || defined(SAMSUNG_YH820) || defined(PHILIPS_SA9200) \
  || defined(PHILIPS_HDD1630) || defined(PHILIPS_HDD6330) \
  || defined(ONDA_VX747) || defined(PBELL_VIBE500) \
- || defined(TOSHIBA_GIGABEAT_S)
+ || defined(TOSHIBA_GIGABEAT_S) || defined(XDUOO_X3)
 bool verbose = false;
 #else
 bool verbose = true;
diff --git a/bootloader/xduoox3.c b/bootloader/xduoox3.c
new file mode 100644
index 0000000000..3db87a866d
--- /dev/null
+++ b/bootloader/xduoox3.c
@@ -0,0 +1,184 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "jz4760b.h"
+#include "../kernel-internal.h"
+#include "backlight.h"
+#include "font.h"
+#include "lcd.h"
+#include "file.h"
+#include "usb.h"
+#include "system.h"
+#include "button.h"
+#include "common.h"
+#include "rb-loader.h"
+#include "loader_strerror.h"
+#include "storage.h"
+#include "file_internal.h"
+#include "disk.h"
+#include "string.h"
+#include "adc.h"
+#include "version.h"
+
+#include "xdebug.h"
+
+extern void show_logo(void);
+extern void power_off(void);
+
+static void show_splash(int timeout, const char *msg)
+{
+    reset_screen();
+    lcd_putsxy( (LCD_WIDTH - (SYSFONT_WIDTH * strlen(msg))) / 2,
+                (LCD_HEIGHT - SYSFONT_HEIGHT) / 2, msg);
+    lcd_update();
+
+    sleep(timeout);
+}
+
+static void usb_mode(void)
+{
+    int button;
+
+    /* Init USB */
+    usb_init();
+    usb_start_monitoring();
+
+    /* Wait for threads to connect */
+    show_splash(HZ/2, "Waiting for USB");
+
+    while (1)
+    {
+        button = button_get_w_tmo(HZ/2);
+
+        if (button == SYS_USB_CONNECTED)
+            break; /* Hit */
+    }
+
+    if (button == SYS_USB_CONNECTED)
+    {
+        /* Got the message - wait for disconnect */
+        show_splash(0, "Bootloader USB mode");
+
+        usb_acknowledge(SYS_USB_CONNECTED_ACK);
+
+        while (1)
+        {
+            button = button_get(true);
+            if (button == SYS_USB_DISCONNECTED)
+                break;
+        }
+    }
+}
+
+static int boot_rockbox(void)
+{
+    int rc;
+    void (*kernel_entry)(void);
+
+    printf("Mounting disk...\n");
+    rc = disk_mount_all();
+    if (rc <= 0)
+    {
+        verbose = true;
+        error(EDISK,rc, true);
+    }
+
+    printf("Loading firmware...\n");
+    rc = load_firmware((unsigned char *)CONFIG_SDRAM_START, BOOTFILE, 0x400000);
+    if(rc <= EFILE_EMPTY)
+        return rc;
+    else
+    {
+        printf("Starting Rockbox...\n");
+        adc_close(); /* Disable SADC, seems to fix the re-init Rockbox does */
+
+        disable_interrupt();
+        kernel_entry = (void*) CONFIG_SDRAM_START;
+        kernel_entry();
+
+        return 0; /* Shouldn't happen */
+    }
+}
+
+static void reset_configuration(void)
+{
+    int rc;
+
+    rc = disk_mount_all();
+    if (rc <= 0)
+    {
+        verbose = true;
+        error(EDISK,rc, true);
+    }
+
+    if(rename(ROCKBOX_DIR "/config.cfg", ROCKBOX_DIR "/config.old") == 0)
+        show_splash(HZ/2, "Configuration reset successfully!");
+    else
+        show_splash(HZ/2, "Couldn't reset configuration!");
+}
+
+int main(void)
+{
+    int rc;
+
+    serial_puts("\n\nSPL Stage 2\n\n");
+
+    kernel_init();
+    lcd_init();
+    font_init();
+    lcd_setfont(FONT_SYSFIXED);
+    button_init();
+    backlight_init();
+
+    show_logo();
+
+    filesystem_init();
+
+    rc = storage_init();
+    if(rc)
+    {
+        verbose = true;
+        error(EATA, rc, true);
+    }
+
+    /* Don't mount the disks yet, there could be file system/partition errors
+       which are fixable in USB mode */
+
+    reset_screen();
+
+    printf(MODEL_NAME" Rockbox Bootloader\n");
+    printf("Version %s\n", rbversion);
+
+    rc = boot_rockbox();
+
+    if(rc <= EFILE_EMPTY)
+    {
+        verbose = true;
+        printf("Error: %s", loader_strerror(rc));
+    }
+
+    /* Halt */
+    while (1)
+        core_idle();
+
+    return 0;
+}
diff --git a/docs/CREDITS b/docs/CREDITS
index 2ce7a86f4b..7743ba0af8 100644
--- a/docs/CREDITS
+++ b/docs/CREDITS
@@ -663,6 +663,9 @@ Constantine Mountantonakis
 Ivan Pesic
 Jonatan Nyberg
 Alessandro Stoppani
+Alexander Yurenin
+Roman Stolyarov
+Solomon Peachy
 
 The libmad team
 The wavpack team
diff --git a/firmware/SOURCES b/firmware/SOURCES
index d2c27b71f0..33d59fa429 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -366,8 +366,10 @@ drivers/rtc/rtc_mr100.c
 drivers/rtc/rtc_mc13783.c
 #elif (CONFIG_RTC == RTC_TCC77X)
 drivers/rtc/rtc_tcc77x.c
-#elif (CONFIG_RTC == RTC_JZ47XX)
+#elif (CONFIG_RTC == RTC_JZ4740)
 drivers/rtc/rtc_jz4740.c
+#elif (CONFIG_RTC == RTC_JZ4760)
+drivers/rtc/rtc_jz4760.c
 #elif (CONFIG_RTC == RTC_S35390A)
 drivers/rtc/rtc_s35390a.c
 #elif (CONFIG_RTC == RTC_S35380A)
@@ -477,6 +479,8 @@ drivers/audio/dummy_codec.c
 drivers/audio/df1704.c
 #elif defined (HAVE_PCM1792_CODEC)
 drivers/audio/pcm1792.c
+#elif defined (HAVE_CS4398)
+drivers/audio/cs4398.c
 #endif /* defined(HAVE_*) */
 #else /* PLATFORM_HOSTED */
 #if defined(SAMSUNG_YPR0) && defined(HAVE_AS3514)
@@ -739,9 +743,9 @@ target/arm/crt0.S
 
 #elif defined(CPU_MIPS) && (CONFIG_PLATFORM & PLATFORM_NATIVE)
 target/mips/mmu-mips.c
-#if CONFIG_CPU==JZ4732
+#if CONFIG_CPU==JZ4732 || CONFIG_CPU==JZ4760B
 target/mips/ingenic_jz47xx/crt0.S
-#endif /* CONFIG_CPU == JZ4732 */
+#endif /* CONFIG_CPU == JZ4732 || JZ4760B */
 
 #else
 
@@ -1725,6 +1729,24 @@ target/mips/ingenic_jz47xx/pcm-jz4740.c
 drivers/nand_id.c
 #endif /* CONFIG_CPU == JZ4732 */
 
+#if CONFIG_CPU == JZ4760B
+target/mips/ingenic_jz47xx/dma_acc-jz4760.c
+target/mips/ingenic_jz47xx/ata-nand-jz4760.c
+target/mips/ingenic_jz47xx/ata-sd-jz4760.c
+target/mips/ingenic_jz47xx/debug-jz4760.c
+target/mips/ingenic_jz47xx/kernel-jz4760.c
+target/mips/ingenic_jz47xx/i2c-jz4760.c
+target/mips/ingenic_jz47xx/lcd-jz4760.c
+target/mips/ingenic_jz47xx/system-jz4760.c
+target/mips/ingenic_jz47xx/usb-jz4760.c
+target/mips/ingenic_jz47xx/timer-jz4760.c
+#ifndef BOOTLOADER
+target/mips/ingenic_jz47xx/codec-jz4760.c
+target/mips/ingenic_jz47xx/pcm-jz4760.c
+#endif /* BOOTLOADER */
+drivers/nand_id.c
+#endif /* CONFIG_CPU == JZ4760B */
+
 #if defined(ONDA_VX747) || defined(ONDA_VX747P) || defined(ONDA_VX777)
 target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx7X7.c
 target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
@@ -1741,6 +1763,13 @@ target/mips/ingenic_jz47xx/onda_vx767/power-onda_vx767.c
 target/mips/ingenic_jz47xx/onda_vx767/sadc-onda_vx767.c
 #endif /* ONDA_VX767 */
 
+#if defined(XDUOO_X3)
+target/mips/ingenic_jz47xx/xduoo_x3/backlight-xduoo_x3.c
+target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c
+target/mips/ingenic_jz47xx/xduoo_x3/power-xduoo_x3.c
+target/mips/ingenic_jz47xx/xduoo_x3/sadc-xduoo_x3.c
+#endif /* XDUOO_X3 */
+
 #if defined(LYRE_PROTO1)
 target/arm/at91sam/lyre_proto1/adc-lyre_proto1.c
 target/arm/at91sam/lyre_proto1/backlight-lyre_proto1.c
diff --git a/firmware/drivers/audio/cs4398.c b/firmware/drivers/audio/cs4398.c
new file mode 100644
index 0000000000..35aa99d08c
--- /dev/null
+++ b/firmware/drivers/audio/cs4398.c
@@ -0,0 +1,41 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "system.h"
+#include "cs4398.h"
+#include "config.h"
+#include "audio.h"
+#include "audiohw.h"
+#include "i2c.h"
+
+void cs4398_write_reg(uint8_t reg, uint8_t val)
+{
+    unsigned char buf[2] = {reg, val};
+    i2c_write(CS4398_I2C_ADDR, (unsigned char *)&buf, 2);
+}
+
+uint8_t cs4398_read_reg(uint8_t reg)
+{
+    unsigned char buf[2] = {reg, 0xff};
+    i2c_write(CS4398_I2C_ADDR, (unsigned char *)&buf[0], 1);
+    i2c_read(CS4398_I2C_ADDR, (unsigned char *)&buf[1], 1);
+    return buf[1];
+}
diff --git a/firmware/drivers/audio/sdl.c b/firmware/drivers/audio/sdl.c
index ae66380d16..a8fd2ffa07 100644
--- a/firmware/drivers/audio/sdl.c
+++ b/firmware/drivers/audio/sdl.c
@@ -122,6 +122,10 @@ void audiohw_set_depth_3d(int value)
 void audiohw_set_lineout_volume(int vol_l, int vol_r)
     { (void)vol_l; (void)vol_r; }
 #endif
+#if defined(AUDIOHW_HAVE_FILTER_ROLL_OFF)
+void audiohw_set_filter_roll_off(int value)
+    { (void)value; }
+#endif
 
 void audiohw_close(void) {}
 
diff --git a/firmware/drivers/nand_id.c b/firmware/drivers/nand_id.c
index f2b9861c7c..56132ab090 100644
--- a/firmware/drivers/nand_id.c
+++ b/firmware/drivers/nand_id.c
@@ -34,27 +34,38 @@ static const struct nand_info samsung[] =
 /*
     id1, id2
     pages/block, blocks, page_size, spare_size, col_cycles, row_cycles, planes
-*/      
+*/
     {0xDC, 0x10, /* K9F4G08UOM */
      64,         4096,   2048,      64,         2,          3,          1 },
-                                              
+
     {0xD3, 0x51, /* K9K8G08UOM */
      64,         8192,   2048,      64,         2,          3,          1 },
-                                              
+
     {0xD5, 0x14, /* K9GAG08UOM */
      128,        4096,   4096,      128,        2,          3,          2 },
-                                              
+
     {0xD5, 0x55, /* K9LAG08UOM, K9HBG08U1M, K9MCG08U5M */
      128,        8192,   2048,      64,         2,          3,          4 },
-                                 
+
     {0xD7, 0x55, /* K9LBG08UOM */
      128,        8192,   4096,      128,        2,          3,          4 },
 };
 
+static const struct nand_info gigadevice[] =
+{
+/*
+    id1, id2
+    pages/block, blocks, page_size, spare_size, col_cycles, row_cycles, planes
+*/
+    {0xB1, 0x80, /* MD5N01G51MSD1B */
+     64,         1024,   2048,      64,         2,          2,          1 },
+};
+
 #define NI(id, x) {id, (struct nand_info*)x, (sizeof(x)/sizeof(struct nand_info))}
 static const struct nand_manufacturer all[] =
 {
     NI(0xEC, samsung),
+    NI(0x98, gigadevice),
 };
 
 // -----------------------------------------------------------------------------
@@ -63,7 +74,7 @@ struct nand_info* nand_identify(unsigned char data[5])
  {
     unsigned int i;
     int found = -1;
-    
+
     for(i = 0; i < (sizeof(all)/sizeof(struct nand_manufacturer)); i++)
     {
         if(data[0] == all[i].id)
@@ -72,16 +83,16 @@ struct nand_info* nand_identify(unsigned char data[5])
             break;
         }
     }
-    
+
     if(found < 0)
         return NULL;
-    
+
     for(i = 0; i < all[found].total; i++)
     {
         if(data[1] == all[found].info[i].dev_id &&
            data[2] == all[found].info[i].dev_id2)
             return &all[found].info[i];
     }
-    
+
     return NULL;
 }
diff --git a/firmware/drivers/rtc/rtc_jz4760.c b/firmware/drivers/rtc/rtc_jz4760.c
new file mode 100644
index 0000000000..cda618d617
--- /dev/null
+++ b/firmware/drivers/rtc/rtc_jz4760.c
@@ -0,0 +1,124 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+ 
+/*
+ * Real Time Clock interface for Jz4760.
+ *
+ */
+
+#include "config.h"
+#include "cpu.h"
+#include "rtc.h"
+#include "timefuncs.h"
+#include "logf.h"
+
+#define RTC_FREQ_DIVIDER     (32768 - 1)
+
+/* Stolen from dietlibc-0.29/libugly/gmtime_r.c (GPLv2) */
+#define SPD (24*60*60)
+#define ISLEAP(year) (!(year%4) && ((year%100) || !(year%400)))
+static void _localtime(const time_t t, struct tm *r)
+{
+    time_t i;
+    register time_t work = t % SPD;
+    static int m_to_d[12] = /* This could be shared with mktime() */
+        {0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334};
+
+    r->tm_sec = work % 60;
+    work /= 60;
+    r->tm_min = work % 60;
+    r->tm_hour = work / 60;
+    work = t / SPD;
+    r->tm_wday = (4 + work) % 7;
+
+    for (i=1970; ; ++i)
+    {
+        register time_t k = ISLEAP(i) ? 366 : 365;
+
+        if (work >= k)
+            work -= k;
+        else
+            break;
+    }
+
+    r->tm_year = i - 1900;
+    r->tm_yday = work;
+
+    r->tm_mday = 1;
+    if (ISLEAP(i) && (work>58))
+    {
+        if (work==59)
+            r->tm_mday=2; /* 29.2. */
+
+        work-=1;
+    }
+
+    for (i=11; i && (m_to_d[i] > work); --i);
+    r->tm_mon = i;
+    r->tm_mday += work - m_to_d[i];
+}
+
+int rtc_read_datetime(struct tm *tm)
+{
+    _localtime(rtc_read_reg(RTC_RTCSR), tm);
+
+    return 1;
+}
+
+int rtc_write_datetime(const struct tm *tm)
+{
+    rtc_write_reg(RTC_RTCSR, mktime((struct tm*)tm));
+
+    return 0;
+}
+
+void rtc_init(void)
+{
+    unsigned int cfc,hspr,rgr_1hz;
+
+    __cpm_select_rtcclk_rtc();
+
+    cfc = HSPR_RTCV;
+    hspr = rtc_read_reg(RTC_HSPR);
+    rgr_1hz = rtc_read_reg(RTC_RTCGR) & RTCGR_NC1HZ_MASK;
+
+    if((hspr != cfc) || (rgr_1hz != RTC_FREQ_DIVIDER))
+    {
+        /* We are powered on for the first time !!! */
+
+        /* Set 32768 rtc clocks per seconds */
+        rtc_write_reg(RTC_RTCGR, RTC_FREQ_DIVIDER);
+
+        /* Set minimum wakeup_n pin low-level assertion time for wakeup: 100ms */
+        rtc_write_reg(RTC_HWFCR, HWFCR_WAIT_TIME(100));
+        rtc_write_reg(RTC_HRCR, HRCR_WAIT_TIME(60));
+
+        /* Reset to the default time */
+        rtc_write_reg(RTC_RTCSR, 946681200); /* 01/01/2000 */
+
+        /* start rtc */
+        rtc_write_reg(RTC_RTCCR, RTCCR_RTCE);
+        rtc_write_reg(RTC_HSPR, cfc);
+    }
+
+    /* clear all rtc flags */
+    rtc_write_reg(RTC_HWRSR, 0);
+}
diff --git a/firmware/export/audiohw.h b/firmware/export/audiohw.h
index 26a1a69f95..09001c8045 100644
--- a/firmware/export/audiohw.h
+++ b/firmware/export/audiohw.h
@@ -209,6 +209,8 @@ struct sound_settings_info
 #include "pcm1792.h"
 #elif defined(HAVE_NWZ_LINUX_CODEC)
 #include "nwzlinux_codec.h"
+#elif defined(HAVE_CS4398)
+#include "cs4398.h"
 #elif (CONFIG_PLATFORM & (PLATFORM_ANDROID | PLATFORM_MAEMO\
        | PLATFORM_PANDORA | PLATFORM_SDL))
 #include "hosted_codec.h"
@@ -576,7 +578,6 @@ void audiohw_set_depth_3d(int val);
 void audiohw_set_filter_roll_off(int val);
 #endif
 
-
 void audiohw_set_frequency(int fsel);
 
 #ifdef HAVE_RECORDING
diff --git a/firmware/export/audiohw_settings.h b/firmware/export/audiohw_settings.h
index 675ec59a7b..f9610421e8 100644
--- a/firmware/export/audiohw_settings.h
+++ b/firmware/export/audiohw_settings.h
@@ -113,6 +113,9 @@ AUDIOHW_SETTINGS(
 #if defined(AUDIOHW_HAVE_FILTER_ROLL_OFF)
     AUDIOHW_SETTING_ENT(FILTER_ROLL_OFF,    sound_set_filter_roll_off)
 #endif
+#if defined(AUDIOHW_HAVE_FUNCTIONAL_MODE)
+    AUDIOHW_SETTING_ENT(FUNCTIONAL_MODE,    sound_set_functional_mode)
+#endif
 /* Hardware EQ tone controls */
 #if defined(AUDIOHW_HAVE_EQ)
     AUDIOHW_SETTING_ENT(EQ_BAND1_GAIN,      sound_set_hw_eq_band1_gain)
diff --git a/firmware/export/config.h b/firmware/export/config.h
index e362000c18..b7a355ce54 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -82,6 +82,7 @@
 #define S5L8701      8701
 #define S5L8702      8702
 #define JZ4732       4732
+#define JZ4760B     47602
 #define AS3525       3525
 #define AT91SAM9260  9260
 #define AS3525v2    35252
@@ -162,11 +163,12 @@
 #define CREATIVE_ZEN_PAD   58
 #define SAMSUNG_YPZ5_PAD   59
 #define IHIFI_PAD          60
-#define SAMSUNG_YPR1_PAD  61
+#define SAMSUNG_YPR1_PAD   61
 #define SAMSUNG_YH92X_PAD  62
 #define DX50_PAD           63
 #define SONY_NWZA860_PAD   64 /* The NWZ-A860 is too different (touchscreen) */
-#define AGPTEK_ROCKER_PAD 65
+#define AGPTEK_ROCKER_PAD  65
+#define XDUOO_X3_PAD       66
 
 /* CONFIG_POWER_SAVE combinable bit flags*/
 #define POWERSV_CPU   0x1
@@ -287,6 +289,7 @@
 #define LCD_SAMSUNGYPR1   62 /* as used by Samsung YP-R1 */
 #define LCD_NWZ_LINUX   63 /* as used in the Linux-based NWZ series */
 #define LCD_INGENIC_LINUX 64
+#define LCD_XDUOOX3       65 /* as used by the xDuoo X3 */
 
 /* LCD_PIXELFORMAT */
 #define HORIZONTAL_PACKING 1
@@ -358,12 +361,13 @@ Lyre prototype 1 */
 #define RTC_MC13783  13 /* Freescale MC13783 PMIC */
 #define RTC_S5L8700  14
 #define RTC_S35390A  15
-#define RTC_JZ47XX   16 /* Ingenic Jz47XX */
+#define RTC_JZ4740   16 /* Ingenic Jz4740 */
 #define RTC_NANO2G   17 /* This seems to be a PCF5063x */
 #define RTC_D2       18 /* Either PCF50606 or PCF50635 */
 #define RTC_S35380A  19
 #define RTC_IMX233   20
 #define RTC_STM41T62 21 /* ST M41T62 */
+#define RTC_JZ4760   22 /* Ingenic Jz4760 */
 
 /* USB On-the-go */
 #define USBOTG_M66591   6591 /* M:Robe 500 */
@@ -372,6 +376,7 @@ Lyre prototype 1 */
 #define USBOTG_M5636    5636 /* iAudio X5 */
 #define USBOTG_ARC      5020 /* PortalPlayer 502x and IMX233 */
 #define USBOTG_JZ4740   4740 /* Ingenic Jz4740/Jz4732 */
+#define USBOTG_JZ4760   4760 /* Ingenic Jz4760/Jz4760B */
 #define USBOTG_AS3525   3525 /* AMS AS3525 */
 #define USBOTG_S3C6400X 6400 /* Samsung S3C6400X, also used in the S5L8701/S5L8702/S5L8720 */
 #define USBOTG_DESIGNWARE 6401 /* Synopsys DesignWare OTG, used in S5L8701/S5L8702/S5L8720/AS3252v2 */
@@ -612,6 +617,8 @@ Lyre prototype 1 */
 #include "config/sonynwze350.h"
 #elif defined(AGPTEK_ROCKER)
 #include "config/agptekrocker.h"
+#elif defined(XDUOO_X3)
+#include "config/xduoox3.h"
 #else
 /* no known platform */
 #endif
@@ -980,7 +987,7 @@ Lyre prototype 1 */
 
 #endif /* BOOTLOADER */
 
-#if defined(HAVE_USBSTACK) || (CONFIG_CPU == JZ4732) \
+#if defined(HAVE_USBSTACK) || (CONFIG_CPU == JZ4732) || (CONFIG_CPU == JZ4760B) \
     || (CONFIG_CPU == AS3525) || (CONFIG_CPU == AS3525v2) \
     || defined(CPU_S5L870X) || (CONFIG_CPU == S3C2440) \
     || defined(APPLICATION) || (CONFIG_CPU == PP5002) \
@@ -1057,14 +1064,14 @@ Lyre prototype 1 */
     (CONFIG_CPU == TCC7801) || \
     (CONFIG_CPU == IMX233 && !defined(PLUGIN) && !defined(CODEC)) || /* IMX233: core only */ \
     defined(CPU_S5L870X)) || /* Samsung S5L8700: core, plugins, codecs */ \
-    (CONFIG_CPU == JZ4732 && !defined(PLUGIN) && !defined(CODEC)) /* Jz4740: core only */
+    ((CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B) && !defined(PLUGIN) && !defined(CODEC)) /* Jz47XX: core only */
 #define ICODE_ATTR      __attribute__ ((section(".icode")))
 #define ICONST_ATTR     __attribute__ ((section(".irodata")))
 #define IDATA_ATTR      __attribute__ ((section(".idata")))
 #define IBSS_ATTR       __attribute__ ((section(".ibss")))
 #define USE_IRAM
 #if CONFIG_CPU != SH7034 && (CONFIG_CPU != AS3525 || MEMORYSIZE > 2) \
-    && CONFIG_CPU != JZ4732 && CONFIG_CPU != AS3525v2 && CONFIG_CPU != IMX233
+    && CONFIG_CPU != JZ4732 && CONFIG_CPU != JZ4760B && CONFIG_CPU != AS3525v2 && CONFIG_CPU != IMX233
 #define PLUGIN_USE_IRAM
 #endif
 #else
@@ -1207,6 +1214,7 @@ Lyre prototype 1 */
 #define USB_HAS_BULK
 #elif (CONFIG_USBOTG == USBOTG_ARC) || \
     (CONFIG_USBOTG == USBOTG_JZ4740) || \
+    (CONFIG_USBOTG == USBOTG_JZ4760) || \
     (CONFIG_USBOTG == USBOTG_M66591) || \
     (CONFIG_USBOTG == USBOTG_DESIGNWARE) || \
     (CONFIG_USBOTG == USBOTG_AS3525)
@@ -1231,7 +1239,8 @@ Lyre prototype 1 */
 #if defined(HAVE_BOOTLOADER_USB_MODE) || \
      defined(CREATIVE_ZVx) || defined(CPU_TCC77X) || defined(CPU_TCC780X) || \
      CONFIG_USBOTG == USBOTG_JZ4740 || CONFIG_USBOTG == USBOTG_AS3525 || \
-     CONFIG_USBOTG == USBOTG_S3C6400X || CONFIG_USBOTG == USBOTG_DESIGNWARE
+     CONFIG_USBOTG == USBOTG_S3C6400X || CONFIG_USBOTG == USBOTG_DESIGNWARE || \
+     CONFIG_USBOTG == USBOTG_JZ4760
 #define USB_ENABLE_STORAGE
 #endif
 
diff --git a/firmware/export/config/ondavx747.h b/firmware/export/config/ondavx747.h
index d02845808f..bf2c47e05c 100644
--- a/firmware/export/config/ondavx747.h
+++ b/firmware/export/config/ondavx747.h
@@ -91,7 +91,7 @@
 #define CONFIG_CODEC SWCODEC
 
 /* define this if you have a real-time clock */
-#define CONFIG_RTC RTC_JZ47XX
+#define CONFIG_RTC RTC_JZ4740
 
 /* Tuner config */
 #define CONFIG_TUNER TEA5767
diff --git a/firmware/export/config/ondavx767.h b/firmware/export/config/ondavx767.h
index 77fce1d1a4..3718d202a2 100644
--- a/firmware/export/config/ondavx767.h
+++ b/firmware/export/config/ondavx767.h
@@ -80,7 +80,7 @@
 #define CONFIG_CODEC SWCODEC
 
 /* define this if you have a real-time clock */
-#define CONFIG_RTC RTC_JZ47XX
+#define CONFIG_RTC RTC_JZ4740
 
 /* Define this for LCD backlight available */
 #define HAVE_BACKLIGHT
diff --git a/firmware/export/config/ondavx777.h b/firmware/export/config/ondavx777.h
index 404d193d4a..17e3eda165 100644
--- a/firmware/export/config/ondavx777.h
+++ b/firmware/export/config/ondavx777.h
@@ -85,7 +85,7 @@
 #define CONFIG_CODEC SWCODEC
 
 /* define this if you have a real-time clock */
-#define CONFIG_RTC RTC_JZ47XX
+#define CONFIG_RTC RTC_JZ4740
 
 /* Tuner config */
 #define CONFIG_TUNER TEA5767
diff --git a/firmware/export/config/xduoox3.h b/firmware/export/config/xduoox3.h
new file mode 100644
index 0000000000..3262917d2c
--- /dev/null
+++ b/firmware/export/config/xduoox3.h
@@ -0,0 +1,195 @@
+/*
+ * This config file is for xDuoo X3
+ */
+
+#define MODEL_NAME   "xDuoo X3"
+#define MODEL_NUMBER 106
+
+/* Offset ( in the firmware file's header ) to the file CRC */
+#define FIRMWARE_OFFSET_FILE_CRC  0
+
+/* Offset ( in the firmware file's header ) to the real data */
+#define FIRMWARE_OFFSET_FILE_DATA 8
+
+/* Support FAT16 for SD cards <= 2GB */
+#define HAVE_FAT16SUPPORT
+
+/* ChinaChip NAND FTL */
+#define CONFIG_NAND NAND_CC
+
+/* define this if you have a bitmap LCD display */
+#define HAVE_LCD_BITMAP
+
+/* define this if you have access to the quickscreen */
+#define HAVE_QUICKSCREEN
+
+/* define this if you would like tagcache to build on this target */
+#define HAVE_TAGCACHE
+
+/* define this if the target has volume keys which can be used in the lists */
+#define HAVE_VOLUME_IN_LIST
+
+/* LCD dimensions */
+#define LCD_WIDTH  128
+#define LCD_HEIGHT 64
+/* sqrt(128^2 + 64^2) / 1.0 = 143.1 */
+#define LCD_DPI 143
+#define LCD_DEPTH  1
+
+#define LCD_PIXELFORMAT VERTICAL_PACKING
+#define HAVE_NEGATIVE_LCD /* bright on dark */
+
+/* Display colours, for screenshots and sim (0xRRGGBB) */
+#define LCD_DARKCOLOR        0x000000
+#define LCD_BRIGHTCOLOR      0x000000
+#define LCD_BL_DARKCOLOR     0x000000
+#define LCD_BL_BRIGHTCOLOR   0x0de2e5
+
+/* define this if you have LCD enable function */
+#define HAVE_LCD_ENABLE
+
+#ifndef BOOTLOADER
+/* Define this if your LCD can be put to sleep.
+ * HAVE_LCD_ENABLE should be defined as well. */
+#define HAVE_LCD_SLEEP
+#define HAVE_LCD_SLEEP_SETTING
+#endif
+
+/* define this if you can flip your LCD */
+#define HAVE_LCD_FLIP
+
+/* define this if you can invert the pixels */
+#define HAVE_LCD_INVERT
+
+/* Define this for LCD backlight available */
+#define HAVE_BACKLIGHT
+#define HAVE_BACKLIGHT_BRIGHTNESS
+
+/* Which backlight fading type? */
+#define CONFIG_BACKLIGHT_FADING BACKLIGHT_FADING_SW_SETTING
+
+#define IRAM_LCDFRAMEBUFFER IDATA_ATTR /* put the lcd frame buffer in IRAM */
+
+/* Define this if you can detect headphones */
+#define HAVE_HEADPHONE_DETECTION
+
+#define CONFIG_KEYPAD XDUOO_X3_PAD
+
+/* Define this if a programmable hotkey is mapped */
+#define HAVE_HOTKEY
+
+/* Define this if you do software codec */
+#define CONFIG_CODEC SWCODEC
+
+/* Define this for LCD backlight available */
+#define HAVE_BACKLIGHT
+
+#ifndef BOOTLOADER
+/* define this if you have a real-time clock */
+#define CONFIG_RTC RTC_JZ4760
+#endif
+
+/* Define this if you have a software controlled poweroff */
+#define HAVE_SW_POWEROFF
+
+/* The number of bytes reserved for loadable codecs */
+#define CODEC_SIZE 0x100000
+
+/* The number of bytes reserved for loadable plugins */
+#define PLUGIN_BUFFER_SIZE 0x100000
+
+#define HAVE_CS4398
+#define CODEC_SLAVE
+
+/* has no tone controls, so we use the software ones */
+#define HAVE_SW_TONE_CONTROLS
+
+/* define the bitmask of hardware sample rates */
+#define HW_SAMPR_CAPS       SAMPR_CAP_ALL
+
+#define AB_REPEAT_ENABLE
+
+#define BATTERY_CAPACITY_DEFAULT 2000 /* default battery capacity */
+#define BATTERY_CAPACITY_MIN 500      /* min. capacity selectable */
+#define BATTERY_CAPACITY_MAX 2000     /* max. capacity selectable */
+#define BATTERY_CAPACITY_INC 100      /* capacity increment */
+#define BATTERY_TYPES_COUNT  1        /* only one type */
+
+#define CONFIG_BATTERY_MEASURE VOLTAGE_MEASURE
+
+/* Hardware controlled charging with monitoring */
+#define CONFIG_CHARGING CHARGING_MONITOR
+
+/* There is only USB charging */
+#define HAVE_USB_POWER
+
+#define CFG_EXTAL 12000000    /* EXT clock: 12 Mhz */
+
+/* define this if the flash memory uses the SecureDigital Memory Card protocol */
+#define CONFIG_STORAGE (STORAGE_SD /* | STORAGE_NAND */)
+
+#define HAVE_MULTIDRIVE
+#define NUM_DRIVES 2
+
+/* Define this if media can be exchanged on the fly */
+#ifndef BOOTLOADER
+#define HAVE_HOTSWAP
+#define HAVE_HOTSWAP_STORAGE_AS_MAIN
+#endif
+
+/* define this if you have a flash memory storage */
+#define HAVE_FLASH_STORAGE
+
+/** Non-simulator section **/
+#ifndef SIMULATOR
+
+/* Define this if you have a Ingenic JZ4760B */
+#define CONFIG_CPU JZ4760B
+
+/* Define this to the CPU frequency */
+#define CPU_FREQ 492000000    /* CPU clock: 492 MHz */
+
+/* Define this if you want to use the JZ47XX i2c interface */
+#define CONFIG_I2C I2C_JZ47XX
+
+#define NEED_ADC_CLOSE 1
+
+/* define this if the hardware can be powered off while charging */
+/* #define HAVE_POWEROFF_WHILE_CHARGING */
+
+/* Type of LCD */
+#define CONFIG_LCD LCD_XDUOOX3
+
+/* USB On-the-go */
+#define CONFIG_USBOTG     USBOTG_JZ4760
+
+/* enable these for the experimental usb stack */
+#define HAVE_USBSTACK
+
+/* Connect by events, not by tick polling */
+#define USB_STATUS_BY_EVENT
+
+#define USB_VENDOR_ID 0x0525
+#define USB_PRODUCT_ID 0xA4A5
+
+#define USB_NUM_ENDPOINTS  3
+#define USB_DEVBSS_ATTR    IBSS_ATTR
+
+#define BOOTFILE_EXT "x3"
+#define BOOTFILE     "rockbox." BOOTFILE_EXT
+#define BOOTDIR      "/.rockbox"
+
+#define INCLUDE_TIMEOUT_API
+
+#define ICODE_ATTR_TREMOR_NOT_MDCT
+
+#endif /* SIMULATOR */
+
+/** Port-specific settings **/
+
+#define CONFIG_SDRAM_START 0x80004000
+
+/* Main LCD backlight brightness range and defaults */
+#define MIN_BRIGHTNESS_SETTING          1
+#define MAX_BRIGHTNESS_SETTING          16
+#define DEFAULT_BRIGHTNESS_SETTING      16 /* "full brightness" */
diff --git a/firmware/export/cpu.h b/firmware/export/cpu.h
index 7405319822..201ffba656 100644
--- a/firmware/export/cpu.h
+++ b/firmware/export/cpu.h
@@ -68,6 +68,9 @@
 #if CONFIG_CPU == JZ4732
 #include "jz4740.h"
 #endif
+#if CONFIG_CPU == JZ4760B
+#include "jz4760b.h"
+#endif
 #if CONFIG_CPU == AS3525
 #include "as3525.h"
 #endif
diff --git a/firmware/export/cs4398.h b/firmware/export/cs4398.h
new file mode 100644
index 0000000000..99dce6b7fa
--- /dev/null
+++ b/firmware/export/cs4398.h
@@ -0,0 +1,116 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef _CS4398_H
+#define _CS4398_H
+
+#define CS4398_VOLUME_MIN       -1270
+#define CS4398_VOLUME_MAX       0
+
+#define AUDIOHW_CAPS (FILTER_ROLL_OFF_CAP | LINEOUT_CAP)
+AUDIOHW_SETTING(VOLUME, "dB", 0, 1, CS4398_VOLUME_MIN/10, CS4398_VOLUME_MAX/10, 0)
+AUDIOHW_SETTING(FILTER_ROLL_OFF, "", 0, 1, 0, 1, 0)
+
+void cs4398_write_reg(uint8_t reg, uint8_t val);
+uint8_t cs4398_read_reg(uint8_t reg);
+
+#define CS4398_I2C_ADDR         0x4f /* 1001111 */
+
+#define CS4398_REG_CHIPID       0x01
+#define CS4398_REG_MODECTL      0x02
+#define CS4398_REG_VOLMIX       0x03
+#define CS4398_REG_MUTE         0x04
+#define CS4398_REG_VOL_A        0x05
+#define CS4398_REG_VOL_B        0x06
+#define CS4398_REG_RAMPFILT     0x07
+#define CS4398_REG_MISC         0x08
+#define CS4398_REG_MISC2        0x09
+
+/* REG_CHIPID */
+#define CS4398_REV_MASK         0x07
+#define CS4398_PART_MASK        0xf8
+#define CS4398_PART_CS4398      0x70
+/* REG_MODECTL */
+#define CS4398_FM_MASK          0x03
+#define CS4398_FM_SINGLE        0x00
+#define CS4398_FM_DOUBLE        0x01
+#define CS4398_FM_QUAD          0x02
+#define CS4398_FM_DSD           0x03
+#define CS4398_DEM_MASK         0x0c
+#define CS4398_DEM_NONE         0x00
+#define CS4398_DEM_44100        0x04
+#define CS4398_DEM_48000        0x08
+#define CS4398_DEM_32000        0x0c
+#define CS4398_DIF_MASK         0x70
+#define CS4398_DIF_LJUST        0x00
+#define CS4398_DIF_I2S          0x10
+#define CS4398_DIF_RJUST_16     0x20
+#define CS4398_DIF_RJUST_24     0x30
+#define CS4398_DIF_RJUST_20     0x40
+#define CS4398_DIF_RJUST_18     0x50
+#define CS4398_DSD_SRC          0x80
+/* REG_VOLMIX */
+#define CS4398_ATAPI_MASK       0x1f
+#define CS4398_ATAPI_B_MUTE     0x00
+#define CS4398_ATAPI_B_R        0x01
+#define CS4398_ATAPI_B_L        0x02
+#define CS4398_ATAPI_B_LR       0x03
+#define CS4398_ATAPI_A_MUTE     0x00
+#define CS4398_ATAPI_A_R        0x04
+#define CS4398_ATAPI_A_L        0x08
+#define CS4398_ATAPI_A_LR       0x0c
+#define CS4398_ATAPI_MIX_LR_VOL 0x10
+#define CS4398_INVERT_B         0x20
+#define CS4398_INVERT_A         0x40
+#define CS4398_VOL_B_EQ_A       0x80
+/* REG_MUTE */
+#define CS4398_MUTEP_MASK       0x03
+#define CS4398_MUTEP_AUTO       0x00
+#define CS4398_MUTEP_LOW        0x02
+#define CS4398_MUTEP_HIGH       0x03
+#define CS4398_MUTE_B           0x08
+#define CS4398_MUTE_A           0x10
+#define CS4398_MUTEC_A_EQ_B     0x20
+#define CS4398_DAMUTE           0x40
+#define CS4398_PAMUTE           0x80
+/* REG_VOL_A */
+#define CS4398_VOL_A_MASK       0xff
+/* REG_VOL_B */
+#define CS4398_VOL_B_MASK       0xff
+/* REG_RAMPFILT */
+#define CS4398_DIR_DSD          0x01
+#define CS4398_FILT_SEL         0x04
+#define CS4398_RMP_DN           0x10
+#define CS4398_RMP_UP           0x20
+#define CS4398_ZERO_CROSS       0x40
+#define CS4398_SOFT_RAMP        0x80
+/* REG_MISC */
+#define CS4398_MCLKDIV3         0x08
+#define CS4398_MCLKDIV2         0x10
+#define CS4398_FREEZE           0x20
+#define CS4398_CPEN             0x40
+#define CS4398_PDN              0x80
+/* REG_MISC2 */
+#define CS4398_DSD_PM_EN        0x01
+#define CS4398_DSD_PM_MODE      0x02
+#define CS4398_INVALID_DSD      0x04
+#define CS4398_STATIC_DSD       0x08
+
+#endif
diff --git a/firmware/export/jz4760b.h b/firmware/export/jz4760b.h
new file mode 100644
index 0000000000..c523cc64c9
--- /dev/null
+++ b/firmware/export/jz4760b.h
@@ -0,0 +1,9643 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ * Copyright (C) 2008 Ingenic Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/*
+ *  jz4760b.h
+ *
+ *  JZ4760B common definition.
+ *
+ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
+ *
+ *  Author: <cwjia@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __JZ4760B_H__
+#define __JZ4760B_H__
+
+#if defined(__ASSEMBLY__) || defined(__LANGUAGE_ASSEMBLY)
+        #ifndef __MIPS_ASSEMBLER
+                #define __MIPS_ASSEMBLER
+        #endif
+        #define REG8(addr)      (addr)
+        #define REG16(addr)     (addr)
+        #define REG32(addr)     (addr)
+#else
+        typedef unsigned char u8;
+        typedef unsigned short u16;
+        typedef unsigned int u32;
+
+        #define REG8(addr)      *((volatile unsigned char *)(addr))
+        #define REG16(addr)     *((volatile unsigned short *)(addr))
+        #define REG32(addr)     *((volatile unsigned int *)(addr))
+
+        #define INREG8(x)               ((unsigned char)(*(volatile unsigned char *)(x)))
+        #define OUTREG8(x, y)           *(volatile unsigned char *)(x) = (y)
+        #define SETREG8(x, y)           OUTREG8(x, INREG8(x)|(y))
+        #define CLRREG8(x, y)           OUTREG8(x, INREG8(x)&~(y))
+        #define CMSREG8(x, y, m)        OUTREG8(x, (INREG8(x)&~(m))|(y))
+
+        #define INREG16(x)              ((unsigned short)(*(volatile unsigned short *)(x)))
+        #define OUTREG16(x, y)          *(volatile unsigned short *)(x) = (y)
+        #define SETREG16(x, y)          OUTREG16(x, INREG16(x)|(y))
+        #define CLRREG16(x, y)          OUTREG16(x, INREG16(x)&~(y))
+        #define CMSREG16(x, y, m)       OUTREG16(x, (INREG16(x)&~(m))|(y))
+
+        #define INREG32(x)              ((unsigned int)(*(volatile unsigned int *)(x)))
+        #define OUTREG32(x, y)          *(volatile unsigned int *)(x) = (y)
+        #define SETREG32(x, y)          OUTREG32(x, INREG32(x)|(y))
+        #define CLRREG32(x, y)          OUTREG32(x, INREG32(x)&~(y))
+        #define CMSREG32(x, y, m)       OUTREG32(x, (INREG32(x)&~(m))|(y))
+#endif
+
+/*
+ * Define the bit field macro to avoid the bit mistake
+ */
+#define BIT0            (1 << 0)
+#define BIT1            (1 << 1)
+#define BIT2            (1 << 2)
+#define BIT3            (1 << 3)
+#define BIT4            (1 << 4)
+#define BIT5            (1 << 5)
+#define BIT6            (1 << 6)
+#define BIT7            (1 << 7)
+#define BIT8            (1 << 8)
+#define BIT9            (1 << 9)
+#define BIT10           (1 << 10)
+#define BIT11           (1 << 11)
+#define BIT12           (1 << 12)
+#define BIT13           (1 << 13)
+#define BIT14           (1 << 14)
+#define BIT15           (1 << 15)
+#define BIT16           (1 << 16)
+#define BIT17           (1 << 17)
+#define BIT18           (1 << 18)
+#define BIT19           (1 << 19)
+#define BIT20           (1 << 20)
+#define BIT21           (1 << 21)
+#define BIT22           (1 << 22)
+#define BIT23           (1 << 23)
+#define BIT24           (1 << 24)
+#define BIT25           (1 << 25)
+#define BIT26           (1 << 26)
+#define BIT27           (1 << 27)
+#define BIT28           (1 << 28)
+#define BIT29           (1 << 29)
+#define BIT30           (1 << 30)
+#define BIT31           (1 << 31)
+
+/* Generate the bit field mask from msb to lsb */
+#define BITS_H2L(msb, lsb)  ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))
+
+/* Get the bit field value from the data which is read from the register */
+#define get_bf_value(data, lsb, mask)  (((data) & (mask)) >> (lsb))
+
+/*
+ * Define the module base addresses
+ */
+/* AHB0 BUS Devices Base */
+#define HARB0_BASE      0xB3000000
+/* AHB1 BUS Devices Base */
+#define HARB1_BASE      0xB3200000
+#define DMAGP0_BASE     0xB3210000
+#define DMAGP1_BASE     0xB3220000
+#define DMAGP2_BASE     0xB3230000
+#define DEBLK_BASE      0xB3270000
+#define IDCT_BASE       0xB3280000
+#define CABAC_BASE      0xB3290000
+#define TCSM0_BASE      0xB32B0000
+#define TCSM1_BASE      0xB32C0000
+#define SRAM_BASE       0xB32D0000
+/* AHB2 BUS Devices Base */
+#define HARB2_BASE      0xB3400000
+#define UHC_BASE        0xB3430000
+#define GPS_BASE        0xB3480000
+#define ETHC_BASE       0xB34B0000
+/* APB BUS Devices Base */
+#define PS2_BASE        0xB0060000
+
+/*
+ * General purpose I/O port module(GPIO) address definition
+ */
+#define GPIO_BASE       0xb0010000
+
+/* GPIO group offset */
+#define GPIO_GOS        0x100
+
+/* Each group address */
+#define GPIO_BASEA      (GPIO_BASE + (0) * GPIO_GOS)
+#define GPIO_BASEB      (GPIO_BASE + (1) * GPIO_GOS)
+#define GPIO_BASEC      (GPIO_BASE + (2) * GPIO_GOS)
+#define GPIO_BASED      (GPIO_BASE + (3) * GPIO_GOS)
+#define GPIO_BASEE      (GPIO_BASE + (4) * GPIO_GOS)
+#define GPIO_BASEF      (GPIO_BASE + (5) * GPIO_GOS)
+
+/*
+ * GPIO registers offset address definition
+ */
+#define GPIO_PXPIN_OFFSET       (0x00)  /*  r, 32, 0x00000000 */
+#define GPIO_PXDAT_OFFSET       (0x10)  /*  r, 32, 0x00000000 */
+#define GPIO_PXDATS_OFFSET      (0x14)  /*  w, 32, 0x???????? */
+#define GPIO_PXDATC_OFFSET      (0x18)  /*  w, 32, 0x???????? */
+#define GPIO_PXIM_OFFSET        (0x20)  /*  r, 32, 0xffffffff */
+#define GPIO_PXIMS_OFFSET       (0x24)  /*  w, 32, 0x???????? */
+#define GPIO_PXIMC_OFFSET       (0x28)  /*  w, 32, 0x???????? */
+#define GPIO_PXPE_OFFSET        (0x30)  /*  r, 32, 0x00000000 */
+#define GPIO_PXPES_OFFSET       (0x34)  /*  w, 32, 0x???????? */
+#define GPIO_PXPEC_OFFSET       (0x38)  /*  w, 32, 0x???????? */
+#define GPIO_PXFUN_OFFSET       (0x40)  /*  r, 32, 0x00000000 */
+#define GPIO_PXFUNS_OFFSET      (0x44)  /*  w, 32, 0x???????? */
+#define GPIO_PXFUNC_OFFSET      (0x48)  /*  w, 32, 0x???????? */
+#define GPIO_PXSEL_OFFSET       (0x50)  /*  r, 32, 0x00000000 */
+#define GPIO_PXSELS_OFFSET      (0x54)  /*  w, 32, 0x???????? */
+#define GPIO_PXSELC_OFFSET      (0x58)  /*  w, 32, 0x???????? */
+#define GPIO_PXDIR_OFFSET       (0x60)  /*  r, 32, 0x00000000 */
+#define GPIO_PXDIRS_OFFSET      (0x64)  /*  w, 32, 0x???????? */
+#define GPIO_PXDIRC_OFFSET      (0x68)  /*  w, 32, 0x???????? */
+#define GPIO_PXTRG_OFFSET       (0x70)  /*  r, 32, 0x00000000 */
+#define GPIO_PXTRGS_OFFSET      (0x74)  /*  w, 32, 0x???????? */
+#define GPIO_PXTRGC_OFFSET      (0x78)  /*  w, 32, 0x???????? */
+#define GPIO_PXFLG_OFFSET       (0x80)  /*  r, 32, 0x00000000 */
+#define GPIO_PXFLGC_OFFSET      (GPIO_PXDATS_OFFSET)  /*  w, 32, 0x???????? */
+#define GPIO_PXDS0_OFFSET       (0xC0)  /*  r, 32, 0x00000000 */
+#define GPIO_PXDS0S_OFFSET      (0xC4)  /*  w, 32, 0x00000000 */
+#define GPIO_PXDS0C_OFFSET      (0xC8)  /*  w, 32, 0x00000000 */
+#define GPIO_PXDS1_OFFSET       (0xD0)  /*  r, 32, 0x00000000 */
+#define GPIO_PXDS1S_OFFSET      (0xD4)  /*  w, 32, 0x00000000 */
+#define GPIO_PXDS1C_OFFSET      (0xD8)  /*  w, 32, 0x00000000 */
+#define GPIO_PXDS2_OFFSET       (0xE0)  /*  r, 32, 0x00000000 */
+#define GPIO_PXDS2S_OFFSET      (0xE4)  /*  w, 32, 0x00000000 */
+#define GPIO_PXDS2C_OFFSET      (0xE8)  /*  w, 32, 0x00000000 */
+#define GPIO_PXSL_OFFSET        (0xF0)  /*  r, 32, 0x00000000 */
+#define GPIO_PXSLS_OFFSET       (0xF4)  /*  w, 32, 0x00000000 */
+#define GPIO_PXSLC_OFFSET       (0xF8)  /*  w, 32, 0x00000000 */
+
+/*
+ * GPIO registers address definition
+ */
+#define GPIO_PXPIN(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPIN_OFFSET)
+#define GPIO_PXDAT(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDAT_OFFSET)
+#define GPIO_PXDATS(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDATS_OFFSET)
+#define GPIO_PXDATC(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDATC_OFFSET)
+#define GPIO_PXIM(n)    (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXIM_OFFSET)
+#define GPIO_PXIMS(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXIMS_OFFSET)
+#define GPIO_PXIMC(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXIMC_OFFSET)
+#define GPIO_PXPE(n)    (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPE_OFFSET)
+#define GPIO_PXPES(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPES_OFFSET)
+#define GPIO_PXPEC(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPEC_OFFSET)
+#define GPIO_PXFUN(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFUN_OFFSET)
+#define GPIO_PXFUNS(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFUNS_OFFSET)
+#define GPIO_PXFUNC(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFUNC_OFFSET)
+#define GPIO_PXSEL(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSEL_OFFSET)
+#define GPIO_PXSELS(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSELS_OFFSET)
+#define GPIO_PXSELC(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSELC_OFFSET)
+#define GPIO_PXDIR(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDIR_OFFSET)
+#define GPIO_PXDIRS(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDIRS_OFFSET)
+#define GPIO_PXDIRC(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDIRC_OFFSET)
+#define GPIO_PXTRG(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXTRG_OFFSET)
+#define GPIO_PXTRGS(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXTRGS_OFFSET)
+#define GPIO_PXTRGC(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXTRGC_OFFSET)
+#define GPIO_PXFLG(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFLG_OFFSET)
+#define GPIO_PXFLGC(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFLGC_OFFSET)
+#define GPIO_PXDS0(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS0_OFFSET)
+#define GPIO_PXDS0S(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS0S_OFFSET)
+#define GPIO_PXDS0C(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS0C_OFFSET)
+#define GPIO_PXDS1(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS1_OFFSET)
+#define GPIO_PXDS1S(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS1S_OFFSET)
+#define GPIO_PXDS1C(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS1C_OFFSET)
+#define GPIO_PXDS2(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS2_OFFSET)
+#define GPIO_PXDS2S(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS2S_OFFSET)
+#define GPIO_PXDS2C(n)  (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS2C_OFFSET)
+#define GPIO_PXSL(n)    (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSL_OFFSET)
+#define GPIO_PXSLS(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSLS_OFFSET)
+#define GPIO_PXSLC(n)   (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSLC_OFFSET)
+
+/*  */
+#define GPIO_PORT_NUM   6
+#define MAX_GPIO_NUM    192
+#define GPIO_WAKEUP     (30)
+
+#ifndef __MIPS_ASSEMBLER
+
+//n = 0,1,2,3,4,5 (PORTA, PORTB, PORTC, PORTD, PORTE, PORTF)
+#define REG_GPIO_PXPIN(n)       REG32(GPIO_PXPIN(n))
+#define REG_GPIO_PXDAT(n)       REG32(GPIO_PXDAT(n))
+#define REG_GPIO_PXDATS(n)      REG32(GPIO_PXDATS(n))
+#define REG_GPIO_PXDATC(n)      REG32(GPIO_PXDATC(n))
+#define REG_GPIO_PXIM(n)        REG32(GPIO_PXIM(n))
+#define REG_GPIO_PXIMS(n)       REG32(GPIO_PXIMS(n))
+#define REG_GPIO_PXIMC(n)       REG32(GPIO_PXIMC(n))
+#define REG_GPIO_PXPE(n)        REG32(GPIO_PXPE(n))
+#define REG_GPIO_PXPES(n)       REG32(GPIO_PXPES(n))
+#define REG_GPIO_PXPEC(n)       REG32(GPIO_PXPEC(n))
+#define REG_GPIO_PXFUN(n)       REG32(GPIO_PXFUN(n))
+#define REG_GPIO_PXFUNS(n)      REG32(GPIO_PXFUNS(n))
+#define REG_GPIO_PXFUNC(n)      REG32(GPIO_PXFUNC(n))
+#define REG_GPIO_PXSEL(n)       REG32(GPIO_PXSEL(n))
+#define REG_GPIO_PXSELS(n)      REG32(GPIO_PXSELS(n))
+#define REG_GPIO_PXSELC(n)      REG32(GPIO_PXSELC(n))
+#define REG_GPIO_PXDIR(n)       REG32(GPIO_PXDIR(n))
+#define REG_GPIO_PXDIRS(n)      REG32(GPIO_PXDIRS(n))
+#define REG_GPIO_PXDIRC(n)      REG32(GPIO_PXDIRC(n))
+#define REG_GPIO_PXTRG(n)       REG32(GPIO_PXTRG(n))
+#define REG_GPIO_PXTRGS(n)      REG32(GPIO_PXTRGS(n))
+#define REG_GPIO_PXTRGC(n)      REG32(GPIO_PXTRGC(n))
+#define REG_GPIO_PXFLG(n)       REG32(GPIO_PXFLG(n))
+#define REG_GPIO_PXFLGC(n)      REG32(GPIO_PXFLGC(n))
+#define REG_GPIO_PXDS0(n)       REG32(GPIO_PXDS0(n))
+#define REG_GPIO_PXDS0S(n)      REG32(GPIO_PXDS0S(n))
+#define REG_GPIO_PXDS0C(n)      REG32(GPIO_PXDS0C(n))
+#define REG_GPIO_PXDS1(n)       REG32(GPIO_PXDS1(n))
+#define REG_GPIO_PXDS1S(n)      REG32(GPIO_PXDS1S(n))
+#define REG_GPIO_PXDS1C(n)      REG32(GPIO_PXDS1C(n))
+#define REG_GPIO_PXDS2(n)       REG32(GPIO_PXDS2(n))
+#define REG_GPIO_PXDS2S(n)      REG32(GPIO_PXDS2S(n))
+#define REG_GPIO_PXDS2C(n)      REG32(GPIO_PXDS2C(n))
+#define REG_GPIO_PXSL(n)        REG32(GPIO_PXSL(n))
+#define REG_GPIO_PXSLS(n)       REG32(GPIO_PXSLS(n))
+#define REG_GPIO_PXSLC(n)       REG32(GPIO_PXSLC(n))
+
+/*----------------------------------------------------------------
+ * p is the port number (0,1,2,3,4,5)
+ * o is the pin offset (0-31) inside the port
+ * n is the absolute number of a pin (0-127), regardless of the port
+ */
+
+//----------------------------------------------------------------
+// Function Pins Mode
+
+#define __gpio_as_func0(n)                      \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXFUNS(p) = (1 << o);          \
+        REG_GPIO_PXTRGC(p) = (1 << o);          \
+        REG_GPIO_PXSELC(p) = (1 << o);          \
+} while (0)
+
+#define __gpio_as_func1(n)                      \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXFUNS(p) = (1 << o);          \
+        REG_GPIO_PXTRGC(p) = (1 << o);          \
+        REG_GPIO_PXSELS(p) = (1 << o);          \
+} while (0)
+
+#define __gpio_as_func2(n)                      \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXFUNS(p) = (1 << o);          \
+        REG_GPIO_PXTRGS(p) = (1 << o);          \
+        REG_GPIO_PXSELC(p) = (1 << o);          \
+} while (0)
+
+#define __gpio_as_func3(n)                      \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXFUNS(p) = (1 << o);          \
+        REG_GPIO_PXTRGS(p) = (1 << o);          \
+        REG_GPIO_PXSELS(p) = (1 << o);          \
+} while (0)
+
+/*
+ * UART0_TxD, UART0_RxD
+ */
+#define __gpio_as_uart0()                       \
+do {                                            \
+        unsigned int bits = BIT3 | BIT0;        \
+        REG_GPIO_PXFUNS(5) = bits;              \
+        REG_GPIO_PXTRGC(5) = bits;              \
+        REG_GPIO_PXSELC(5) = bits;              \
+        REG_GPIO_PXPES(5)  = bits;              \
+} while (0)
+
+/*
+ * UART0_TxD, UART0_RxD, UART0_CTS, UART0_RTS
+ */
+#define __gpio_as_uart0_ctsrts()                \
+do {                                            \
+        unsigned int bits = BITS_H2L(3, 0);     \
+        REG_GPIO_PXFUNS(5) = bits;              \
+        REG_GPIO_PXTRGC(5) = bits;              \
+        REG_GPIO_PXSELC(5) = bits;              \
+        REG_GPIO_PXPES(5)  = bits;              \
+} while (0)
+
+/*
+ * UART1_TxD, UART1_RxD
+ */
+#define __gpio_as_uart1()                       \
+do {                                            \
+        unsigned int bits = BIT28 | BIT26;      \
+        REG_GPIO_PXFUNS(3) = bits;              \
+        REG_GPIO_PXTRGC(3) = bits;              \
+        REG_GPIO_PXSELC(3) = bits;              \
+        REG_GPIO_PXPES(3)  = bits;              \
+} while (0)
+
+/*
+ * UART1_TxD, UART1_RxD, UART1_CTS, UART1_RTS
+ */
+#define __gpio_as_uart1_ctsrts()                \
+do {                                            \
+        unsigned int bits = BITS_H2L(29, 26);   \
+        REG_GPIO_PXFUNS(3) = bits;              \
+        REG_GPIO_PXTRGC(3) = bits;              \
+        REG_GPIO_PXSELC(3) = bits;              \
+        REG_GPIO_PXPES(3)  = bits;              \
+} while (0)
+
+/*
+ * UART2_TxD, UART2_RxD
+ */
+#define __gpio_as_uart2()                       \
+do {                                            \
+        unsigned int bits = BIT30 | BIT28;      \
+        REG_GPIO_PXFUNS(2) = bits;              \
+        REG_GPIO_PXTRGC(2) = bits;              \
+        REG_GPIO_PXSELC(2) = bits;              \
+        REG_GPIO_PXPES(2)  = bits;              \
+} while (0)
+
+/*
+ * UART2_TxD, UART2_RxD, UART2_CTS, UART2_RTS
+ */
+#define __gpio_as_uart2_ctsrts()                \
+do {                                            \
+        unsigned int bits = BITS_H2L(31, 28);   \
+        REG_GPIO_PXFUNS(2) = bits;              \
+        REG_GPIO_PXTRGC(2) = bits;              \
+        REG_GPIO_PXSELC(2) = bits;              \
+        REG_GPIO_PXPES(2)  = bits;              \
+} while (0)
+
+/* WARNING: the folloing macro do NOT check */
+/*
+ * UART3_TxD, UART3_RxD
+ */
+#define __gpio_as_uart3()                       \
+do {                                            \
+        unsigned int bits = BIT12;      \
+        REG_GPIO_PXFUNS(3) = bits;              \
+        REG_GPIO_PXTRGC(3) = bits;              \
+        REG_GPIO_PXSELS(3) = bits;              \
+        REG_GPIO_PXPES(3)  = bits;      \
+        bits = BIT5;    \
+        REG_GPIO_PXFUNS(4) = bits;              \
+        REG_GPIO_PXTRGC(4) = bits;              \
+        REG_GPIO_PXSELS(4) = bits;              \
+        REG_GPIO_PXPES(4)  = bits;      \
+} while (0)
+/*
+ * UART3_TxD, UART3_RxD, UART3_CTS, UART3_RTS
+ */
+#define __gpio_as_uart3_ctsrts()                \
+do {                                            \
+        REG_GPIO_PXFUNS(3) = (1 << 12);         \
+        REG_GPIO_PXTRGC(3) = (1 << 12);         \
+        REG_GPIO_PXSELC(3) = (1 << 12);         \
+        REG_GPIO_PXPES(3)  = (1 << 12);         \
+        REG_GPIO_PXFUNS(4) = 0x00000320;        \
+        REG_GPIO_PXTRGC(4) = 0x00000320;        \
+        REG_GPIO_PXSELS(4) = 0x00000020;        \
+        REG_GPIO_PXSELC(4) = 0x00000300;        \
+        REG_GPIO_PXPES(4)  = 0x00000320;        \
+} while (0)
+
+/*
+ * SD0 ~ SD7, CS1#, CLE, ALE, FRE#, FWE#, FRB#
+ * @n: chip select number(1 ~ 6)
+ */
+#define __gpio_as_nand_8bit(n)                                          \
+do {                                                                    \
+                                                                        \
+        REG_GPIO_PXFUNS(0) = 0x000c00ff; /* SD0 ~ SD7, FRE#, FWE# */ \
+        REG_GPIO_PXSELC(0) = 0x000c00ff;                                \
+        REG_GPIO_PXTRGC(0) = 0x000c00ff;                                \
+        REG_GPIO_PXPES(0) = 0x000c00ff;                                 \
+        REG_GPIO_PXFUNS(1) = 0x00000003; /* CLE(SA0_CL), ALE(SA1_AL) */ \
+        REG_GPIO_PXSELC(1) = 0x00000003;                                \
+        REG_GPIO_PXTRGC(1) = 0x00000003;                                \
+        REG_GPIO_PXPES(1) = 0x00000003;                                 \
+                                                                        \
+        REG_GPIO_PXFUNS(0) = 0x00200000 << ((n)-1); /* CSn */           \
+        REG_GPIO_PXSELC(0) = 0x00200000 << ((n)-1);                     \
+        REG_GPIO_PXTRGC(0) = 0x00200000 << ((n)-1);                     \
+        REG_GPIO_PXPES(0) = 0x00200000 << ((n)-1);                      \
+                                                                        \
+        REG_GPIO_PXFUNC(0) = 0x00100000; /* FRB#(input) */              \
+        REG_GPIO_PXSELC(0) = 0x00100000;                                \
+        REG_GPIO_PXDIRC(0) = 0x00100000;                                \
+        REG_GPIO_PXPES(0) = 0x00100000;                                 \
+} while (0)
+
+#define __gpio_as_nand_16bit(n)                                         \
+do {                                                                    \
+                                                                        \
+        REG_GPIO_PXFUNS(0) = 0x000cffff; /* SD0 ~ SD15, CS1#, FRE#, FWE# */ \
+        REG_GPIO_PXSELC(0) = 0x000cffff;                                \
+        REG_GPIO_PXTRGC(0) = 0x000cffff;                                \
+        REG_GPIO_PXPES(0) = 0x000cffff;                                 \
+        REG_GPIO_PXFUNS(1) = 0x00000003; /* CLE(SA2), ALE(SA3) */       \
+        REG_GPIO_PXSELC(1) = 0x00000003;                                \
+        REG_GPIO_PXTRGC(1) = 0x00000003;                                \
+        REG_GPIO_PXPES(1) = 0x00000003;                                 \
+                                                                        \
+        REG_GPIO_PXFUNS(0) = 0x00200000 << ((n)-1); /* CSn */           \
+        REG_GPIO_PXSELC(0) = 0x00200000 << ((n)-1);                     \
+        REG_GPIO_PXTRGC(0) = 0x00200000 << ((n)-1);                     \
+        REG_GPIO_PXPES(0) = 0x00200000 << ((n)-1);                      \
+                                                                        \
+        REG_GPIO_PXFUNC(0) = 0x00100000; /* FRB#(input) */              \
+        REG_GPIO_PXSELC(0) = 0x00100000;                                \
+        REG_GPIO_PXDIRC(0) = 0x00100000;                                \
+        REG_GPIO_PXPES(0) = 0x00100000;                                 \
+} while (0)
+
+/*
+ *  SLCD
+ */
+#define __gpio_as_slcd_16bit() \
+do {                                            \
+        REG_GPIO_PXFUNS(2) = 0x03cff0fc;        \
+        REG_GPIO_PXTRGC(2) = 0x03cff0fc;        \
+        REG_GPIO_PXSELC(2) = 0x03cff0fc;    \
+        REG_GPIO_PXPES(2) = 0x03cff0fc;    \
+} while (0)
+
+/*
+ * LCD_R3~LCD_R7, LCD_G2~LCD_G7, LCD_B3~LCD_B7,
+ * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
+ */
+#define __gpio_as_lcd_16bit()                   \
+do {                                            \
+        REG_GPIO_PXFUNS(2) = 0x0f8ff3f8;        \
+        REG_GPIO_PXTRGC(2) = 0x0f8ff3f8;        \
+        REG_GPIO_PXSELC(2) = 0x0f8ff3f8;        \
+        REG_GPIO_PXPES(2) = 0x0f8ff3f8;         \
+} while (0)
+
+/*
+ * LCD_R2~LCD_R7, LCD_G2~LCD_G7, LCD_B2~LCD_B7,
+ * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
+ */
+#define __gpio_as_lcd_18bit()                   \
+do {                                            \
+        REG_GPIO_PXFUNS(2) = 0x0fcff3fc;        \
+        REG_GPIO_PXTRGC(2) = 0x0fcff3fc;        \
+        REG_GPIO_PXSELC(2) = 0x0fcff3fc;        \
+        REG_GPIO_PXPES(2) = 0x0fcff3fc;         \
+} while (0)
+
+/*
+ * LCD_R0~LCD_R7, LCD_G0~LCD_G7, LCD_B0~LCD_B7,
+ * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
+ */
+#define __gpio_as_lcd_24bit()                   \
+do {                                            \
+        REG_GPIO_PXFUNS(2) = 0x0fffffff;        \
+        REG_GPIO_PXTRGC(2) = 0x0fffffff;        \
+        REG_GPIO_PXSELC(2) = 0x0fffffff;        \
+        REG_GPIO_PXPES(2) = 0x0fffffff;         \
+} while (0)
+
+/*
+ * LCD_R0~LCD_R7, LCD_G0~LCD_G7, LCD_B0~LCD_B7,
+ * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
+ */
+#define __gpio_clear_lcd_24bit()                \
+do {                                            \
+        REG_GPIO_PXFUNC(2) = 0x0fffffff;        \
+        REG_GPIO_PXTRGC(2) = 0x0fffffff;        \
+        REG_GPIO_PXSELC(2) = 0x0fffffff;        \
+        REG_GPIO_PXDIRS(2) = 0x0fffffff;        \
+        REG_GPIO_PXDATC(2) = 0x0fffffff;        \
+        REG_GPIO_PXPES(2) = 0x0fffffff;         \
+} while (0)
+
+/* Set data pin driver strength v: 0~7 */
+#define __gpio_set_lcd_data_driving_strength(v) \
+do {                                            \
+        unsigned int d;                 \
+        d = v & 0x1;                            \
+        if(d) REG_GPIO_PXDS0S(2) = 0x0ff3fcff;  \
+        else REG_GPIO_PXDS0C(2) = 0x0ff3fcff;   \
+        d = v & 0x2;                            \
+        if(d) REG_GPIO_PXDS1S(2) = 0x0ff3fcff;  \
+        else REG_GPIO_PXDS1C(2) = 0x0ff3fcff;   \
+        d = v & 0x4;                            \
+        if(d) REG_GPIO_PXDS2S(2) = 0x0ff3fcff;  \
+        else REG_GPIO_PXDS2C(2) = 0x0ff3fcff;   \
+} while(0)
+/* Set HSYNC VSYNC DE driver strength v: 0~7 */
+#define __gpio_set_lcd_sync_driving_strength(v) \
+do {                                            \
+        unsigned int d;                         \
+        d = v & 0x1;                            \
+        if(d) REG_GPIO_PXDS0S(2) = 0x000c0200;  \
+        else REG_GPIO_PXDS0C(2) = 0x000c0200;   \
+        d = v & 0x2;                            \
+        if(d) REG_GPIO_PXDS1S(2) = 0x000c0200;  \
+        else REG_GPIO_PXDS1C(2) = 0x000c0200;   \
+        d = v & 0x4;                            \
+        if(d) REG_GPIO_PXDS2S(2) = 0x000c0200;  \
+        else REG_GPIO_PXDS2C(2) = 0x000c0200;   \
+} while(0)
+/* Set PCLK driver strength v: 0~7 */
+#define __gpio_set_lcd_clk_driving_strength(v)  \
+do {                                            \
+        unsigned int d;                         \
+        d = v & 0x1;                            \
+        if(d) REG_GPIO_PXDS0S(2) = (1 << 8);    \
+        else REG_GPIO_PXDS0C(2) = (1 << 8);     \
+        d = v & 0x2;                            \
+        if(d) REG_GPIO_PXDS1S(2) = (1 << 8);    \
+        else REG_GPIO_PXDS1C(2) = (1 << 8);     \
+        d = v & 0x4;                            \
+        if(d) REG_GPIO_PXDS2S(2) = (1 << 8);    \
+        else REG_GPIO_PXDS2C(2) = (1 << 8);     \
+} while(0)
+
+/* Set fast slew rate */
+#define __gpio_set_lcd_data_fslew(n)            \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXSLS(p) = 0x0ff3fcff;         \
+} while(0)
+
+/* Set slow slew rate */
+#define __gpio_set_lcd_data_sslew(n)                    \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXSLC(p) = 0x0ff3fcff;         \
+} while(0)
+
+/* Set fast slew rate */
+#define __gpio_set_lcd_sync_fslew(n)            \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXSLS(p) = 0x000c0200;         \
+} while(0)
+
+/* Set slow slew rate */
+#define __gpio_set_lcd_sync_sslew(n)                    \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXSLC(p) = 0x000c0200;         \
+} while(0)
+
+/* Set fast slew rate */
+#define __gpio_set_lcd_pclk_fslew(n)            \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXSLS(p) = (1 << 8);           \
+} while(0)
+
+/* Set slow slew rate */
+#define __gpio_set_lcd_pclk_sslew(n)                    \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXSLC(p) = (1 << 8);           \
+} while(0)
+
+/*
+ *  LCD_CLS, LCD_SPL, LCD_PS, LCD_REV
+ */
+#define __gpio_as_lcd_special()                 \
+do {                                            \
+        REG_GPIO_PXFUNS(2) = 0x0fffffff;        \
+        REG_GPIO_PXTRGC(2) = 0x0fffffff;        \
+        REG_GPIO_PXSELC(2) = 0x0feffbfc;        \
+        REG_GPIO_PXSELS(2) = 0x00100403;        \
+        REG_GPIO_PXPES(2) = 0x0fffffff;         \
+} while (0)
+
+#define __gpio_as_epd()                         \
+do {                                            \
+        REG_GPIO_PXFUNS(1) = 0x00011e00;        \
+        REG_GPIO_PXTRGS(1) = 0x00011e00;        \
+        REG_GPIO_PXSELS(1) = 0x00011e00;        \
+        REG_GPIO_PXPES(1)  = 0x00011e00;        \
+} while (0)
+/*
+ * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
+ */
+#define __gpio_as_cim()                         \
+do {                                            \
+        REG_GPIO_PXFUNS(1) = 0x0003ffc0;        \
+        REG_GPIO_PXTRGC(1) = 0x0003ffc0;        \
+        REG_GPIO_PXSELC(1) = 0x0003ffc0;        \
+        REG_GPIO_PXPES(1)  = 0x0003ffc0;        \
+} while (0)
+
+/*
+ * SDATO, SDATI, BCLK, SYNC, SCLK_RSTN(gpio sepc) or
+ * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET(aic spec)
+ */
+#define __gpio_as_aic()         \
+do {                                    \
+        REG_GPIO_PXFUNS(3) = 0x00003000;        \
+        REG_GPIO_PXTRGC(3) = 0x00003000;        \
+        REG_GPIO_PXSELS(3) = 0x00001000;        \
+        REG_GPIO_PXSELC(3) = 0x00002000;        \
+        REG_GPIO_PXPES(3)  = 0x00003000;        \
+        REG_GPIO_PXFUNS(4) = 0x000000e0;        \
+        REG_GPIO_PXTRGS(4) = 0x00000020;        \
+        REG_GPIO_PXTRGC(4) = 0x000000c0;        \
+        REG_GPIO_PXSELC(4) = 0x000000e0;        \
+        REG_GPIO_PXPES(4)  = 0x000000e0;        \
+} while (0)
+
+#define __gpio_as_spdif()               \
+do {                                    \
+        REG_GPIO_PXFUNS(3) = 0x00003000;        \
+        REG_GPIO_PXTRGC(3) = 0x00003000;        \
+        REG_GPIO_PXSELS(3) = 0x00001000;        \
+        REG_GPIO_PXSELC(3) = 0x00002000;        \
+        REG_GPIO_PXPES(3)  = 0x00003000;        \
+        REG_GPIO_PXFUNS(4) = 0x000038e0;        \
+        REG_GPIO_PXTRGC(4) = 0x000038c0;        \
+        REG_GPIO_PXTRGS(4) = 0x00000020;        \
+        REG_GPIO_PXSELC(4) = 0x000038e0;        \
+        REG_GPIO_PXPES(4)  = 0x000038e0;        \
+} while (0)
+
+/*
+ * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D3
+ */
+#define __gpio_as_msc0_pa_4bit()                \
+do {                                            \
+        REG_GPIO_PXFUNS(0) = 0x00fc0000;        \
+        REG_GPIO_PXTRGC(0) = 0x00fc0000;        \
+        REG_GPIO_PXSELS(0) = 0x00ec0000;        \
+        REG_GPIO_PXSELC(0) = 0x00100000;        \
+        REG_GPIO_PXPES(0)  = 0x00fc0000;        \
+} while (0)
+
+/*
+ * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D7
+ */
+#define __gpio_as_msc0_pe_8bit()                        \
+do {                                            \
+        REG_GPIO_PXFUNS(4) = 0x3ff00000;        \
+        REG_GPIO_PXTRGC(4) = 0x3ff00000;        \
+        REG_GPIO_PXSELC(4) = 0x3ff00000;        \
+        REG_GPIO_PXPES(4)  = 0x3ff00000;        \
+        REG_GPIO_PXDS0S(4) = 0x3ff00000;        \
+} while (0)
+/*
+ * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D3
+ */
+#define __gpio_as_msc0_pe_4bit()                        \
+do {                                            \
+        REG_GPIO_PXFUNS(4) = 0x30f00000;        \
+        REG_GPIO_PXTRGC(4) = 0x30f00000;        \
+        REG_GPIO_PXSELC(4) = 0x30f00000;        \
+        REG_GPIO_PXPES(4)  = 0x30f00000;        \
+        REG_GPIO_PXDS0S(4) = 0x30f00000;        \
+} while (0)
+
+#define __gpio_as_msc0_boot()                   \
+do {                                            \
+        REG_GPIO_PXFUNS(0) = 0x00ec0000;        \
+        REG_GPIO_PXTRGC(0) = 0x00ec0000;        \
+        REG_GPIO_PXSELS(0) = 0x00ec0000;        \
+        REG_GPIO_PXPES(0)  = 0x00ec0000;        \
+        REG_GPIO_PXFUNS(0) = 0x00100000;        \
+        REG_GPIO_PXTRGC(0) = 0x00100000;        \
+        REG_GPIO_PXSELC(0) = 0x00100000;        \
+        REG_GPIO_PXPES(0)  = 0x00100000;        \
+                                                \
+} while (0)
+
+/*
+ * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D7
+ */
+#define __gpio_as_msc1_pe_8bit()                        \
+do {                                            \
+        REG_GPIO_PXFUNS(4) = 0x3ff00000;        \
+        REG_GPIO_PXTRGC(4) = 0x3ff00000;        \
+        REG_GPIO_PXSELS(4) = 0x3ff00000;        \
+        REG_GPIO_PXPES(4)  = 0x3ff00000;        \
+        REG_GPIO_PXDS0S(4) = 0x3ff00000;        \
+} while (0)
+/*
+ * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D3
+ */
+#define __gpio_as_msc1_pe_4bit()                        \
+do {                                            \
+        REG_GPIO_PXFUNS(4) = 0x30f00000;        \
+        REG_GPIO_PXTRGC(4) = 0x30f00000;        \
+        REG_GPIO_PXSELS(4) = 0x30f00000;        \
+        REG_GPIO_PXPES(4)  = 0x30f00000;        \
+        REG_GPIO_PXDS0S(4) = 0x30f00000;        \
+} while (0)
+
+/*
+ * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D3
+ */
+#define __gpio_as_msc1_pd_4bit()                        \
+do {                                            \
+        REG_GPIO_PXFUNS(3) = 0x03f00000;        \
+        REG_GPIO_PXTRGC(3) = 0x03f00000;        \
+        REG_GPIO_PXSELC(3) = 0x03f00000;        \
+        REG_GPIO_PXPES(3)  = 0x03f00000;        \
+        REG_GPIO_PXDS0S(3) = 0x03f00000;        \
+} while (0)
+
+/* Port B
+ * MSC2_CMD, MSC2_CLK, MSC2_D0 ~ MSC2_D3
+ */
+#define __gpio_as_msc2_pb_4bit()                \
+do {                                            \
+        REG_GPIO_PXFUNS(1) = 0xf0300000;        \
+        REG_GPIO_PXTRGC(1) = 0xf0300000;        \
+        REG_GPIO_PXSELC(1) = 0xf0300000;        \
+        REG_GPIO_PXPES(1)  = 0xf0300000;        \
+        REG_GPIO_PXDS0S(1) = 0xf0300000;        \
+} while (0)
+
+/*
+ * MSC2_CMD, MSC2_CLK, MSC2_D0 ~ MSC2_D7
+ */
+#define __gpio_as_msc2_pe_8bit()                        \
+do {                                            \
+        REG_GPIO_PXFUNS(4) = 0x3ff00000;        \
+        REG_GPIO_PXTRGS(4) = 0x3ff00000;        \
+        REG_GPIO_PXSELC(4) = 0x3ff00000;        \
+        REG_GPIO_PXPES(4)  = 0x3ff00000;        \
+        REG_GPIO_PXDS0S(4) = 0x3ff00000;        \
+} while (0)
+/*
+ * MSC2_CMD, MSC2_CLK, MSC2_D0 ~ MSC2_D3
+ */
+#define __gpio_as_msc2_pe_4bit()                        \
+do {                                            \
+        REG_GPIO_PXFUNS(4) = 0x30f00000;        \
+        REG_GPIO_PXTRGS(4) = 0x30f00000;        \
+        REG_GPIO_PXSELC(4) = 0x30f00000;        \
+        REG_GPIO_PXPES(4)  = 0x30f00000;        \
+        REG_GPIO_PXDS0S(4)= 0x30f00000;         \
+} while (0)
+#define __gpio_as_msc0_4bit     __gpio_as_msc0_pe_4bit /* default as msc0 4bit */
+#define __gpio_as_msc1_4bit     __gpio_as_msc1_pd_4bit /* msc1 only support 4bit */
+#define __gpio_as_msc           __gpio_as_msc0_4bit /* default as msc0 4bit */
+#define __gpio_as_msc0          __gpio_as_msc0_4bit /* msc0 default as 4bit */
+#define __gpio_as_msc1          __gpio_as_msc1_4bit /* msc1 only support 4bit */
+#define __gpio_as_msc0_8bit     __gpio_as_msc0_pe_8bit /* default as msc0 8bit */
+#define __gpio_as_msc1_8bit     __gpio_as_msc1_pd_8bit /* msc1 only support 8bit */
+/*
+ * TSCLK, TSSTR, TSFRM, TSFAIL, TSDI0~7
+ */
+#define __gpio_as_tssi_1()                      \
+do {                                            \
+        REG_GPIO_PXFUNS(1) = 0x0003ffc0;        \
+        REG_GPIO_PXTRGC(1) = 0x0003ffc0;        \
+        REG_GPIO_PXSELS(1) = 0x0003ffc0;        \
+        REG_GPIO_PXPES(1)  = 0x0003ffc0;        \
+} while (0)
+
+/*
+ * TSCLK, TSSTR, TSFRM, TSFAIL, TSDI0~7
+ */
+#define __gpio_as_tssi_2()                      \
+do {                                            \
+        REG_GPIO_PXFUNS(1) = 0xfff00000;        \
+        REG_GPIO_PXTRGC(1) = 0x0fc00000;        \
+        REG_GPIO_PXTRGS(1) = 0xf0300000;        \
+        REG_GPIO_PXSELC(1) = 0xfff00000;        \
+        REG_GPIO_PXPES(1)  = 0xfff00000;        \
+} while (0)
+
+/*
+ * SSI_CE0, SSI_CE1, SSI_GPC, SSI_CLK, SSI_DT, SSI_DR
+ */
+#define __gpio_as_ssi()                         \
+do {                                            \
+        REG_GPIO_PXFUNS(0) = 0x002c0000; /* SSI0_CE0, SSI0_CLK, SSI0_DT */ \
+        REG_GPIO_PXTRGS(0) = 0x002c0000;        \
+        REG_GPIO_PXSELC(0) = 0x002c0000;        \
+        REG_GPIO_PXPES(0)  = 0x002c0000;        \
+                                                \
+        REG_GPIO_PXFUNS(0) = 0x00100000; /* SSI0_DR */  \
+        REG_GPIO_PXTRGC(0) = 0x00100000;        \
+        REG_GPIO_PXSELS(0) = 0x00100000;        \
+        REG_GPIO_PXPES(0)  = 0x00100000;        \
+} while (0)
+
+/*
+ * SSI_CE0, SSI_CE2, SSI_GPC, SSI_CLK, SSI_DT, SSI1_DR
+ */
+#define __gpio_as_ssi_1()                       \
+do {                                            \
+        REG_GPIO_PXFUNS(5) = 0x0000fc00;        \
+        REG_GPIO_PXTRGC(5) = 0x0000fc00;        \
+        REG_GPIO_PXSELC(5) = 0x0000fc00;        \
+        REG_GPIO_PXPES(5)  = 0x0000fc00;        \
+} while (0)
+
+/* Port B
+ * SSI2_CE0, SSI2_CE2, SSI2_GPC, SSI2_CLK, SSI2_DT, SSI12_DR
+ */
+#define __gpio_as_ssi2_1()                      \
+do {                                            \
+        REG_GPIO_PXFUNS(5) = 0xf0300000;        \
+        REG_GPIO_PXTRGC(5) = 0xf0300000;        \
+        REG_GPIO_PXSELS(5) = 0xf0300000;        \
+        REG_GPIO_PXPES(5)  = 0xf0300000;        \
+} while (0)
+
+#define __gpio_as_pcm0() \
+do {                                            \
+        REG_GPIO_PXFUNS(3) = 0xf;       \
+        REG_GPIO_PXTRGC(3) = 0xf;       \
+        REG_GPIO_PXSELC(3) = 0xf;       \
+        REG_GPIO_PXPES(3)  = 0xf;       \
+} while (0)
+
+#define __gpio_as_pcm1() \
+do {                                            \
+        REG_GPIO_PXFUNS(3) = 0x1000;    \
+        REG_GPIO_PXTRGS(3) = 0x1000;    \
+        REG_GPIO_PXSELC(3) = 0x1000;    \
+        REG_GPIO_PXPES(3)  = 0x1000;    \
+        REG_GPIO_PXFUNS(4) = 0x1000;    \
+        REG_GPIO_PXTRGC(4) = 0x300;     \
+        REG_GPIO_PXTRGS(4) = 0x20;      \
+        REG_GPIO_PXSELS(4) = 0x320;     \
+        REG_GPIO_PXPES(4)  = 0x320;     \
+} while (0)
+/*
+ * I2C_SCK, I2C_SDA
+ */
+#define __gpio_as_i2c(n)                       \
+do {                                            \
+        REG_GPIO_PXFUNS(3+(n)) = 0xc0000000;    \
+        REG_GPIO_PXTRGC(3+(n)) = 0xc0000000;    \
+        REG_GPIO_PXSELC(3+(n)) = 0xc0000000;    \
+        REG_GPIO_PXPES(3+(n))  = 0xc0000000;    \
+} while (0)
+
+/*
+ * PWM0
+ */
+#define __gpio_as_pwm0()                        \
+do {                                            \
+        REG_GPIO_PXFUNS(4) = 0x1;       \
+        REG_GPIO_PXTRGC(4) = 0x1;       \
+        REG_GPIO_PXSELC(4) = 0x1;       \
+        REG_GPIO_PXPES(4) = 0x1;                \
+} while (0)
+
+/*
+ * PWM1
+ */
+#define __gpio_as_pwm1()                        \
+do {                                            \
+        REG_GPIO_PXFUNS(4) = 0x2;               \
+        REG_GPIO_PXTRGC(4) = 0x2;               \
+        REG_GPIO_PXSELC(4) = 0x2;               \
+        REG_GPIO_PXPEC(4) = 0x2;                \
+} while (0)
+
+/*
+ * PWM2
+ */
+#define __gpio_as_pwm2()                \
+do {                                    \
+        REG_GPIO_PXFUNS(4) = 0x4;       \
+        REG_GPIO_PXTRGC(4) = 0x4;       \
+        REG_GPIO_PXSELC(4) = 0x4;       \
+        REG_GPIO_PXPES(4) = 0x4;        \
+} while (0)
+
+/*
+ * PWM3
+ */
+#define __gpio_as_pwm3()                \
+do {                                    \
+        REG_GPIO_PXFUNS(4) = 0x8;       \
+        REG_GPIO_PXTRGC(4) = 0x8;       \
+        REG_GPIO_PXSELC(4) = 0x8;       \
+        REG_GPIO_PXPES(4) = 0x8;        \
+} while (0)
+
+/*
+ * PWM4
+ */
+#define __gpio_as_pwm4()                \
+do {                                    \
+        REG_GPIO_PXFUNS(4) = 0x10;      \
+        REG_GPIO_PXTRGC(4) = 0x10;      \
+        REG_GPIO_PXSELC(4) = 0x10;      \
+        REG_GPIO_PXPES(4) = 0x10;       \
+} while (0)
+
+/*
+ * PWM5
+ */
+#define __gpio_as_pwm5()                \
+do {                                    \
+        REG_GPIO_PXFUNS(4) = 0x20;      \
+        REG_GPIO_PXTRGC(4) = 0x20;      \
+        REG_GPIO_PXSELC(4) = 0x20;      \
+        REG_GPIO_PXPES(4) = 0x20;       \
+} while (0)
+
+/*
+ * n = 0 ~ 5
+ */
+#define __gpio_as_pwm(n)        __gpio_as_pwm##n()
+
+/*
+ * OWI - PA29 function 1
+ */
+#define __gpio_as_owi()                         \
+do {                                            \
+        REG_GPIO_PXFUNS(0) = 0x20000000;        \
+        REG_GPIO_PXTRGC(0) = 0x20000000;        \
+        REG_GPIO_PXSELS(0) = 0x20000000;        \
+} while (0)
+
+/*
+ * SCC - PD08 function 0
+ *       PD09 function 0
+ */
+#define __gpio_as_scc()                         \
+do {                                            \
+        REG_GPIO_PXFUNS(3) = 0xc0000300;        \
+        REG_GPIO_PXTRGC(3) = 0xc0000300;        \
+        REG_GPIO_PXSELC(3) = 0xc0000300;        \
+} while (0)
+
+#define __gpio_as_otg_drvvbus() \
+do {    \
+        REG_GPIO_PXDATC(4) = (1 << 10);         \
+        REG_GPIO_PXPEC(4) = (1 << 10);          \
+        REG_GPIO_PXSELC(4) = (1 << 10);         \
+        REG_GPIO_PXTRGC(4) = (1 << 10);         \
+        REG_GPIO_PXFUNS(4) = (1 << 10);         \
+} while (0)
+
+//-------------------------------------------
+// GPIO or Interrupt Mode
+
+#define __gpio_get_port(p)      (REG_GPIO_PXPIN(p))
+
+#define __gpio_port_as_output(p, o)             \
+do {                                            \
+    REG_GPIO_PXFUNC(p) = (1 << (o));            \
+    REG_GPIO_PXSELC(p) = (1 << (o));            \
+    REG_GPIO_PXDIRS(p) = (1 << (o));            \
+    REG_GPIO_PXPES(p) = (1 << (o));             \
+} while (0)
+
+#define __gpio_port_as_input(p, o)              \
+do {                                            \
+    REG_GPIO_PXFUNC(p) = (1 << (o));            \
+    REG_GPIO_PXSELC(p) = (1 << (o));            \
+    REG_GPIO_PXDIRC(p) = (1 << (o));            \
+} while (0)
+
+#define __gpio_as_output(n)                     \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        __gpio_port_as_output(p, o);            \
+} while (0)
+
+#define __gpio_as_input(n)                      \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        __gpio_port_as_input(p, o);             \
+} while (0)
+
+#define __gpio_set_pin(n)                       \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXDATS(p) = (1 << o);          \
+} while (0)
+
+#define __gpio_clear_pin(n)                     \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXDATC(p) = (1 << o);          \
+} while (0)
+
+#define __gpio_get_pin(n)                       \
+({                                              \
+        unsigned int p, o, v;                   \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        if (__gpio_get_port(p) & (1 << o))      \
+                v = 1;                          \
+        else                                    \
+                v = 0;                          \
+        v;                                      \
+})
+
+#define __gpio_as_irq_high_level(n)             \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXIMS(p) = (1 << o);           \
+        REG_GPIO_PXTRGC(p) = (1 << o);          \
+        REG_GPIO_PXFUNC(p) = (1 << o);          \
+        REG_GPIO_PXSELS(p) = (1 << o);          \
+        REG_GPIO_PXDIRS(p) = (1 << o);          \
+        REG_GPIO_PXFLGC(p) = (1 << o);          \
+        REG_GPIO_PXIMC(p) = (1 << o);           \
+} while (0)
+
+#define __gpio_as_irq_low_level(n)              \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXIMS(p) = (1 << o);           \
+        REG_GPIO_PXTRGC(p) = (1 << o);          \
+        REG_GPIO_PXFUNC(p) = (1 << o);          \
+        REG_GPIO_PXSELS(p) = (1 << o);          \
+        REG_GPIO_PXDIRC(p) = (1 << o);          \
+        REG_GPIO_PXFLGC(p) = (1 << o);          \
+        REG_GPIO_PXIMC(p) = (1 << o);           \
+} while (0)
+
+#define __gpio_as_irq_rise_edge(n)              \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXIMS(p) = (1 << o);           \
+        REG_GPIO_PXTRGS(p) = (1 << o);          \
+        REG_GPIO_PXFUNC(p) = (1 << o);          \
+        REG_GPIO_PXSELS(p) = (1 << o);          \
+        REG_GPIO_PXDIRS(p) = (1 << o);          \
+        REG_GPIO_PXFLGC(p) = (1 << o);          \
+        REG_GPIO_PXIMC(p) = (1 << o);           \
+} while (0)
+
+#define __gpio_as_irq_fall_edge(n)              \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXIMS(p) = (1 << o);           \
+        REG_GPIO_PXTRGS(p) = (1 << o);          \
+        REG_GPIO_PXFUNC(p) = (1 << o);          \
+        REG_GPIO_PXSELS(p) = (1 << o);          \
+        REG_GPIO_PXDIRC(p) = (1 << o);          \
+        REG_GPIO_PXFLGC(p) = (1 << o);          \
+        REG_GPIO_PXIMC(p) = (1 << o);           \
+} while (0)
+
+#define __gpio_mask_irq(n)                      \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXIMS(p) = (1 << o);           \
+} while (0)
+
+#define __gpio_unmask_irq(n)                    \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXIMC(p) = (1 << o);           \
+} while (0)
+
+#define __gpio_ack_irq(n)                       \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXFLGC(p) = (1 << o);          \
+} while (0)
+
+#define __gpio_get_irq()                        \
+({                                              \
+        unsigned int tmp, v = 0;                \
+        for (int p = 5; p >= 0; p--) {          \
+                tmp = REG_GPIO_PXFLG(p);        \
+                for (int i = 0; i < 32; i++)    \
+                        if (tmp & (1 << i))     \
+                                v = (32*p + i); \
+        }                                       \
+        v;                                      \
+})
+
+#define __gpio_group_irq(n)                     \
+({                                              \
+        register int tmp, i;                    \
+        tmp = REG_GPIO_PXFLG(n) & (~REG_GPIO_PXIM(n));  \
+        for (i=31;i>=0;i--)                     \
+                if (tmp & (1 << i))             \
+                        break;                  \
+        i;                                      \
+})
+
+#define __gpio_enable_pull(n)                   \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXPEC(p) = (1 << o);           \
+} while (0)
+
+#define __gpio_disable_pull(n)                  \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXPES(p) = (1 << o);           \
+} while (0)
+
+/* Set pin driver strength v: 0~7 */
+#define __gpio_set_driving_strength(n, v)       \
+do {                                            \
+        unsigned int p, o, d;                   \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        d = v & 0x1;                            \
+        if(d) REG_GPIO_PXDS0S(p) = (1 << o);    \
+        else REG_GPIO_PXDS0C(p) = (1 << o);     \
+        d = v & 0x2;                            \
+        if(d) REG_GPIO_PXDS1S(p) = (1 << o);    \
+        else REG_GPIO_PXDS1C(p) = (1 << o);     \
+        d = v & 0x4;                            \
+        if(d) REG_GPIO_PXDS2S(p) = (1 << o);    \
+        else REG_GPIO_PXDS2C(p) = (1 << o);     \
+} while(0)
+
+/* Set fast slew rate */
+#define __gpio_set_fslew(n)     \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXSLS(p) = (1 << o);   \
+} while(0)
+
+/* Set slow slew rate */
+#define __gpio_set_sslew(n)     \
+do {                                            \
+        unsigned int p, o;                      \
+        p = (n) / 32;                           \
+        o = (n) % 32;                           \
+        REG_GPIO_PXSLC(p) = (1 << o);   \
+} while(0)
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define DMAC_BASE       0xB3420000
+
+/*************************************************************************
+ * DMAC (DMA Controller)
+ *************************************************************************/
+
+#define MAX_DMA_NUM     12  /* max 12 channels */
+#define MAX_MDMA_NUM    3   /* max 3  channels */
+#define MAX_BDMA_NUM    3   /* max 3  channels */
+#define HALF_DMA_NUM    6   /* the number of one dma controller's channels */
+
+/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
+
+#define DMAC_DSAR(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x00 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA source address */
+#define DMAC_DTAR(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x04 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA target address */
+#define DMAC_DTCR(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x08 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA transfer count */
+#define DMAC_DRSR(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x0c + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA request source */
+#define DMAC_DCCSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x10 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA control/status */
+#define DMAC_DCMD(n)  (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x14 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA command */
+#define DMAC_DDA(n)   (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x18 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA descriptor address */
+#define DMAC_DSD(n)   (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0xc0 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x04)) /* DMA Stride Address */
+
+#define DMAC_DMACR(m)   (DMAC_BASE + 0x0300 + 0x100 * (m))              /* DMA control register */
+#define DMAC_DMAIPR(m)  (DMAC_BASE + 0x0304 + 0x100 * (m))              /* DMA interrupt pending */
+#define DMAC_DMADBR(m)  (DMAC_BASE + 0x0308 + 0x100 * (m))              /* DMA doorbell */
+#define DMAC_DMADBSR(m) (DMAC_BASE + 0x030C + 0x100 * (m))              /* DMA doorbell set */
+#define DMAC_DMACKE(m)  (DMAC_BASE + 0x0310 + 0x100 * (m))
+#define DMAC_DMACKES(m) (DMAC_BASE + 0x0314 + 0x100 * (m))
+#define DMAC_DMACKEC(m) (DMAC_BASE + 0x0318 + 0x100 * (m))
+
+#define REG_DMAC_DSAR(n)        REG32(DMAC_DSAR((n)))
+#define REG_DMAC_DTAR(n)        REG32(DMAC_DTAR((n)))
+#define REG_DMAC_DTCR(n)        REG32(DMAC_DTCR((n)))
+#define REG_DMAC_DRSR(n)        REG32(DMAC_DRSR((n)))
+#define REG_DMAC_DCCSR(n)       REG32(DMAC_DCCSR((n)))
+#define REG_DMAC_DCMD(n)        REG32(DMAC_DCMD((n)))
+#define REG_DMAC_DDA(n)         REG32(DMAC_DDA((n)))
+#define REG_DMAC_DSD(n)         REG32(DMAC_DSD(n))
+#define REG_DMAC_DMACR(m)       REG32(DMAC_DMACR(m))
+#define REG_DMAC_DMAIPR(m)      REG32(DMAC_DMAIPR(m))
+#define REG_DMAC_DMADBR(m)      REG32(DMAC_DMADBR(m))
+#define REG_DMAC_DMADBSR(m)     REG32(DMAC_DMADBSR(m))
+#define REG_DMAC_DMACKE(m)      REG32(DMAC_DMACKE(m))
+#define REG_DMAC_DMACKES(m)     REG32(DMAC_DMACKES(m))
+#define REG_DMAC_DMACKEC(m)     REG32(DMAC_DMACKEC(m))
+
+// DMA request source register
+#define DMAC_DRSR_RS_BIT        0
+#define DMAC_DRSR_RS_MASK       (0x3f << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_NAND     (1 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_BCH_ENC  (2 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_BCH_DEC  (3 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_AUTO     (0x08 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_TSSIIN   (0x09 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_EXT      (0x0c << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_UART3OUT (0x0e << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_UART3IN  (0x0f << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_UART2OUT (0x10 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_UART2IN  (0x11 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_UART1OUT (0x12 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_UART1IN  (0x13 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_UART0OUT (0x14 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_UART0IN  (0x15 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_SSI0OUT  (0x16 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_SSI0IN   (0x17 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_AICOUT   (0x18 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_AICIN    (0x19 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_MSC0OUT  (0x1a << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_MSC0IN   (0x1b << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_TCU      (0x1c << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_SADC     (0x1d << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_MSC1OUT  (0x1e << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_MSC1IN   (0x1f << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_SSI1OUT  (0x20 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_SSI1IN   (0x21 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_PMOUT    (0x22 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_PMIN     (0x23 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_MSC2OUT  (0x24 << DMAC_DRSR_RS_BIT)
+  #define DMAC_DRSR_RS_MSC2IN   (0x25 << DMAC_DRSR_RS_BIT)
+
+// DMA channel control/status register
+#define DMAC_DCCSR_NDES         (1 << 31) /* descriptor (0) or not (1) ? */
+#define DMAC_DCCSR_DES8         (1 << 30) /* Descriptor 8 Word */
+#define DMAC_DCCSR_DES4         (0 << 30) /* Descriptor 4 Word */
+#define DMAC_DCCSR_CDOA_BIT     16        /* copy of DMA offset address */
+#define DMAC_DCCSR_CDOA_MASK    (0xff << DMAC_DCCSR_CDOA_BIT)
+
+#define DMAC_DCCSR_AR           (1 << 4)  /* address error */
+#define DMAC_DCCSR_TT           (1 << 3)  /* transfer terminated */
+#define DMAC_DCCSR_HLT          (1 << 2)  /* DMA halted */
+#define DMAC_DCCSR_CT           (1 << 1)  /* count terminated */
+#define DMAC_DCCSR_EN           (1 << 0)  /* channel enable bit */
+
+// DMA channel command register 
+#define DMAC_DCMD_EACKS_LOW     (1 << 31) /* External DACK Output Level Select, active low */
+#define DMAC_DCMD_EACKS_HIGH    (0 << 31) /* External DACK Output Level Select, active high */
+#define DMAC_DCMD_EACKM_WRITE   (1 << 30) /* External DACK Output Mode Select, output in write cycle */
+#define DMAC_DCMD_EACKM_READ    (0 << 30) /* External DACK Output Mode Select, output in read cycle */
+#define DMAC_DCMD_ERDM_BIT      28        /* External DREQ Detection Mode Select */
+#define DMAC_DCMD_ERDM_MASK     (0x03 << DMAC_DCMD_ERDM_BIT)
+  #define DMAC_DCMD_ERDM_LOW    (0 << DMAC_DCMD_ERDM_BIT)
+  #define DMAC_DCMD_ERDM_FALL   (1 << DMAC_DCMD_ERDM_BIT)
+  #define DMAC_DCMD_ERDM_HIGH   (2 << DMAC_DCMD_ERDM_BIT)
+  #define DMAC_DCMD_ERDM_RISE   (3 << DMAC_DCMD_ERDM_BIT)
+#define DMAC_DCMD_BLAST         (1 << 25) /* BCH last */
+#define DMAC_DCMD_SAI           (1 << 23) /* source address increment */
+#define DMAC_DCMD_DAI           (1 << 22) /* dest address increment */
+#define DMAC_DCMD_RDIL_BIT      16        /* request detection interval length */
+#define DMAC_DCMD_RDIL_MASK     (0x0f << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_IGN    (0 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_2      (0x01 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_4      (0x02 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_8      (0x03 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_12     (0x04 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_16     (0x05 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_20     (0x06 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_24     (0x07 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_28     (0x08 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_32     (0x09 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_48     (0x0a << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_60     (0x0b << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_64     (0x0c << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_124    (0x0d << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_128    (0x0e << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_200    (0x0f << DMAC_DCMD_RDIL_BIT)
+#define DMAC_DCMD_SWDH_BIT      14  /* source port width */
+#define DMAC_DCMD_SWDH_MASK     (0x03 << DMAC_DCMD_SWDH_BIT)
+  #define DMAC_DCMD_SWDH_32     (0 << DMAC_DCMD_SWDH_BIT)
+  #define DMAC_DCMD_SWDH_8      (1 << DMAC_DCMD_SWDH_BIT)
+  #define DMAC_DCMD_SWDH_16     (2 << DMAC_DCMD_SWDH_BIT)
+#define DMAC_DCMD_DWDH_BIT      12  /* dest port width */
+#define DMAC_DCMD_DWDH_MASK     (0x03 << DMAC_DCMD_DWDH_BIT)
+  #define DMAC_DCMD_DWDH_32     (0 << DMAC_DCMD_DWDH_BIT)
+  #define DMAC_DCMD_DWDH_8      (1 << DMAC_DCMD_DWDH_BIT)
+  #define DMAC_DCMD_DWDH_16     (2 << DMAC_DCMD_DWDH_BIT)
+#define DMAC_DCMD_DS_BIT        8  /* transfer data size of a data unit */
+#define DMAC_DCMD_DS_MASK       (0x07 << DMAC_DCMD_DS_BIT)
+  #define DMAC_DCMD_DS_32BIT    (0 << DMAC_DCMD_DS_BIT)
+  #define DMAC_DCMD_DS_8BIT     (1 << DMAC_DCMD_DS_BIT)
+  #define DMAC_DCMD_DS_16BIT    (2 << DMAC_DCMD_DS_BIT)
+  #define DMAC_DCMD_DS_16BYTE   (3 << DMAC_DCMD_DS_BIT)
+  #define DMAC_DCMD_DS_32BYTE   (4 << DMAC_DCMD_DS_BIT)
+  #define DMAC_DCMD_DS_64BYTE   (5 << DMAC_DCMD_DS_BIT)
+
+#define DMAC_DCMD_STDE          (1 << 2)  /* Stride enable */
+#define DMAC_DCMD_TIE           (1 << 1)  /* DMA transfer interrupt enable */
+#define DMAC_DCMD_LINK          (1 << 0)  /* descriptor link enable */
+
+// DMA descriptor address register
+#define DMAC_DDA_BASE_BIT       12  /* descriptor base address */
+#define DMAC_DDA_BASE_MASK      (0x0fffff << DMAC_DDA_BASE_BIT)
+#define DMAC_DDA_OFFSET_BIT     4   /* descriptor offset address */
+#define DMAC_DDA_OFFSET_MASK    (0x0ff << DMAC_DDA_OFFSET_BIT)
+
+// DMA stride address register
+#define DMAC_DSD_TSD_BIT        16  /* target stride address */
+#define DMAC_DSD_TSD_MASK       (0xffff << DMAC_DSD_TSD_BIT)
+#define DMAC_DSD_SSD_BIT        0  /* source stride address */
+#define DMAC_DSD_SSD_MASK       (0xffff << DMAC_DSD_SSD_BIT)
+
+// DMA control register
+#define DMAC_DMACR_FMSC         (1 << 31)  /* MSC Fast DMA mode */
+#define DMAC_DMACR_FSSI         (1 << 30)  /* SSI Fast DMA mode */
+#define DMAC_DMACR_FTSSI        (1 << 29)  /* TSSI Fast DMA mode */
+#define DMAC_DMACR_FUART        (1 << 28)  /* UART Fast DMA mode */
+#define DMAC_DMACR_FAIC         (1 << 27)  /* AIC Fast DMA mode */
+#define DMAC_DMACR_PR_BIT       8  /* channel priority mode */
+#define DMAC_DMACR_PR_MASK      (0x03 << DMAC_DMACR_PR_BIT)
+  #define DMAC_DMACR_PR_012345  (0 << DMAC_DMACR_PR_BIT)
+  #define DMAC_DMACR_PR_120345  (1 << DMAC_DMACR_PR_BIT)
+  #define DMAC_DMACR_PR_230145  (2 << DMAC_DMACR_PR_BIT)
+  #define DMAC_DMACR_PR_340125  (3 << DMAC_DMACR_PR_BIT)
+#define DMAC_DMACR_HLT          (1 << 3)  /* DMA halt flag */
+#define DMAC_DMACR_AR           (1 << 2)  /* address error flag */
+#define DMAC_DMACR_DMAE         (1 << 0)  /* DMA enable bit */
+
+// DMA doorbell register
+#define DMAC_DMADBR_DB5         (1 << 5)  /* doorbell for channel 5 */
+#define DMAC_DMADBR_DB4         (1 << 4)  /* doorbell for channel 4 */
+#define DMAC_DMADBR_DB3         (1 << 3)  /* doorbell for channel 3 */
+#define DMAC_DMADBR_DB2         (1 << 2)  /* doorbell for channel 2 */
+#define DMAC_DMADBR_DB1         (1 << 1)  /* doorbell for channel 1 */
+#define DMAC_DMADBR_DB0         (1 << 0)  /* doorbell for channel 0 */
+
+// DMA doorbell set register
+#define DMAC_DMADBSR_DBS5       (1 << 5)  /* enable doorbell for channel 5 */
+#define DMAC_DMADBSR_DBS4       (1 << 4)  /* enable doorbell for channel 4 */
+#define DMAC_DMADBSR_DBS3       (1 << 3)  /* enable doorbell for channel 3 */
+#define DMAC_DMADBSR_DBS2       (1 << 2)  /* enable doorbell for channel 2 */
+#define DMAC_DMADBSR_DBS1       (1 << 1)  /* enable doorbell for channel 1 */
+#define DMAC_DMADBSR_DBS0       (1 << 0)  /* enable doorbell for channel 0 */
+
+// DMA interrupt pending register
+#define DMAC_DMAIPR_CIRQ5       (1 << 5)  /* irq pending status for channel 5 */
+#define DMAC_DMAIPR_CIRQ4       (1 << 4)  /* irq pending status for channel 4 */
+#define DMAC_DMAIPR_CIRQ3       (1 << 3)  /* irq pending status for channel 3 */
+#define DMAC_DMAIPR_CIRQ2       (1 << 2)  /* irq pending status for channel 2 */
+#define DMAC_DMAIPR_CIRQ1       (1 << 1)  /* irq pending status for channel 1 */
+#define DMAC_DMAIPR_CIRQ0       (1 << 0)  /* irq pending status for channel 0 */
+
+#ifndef __MIPS_ASSEMBLER
+
+/***************************************************************************
+ * DMAC
+ ***************************************************************************/
+
+/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
+
+#define __dmac_enable_module(m) \
+        ( REG_DMAC_DMACR(m) |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_012345 )
+#define __dmac_disable_module(m) \
+        ( REG_DMAC_DMACR(m) &= ~DMAC_DMACR_DMAE )
+
+/* p=0,1,2,3 */
+#define __dmac_set_priority(m,p)                        \
+do {                                                    \
+        REG_DMAC_DMACR(m) &= ~DMAC_DMACR_PR_MASK;       \
+        REG_DMAC_DMACR(m) |= ((p) << DMAC_DMACR_PR_BIT);        \
+} while (0)
+
+#define __dmac_test_halt_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_HLT )
+#define __dmac_test_addr_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_AR )
+
+#define __dmac_channel_enable_clk(n) \
+        REG_DMAC_DMACKES((n)/HALF_DMA_NUM) = 1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM);
+
+#define __dmac_channel_disable_clk(n) \
+        REG_DMAC_DMACKEC((n)/HALF_DMA_NUM) = 1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM);
+
+#define __dmac_enable_descriptor(n) \
+  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
+#define __dmac_disable_descriptor(n) \
+  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
+
+#define __dmac_enable_channel(n)                 \
+do {                                             \
+        REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN;    \
+} while (0)
+#define __dmac_disable_channel(n)                \
+do {                                             \
+        REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN;   \
+} while (0)
+#define __dmac_channel_enabled(n) \
+  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )
+
+#define __dmac_channel_enable_irq(n) \
+  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )
+#define __dmac_channel_disable_irq(n) \
+  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
+
+#define __dmac_channel_transmit_halt_detected(n) \
+  (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
+#define __dmac_channel_transmit_end_detected(n) \
+  (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
+#define __dmac_channel_address_error_detected(n) \
+  (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
+
+#define __dmac_channel_count_terminated_detected(n) \
+  (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )
+#define __dmac_channel_descriptor_invalid_detected(n) \
+  (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )
+
+#define __dmac_channel_clear_transmit_halt(n)                           \
+        do {                                                            \
+                /* clear both channel halt error and globle halt error */ \
+                REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT;                   \
+                REG_DMAC_DMACR(n/HALF_DMA_NUM) &= ~DMAC_DMACR_HLT;      \
+        } while (0)
+#define __dmac_channel_clear_transmit_end(n) \
+  (  REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
+#define __dmac_channel_clear_address_error(n)                           \
+        do {                                                            \
+                REG_DMAC_DDA(n) = 0; /* clear descriptor address register */ \
+                REG_DMAC_DSAR(n) = 0; /* clear source address register */ \
+                REG_DMAC_DTAR(n) = 0; /* clear target address register */ \
+                /* clear both channel addr error and globle address error */ \
+                REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR;                    \
+                REG_DMAC_DMACR(n/HALF_DMA_NUM) &= ~DMAC_DMACR_AR;       \
+        } while (0)
+
+#define __dmac_channel_clear_count_terminated(n) \
+  (  REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
+#define __dmac_channel_clear_descriptor_invalid(n) \
+  (  REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
+
+#define __dmac_channel_set_transfer_unit_32bit(n)       \
+do {                                                    \
+        REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;       \
+        REG_DMAC_DCMD((n)) |= MAC_DCMD_DS_32BIT;        \
+} while (0)
+
+#define __dmac_channel_set_transfer_unit_16bit(n)       \
+do {                                                    \
+        REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;       \
+        REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT;       \
+} while (0)
+
+#define __dmac_channel_set_transfer_unit_8bit(n)        \
+do {                                                    \
+        REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;       \
+        REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT;        \
+} while (0)
+
+#define __dmac_channel_set_transfer_unit_16byte(n)      \
+do {                                                    \
+        REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;       \
+        REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE;      \
+} while (0)
+
+#define __dmac_channel_set_transfer_unit_32byte(n)      \
+do {                                                    \
+        REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;       \
+        REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE;      \
+} while (0)
+
+/* w=8,16,32 */
+#define __dmac_channel_set_dest_port_width(n,w)         \
+do {                                                    \
+        REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK;     \
+        REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w;       \
+} while (0)
+
+/* w=8,16,32 */
+#define __dmac_channel_set_src_port_width(n,w)          \
+do {                                                    \
+        REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK;     \
+        REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w;       \
+} while (0)
+
+/* v=0-15 */
+#define __dmac_channel_set_rdil(n,v)                            \
+do {                                                            \
+        REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK;             \
+        REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT);       \
+} while (0)
+
+#define __dmac_channel_dest_addr_fixed(n) \
+  (  REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )
+#define __dmac_channel_dest_addr_increment(n) \
+  (  REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )
+
+#define __dmac_channel_src_addr_fixed(n) \
+  (  REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )
+#define __dmac_channel_src_addr_increment(n) \
+  (  REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )
+
+#define __dmac_channel_set_doorbell(n)  \
+        (  REG_DMAC_DMADBSR((n)/HALF_DMA_NUM) = (1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) )
+
+#define __dmac_channel_irq_detected(n)  ( REG_DMAC_DMAIPR((n)/HALF_DMA_NUM) & (1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) )
+#define __dmac_channel_ack_irq(n)       ( REG_DMAC_DMAIPR((n)/HALF_DMA_NUM) &= ~(1 <<((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) )
+
+static __inline__ int __dmac_get_irq(void)
+{
+        int i;
+        for (i = 0; i < MAX_DMA_NUM; i++)
+                if (__dmac_channel_irq_detected(i))
+                        return i;
+        return -1;
+}
+
+#endif /* __MIPS_ASSEMBLER */
+
+/*
+ * Interrupt controller module(INTC) address definition
+ */
+#define INTC_BASE       0xB0001000
+
+/*
+ * INTC registers offset address definition
+ */
+#define INTC_ICSR_OFFSET        (0x00)  /* 32, r,  0x00000000 */
+#define INTC_ICMR_OFFSET        (0x04)  /* 32, rw, 0xffffffff */
+#define INTC_ICMSR_OFFSET       (0x08)  /* 32, w,  0x???????? */
+#define INTC_ICMCR_OFFSET       (0x0c)  /* 32, w,  0x???????? */
+#define INTC_ICPR_OFFSET        (0x10)  /* 32, r,  0x00000000 */
+
+/* INTC groups offset */
+#define INTC_GOS                0x20
+
+/*
+ * INTC registers address definition
+ */
+#define INTC_ICSR(n)    (INTC_BASE + (n) * INTC_GOS + INTC_ICSR_OFFSET)
+#define INTC_ICMR(n)    (INTC_BASE + (n) * INTC_GOS + INTC_ICMR_OFFSET)
+#define INTC_ICMSR(n)   (INTC_BASE + (n) * INTC_GOS + INTC_ICMSR_OFFSET)
+#define INTC_ICMCR(n)   (INTC_BASE + (n) * INTC_GOS + INTC_ICMCR_OFFSET)
+#define INTC_ICPR(n)    (INTC_BASE + (n) * INTC_GOS + INTC_ICPR_OFFSET)
+
+/*
+ * INTC registers common define
+ */
+
+/* 1st-level interrupts */
+#define IRQ_I2C1        0
+#define IRQ_I2C0        1
+#define IRQ_UART3       2
+#define IRQ_UART2       3
+#define IRQ_UART1       4
+#define IRQ_UART0       5
+#define IRQ_GPU         6
+#define IRQ_SSI1        7
+#define IRQ_SSI0        8
+#define IRQ_TSSI        9
+#define IRQ_BDMA        10
+#define IRQ_KBC         11
+#define IRQ_GPIO5       12
+#define IRQ_GPIO4       13
+#define IRQ_GPIO3       14
+#define IRQ_GPIO2       15
+#define IRQ_GPIO1       16
+#define IRQ_GPIO0       17
+#define IRQ_SADC        18
+#define IRQ_ETH         19
+#define IRQ_UHC         20
+#define IRQ_OTG         21
+#define IRQ_MDMA        22
+#define IRQ_DMAC1       23
+#define IRQ_DMAC0       24
+#define IRQ_TCU2        25
+#define IRQ_TCU1        26
+#define IRQ_TCU0        27
+#define IRQ_GPS         28
+#define IRQ_IPU         29
+#define IRQ_CIM         30
+#define IRQ_LCD         31
+
+#define IRQ_RTC         32      /* 32 + 0 */
+#define IRQ_OWI         33      /* 32 + 1 */
+#define IRQ_AIC         34      /* 32 + 2 */
+#define IRQ_MSC2        35      /* 32 + 3 */
+#define IRQ_MSC1        36      /* 32 + 4 */
+#define IRQ_MSC0        37      /* 32 + 5 */
+#define IRQ_SCC         38      /* 32 + 6 */
+#define IRQ_BCH         39      /* 32 + 7 */
+#define IRQ_PCM         40      /* 32 + 8 */
+#define IRQ_HARB0       41      /* 32 + 9 */
+#define IRQ_HARB2       42      /* 32 + 10 */
+#define IRQ_AOSD        43      /* 32 + 11 */
+#define IRQ_CPM         44      /* 32 + 12 */
+
+#define IRQ_INTC_MAX    45
+
+/* 2nd-level interrupts */
+#define IRQ_DMA_BASE    (IRQ_INTC_MAX)
+#define IRQ_DMA_MAX     (IRQ_DMA_BASE + NUM_DMA)
+
+#define IRQ_MDMA_BASE   (IRQ_DMA_MAX)
+#define IRQ_MDMA_MAX    (IRQ_MDMA_BASE + NUM_MDMA)
+
+#define IRQ_BDMA_BASE   (IRQ_MDMA_MAX)
+#define IRQ_BDMA_MAX    (IRQ_BDMA_BASE + NUM_BDMA)
+
+/* To be cleanup begin */
+#define IRQ_DMA_0       46
+#define IRQ_DMA_1       (IRQ_DMA_0 + HALF_DMA_NUM)      /* 46 +  6 = 52 */
+#define IRQ_MDMA_0      (IRQ_DMA_0 + MAX_DMA_NUM)       /* 46 + 12 = 58 */
+#define IRQ_BDMA_0      (IRQ_DMA_0 + MAX_DMA_NUM + MAX_MDMA_NUM)        /* 46 + 12 + 2 = 60 */
+
+#define IRQ_GPIO_0              64  /* 64 to (64+MAX_GPIO_NUM-1) for GPIO pin 0 to MAX_GPIO_NUM-1 */
+
+#define NUM_INTC                45
+#define NUM_DMA                 MAX_DMA_NUM
+#define NUM_MDMA                MAX_MDMA_NUM
+#define NUM_BDMA                MAX_BDMA_NUM
+#define NUM_GPIO                MAX_GPIO_NUM
+/* To be cleanup end */
+
+#ifndef __MIPS_ASSEMBLER
+
+#define REG_INTC_ICMR(n)        REG32(INTC_ICMR(n))
+#define REG_INTC_ICMSR(n)       REG32(INTC_ICMSR(n))
+#define REG_INTC_ICMCR(n)       REG32(INTC_ICMCR(n))
+#define REG_INTC_ICPR(n)        REG32(INTC_ICPR(n))
+
+#define __intc_unmask_irq(n)    (REG_INTC_ICMCR((n)/32) = (1 << ((n)%32)))
+#define __intc_mask_irq(n)      (REG_INTC_ICMSR((n)/32) = (1 << ((n)%32)))
+
+#endif /* __MIPS_ASSEMBLER */
+
+/*
+ * AC97 and I2S controller module(AIC) address definition
+ */
+#define AIC_BASE        0xb0020000
+
+/*
+ * AIC registers offset address definition
+ */
+#define AIC_FR_OFFSET           (0x00)
+#define AIC_CR_OFFSET           (0x04)
+#define AIC_ACCR1_OFFSET        (0x08)
+#define AIC_ACCR2_OFFSET        (0x0c)
+#define AIC_I2SCR_OFFSET        (0x10)
+#define AIC_SR_OFFSET           (0x14)
+#define AIC_ACSR_OFFSET         (0x18)
+#define AIC_I2SSR_OFFSET        (0x1c)
+#define AIC_ACCAR_OFFSET        (0x20)
+#define AIC_ACCDR_OFFSET        (0x24)
+#define AIC_ACSAR_OFFSET        (0x28)
+#define AIC_ACSDR_OFFSET        (0x2c)
+#define AIC_I2SDIV_OFFSET       (0x30)
+#define AIC_DR_OFFSET           (0x34)
+
+#define SPDIF_ENA_OFFSET        (0x80)
+#define SPDIF_CTRL_OFFSET       (0x84)
+#define SPDIF_STATE_OFFSET      (0x88)
+#define SPDIF_CFG1_OFFSET       (0x8c)
+#define SPDIF_CFG2_OFFSET       (0x90)
+#define SPDIF_FIFO_OFFSET       (0x94)
+
+#define ICDC_RGADW_OFFSET       (0xa4)
+#define ICDC_RGDATA_OFFSET      (0xa8)
+
+/*
+ * AIC registers address definition
+ */
+#define AIC_FR          (AIC_BASE + AIC_FR_OFFSET)
+#define AIC_CR          (AIC_BASE + AIC_CR_OFFSET)
+#define AIC_ACCR1       (AIC_BASE + AIC_ACCR1_OFFSET)
+#define AIC_ACCR2       (AIC_BASE + AIC_ACCR2_OFFSET)
+#define AIC_I2SCR       (AIC_BASE + AIC_I2SCR_OFFSET)
+#define AIC_SR          (AIC_BASE + AIC_SR_OFFSET)
+#define AIC_ACSR        (AIC_BASE + AIC_ACSR_OFFSET)
+#define AIC_I2SSR       (AIC_BASE + AIC_I2SSR_OFFSET)
+#define AIC_ACCAR       (AIC_BASE + AIC_ACCAR_OFFSET)
+#define AIC_ACCDR       (AIC_BASE + AIC_ACCDR_OFFSET)
+#define AIC_ACSAR       (AIC_BASE + AIC_ACSAR_OFFSET)
+#define AIC_ACSDR       (AIC_BASE + AIC_ACSDR_OFFSET)
+#define AIC_I2SDIV      (AIC_BASE + AIC_I2SDIV_OFFSET)
+#define AIC_DR          (AIC_BASE + AIC_DR_OFFSET)
+
+#define SPDIF_ENA       (AIC_BASE + SPDIF_ENA_OFFSET)
+#define SPDIF_CTRL      (AIC_BASE + SPDIF_CTRL_OFFSET)
+#define SPDIF_STATE     (AIC_BASE + SPDIF_STATE_OFFSET)
+#define SPDIF_CFG1      (AIC_BASE + SPDIF_CFG1_OFFSET)
+#define SPDIF_CFG2      (AIC_BASE + SPDIF_CFG2_OFFSET)
+#define SPDIF_FIFO      (AIC_BASE + SPDIF_FIFO_OFFSET)
+
+#define ICDC_RGADW      (AIC_BASE + ICDC_RGADW_OFFSET)
+#define ICDC_RGDATA     (AIC_BASE + ICDC_RGDATA_OFFSET)
+
+/*
+ * AIC registers common define
+ */
+
+/* AIC controller configuration register(AICFR) */
+#define AIC_FR_LSMP             BIT6
+#define AIC_FR_ICDC             BIT5
+#define AIC_FR_AUSEL            BIT4
+#define AIC_FR_RST              BIT3
+#define AIC_FR_BCKD             BIT2
+#define AIC_FR_SYNCD            BIT1
+#define AIC_FR_ENB              BIT0
+
+#define AIC_FR_RFTH_LSB         24
+#define AIC_FR_RFTH_MASK        BITS_H2L(27, AIC_FR_RFTH_LSB)
+
+#define AIC_FR_TFTH_LSB         16
+#define AIC_FR_TFTH_MASK        BITS_H2L(20, AIC_FR_TFTH_LSB)
+
+/* AIC controller common control register(AICCR) */
+#define AIC_CR_PACK16           BIT28
+#define AIC_CR_RDMS             BIT15
+#define AIC_CR_TDMS             BIT14
+#define AIC_CR_M2S              BIT11
+#define AIC_CR_ENDSW            BIT10
+#define AIC_CR_AVSTSU           BIT9
+#define AIC_CR_TFLUSH           BIT8
+#define AIC_CR_RFLUSH           BIT7
+#define AIC_CR_EROR             BIT6
+#define AIC_CR_ETUR             BIT5
+#define AIC_CR_ERFS             BIT4
+#define AIC_CR_ETFS             BIT3
+#define AIC_CR_ENLBF            BIT2
+#define AIC_CR_ERPL             BIT1
+#define AIC_CR_EREC             BIT0
+
+#define AIC_CR_CHANNEL_LSB      24
+#define AIC_CR_CHANNEL_MASK     BITS_H2L(26, AIC_CR_CHANNEL_LSB)
+
+#define AIC_CR_OSS_LSB          19
+#define AIC_CR_OSS_MASK         BITS_H2L(21, AIC_CR_OSS_LSB)
+ #define AIC_CR_OSS(n)          (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_OSS_LSB)  /* n = 8, 16, 18, 20, 24 */
+
+#define AIC_CR_ISS_LSB          16
+#define AIC_CR_ISS_MASK         BITS_H2L(18, AIC_CR_ISS_LSB)
+ #define AIC_CR_ISS(n)          (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_ISS_LSB)  /* n = 8, 16, 18, 20, 24 */
+
+/* AIC controller AC-link control register 1(ACCR1) */
+#define AIC_ACCR1_RS_LSB        16
+#define AIC_ACCR1_RS_MASK       BITS_H2L(25, AIC_ACCR1_RS_LSB)
+ #define AIC_ACCR1_RS_SLOT(n)   ((1 << ((n) - 3)) << AIC_ACCR1_RS_LSB)  /* n = 3 .. 12 */
+
+#define AIC_ACCR1_XS_LSB        0
+#define AIC_ACCR1_XS_MASK       BITS_H2L(9, AIC_ACCR1_XS_LSB)
+ #define AIC_ACCR1_XS_SLOT(n)   ((1 << ((n) - 3)) << AIC_ACCR1_XS_LSB)  /* n = 3 .. 12 */
+
+/* AIC controller AC-link control register 2 (ACCR2) */
+#define AIC_ACCR2_ERSTO         BIT18
+#define AIC_ACCR2_ESADR         BIT17
+#define AIC_ACCR2_ECADT         BIT16
+#define AIC_ACCR2_SO            BIT3
+#define AIC_ACCR2_SR            BIT2
+#define AIC_ACCR2_SS            BIT1
+#define AIC_ACCR2_SA            BIT0
+
+/* AIC controller i2s/msb-justified control register (I2SCR) */
+#define AIC_I2SCR_RFIRST        BIT17
+#define AIC_I2SCR_SWLH          BIT16
+#define AIC_I2SCR_STPBK         BIT12
+#define AIC_I2SCR_ESCLK         BIT4
+#define AIC_I2SCR_AMSL          BIT0
+
+/* AIC controller FIFO status register (AICSR) */
+#define AIC_SR_ROR              BIT6
+#define AIC_SR_TUR              BIT5
+#define AIC_SR_RFS              BIT4
+#define AIC_SR_TFS              BIT3
+
+#define AIC_SR_RFL_LSB          24
+#define AIC_SR_RFL_MASK         BITS_H2L(29, AIC_SR_RFL_LSB)
+
+#define AIC_SR_TFL_LSB          8
+#define AIC_SR_TFL_MASK         BITS_H2L(13, AIC_SR_TFL_LSB)
+
+/* AIC controller AC-link status register (ACSR) */
+#define AIC_ACSR_SLTERR         BIT21
+#define AIC_ACSR_CRDY           BIT20
+#define AIC_ACSR_CLPM           BIT19
+#define AIC_ACSR_RSTO           BIT18
+#define AIC_ACSR_SADR           BIT17
+#define AIC_ACSR_CADT           BIT16
+
+/* AIC controller I2S/MSB-justified status register (I2SSR) */
+#define AIC_I2SSR_CHBSY         BIT5
+#define AIC_I2SSR_TBSY          BIT4
+#define AIC_I2SSR_RBSY          BIT3
+#define AIC_I2SSR_BSY           BIT2
+
+/* AIC controller AC97 codec command address register (ACCAR) */
+#define AIC_ACCAR_CAR_LSB       0
+#define AIC_ACCAR_CAR_MASK      BITS_H2L(19, AIC_ACCAR_CAR_LSB)
+
+/* AIC controller AC97 codec command data register (ACCDR) */
+#define AIC_ACCDR_CDR_LSB       0
+#define AIC_ACCDR_CDR_MASK      BITS_H2L(19, AIC_ACCDR_CDR_LSB)
+
+/* AC97 read and write macro based on ACCAR and ACCDR */
+#define AC97_READ_CMD           BIT19
+#define AC97_WRITE_CMD          (BIT19 & ~BIT19)
+
+#define AC97_INDEX_LSB          12
+#define AC97_INDEX_MASK         BITS_H2L(18, AC97_INDEX_LSB)
+
+#define AC97_DATA_LSB           4
+#define AC97_DATA_MASK          BITS_H2L(19, AC97_DATA_LSB)
+
+/* AIC controller AC97 codec status address register (ACSAR) */
+#define AIC_ACSAR_SAR_LSB       0
+#define AIC_ACSAR_SAR_MASK      BITS_H2L(19, AIC_ACSAR_SAR_LSB)
+
+/* AIC controller AC97 codec status data register (ACSDR) */
+#define AIC_ACSDR_SDR_LSB       0
+#define AIC_ACSDR_SDR_MASK      BITS_H2L(19, AIC_ACSDR_SDR_LSB)
+
+/* AIC controller I2S/MSB-justified clock divider register (I2SDIV) */
+#define AIC_I2SDIV_DIV_LSB      0
+#define AIC_I2SDIV_DIV_MASK     BITS_H2L(3, AIC_I2SDIV_DIV_LSB)
+
+/* SPDIF enable register (SPDIF_ENA) */
+#define SPDIF_ENA_SPEN          BIT0
+
+/* SPDIF control register (SPDIF_CTRL) */
+#define SPDIF_CTRL_DMAEN        BIT15
+#define SPDIF_CTRL_DTYPE        BIT14
+#define SPDIF_CTRL_SIGN         BIT13
+#define SPDIF_CTRL_INVALID      BIT12
+#define SPDIF_CTRL_RST          BIT11
+#define SPDIF_CTRL_SPDIFI2S     BIT10
+#define SPDIF_CTRL_MTRIG        BIT1
+#define SPDIF_CTRL_MFFUR        BIT0
+
+/* SPDIF state register (SPDIF_STAT) */
+#define SPDIF_STAT_BUSY         BIT7
+#define SPDIF_STAT_FTRIG        BIT1
+#define SPDIF_STAT_FUR          BIT0
+
+#define SPDIF_STAT_FLVL_LSB     8
+#define SPDIF_STAT_FLVL_MASK    BITS_H2L(14, SPDIF_STAT_FLVL_LSB)
+
+/* SPDIF configure 1 register (SPDIF_CFG1) */
+#define SPDIF_CFG1_INITLVL      BIT17
+#define SPDIF_CFG1_ZROVLD       BIT16
+
+#define SPDIF_CFG1_TRIG_LSB     12
+#define SPDIF_CFG1_TRIG_MASK    BITS_H2L(13, SPDIF_CFG1_TRIG_LSB)
+#define SPDIF_CFG1_TRIG(n)      (((n) > 16 ? 3 : (n)/8) << SPDIF_CFG1_TRIG_LSB) /* n = 4, 8, 16, 32 */
+
+#define SPDIF_CFG1_SRCNUM_LSB   8
+#define SPDIF_CFG1_SRCNUM_MASK  BITS_H2L(11, SPDIF_CFG1_SRCNUM_LSB)
+
+#define SPDIF_CFG1_CH1NUM_LSB   4
+#define SPDIF_CFG1_CH1NUM_MASK  BITS_H2L(7, SPDIF_CFG1_CH1NUM_LSB)
+
+#define SPDIF_CFG1_CH2NUM_LSB   0
+#define SPDIF_CFG1_CH2NUM_MASK  BITS_H2L(3, SPDIF_CFG1_CH2NUM_LSB)
+
+/* SPDIF configure 2 register (SPDIF_CFG2) */
+#define SPDIF_CFG2_MAXWL        BIT18
+#define SPDIF_CFG2_PRE          BIT3
+#define SPDIF_CFG2_COPYN        BIT2
+#define SPDIF_CFG2_AUDION       BIT1
+#define SPDIF_CFG2_CONPRO       BIT0
+
+#define SPDIF_CFG2_FS_LSB       26
+#define SPDIF_CFG2_FS_MASK      BITS_H2L(29, SPDIF_CFG2_FS_LSB)
+
+#define SPDIF_CFG2_ORGFRQ_LSB   22
+#define SPDIF_CFG2_ORGFRQ_MASK  BITS_H2L(25, SPDIF_CFG2_ORGFRQ_LSB)
+
+#define SPDIF_CFG2_SAMWL_LSB    19
+#define SPDIF_CFG2_SAMWL_MASK   BITS_H2L(21, SPDIF_CFG2_SAMWL_LSB)
+
+#define SPDIF_CFG2_CLKACU_LSB   16
+#define SPDIF_CFG2_CLKACU_MASK  BITS_H2L(17, SPDIF_CFG2_CLKACU_LSB)
+
+#define SPDIF_CFG2_CATCODE_LSB  8
+#define SPDIF_CFG2_CATCODE_MASK BITS_H2L(15, SPDIF_CFG2_CATCODE_LSB)
+
+#define SPDIF_CFG2_CHMD_LSB     6
+#define SPDIF_CFG2_CHMD_MASK    BITS_H2L(7, SPDIF_CFG2_CHMD_LSB)
+
+/* ICDC internal register access control register(RGADW) */
+#define ICDC_RGADW_RGWR         BIT16
+
+#define ICDC_RGADW_RGADDR_LSB   8
+#define ICDC_RGADW_RGADDR_MASK  BITS_H2L(14, ICDC_RGADW_RGADDR_LSB)
+
+#define ICDC_RGADW_RGDIN_LSB    0
+#define ICDC_RGADW_RGDIN_MASK   BITS_H2L(7, ICDC_RGADW_RGDIN_LSB)
+
+/* ICDC internal register data output register (RGDATA)*/
+#define ICDC_RGDATA_IRQ         BIT8
+
+#define ICDC_RGDATA_RGDOUT_LSB  0
+#define ICDC_RGDATA_RGDOUT_MASK BITS_H2L(7, ICDC_RGDATA_RGDOUT_LSB)
+
+#ifndef __MIPS_ASSEMBLER
+
+#define REG_AIC_FR              REG32(AIC_FR)
+#define REG_AIC_CR              REG32(AIC_CR)
+#define REG_AIC_ACCR1           REG32(AIC_ACCR1)
+#define REG_AIC_ACCR2           REG32(AIC_ACCR2)
+#define REG_AIC_I2SCR           REG32(AIC_I2SCR)
+#define REG_AIC_SR              REG32(AIC_SR)
+#define REG_AIC_ACSR            REG32(AIC_ACSR)
+#define REG_AIC_I2SSR           REG32(AIC_I2SSR)
+#define REG_AIC_ACCAR           REG32(AIC_ACCAR)
+#define REG_AIC_ACCDR           REG32(AIC_ACCDR)
+#define REG_AIC_ACSAR           REG32(AIC_ACSAR)
+#define REG_AIC_ACSDR           REG32(AIC_ACSDR)
+#define REG_AIC_I2SDIV          REG32(AIC_I2SDIV)
+#define REG_AIC_DR              REG32(AIC_DR)
+
+#define REG_SPDIF_ENA           REG32(SPDIF_ENA)
+#define REG_SPDIF_CTRL          REG32(SPDIF_CTRL)
+#define REG_SPDIF_STATE         REG32(SPDIF_STATE)
+#define REG_SPDIF_CFG1          REG32(SPDIF_CFG1)
+#define REG_SPDIF_CFG2          REG32(SPDIF_CFG2)
+#define REG_SPDIF_FIFO          REG32(SPDIF_FIFO)
+
+#define REG_ICDC_RGADW          REG32(ICDC_RGADW)
+#define REG_ICDC_RGDATA         REG32(ICDC_RGDATA)
+
+#define __aic_enable()          ( REG_AIC_FR |= AIC_FR_ENB )
+#define __aic_disable()         ( REG_AIC_FR &= ~AIC_FR_ENB )
+
+#define __aic_select_ac97()     ( REG_AIC_FR &= ~AIC_FR_AUSEL )
+#define __aic_select_i2s()      ( REG_AIC_FR |= AIC_FR_AUSEL )
+
+#define __aic_play_zero()       ( REG_AIC_FR &= ~AIC_FR_LSMP )
+#define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP )
+
+#define __i2s_as_master()       ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
+#define __i2s_as_slave()        ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
+#define __aic_reset_status()          ( REG_AIC_FR & AIC_FR_RST )
+
+#define __i2s_enable_sclk()     ( REG_AIC_I2SCR |= AIC_I2SCR_ESCLK )
+#define __i2s_disable_sclk()    ( REG_AIC_I2SCR &= ~AIC_I2SCR_ESCLK )
+
+#define __aic_reset()                                   \
+do {                                                    \
+        REG_AIC_FR |= AIC_FR_RST;                       \
+} while(0)
+
+#define __aic_set_transmit_trigger(n)                   \
+do {                                                    \
+        REG_AIC_FR &= ~AIC_FR_TFTH_MASK;                \
+        REG_AIC_FR |= ((n) << AIC_FR_TFTH_LSB);         \
+} while(0)
+
+#define __aic_set_receive_trigger(n)                    \
+do {                                                    \
+        REG_AIC_FR &= ~AIC_FR_RFTH_MASK;                \
+        REG_AIC_FR |= ((n) << AIC_FR_RFTH_LSB);         \
+} while(0)
+
+#define __aic_enable_oldstyle()
+#define __aic_enable_newstyle()
+#define __aic_enable_pack16()   ( REG_AIC_CR |= AIC_CR_PACK16 )
+#define __aic_enable_unpack16() ( REG_AIC_CR &= ~AIC_CR_PACK16)
+
+/* n = AIC_CR_CHANNEL_MONO,AIC_CR_CHANNEL_STEREO ... */
+#define __aic_out_channel_select(n)                    \
+do {                                                   \
+        REG_AIC_CR &= ~AIC_CR_CHANNEL_MASK;            \
+        REG_AIC_CR |= ((n) << AIC_CR_CHANNEL_LSB );                            \
+} while(0)
+
+#define __aic_enable_record()   ( REG_AIC_CR |= AIC_CR_EREC )
+#define __aic_disable_record()  ( REG_AIC_CR &= ~AIC_CR_EREC )
+#define __aic_enable_replay()   ( REG_AIC_CR |= AIC_CR_ERPL )
+#define __aic_disable_replay()  ( REG_AIC_CR &= ~AIC_CR_ERPL )
+#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
+#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
+
+#define __aic_flush_tfifo()     ( REG_AIC_CR |= AIC_CR_TFLUSH )
+#define __aic_unflush_tfifo()   ( REG_AIC_CR &= ~AIC_CR_TFLUSH )
+#define __aic_flush_rfifo()     ( REG_AIC_CR |= AIC_CR_RFLUSH )
+#define __aic_unflush_rfifo()   ( REG_AIC_CR &= ~AIC_CR_RFLUSH )
+
+#define __aic_enable_transmit_intr() \
+  ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
+#define __aic_disable_transmit_intr() \
+  ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
+#define __aic_enable_receive_intr() \
+  ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
+#define __aic_disable_receive_intr() \
+  ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
+
+#define __aic_enable_transmit_dma()  ( REG_AIC_CR |= AIC_CR_TDMS )
+#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
+#define __aic_enable_receive_dma()   ( REG_AIC_CR |= AIC_CR_RDMS )
+#define __aic_disable_receive_dma()  ( REG_AIC_CR &= ~AIC_CR_RDMS )
+
+#define __aic_enable_mono2stereo()   ( REG_AIC_CR |= AIC_CR_M2S )
+#define __aic_disable_mono2stereo()  ( REG_AIC_CR &= ~AIC_CR_M2S )
+#define __aic_enable_byteswap()      ( REG_AIC_CR |= AIC_CR_ENDSW )
+#define __aic_disable_byteswap()     ( REG_AIC_CR &= ~AIC_CR_ENDSW )
+#define __aic_enable_unsignadj()     ( REG_AIC_CR |= AIC_CR_AVSTSU )
+#define __aic_disable_unsignadj()    ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
+
+#define AC97_PCM_XS_L_FRONT     AIC_ACCR1_XS_SLOT(3)
+#define AC97_PCM_XS_R_FRONT     AIC_ACCR1_XS_SLOT(4)
+#define AC97_PCM_XS_CENTER      AIC_ACCR1_XS_SLOT(6)
+#define AC97_PCM_XS_L_SURR      AIC_ACCR1_XS_SLOT(7)
+#define AC97_PCM_XS_R_SURR      AIC_ACCR1_XS_SLOT(8)
+#define AC97_PCM_XS_LFE         AIC_ACCR1_XS_SLOT(9)
+
+#define AC97_PCM_RS_L_FRONT     AIC_ACCR1_RS_SLOT(3)
+#define AC97_PCM_RS_R_FRONT     AIC_ACCR1_RS_SLOT(4)
+#define AC97_PCM_RS_CENTER      AIC_ACCR1_RS_SLOT(6)
+#define AC97_PCM_RS_L_SURR      AIC_ACCR1_RS_SLOT(7)
+#define AC97_PCM_RS_R_SURR      AIC_ACCR1_RS_SLOT(8)
+#define AC97_PCM_RS_LFE         AIC_ACCR1_RS_SLOT(9)
+
+#define __ac97_set_xs_none()    ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
+#define __ac97_set_xs_mono()                                            \
+do {                                                                    \
+        REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK;                            \
+        REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT;                           \
+} while(0)
+#define __ac97_set_xs_stereo()                                          \
+do {                                                                    \
+        REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK;                            \
+        REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT;     \
+} while(0)
+
+/* In fact, only stereo is support now. */
+#define __ac97_set_rs_none()    ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
+#define __ac97_set_rs_mono()                                            \
+do {                                                                    \
+        REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK;                            \
+        REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT;                           \
+} while(0)
+#define __ac97_set_rs_stereo()                                          \
+do {                                                                    \
+        REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK;                            \
+        REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT;     \
+} while(0)
+
+#define __ac97_warm_reset_codec()               \
+ do {                                           \
+        REG_AIC_ACCR2 |= AIC_ACCR2_SA;          \
+        REG_AIC_ACCR2 |= AIC_ACCR2_SS;          \
+        udelay(2);                              \
+        REG_AIC_ACCR2 &= ~AIC_ACCR2_SS;         \
+        REG_AIC_ACCR2 &= ~AIC_ACCR2_SA;         \
+ } while (0)
+
+#define __ac97_cold_reset_codec()               \
+ do {                                           \
+        REG_AIC_ACCR2 |=  AIC_ACCR2_SR;         \
+        udelay(2);                              \
+        REG_AIC_ACCR2 &= ~AIC_ACCR2_SR;         \
+ } while (0)
+
+/* n=8,16,18,20 */
+#define __ac97_set_iass(n) \
+ ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
+#define __ac97_set_oass(n) \
+ ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
+
+/* This bit should only be set in 2 channels configuration */
+#define __i2s_send_rfirst()   ( REG_AIC_I2SCR |= AIC_I2SCR_RFIRST )  /* RL */
+#define __i2s_send_lfirst()   ( REG_AIC_I2SCR &= ~AIC_I2SCR_RFIRST ) /* LR */
+
+/* This bit should only be set in 2 channels configuration and 16bit-packed mode */
+#define __i2s_switch_lr()     ( REG_AIC_I2SCR |= AIC_I2SCR_SWLH )
+#define __i2s_unswitch_lr()   ( REG_AIC_I2SCR &= ~AIC_I2SCR_SWLH )
+
+#define __i2s_select_i2s()            ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
+#define __i2s_select_msbjustified()   ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
+
+/* n=8,16,18,20,24 */
+/*#define __i2s_set_sample_size(n) \
+ ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
+
+#define __i2s_out_channel_select(n) __aic_out_channel_select(n)
+
+#define __i2s_set_oss_sample_size(n) \
+ ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS(n))
+#define __i2s_set_iss_sample_size(n) \
+ ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS(n))
+
+#define __i2s_stop_bitclk()   ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
+#define __i2s_start_bitclk()  ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
+
+#define __aic_transmit_request()  ( REG_AIC_SR & AIC_SR_TFS )
+#define __aic_receive_request()   ( REG_AIC_SR & AIC_SR_RFS )
+#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
+#define __aic_receive_overrun()   ( REG_AIC_SR & AIC_SR_ROR )
+
+#define __aic_clear_errors()      ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
+
+#define __aic_get_transmit_resident() \
+  ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_LSB )
+#define __aic_get_receive_count() \
+  ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_LSB )
+
+#define __ac97_command_transmitted()     ( REG_AIC_ACSR & AIC_ACSR_CADT )
+#define __ac97_status_received()         ( REG_AIC_ACSR & AIC_ACSR_SADR )
+#define __ac97_status_receive_timeout()  ( REG_AIC_ACSR & AIC_ACSR_RSTO )
+#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
+#define __ac97_codec_is_ready()          ( REG_AIC_ACSR & AIC_ACSR_CRDY )
+#define __ac97_slot_error_detected()     ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
+#define __ac97_clear_slot_error()        ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
+
+#define __i2s_is_busy()         ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
+
+#define __ac97_out_rcmd_addr(reg)                                       \
+do {                                                                    \
+    REG_AIC_ACCAR = AC97_READ_CMD | ((reg) << AC97_INDEX_LSB);  \
+} while (0)
+
+#define __ac97_out_wcmd_addr(reg)                                       \
+do {                                                                    \
+    REG_AIC_ACCAR = AC97_WRITE_CMD | ((reg) << AC97_INDEX_LSB);         \
+} while (0)
+
+#define __ac97_out_data(value)                                          \
+do {                                                                    \
+    REG_AIC_ACCDR = ((value) << AC97_DATA_LSB);                         \
+} while (0)
+
+#define __ac97_in_data() \
+ ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> AC97_DATA_LSB )
+
+#define __ac97_in_status_addr() \
+ ( (REG_AIC_ACSAR & AC97_INDEX_MASK) >> AC97_INDEX_LSB )
+
+#define __i2s_set_sample_rate(i2sclk, sync) \
+  ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
+
+#define __i2s_set_i2sdiv(n) \
+  ( REG_AIC_I2SDIV = (n) )
+
+#define __aic_write_tfifo(v)  ( REG_AIC_DR = (v) )
+#define __aic_read_rfifo()    ( REG_AIC_DR )
+
+#define __aic_internal_codec()  ( REG_AIC_FR |= AIC_FR_ICDC )
+#define __aic_external_codec()  ( REG_AIC_FR &= ~AIC_FR_ICDC )
+
+//
+// Define next ops for AC97 compatible
+//
+
+#define AC97_ACSR       AIC_ACSR
+
+#define __ac97_enable()         __aic_enable(); __aic_select_ac97()
+#define __ac97_disable()        __aic_disable()
+#define __ac97_reset()          __aic_reset()
+
+#define __ac97_set_transmit_trigger(n)  __aic_set_transmit_trigger(n)
+#define __ac97_set_receive_trigger(n)   __aic_set_receive_trigger(n)
+
+#define __ac97_enable_record()          __aic_enable_record()
+#define __ac97_disable_record()         __aic_disable_record()
+#define __ac97_enable_replay()          __aic_enable_replay()
+#define __ac97_disable_replay()         __aic_disable_replay()
+#define __ac97_enable_loopback()        __aic_enable_loopback()
+#define __ac97_disable_loopback()       __aic_disable_loopback()
+
+#define __ac97_enable_transmit_dma()    __aic_enable_transmit_dma()
+#define __ac97_disable_transmit_dma()   __aic_disable_transmit_dma()
+#define __ac97_enable_receive_dma()     __aic_enable_receive_dma()
+#define __ac97_disable_receive_dma()    __aic_disable_receive_dma()
+
+#define __ac97_transmit_request()       __aic_transmit_request()
+#define __ac97_receive_request()        __aic_receive_request()
+#define __ac97_transmit_underrun()      __aic_transmit_underrun()
+#define __ac97_receive_overrun()        __aic_receive_overrun()
+
+#define __ac97_clear_errors()           __aic_clear_errors()
+
+#define __ac97_get_transmit_resident()  __aic_get_transmit_resident()
+#define __ac97_get_receive_count()      __aic_get_receive_count()
+
+#define __ac97_enable_transmit_intr()   __aic_enable_transmit_intr()
+#define __ac97_disable_transmit_intr()  __aic_disable_transmit_intr()
+#define __ac97_enable_receive_intr()    __aic_enable_receive_intr()
+#define __ac97_disable_receive_intr()   __aic_disable_receive_intr()
+
+#define __ac97_write_tfifo(v)           __aic_write_tfifo(v)
+#define __ac97_read_rfifo()             __aic_read_rfifo()
+
+//
+// Define next ops for I2S compatible
+//
+
+#define I2S_ACSR        AIC_I2SSR
+
+#define __i2s_enable()           __aic_enable(); __aic_select_i2s()
+#define __i2s_disable()         __aic_disable()
+#define __i2s_reset()           __aic_reset()
+
+#define __i2s_set_transmit_trigger(n)   __aic_set_transmit_trigger(n)
+#define __i2s_set_receive_trigger(n)    __aic_set_receive_trigger(n)
+
+#define __i2s_enable_record()           __aic_enable_record()
+#define __i2s_disable_record()          __aic_disable_record()
+#define __i2s_enable_replay()           __aic_enable_replay()
+#define __i2s_disable_replay()          __aic_disable_replay()
+#define __i2s_enable_loopback()         __aic_enable_loopback()
+#define __i2s_disable_loopback()        __aic_disable_loopback()
+
+#define __i2s_enable_transmit_dma()     __aic_enable_transmit_dma()
+#define __i2s_disable_transmit_dma()    __aic_disable_transmit_dma()
+#define __i2s_enable_receive_dma()      __aic_enable_receive_dma()
+#define __i2s_disable_receive_dma()     __aic_disable_receive_dma()
+
+#define __i2s_transmit_request()        __aic_transmit_request()
+#define __i2s_receive_request()         __aic_receive_request()
+#define __i2s_transmit_underrun()       __aic_transmit_underrun()
+#define __i2s_receive_overrun()         __aic_receive_overrun()
+
+#define __i2s_clear_errors()            __aic_clear_errors()
+
+#define __i2s_get_transmit_resident()   __aic_get_transmit_resident()
+#define __i2s_get_receive_count()       __aic_get_receive_count()
+
+#define __i2s_enable_transmit_intr()    __aic_enable_transmit_intr()
+#define __i2s_disable_transmit_intr()   __aic_disable_transmit_intr()
+#define __i2s_enable_receive_intr()     __aic_enable_receive_intr()
+#define __i2s_disable_receive_intr()    __aic_disable_receive_intr()
+
+#define __i2s_write_tfifo(v)            __aic_write_tfifo(v)
+#define __i2s_read_rfifo()              __aic_read_rfifo()
+
+#define __i2s_enable_pack16()           __aic_enable_pack16()
+#define __i2s_enable_unpack16()         __aic_enable_unpack16()
+
+#define __i2s_reset_codec()                     \
+ do {                                           \
+ } while (0)
+
+/*************************************************************************
+ * SPDIF INTERFACE in AIC Controller
+ *************************************************************************/
+
+#define __spdif_enable()        ( REG_SPDIF_ENA |= SPDIF_ENA_SPEN )
+#define __spdif_disable()       ( REG_SPDIF_ENA &= ~SPDIF_ENA_SPEN )
+
+#define __spdif_enable_transmit_dma()     ( REG_SPDIF_CTRL |= SPDIF_CTRL_DMAEN )
+#define __spdif_disable_transmit_dma()    ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DMAEN )
+#define __spdif_enable_dtype()            ( REG_SPDIF_CTRL |= SPDIF_CTRL_DTYPE )
+#define __spdif_disable_dtype()           ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DTYPE )
+#define __spdif_enable_sign()             ( REG_SPDIF_CTRL |= SPDIF_CTRL_SIGN )
+#define __spdif_disable_sign()            ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SIGN )
+#define __spdif_enable_invalid()          ( REG_SPDIF_CTRL |= SPDIF_CTRL_INVALID )
+#define __spdif_disable_invalid()         ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_INVALID )
+#define __spdif_enable_reset()            ( REG_SPDIF_CTRL |= SPDIF_CTRL_RST )
+#define __spdif_select_spdif()            ( REG_SPDIF_CTRL |= SPDIF_CTRL_SPDIFI2S )
+#define __spdif_select_i2s()              ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SPDIFI2S )
+#define __spdif_enable_MTRIGmask()        ( REG_SPDIF_CTRL |= SPDIF_CTRL_MTRIG )
+#define __spdif_disable_MTRIGmask()       ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MTRIG )
+#define __spdif_enable_MFFURmask()        ( REG_SPDIF_CTRL |= SPDIF_CTRL_MFFUR )
+#define __spdif_disable_MFFURmask()       ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MFFUR )
+
+#define __spdif_enable_initlvl_high()     ( REG_SPDIF_CFG1 |=  SPDIF_CFG1_INITLVL )
+#define __spdif_enable_initlvl_low()      ( REG_SPDIF_CFG1 &=  ~SPDIF_CFG1_INITLVL )
+#define __spdif_enable_zrovld_invald()    ( REG_SPDIF_CFG1 |=  SPDIF_CFG1_ZROVLD )
+#define __spdif_enable_zrovld_vald()      ( REG_SPDIF_CFG1 &=  ~SPDIF_CFG1_ZROVLD )
+
+/* 0, 1, 2, 3 */
+#define __spdif_set_transmit_trigger(n)                 \
+do {                                                    \
+        REG_SPDIF_CFG1 &= ~SPDIF_CFG1_TRIG_MASK;        \
+        REG_SPDIF_CFG1 |= SPDIF_CFG1_TRIG(n);   \
+} while(0)
+
+/* 1 ~ 15 */
+#define __spdif_set_srcnum(n)                           \
+do {                                                    \
+        REG_SPDIF_CFG1 &= ~SPDIF_CFG1_SRCNUM_MASK;      \
+        REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_SRCNUM_LSB);       \
+} while(0)
+
+/* 1 ~ 15 */
+#define __spdif_set_ch1num(n)                           \
+do {                                                    \
+        REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH1NUM_MASK;      \
+        REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH1NUM_LSB);       \
+} while(0)
+
+/* 1 ~ 15 */
+#define __spdif_set_ch2num(n)                           \
+do {                                                    \
+        REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH2NUM_MASK;      \
+        REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH2NUM_LSB);       \
+} while(0)
+
+/* 0x0, 0x2, 0x3, 0xa, 0xe */
+#define __spdif_set_fs(n)                               \
+do {                                                    \
+        REG_SPDIF_CFG2 &= ~SPDIF_CFG2_FS_MASK;          \
+        REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_FS_LSB);   \
+} while(0)
+
+/* 0xd, 0xc, 0x5, 0x1 */
+#define __spdif_set_orgfrq(n)                           \
+do {                                                    \
+        REG_SPDIF_CFG2 &= ~SPDIF_CFG2_ORGFRQ_MASK;      \
+        REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_ORGFRQ_LSB);       \
+} while(0)
+
+/* 0x1, 0x6, 0x2, 0x4, 0x5 */
+#define __spdif_set_samwl(n)                            \
+do {                                                    \
+        REG_SPDIF_CFG2 &= ~SPDIF_CFG2_SAMWL_MASK;       \
+        REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_SAMWL_LSB);        \
+} while(0)
+
+#define __spdif_enable_samwl_24()    ( REG_SPDIF_CFG2 |= SPDIF_CFG2_MAXWL )
+#define __spdif_enable_samwl_20()    ( REG_SPDIF_CFG1 &= ~SPDIF_CFG2_MAXWL )
+
+/* 0x1, 0x1, 0x2, 0x3 */
+#define __spdif_set_clkacu(n)                           \
+do {                                                    \
+        REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CLKACU_MASK;      \
+        REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CLKACU_LSB);       \
+} while(0)
+
+/* see IEC60958-3 */
+#define __spdif_set_catcode(n)                          \
+do {                                                    \
+        REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CATCODE_MASK;     \
+        REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CATCODE_LSB);      \
+} while(0)
+
+/* n = 0x0, */
+#define __spdif_set_chmode(n)                           \
+do {                                                    \
+        REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CHMD_MASK;        \
+        REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CHMD_LSB); \
+} while(0)
+
+#define __spdif_enable_pre()       ( REG_SPDIF_CFG2 |= SPDIF_CFG2_PRE )
+#define __spdif_disable_pre()      ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_PRE )
+#define __spdif_enable_copyn()     ( REG_SPDIF_CFG2 |= SPDIF_CFG2_COPYN )
+#define __spdif_disable_copyn()    ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_COPYN )
+/* audio sample word represents linear PCM samples */
+#define __spdif_enable_audion()    ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_AUDION )
+/* udio sample word used for other purpose */
+#define __spdif_disable_audion()   ( REG_SPDIF_CFG2 |= SPDIF_CFG2_AUDION )
+#define __spdif_enable_conpro()    ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CONPRO )
+#define __spdif_disable_conpro()   ( REG_SPDIF_CFG2 |= SPDIF_CFG2_CONPRO )
+
+/***************************************************************************
+ * ICDC
+ ***************************************************************************/
+#define __i2s_internal_codec()         __aic_internal_codec()
+#define __i2s_external_codec()         __aic_external_codec()
+
+#define __icdc_clk_ready()             ( REG_ICDC_CKCFG & ICDC_CKCFG_CKRDY )
+#define __icdc_sel_adc()               ( REG_ICDC_CKCFG |= ICDC_CKCFG_SELAD )
+#define __icdc_sel_dac()               ( REG_ICDC_CKCFG &= ~ICDC_CKCFG_SELAD )
+
+#define __icdc_set_rgwr()              ( REG_ICDC_RGADW |= ICDC_RGADW_RGWR )
+#define __icdc_clear_rgwr()            ( REG_ICDC_RGADW &= ~ICDC_RGADW_RGWR )
+#define __icdc_rgwr_ready()            ( REG_ICDC_RGADW & ICDC_RGADW_RGWR )
+
+#define __icdc_set_addr(n)                              \
+do {                                                    \
+        REG_ICDC_RGADW &= ~ICDC_RGADW_RGADDR_MASK;      \
+        REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGADDR_LSB; \
+} while(0)
+
+#define __icdc_set_cmd(n)                               \
+do {                                                    \
+        REG_ICDC_RGADW &= ~ICDC_RGADW_RGDIN_MASK;       \
+        REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGDIN_LSB;  \
+} while(0)
+
+#define __icdc_irq_pending()            ( REG_ICDC_RGDATA & ICDC_RGDATA_IRQ )
+#define __icdc_get_value()              ( REG_ICDC_RGDATA & ICDC_RGDATA_RGDOUT_MASK )
+
+#endif /* __MIPS_ASSEMBLER */
+
+/*
+ * Bose-Chaudhuri-Hocquenghem controller module(BCH) address definition
+ */
+#define BCH_BASE        0xb34d0000
+
+/*
+ * BCH registers offset addresses definition
+ */
+#define BCH_BHCR_OFFSET         (0x00)  /*  r, 32, 0x00000000 */
+#define BCH_BHCSR_OFFSET        (0x04)  /*  w, 32, 0x???????? */
+#define BCH_BHCCR_OFFSET        (0x08)  /*  w, 32, 0x???????? */
+#define BCH_BHCNT_OFFSET        (0x0c)  /* rw, 32, 0x00000000 */
+#define BCH_BHDR_OFFSET         (0x10)  /*  w,  8, 0x???????? */
+#define BCH_BHPAR0_OFFSET       (0x14)  /* rw, 32, 0x00000000 */
+#define BCH_BHPAR1_OFFSET       (0x18)  /* rw, 32, 0x00000000 */
+#define BCH_BHPAR2_OFFSET       (0x1c)  /* rw, 32, 0x00000000 */
+#define BCH_BHPAR3_OFFSET       (0x20)  /* rw, 32, 0x00000000 */
+#define BCH_BHPAR4_OFFSET       (0x24)  /* rw, 32, 0x00000000 */
+#define BCH_BHPAR5_OFFSET       (0x28)  /* rw, 32, 0x00000000 */
+#define BCH_BHPAR6_OFFSET       (0x2c)  /* rw, 32, 0x00000000 */
+#define BCH_BHPAR7_OFFSET       (0x30)  /* rw, 32, 0x00000000 */
+#define BCH_BHPAR8_OFFSET       (0x34)  /* rw, 32, 0x00000000 */
+#define BCH_BHPAR9_OFFSET       (0x38)  /* rw, 32, 0x00000000 */
+#define BCH_BHERR0_OFFSET       (0x3c)  /*  r, 32, 0x00000000 */
+#define BCH_BHERR1_OFFSET       (0x40)  /*  r, 32, 0x00000000 */
+#define BCH_BHERR2_OFFSET       (0x44)  /*  r, 32, 0x00000000 */
+#define BCH_BHERR3_OFFSET       (0x48)  /*  r, 32, 0x00000000 */
+#define BCH_BHERR4_OFFSET       (0x4c)  /*  r, 32, 0x00000000 */
+#define BCH_BHERR5_OFFSET       (0x50)  /*  r, 32, 0x00000000 */
+#define BCH_BHERR6_OFFSET       (0x54)  /*  r, 32, 0x00000000 */
+#define BCH_BHERR7_OFFSET       (0x58)  /*  r, 32, 0x00000000 */
+#define BCH_BHERR8_OFFSET       (0x5c)  /*  r, 32, 0x00000000 */
+#define BCH_BHERR9_OFFSET       (0x60)  /*  r, 32, 0x00000000 */
+#define BCH_BHERR10_OFFSET      (0x64)  /*  r, 32, 0x00000000 */
+#define BCH_BHERR11_OFFSET      (0x68)  /*  r, 32, 0x00000000 */
+#define BCH_BHINT_OFFSET        (0x6c)  /*  r, 32, 0x00000000 */
+#define BCH_BHINTE_OFFSET       (0x70)  /* rw, 32, 0x00000000 */
+#define BCH_BHINTES_OFFSET      (0x74)  /*  w, 32, 0x???????? */
+#define BCH_BHINTEC_OFFSET      (0x78)  /*  w, 32, 0x???????? */
+
+/*
+ * BCH registers addresses definition
+ */
+#define BCH_BHCR        (BCH_BASE + BCH_BHCR_OFFSET)
+#define BCH_BHCSR       (BCH_BASE + BCH_BHCSR_OFFSET)
+#define BCH_BHCCR       (BCH_BASE + BCH_BHCCR_OFFSET)
+#define BCH_BHCNT       (BCH_BASE + BCH_BHCNT_OFFSET)
+#define BCH_BHDR        (BCH_BASE + BCH_BHDR_OFFSET)
+#define BCH_BHPAR0      (BCH_BASE + BCH_BHPAR0_OFFSET)
+#define BCH_BHPAR1      (BCH_BASE + BCH_BHPAR1_OFFSET)
+#define BCH_BHPAR2      (BCH_BASE + BCH_BHPAR2_OFFSET)
+#define BCH_BHPAR3      (BCH_BASE + BCH_BHPAR3_OFFSET)
+#define BCH_BHPAR4      (BCH_BASE + BCH_BHPAR4_OFFSET)
+#define BCH_BHPAR5      (BCH_BASE + BCH_BHPAR5_OFFSET)
+#define BCH_BHPAR6      (BCH_BASE + BCH_BHPAR6_OFFSET)
+#define BCH_BHPAR7      (BCH_BASE + BCH_BHPAR7_OFFSET)
+#define BCH_BHPAR8      (BCH_BASE + BCH_BHPAR8_OFFSET)
+#define BCH_BHPAR9      (BCH_BASE + BCH_BHPAR9_OFFSET)
+#define BCH_BHERR0      (BCH_BASE + BCH_BHERR0_OFFSET)
+#define BCH_BHERR1      (BCH_BASE + BCH_BHERR1_OFFSET)
+#define BCH_BHERR2      (BCH_BASE + BCH_BHERR2_OFFSET)
+#define BCH_BHERR3      (BCH_BASE + BCH_BHERR3_OFFSET)
+#define BCH_BHERR4      (BCH_BASE + BCH_BHERR4_OFFSET)
+#define BCH_BHERR5      (BCH_BASE + BCH_BHERR5_OFFSET)
+#define BCH_BHERR6      (BCH_BASE + BCH_BHERR6_OFFSET)
+#define BCH_BHERR7      (BCH_BASE + BCH_BHERR7_OFFSET)
+#define BCH_BHERR8      (BCH_BASE + BCH_BHERR8_OFFSET)
+#define BCH_BHERR9      (BCH_BASE + BCH_BHERR9_OFFSET)
+#define BCH_BHERR10     (BCH_BASE + BCH_BHERR10_OFFSET)
+#define BCH_BHERR11     (BCH_BASE + BCH_BHERR11_OFFSET)
+#define BCH_BHINT       (BCH_BASE + BCH_BHINT_OFFSET)
+#define BCH_BHINTES     (BCH_BASE + BCH_BHINTES_OFFSET)
+#define BCH_BHINTEC     (BCH_BASE + BCH_BHINTEC_OFFSET)
+#define BCH_BHINTE      (BCH_BASE + BCH_BHINTE_OFFSET)
+
+/*
+ * BCH registers common define
+ */
+
+/* BCH control register (BHCR) */
+#define BHCR_DMAE               BIT7  /* BCH DMA enable */
+#define BHCR_ENCE               BIT2
+#define BHCR_BRST               BIT1  /* BCH reset */
+#define BHCR_BCHE               BIT0  /* BCH enable */
+
+#define BHCR_BSEL_LSB           3
+#define BHCR_BSEL_MASK          BITS_H2L(5, BHCR_BSEL_LSB)
+ #define BHCR_BSEL(n)           (((n)/4 - 1) << BHCR_BSEL_LSB)  /* n = 4, 8, 12, 16, 20, 24 */
+
+/* BCH interrupt status register (BHINT) */
+#define BHINT_ALL_F             BIT4
+#define BHINT_DECF              BIT3
+#define BHINT_ENCF              BIT2
+#define BHINT_UNCOR             BIT1
+#define BHINT_ERR               BIT0
+
+#define BHINT_ERRC_LSB          27
+#define BHINT_ERRC_MASK         BITS_H2L(31, BHINT_ERRC_LSB)
+
+/* BCH ENC/DEC count register (BHCNT) */
+#define BHCNT_DEC_LSB           16
+#define BHCNT_DEC_MASK          BITS_H2L(26, BHCNT_DEC_LSB)
+
+#define BHCNT_ENC_LSB           0
+#define BHCNT_ENC_MASK          BITS_H2L(10, BHCNT_ENC_LSB)
+
+/* BCH error report register (BCHERR)*/
+#define BCH_ERR_INDEX_LSB       0
+#define BCH_ERR_INDEX_MASK      BITS_H2L(12, BCH_ERR_INDEX_LSB)
+
+/* BCH common macro define */
+#define BCH_ENCODE              1
+#define BCH_DECODE              0
+
+#ifndef __MIPS_ASSEMBLER
+
+#define REG_BCH_BHCR            REG32(BCH_BHCR)
+#define REG_BCH_BHCSR           REG32(BCH_BHCSR)
+#define REG_BCH_BHCCR           REG32(BCH_BHCCR)
+#define REG_BCH_BHCNT           REG32(BCH_BHCNT)
+#define REG_BCH_BHDR            REG8(BCH_BHDR)
+#define REG_BCH_BHPAR0          REG32(BCH_BHPAR0)
+#define REG_BCH_BHPAR1          REG32(BCH_BHPAR1)
+#define REG_BCH_BHPAR2          REG32(BCH_BHPAR2)
+#define REG_BCH_BHPAR3          REG32(BCH_BHPAR3)
+#define REG_BCH_BHPAR4          REG32(BCH_BHPAR4)
+#define REG_BCH_BHPAR5          REG32(BCH_BHPAR5)
+#define REG_BCH_BHPAR6          REG32(BCH_BHPAR6)
+#define REG_BCH_BHPAR7          REG32(BCH_BHPAR7)
+#define REG_BCH_BHPAR8          REG32(BCH_BHPAR8)
+#define REG_BCH_BHPAR9          REG32(BCH_BHPAR9)
+#define REG_BCH_BHERR0          REG32(BCH_BHERR0)
+#define REG_BCH_BHERR1          REG32(BCH_BHERR1)
+#define REG_BCH_BHERR2          REG32(BCH_BHERR2)
+#define REG_BCH_BHERR3          REG32(BCH_BHERR3)
+#define REG_BCH_BHERR4          REG32(BCH_BHERR4)
+#define REG_BCH_BHERR5          REG32(BCH_BHERR5)
+#define REG_BCH_BHERR6          REG32(BCH_BHERR6)
+#define REG_BCH_BHERR7          REG32(BCH_BHERR7)
+#define REG_BCH_BHERR8          REG32(BCH_BHERR8)
+#define REG_BCH_BHERR9          REG32(BCH_BHERR9)
+#define REG_BCH_BHERR10         REG32(BCH_BHERR10)
+#define REG_BCH_BHERR11         REG32(BCH_BHERR11)
+#define REG_BCH_BHINT           REG32(BCH_BHINT)
+#define REG_BCH_BHINTE          REG32(BCH_BHINTE)
+#define REG_BCH_BHINTEC         REG32(BCH_BHINTEC)
+#define REG_BCH_BHINTES         REG32(BCH_BHINTES)
+
+#define __ecc_enable(encode, bit)                       \
+do {                                                    \
+        unsigned int tmp = BHCR_BRST | BHCR_BCHE;       \
+        if (encode)                                     \
+                tmp |= BHCR_ENCE;                       \
+        tmp |= BHCR_BSEL(bit);                          \
+        REG_BCH_BHCSR = tmp;                            \
+        REG_BCH_BHCCR = ~tmp;                           \
+} while (0)
+#define __ecc_disable()         (REG_BCH_BHCCR = BHCR_BCHE)
+
+#define __ecc_dma_enable()      (REG_BCH_BHCSR = BHCR_DMAE)
+#define __ecc_dma_disable()     (REG_BCH_BHCCR = BHCR_DMAE)
+
+#define __ecc_cnt_enc(n)        CMSREG32(BCH_BHCNT, (n) << BHCNT_ENC_LSB, BHCNT_ENC_MASK)
+#define __ecc_cnt_dec(n)        CMSREG32(BCH_BHCNT, (n) << BHCNT_DEC_LSB, BHCNT_DEC_MASK)
+
+#define __ecc_encode_sync()                             \
+do {                                                    \
+        unsigned int i = 1;                             \
+        while (!(REG_BCH_BHINT & BHINT_ENCF) && i++);   \
+} while (0)
+
+#define __ecc_decode_sync()                             \
+do {                                                    \
+        unsigned int i = 1;                             \
+        while (!(REG_BCH_BHINT & BHINT_DECF) && i++);   \
+} while (0)
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define BDMAC_BASE  0xB3450000
+
+/*************************************************************************
+ * BDMAC (BCH & NAND DMA Controller)
+ *************************************************************************/
+
+/* n is the DMA channel index (0 - 2) */
+#define BDMAC_DSAR(n)           (BDMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
+#define BDMAC_DTAR(n)           (BDMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
+#define BDMAC_DTCR(n)           (BDMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
+#define BDMAC_DRSR(n)           (BDMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
+#define BDMAC_DCCSR(n)          (BDMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
+#define BDMAC_DCMD(n)           (BDMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
+#define BDMAC_DDA(n)            (BDMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
+#define BDMAC_DSD(n)            (BDMAC_BASE + (0x1c + (n) * 0x20)) /* DMA Stride Address */
+#define BDMAC_DNT(n)            (BDMAC_BASE + (0xc0 + (n) * 0x04)) /* NAND Detect Timer */
+
+#define BDMAC_DMACR             (BDMAC_BASE + 0x0300)   /* DMA control register */
+#define BDMAC_DMAIPR            (BDMAC_BASE + 0x0304)   /* DMA interrupt pending */
+#define BDMAC_DMADBR            (BDMAC_BASE + 0x0308)   /* DMA doorbell */
+#define BDMAC_DMADBSR           (BDMAC_BASE + 0x030C)   /* DMA doorbell set */
+#define BDMAC_DMACKE            (BDMAC_BASE + 0x0310)
+#define BDMAC_DMACKES           (BDMAC_BASE + 0x0314)
+#define BDMAC_DMACKEC           (BDMAC_BASE + 0x0318)
+
+#define REG_BDMAC_DSAR(n)       REG32(BDMAC_DSAR((n)))
+#define REG_BDMAC_DTAR(n)       REG32(BDMAC_DTAR((n)))
+#define REG_BDMAC_DTCR(n)       REG32(BDMAC_DTCR((n)))
+#define REG_BDMAC_DRSR(n)       REG32(BDMAC_DRSR((n)))
+#define REG_BDMAC_DCCSR(n)      REG32(BDMAC_DCCSR((n)))
+#define REG_BDMAC_DCMD(n)       REG32(BDMAC_DCMD((n)))
+#define REG_BDMAC_DDA(n)        REG32(BDMAC_DDA((n)))
+#define REG_BDMAC_DSD(n)    REG32(BDMAC_DSD(n))
+#define REG_BDMAC_DNT(n)        REG32(BDMAC_DNT(n))
+
+#define REG_BDMAC_DMACR         REG32(BDMAC_DMACR)
+#define REG_BDMAC_DMAIPR        REG32(BDMAC_DMAIPR)
+#define REG_BDMAC_DMADBR        REG32(BDMAC_DMADBR)
+#define REG_BDMAC_DMADBSR       REG32(BDMAC_DMADBSR)
+#define REG_BDMAC_DMACKE        REG32(BDMAC_DMACKE)
+#define REG_BDMAC_DMACKES       REG32(BDMAC_DMACKES)
+#define REG_BDMAC_DMACKEC       REG32(BDMAC_DMACKEC)
+
+// BDMA request source register
+#define BDMAC_DRSR_RS_BIT       0
+  #define BDMAC_DRSR_RS_MASK    (0x3f << DMAC_DRSR_RS_BIT)
+  #define BDMAC_DRSR_RS_BCH_ENC (2 << DMAC_DRSR_RS_BIT)
+  #define BDMAC_DRSR_RS_BCH_DEC (3 << DMAC_DRSR_RS_BIT)
+  #define BDMAC_DRSR_RS_NAND0   (6 << DMAC_DRSR_RS_BIT)
+  #define BDMAC_DRSR_RS_NAND1   (7 << DMAC_DRSR_RS_BIT)
+  #define BDMAC_DRSR_RS_NAND    (BDMAC_DRSR_RS_NAND0)
+  #define BDMAC_DRSR_RS_AUTO    (8 << DMAC_DRSR_RS_BIT)
+  #define BDMAC_DRSR_RS_EXT     (12 << DMAC_DRSR_RS_BIT)
+
+// BDMA channel control/status register
+#define BDMAC_DCCSR_NDES        (1 << 31) /* descriptor (0) or not (1) ? */
+#define BDMAC_DCCSR_DES8        (1 << 30) /* Descriptor 8 Word */
+#define BDMAC_DCCSR_DES4        (0 << 30) /* Descriptor 4 Word */
+#define BDMAC_DCCSR_LASTMD_BIT  28
+#define BDMAC_DCCSR_LASTMD_MASK (0x3 << BDMAC_DCCSR_LASTMD_BIT)
+#define BDMAC_DCCSR_LASTMD0     (0 << 28) /* BCH Decoding last mode 0, there's one descriptor for decoding blcok*/
+#define BDMAC_DCCSR_LASTMD1     (1 << 28) /* BCH Decoding last mode 1, there's two descriptor for decoding blcok*/
+#define BDMAC_DCCSR_LASTMD2     (2 << 28) /* BCH Decoding last mode 2, there's three descriptor for decoding blcok*/
+#define BDMAC_DCCSR_FRBS(n)     ((n) << 24)
+#define BDMAC_DCCSR_FRBS_BIT    24
+#define BDMAC_DCCSR_FRBS_MASK   (0x7 << BDMAC_DCCSR_FRBS_BIT)
+#define BDMAC_DCCSR_CDOA_BIT    16        /* copy of DMA offset address */
+#define BDMAC_DCCSR_CDOA_MASK   (0xff << BDMACC_DCCSR_CDOA_BIT)
+#define BDMAC_DCCSR_BERR_BIT    7
+#define BDMAC_DCCSR_BERR_MASK   (0x1f << BDMAC_DCCSR_BERR_BIT)
+#define BDMAC_DCCSR_BUERR       (1 << 5)
+#define BDMAC_DCCSR_AR          (1 << 4)  /* address error */
+#define BDMAC_DCCSR_TT          (1 << 3)  /* transfer terminated */
+#define BDMAC_DCCSR_HLT         (1 << 2)  /* DMA halted */
+#define BDMAC_DCCSR_BAC         (1 << 1)
+#define BDMAC_DCCSR_EN          (1 << 0)  /* channel enable bit */
+
+// BDMA channel command register
+#define BDMAC_DCMD_EACKS_LOW    (1 << 31) /* External DACK Output Level Select, active low */
+#define BDMAC_DCMD_EACKS_HIGH   (0 << 31) /* External DACK Output Level Select, active high */
+#define BDMAC_DCMD_EACKM_WRITE  (1 << 30) /* External DACK Output Mode Select, output in write cycle */
+#define BDMAC_DCMD_EACKM_READ   (0 << 30) /* External DACK Output Mode Select, output in read cycle */
+#define BDMAC_DCMD_ERDM_BIT     28        /* External DREQ Detection Mode Select */
+  #define BDMAC_DCMD_ERDM_MASK  (0x03 << BDMAC_DCMD_ERDM_BIT)
+  #define BDMAC_DCMD_ERDM_LOW   (0 << BDMAC_DCMD_ERDM_BIT)
+  #define BDMAC_DCMD_ERDM_FALL  (1 << BDMAC_DCMD_ERDM_BIT)
+  #define BDMAC_DCMD_ERDM_HIGH  (2 << BDMAC_DCMD_ERDM_BIT)
+  #define BDMAC_DCMD_ERDM_RISE  (3 << BDMAC_DCMD_ERDM_BIT)
+#define BDMAC_DCMD_BLAST        (1 << 25) /* BCH last */
+#define BDMAC_DCMD_SAI          (1 << 23) /* source address increment */
+#define BDMAC_DCMD_DAI          (1 << 22) /* dest address increment */
+#define BDMAC_DCMD_SWDH_BIT     14  /* source port width */
+  #define BDMAC_DCMD_SWDH_MASK  (0x03 << BDMAC_DCMD_SWDH_BIT)
+  #define BDMAC_DCMD_SWDH_32    (0 << BDMAC_DCMD_SWDH_BIT)
+  #define BDMAC_DCMD_SWDH_8     (1 << BDMAC_DCMD_SWDH_BIT)
+  #define BDMAC_DCMD_SWDH_16    (2 << BDMAC_DCMD_SWDH_BIT)
+#define BDMAC_DCMD_DWDH_BIT     12  /* dest port width */
+  #define BDMAC_DCMD_DWDH_MASK  (0x03 << BDMAC_DCMD_DWDH_BIT)
+  #define BDMAC_DCMD_DWDH_32    (0 << BDMAC_DCMD_DWDH_BIT)
+  #define BDMAC_DCMD_DWDH_8     (1 << BDMAC_DCMD_DWDH_BIT)
+  #define BDMAC_DCMD_DWDH_16    (2 << BDMAC_DCMD_DWDH_BIT)
+#define BDMAC_DCMD_DS_BIT       8  /* transfer data size of a data unit */
+  #define BDMAC_DCMD_DS_MASK    (0x07 << BDMAC_DCMD_DS_BIT)
+  #define BDMAC_DCMD_DS_32BIT   (0 << BDMAC_DCMD_DS_BIT)
+  #define BDMAC_DCMD_DS_8BIT    (1 << BDMAC_DCMD_DS_BIT)
+  #define BDMAC_DCMD_DS_16BIT   (2 << BDMAC_DCMD_DS_BIT)
+  #define BDMAC_DCMD_DS_16BYTE  (3 << BDMAC_DCMD_DS_BIT)
+  #define BDMAC_DCMD_DS_32BYTE  (4 << BDMAC_DCMD_DS_BIT)
+  #define BDMAC_DCMD_DS_64BYTE  (5 << BDMAC_DCMD_DS_BIT)
+#define BDMAC_DCMD_NRD          (1 << 7)  /* NAND direct read */
+#define BDMAC_DCMD_NWR          (1 << 6)  /* NAND direct write */
+#define BDMAC_DCMD_NAC          (1 << 5)  /* NAND AL/CL enable */
+#define BDMAC_DCMD_NSTA         (1 << 4)
+#define BDMAC_DCMD_STDE         (1 << 2)  /* Stride Disable/Enable */
+#define BDMAC_DCMD_TIE          (1 << 1)  /* DMA transfer interrupt enable */
+#define BDMAC_DCMD_LINK         (1 << 0)  /* descriptor link enable */
+
+// BDMA descriptor address register
+#define BDMAC_DDA_BASE_BIT      12  /* descriptor base address */
+  #define BDMAC_DDA_BASE_MASK   (0x0fffff << BDMAC_DDA_BASE_BIT)
+#define BDMAC_DDA_OFFSET_BIT    4   /* descriptor offset address */
+  #define BDMAC_DDA_OFFSET_MASK (0x0ff << BDMAC_DDA_OFFSET_BIT)
+
+// BDMA stride address register
+#define BDMAC_DSD_TSD_BIT       16      /* target stride address */
+  #define BDMAC_DSD_TSD_MASK    (0xffff << BDMAC_DSD_TSD_BIT)
+#define BDMAC_DSD_SSD_BIT       0       /* source stride address */
+  #define BDMAC_DSD_SSD_MASK    (0xffff << BDMAC_DSD_SSD_BIT)
+
+// BDMA NAND Detect timer register
+#define BDMAC_NDTCTIMER_EN      (1 << 15)  /* enable detect timer */
+#define BDMAC_TAILCNT_BIT       16
+
+// BDMA control register
+#define BDMAC_DMACR_PR_BIT      8       /* channel priority mode */
+  #define BDMAC_DMACR_PR_MASK   (0x03 << DMAC_DMACR_PR_BIT)
+  #define BDMAC_DMACR_PR_01_2   (0 << BDMAC_DMACR_PR_BIT)
+  #define BDMAC_DMACR_PR_12_0   (1 << BDMAC_DMACR_PR_BIT)
+  #define BDMAC_DMACR_PR_20_1   (2 << BDMAC_DMACR_PR_BIT)
+  #define BDMAC_DMACR_PR_012    (3 << BDMAC_DMACR_PR_BIT)
+#define BDMAC_DMACR_HLT         (1 << 3)  /* DMA halt flag */
+#define BDMAC_DMACR_AR          (1 << 2)  /* address error flag */
+#define BDMAC_DMACR_DMAE        (1 << 0)  /* DMA enable bit */
+
+// BDMA interrupt pending register
+#define BDMAC_DMAIPR_CIRQ2      (1 << 2)  /* irq pending status for channel 2 */
+#define BDMAC_DMAIPR_CIRQ1      (1 << 1)  /* irq pending status for channel 1 */
+#define BDMAC_DMAIPR_CIRQ0      (1 << 0)  /* irq pending status for channel 0 */
+
+// BDMA doorbell register
+#define BDMAC_DMADBR_DB2        (1 << 2)  /* doorbell for channel 2 */
+#define BDMAC_DMADBR_DB1        (1 << 1)  /* doorbell for channel 1 */
+#define BDMAC_DMADBR_DB0        (1 << 0)  /* doorbell for channel 0 */
+
+// BDMA doorbell set register
+#define BDMAC_DMADBSR_DBS2      (1 << 2)  /* enable doorbell for channel 2 */
+#define BDMAC_DMADBSR_DBS1      (1 << 1)  /* enable doorbell for channel 1 */
+#define BDMAC_DMADBSR_DBS0      (1 << 0)  /* enable doorbell for channel 0 */
+
+#ifndef __MIPS_ASSEMBLER
+
+/***************************************************************************
+ * BCH & NAND DMAC
+ ***************************************************************************/
+
+#define __bdmac_enable_module() \
+        ( REG_BDMAC_DMACR |= BDMAC_DMACR_DMAE )
+#define __bdmac_disable_module() \
+        ( REG_BDMAC_DMACR &= ~BDMAC_DMACR_DMAE )
+
+/* n is the DMA channel index (0 - 2) */
+
+#define __bdmac_test_halt_error ( REG_BDMAC_DMACR & BDMAC_DMACR_HLT )
+#define __bdmac_test_addr_error ( REG_BDMAC_DMACR & BDMAC_DMACR_AR )
+
+#define __bdmac_channel_enable_clk(n)           \
+        REG_BDMAC_DMACKES = 1 << (n);
+
+#define __bdmac_enable_descriptor(n) \
+  ( REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_NDES )
+#define __bdmac_disable_descriptor(n) \
+  ( REG_BDMAC_DCCSR((n)) |= BDMAC_DCCSR_NDES )
+
+#define __bdmac_enable_channel(n)                 \
+do {                                             \
+        REG_BDMAC_DCCSR((n)) |= BDMAC_DCCSR_EN;    \
+} while (0)
+#define __bdmac_disable_channel(n)                \
+do {                                             \
+        REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_EN;   \
+} while (0)
+
+#define __bdmac_channel_enable_irq(n) \
+  ( REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_TIE )
+#define __bdmac_channel_disable_irq(n) \
+  ( REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_TIE )
+
+#define __bdmac_channel_transmit_halt_detected(n) \
+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_HLT )
+#define __bdmac_channel_transmit_end_detected(n) \
+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_TT )
+/* Nand ops status error, only for channel 1 */
+#define __bdmac_channel_status_error_detected() \
+  (  REG_BDMAC_DCCSR(1) & BDMAC_DCCSR_NSERR )
+#define __bdmac_channel_address_error_detected(n) \
+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_AR )
+#define __bdmac_channel_count_terminated_detected(n) \
+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_CT )
+#define __bdmac_channel_descriptor_invalid_detected(n) \
+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_INV )
+#define __bdmac_BCH_error_detected(n) \
+  (  REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_BERR )
+
+#define __bdmac_channel_clear_transmit_halt(n)                          \
+        do {                                                            \
+                /* clear both channel halt error and globle halt error */ \
+                REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_HLT;                 \
+                REG_BDMAC_DMACR &= ~BDMAC_DMACR_HLT;    \
+        } while (0)
+#define __bdmac_channel_clear_transmit_end(n) \
+  (  REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_TT )
+/* Nand ops status error, only for channel 1 */
+#define __bdmac_channel_clear_status_error() \
+  ( REG_BDMAC_DCCSR(1) &= ~BDMAC_DCCSR_NSERR )
+#define __bdmac_channel_clear_address_error(n)                          \
+        do {                                                            \
+                REG_BDMAC_DDA(n) = 0; /* clear descriptor address register */ \
+                REG_BDMAC_DSAR(n) = 0; /* clear source address register */ \
+                REG_BDMAC_DTAR(n) = 0; /* clear target address register */ \
+                /* clear both channel addr error and globle address error */ \
+                REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_AR;                  \
+                REG_BDMAC_DMACR &= ~BDMAC_DMACR_AR;     \
+        } while (0)
+#define __bdmac_channel_clear_count_terminated(n) \
+  (  REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_CT )
+#define __bdmac_channel_clear_descriptor_invalid(n) \
+  (  REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_INV )
+
+#define __bdmac_channel_set_transfer_unit_32bit(n)      \
+do {                                                    \
+        REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK;     \
+        REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_32BIT;     \
+} while (0)
+
+#define __bdmac_channel_set_transfer_unit_16bit(n)      \
+do {                                                    \
+        REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK;     \
+        REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_16BIT;     \
+} while (0)
+
+#define __bdmac_channel_set_transfer_unit_8bit(n)       \
+do {                                                    \
+        REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK;     \
+        REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_8BIT;      \
+} while (0)
+
+#define __bdmac_channel_set_transfer_unit_16byte(n)     \
+do {                                                    \
+        REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK;     \
+        REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_16BYTE;    \
+} while (0)
+
+#define __bdmac_channel_set_transfer_unit_32byte(n)     \
+do {                                                    \
+        REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK;     \
+        REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_32BYTE;    \
+} while (0)
+
+/* w=8,16,32 */
+#define __bdmac_channel_set_dest_port_width(n,w)                \
+do {                                                    \
+        REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DWDH_MASK;   \
+        REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DWDH_##w;     \
+} while (0)
+
+/* w=8,16,32 */
+#define __bdmac_channel_set_src_port_width(n,w)         \
+do {                                                    \
+        REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_SWDH_MASK;   \
+        REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_SWDH_##w;     \
+} while (0)
+
+#define __bdmac_channel_dest_addr_fixed(n) \
+        (REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DAI)
+#define __bdmac_channel_dest_addr_increment(n) \
+        (REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DAI)
+
+#define __bdmac_channel_src_addr_fixed(n) \
+        (REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_SAI)
+#define __bdmac_channel_src_addr_increment(n) \
+        (REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_SAI)
+
+#define __bdmac_channel_set_doorbell(n) \
+        (REG_BDMAC_DMADBSR = (1 << (n)))
+
+#define __bdmac_channel_irq_detected(n)  (REG_BDMAC_DMAIPR & (1 << (n)))
+#define __bdmac_channel_ack_irq(n)       (REG_BDMAC_DMAIPR &= ~(1 <<(n)))
+
+static __inline__ int __bdmac_get_irq(void)
+{
+        int i;
+        for (i = 0; i < MAX_BDMA_NUM; i++)
+                if (__bdmac_channel_irq_detected(i))
+                        return i;
+        return -1;
+}
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define CIM_BASE        0xB3060000
+
+/*************************************************************************
+ * CIM
+ *************************************************************************/
+#define CIM_CFG                 (CIM_BASE + 0x0000)
+#define CIM_CTRL                (CIM_BASE + 0x0004)
+#define CIM_STATE               (CIM_BASE + 0x0008)
+#define CIM_IID                 (CIM_BASE + 0x000C)
+#define CIM_DA                  (CIM_BASE + 0x0020)
+#define CIM_FA                  (CIM_BASE + 0x0024)
+#define CIM_FID                 (CIM_BASE + 0x0028)
+#define CIM_CMD                 (CIM_BASE + 0x002C)
+#define CIM_SIZE                (CIM_BASE + 0x0030)
+#define CIM_OFFSET              (CIM_BASE + 0x0034)
+#define CIM_YFA                 (CIM_BASE + 0x0038)
+#define CIM_YCMD                (CIM_BASE + 0x003C)
+#define CIM_CBFA                (CIM_BASE + 0x0040)
+#define CIM_CBCMD               (CIM_BASE + 0x0044)
+#define CIM_CRFA                (CIM_BASE + 0x0048)
+#define CIM_CRCMD               (CIM_BASE + 0x004C)
+#define CIM_CTRL2               (CIM_BASE + 0x0050)
+
+#define CIM_RAM_ADDR            (CIM_BASE + 0x1000)
+
+#define REG_CIM_CFG             REG32(CIM_CFG)
+#define REG_CIM_CTRL            REG32(CIM_CTRL)
+#define REG_CIM_STATE           REG32(CIM_STATE)
+#define REG_CIM_IID             REG32(CIM_IID)
+#define REG_CIM_DA              REG32(CIM_DA)
+#define REG_CIM_FA              REG32(CIM_FA)
+#define REG_CIM_FID             REG32(CIM_FID)
+#define REG_CIM_CMD             REG32(CIM_CMD)
+#define REG_CIM_SIZE            REG32(CIM_SIZE)
+#define REG_CIM_OFFSET          REG32(CIM_OFFSET)
+#define REG_CIM_YFA             REG32(CIM_YFA)
+#define REG_CIM_YCMD            REG32(CIM_YCMD)
+#define REG_CIM_CBFA            REG32(CIM_CBFA)
+#define REG_CIM_CBCMD           REG32(CIM_CBCMD)
+#define REG_CIM_CRFA            REG32(CIM_CRFA)
+#define REG_CIM_CRCMD           REG32(CIM_CRCMD)
+#define REG_CIM_CTRL2           REG32(CIM_CTRL2)
+
+#define CIM_CFG_EEOFEN                  (1 << 31)
+#define CIM_CFG_EXP                     (1 << 30)
+
+#define CIM_CFG_RXF_TRIG_BIT            24
+#define CIM_CFG_RXF_TRIG_MASK           (0x3f << CIM_CFG_RXF_TRIG_BIT)
+
+#define CIM_CFG_BW_BIT                  22
+#define CIM_CFG_BW_MASK                 (0x3 << CIM_CFG_BW_BIT)
+
+#define CIM_CFG_SEP                     (1 << 20)
+
+#define CIM_CFG_ORDER_BIT               18
+#define CIM_CFG_ORDER_MASK              (0x3 << CIM_CFG_ORDER_BIT)
+#define CIM_CFG_ORDER_0                 (0x0 << CIM_CFG_ORDER_BIT)      /* Y0CbY1Cr; YCbCr */
+#define CIM_CFG_ORDER_1                 (0x1 << CIM_CFG_ORDER_BIT)      /* Y0CrY1Cb; YCrCb */
+#define CIM_CFG_ORDER_2                 (0x2 << CIM_CFG_ORDER_BIT)      /* CbY0CrY1; CbCrY */
+#define CIM_CFG_ORDER_3                 (0x3 << CIM_CFG_ORDER_BIT)      /* CrY0CbY1; CrCbY */
+
+#define CIM_CFG_DF_BIT                  16
+#define CIM_CFG_DF_MASK                 (0x3 << CIM_CFG_DF_BIT)
+#define CIM_CFG_DF_YUV444               (0x1 << CIM_CFG_DF_BIT)         /* YCbCr444 */
+#define CIM_CFG_DF_YUV422               (0x2 << CIM_CFG_DF_BIT) /* YCbCr422 */
+#define CIM_CFG_DF_ITU656               (0x3 << CIM_CFG_DF_BIT) /* ITU656 YCbCr422 */
+
+#define CIM_CFG_INV_DAT                 (1 << 15)
+#define CIM_CFG_VSP                     (1 << 14) /* VSYNC Polarity:0-rising edge active,1-falling edge active */
+#define CIM_CFG_HSP                     (1 << 13) /* HSYNC Polarity:0-rising edge active,1-falling edge active */
+#define CIM_CFG_PCP                     (1 << 12) /* PCLK working edge: 0-rising, 1-falling */
+
+#define CIM_CFG_DMA_BURST_TYPE_BIT      10
+#define CIM_CFG_DMA_BURST_TYPE_MASK     (0x3 << CIM_CFG_DMA_BURST_TYPE_BIT)
+#define CIM_CFG_DMA_BURST_INCR4         (0 << CIM_CFG_DMA_BURST_TYPE_BIT)
+#define CIM_CFG_DMA_BURST_INCR8         (1 << CIM_CFG_DMA_BURST_TYPE_BIT)       /* Suggested */
+#define CIM_CFG_DMA_BURST_INCR16        (2 << CIM_CFG_DMA_BURST_TYPE_BIT)       /* Suggested High speed AHB*/
+#define CIM_CFG_DMA_BURST_INCR32        (3 << CIM_CFG_DMA_BURST_TYPE_BIT)       /* Suggested High speed AHB*/
+
+#define CIM_CFG_DUMMY_ZERO              (1 << 9)
+#define CIM_CFG_EXT_VSYNC               (1 << 8)        /* Only for ITU656 Progressive mode */
+#define CIM_CFG_LM                      (1 << 7)        /* Only for ITU656 Progressive mode */
+#define CIM_CFG_PACK_BIT                4
+#define CIM_CFG_PACK_MASK               (0x7 << CIM_CFG_PACK_BIT)
+#define CIM_CFG_PACK_0                  (0 << CIM_CFG_PACK_BIT) /* 11 22 33 44 0xY0CbY1Cr */
+#define CIM_CFG_PACK_1                  (1 << CIM_CFG_PACK_BIT) /* 22 33 44 11 0xCbY1CrY0 */
+#define CIM_CFG_PACK_2                  (2 << CIM_CFG_PACK_BIT) /* 33 44 11 22 0xY1CrY0Cb */
+#define CIM_CFG_PACK_3                  (3 << CIM_CFG_PACK_BIT) /* 44 11 22 33 0xCrY0CbY1 */
+#define CIM_CFG_PACK_4                  (4 << CIM_CFG_PACK_BIT) /* 44 33 22 11 0xCrY1CbY0 */
+#define CIM_CFG_PACK_5                  (5 << CIM_CFG_PACK_BIT) /* 33 22 11 44 0xY1CbY0Cr */
+#define CIM_CFG_PACK_6                  (6 << CIM_CFG_PACK_BIT) /* 22 11 44 33 0xCbY0CrY1 */
+#define CIM_CFG_PACK_7                  (7 << CIM_CFG_PACK_BIT) /* 11 44 33 22 0xY0CrY1Cb */
+#define CIM_CFG_FP                      (1 << 3)        /* Only for ITU656 Progressive mode */
+#define CIM_CFG_BYPASS_BIT              2
+#define CIM_CFG_BYPASS_MASK             (1 << CIM_CFG_BYPASS_BIT)
+#define CIM_CFG_BYPASS                  (1 << CIM_CFG_BYPASS_BIT)
+#define CIM_CFG_DSM_BIT                 0
+#define CIM_CFG_DSM_MASK                (0x3 << CIM_CFG_DSM_BIT)
+#define CIM_CFG_DSM_CPM                 (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
+#define CIM_CFG_DSM_CIM                 (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
+#define CIM_CFG_DSM_GCM                 (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
+
+/* CIM Control Register  (CIM_CTRL) */
+#define CIM_CTRL_EEOF_LINE_BIT  20
+#define CIM_CTRL_EEOF_LINE_MASK (0xfff << CIM_CTRL_EEOF_LINE_BIT)
+
+#define CIM_CTRL_FRC_BIT        16
+#define CIM_CTRL_FRC_MASK       (0xf << CIM_CTRL_FRC_BIT)
+#define CIM_CTRL_FRC_1    (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
+#define CIM_CTRL_FRC_2    (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
+#define CIM_CTRL_FRC_3    (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
+#define CIM_CTRL_FRC_4    (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
+#define CIM_CTRL_FRC_5    (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
+#define CIM_CTRL_FRC_6    (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
+#define CIM_CTRL_FRC_7    (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
+#define CIM_CTRL_FRC_8    (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
+#define CIM_CTRL_FRC_9    (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
+#define CIM_CTRL_FRC_10   (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
+#define CIM_CTRL_FRC_11   (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
+#define CIM_CTRL_FRC_12   (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
+#define CIM_CTRL_FRC_13   (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
+#define CIM_CTRL_FRC_14   (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
+#define CIM_CTRL_FRC_15   (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
+#define CIM_CTRL_FRC_16   (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
+
+#define CIM_CTRL_DMA_EEOF       (1 << 15)       /* Enable EEOF interrupt */
+#define CIM_CTRL_WIN_EN         (1 << 14)
+#define CIM_CTRL_VDDM           (1 << 13) /* VDD interrupt enable */
+#define CIM_CTRL_DMA_SOFM       (1 << 12)
+#define CIM_CTRL_DMA_EOFM       (1 << 11)
+#define CIM_CTRL_DMA_STOPM      (1 << 10)
+#define CIM_CTRL_RXF_TRIGM      (1 << 9)
+#define CIM_CTRL_RXF_OFM        (1 << 8)
+#define CIM_CTRL_DMA_SYNC       (1 << 7)        /*when change DA, do frame sync */
+#define CIM_CTRL_H_SYNC         (1 << 6) /*Enable horizental sync when CIMCFG.SEP is 1*/       
+
+#define CIM_CTRL_PPW_BIT        3
+#define CIM_CTRL_PPW_MASK       (0x3 << CIM_CTRL_PPW_BIT)
+
+#define CIM_CTRL_DMA_EN         (1 << 2) /* Enable DMA */
+#define CIM_CTRL_RXF_RST        (1 << 1) /* RxFIFO reset */
+#define CIM_CTRL_ENA            (1 << 0) /* Enable CIM */
+
+/* cim control2 */
+#define CIM_CTRL2_OPG_BIT       4
+#define CIM_CTRL2_OPG_MASK      (0x3 << CIM_CTRL2_OPG_BIT)
+#define CIM_CTRL2_OPE           (1 << 2)
+#define CIM_CTRL2_EME           (1 << 1)
+#define CIM_CTRL2_APM           (1 << 0)
+
+/* CIM State Register  (CIM_STATE) */
+#define CIM_STATE_CR_RF_OF      (1 << 27)
+#define CIM_STATE_CR_RF_TRIG    (1 << 26)
+#define CIM_STATE_CR_RF_EMPTY   (1 << 25)
+#define CIM_STATE_CB_RF_OF      (1 << 19)
+#define CIM_STATE_CB_RF_TRIG    (1 << 18)
+#define CIM_STATE_CB_RF_EMPTY   (1 << 17)
+#define CIM_STATE_Y_RF_OF       (1 << 11)
+#define CIM_STATE_Y_RF_TRIG     (1 << 10)
+#define CIM_STATE_Y_RF_EMPTY    (1 << 9)
+#define CIM_STATE_DMA_EEOF      (1 << 7) /* DMA Line EEOf irq */
+#define CIM_STATE_DMA_SOF       (1 << 6) /* DMA start irq */
+#define CIM_STATE_DMA_EOF       (1 << 5) /* DMA end irq */
+#define CIM_STATE_DMA_STOP      (1 << 4) /* DMA stop irq */
+#define CIM_STATE_RXF_OF        (1 << 3) /* RXFIFO over flow irq */
+#define CIM_STATE_RXF_TRIG      (1 << 2) /* RXFIFO triger meet irq */
+#define CIM_STATE_RXF_EMPTY     (1 << 1) /* RXFIFO empty irq */
+#define CIM_STATE_VDD           (1 << 0) /* CIM disabled irq */
+
+/* CIM DMA Command Register (CIM_CMD) */
+
+#define CIM_CMD_SOFINT          (1 << 31) /* enable DMA start irq */
+#define CIM_CMD_EOFINT          (1 << 30) /* enable DMA end irq */
+#define CIM_CMD_EEOFINT         (1 << 29) /* enable DMA EEOF irq */
+#define CIM_CMD_STOP            (1 << 28) /* enable DMA stop irq */
+#define CIM_CMD_OFRCV           (1 << 27) /* enable recovery when TXFiFo overflow */
+#define CIM_CMD_LEN_BIT         0
+#define CIM_CMD_LEN_MASK        (0xffffff << CIM_CMD_LEN_BIT)
+
+/* CIM Window-Image Size Register  (CIM_SIZE) */
+#define CIM_SIZE_LPF_BIT        16 /* Lines per freame for csc output image */
+#define CIM_SIZE_LPF_MASK       (0x1fff << CIM_SIZE_LPF_BIT)
+#define CIM_SIZE_PPL_BIT        0 /* Pixels per line for csc output image, should be an even number */
+#define CIM_SIZE_PPL_MASK       (0x1fff << CIM_SIZE_PPL_BIT)
+
+/* CIM Image Offset Register  (CIM_OFFSET) */
+#define CIM_OFFSET_V_BIT        16 /* Vertical offset */
+#define CIM_OFFSET_V_MASK       (0xfff << CIM_OFFSET_V_BIT)
+#define CIM_OFFSET_H_BIT        0 /* Horizontal offset, should be an enen number */
+#define CIM_OFFSET_H_MASK       (0xfff << CIM_OFFSET_H_BIT) /*OFFSET_H should be even number*/
+
+#define CIM_YCMD_SOFINT         (1 << 31) /* enable DMA start irq */
+#define CIM_YCMD_EOFINT         (1 << 30) /* enable DMA end irq */
+#define CIM_YCMD_EEOFINT        (1 << 29) /* enable DMA EEOF irq */
+#define CIM_YCMD_STOP           (1 << 28) /* enable DMA stop irq */
+#define CIM_YCMD_OFRCV          (1 << 27) /* enable recovery when TXFiFo overflow */
+#define CIM_YCMD_LEN_BIT        0
+#define CIM_YCMD_LEN_MASK       (0xffffff << CIM_YCMD_LEN_BIT)
+
+#define CIM_CBCMD_LEN_BIT       0
+#define CIM_CBCMD_LEN_MASK      (0xffffff << CIM_CBCMD_LEN_BIT)
+
+#define CIM_CRCMD_LEN_BIT       0
+#define CIM_CRCMD_LEN_MASK      (0xffffff << CIM_CRCMD_LEN_BIT)
+
+#ifndef __MIPS_ASSEMBLER
+
+/***************************************************************************
+ * CIM
+ ***************************************************************************/
+
+#define __cim_enable()  ( REG_CIM_CTRL |= CIM_CTRL_ENA )
+#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA )
+
+#define __cim_enable_sep() (REG_CIM_CFG |= CIM_CFG_SEP)
+#define __cim_disable_sep() (REG_CIM_CFG &= ~CIM_CFG_SEP)
+
+/* n = 0, 1, 2, 3 */
+#define __cim_set_input_data_stream_order(n)                            \
+        do {                                                            \
+                REG_CIM_CFG &= ~CIM_CFG_ORDER_MASK;                     \
+                REG_CIM_CFG |= ((n)<<CIM_CFG_ORDER_BIT)&CIM_CFG_ORDER_MASK; \
+        } while (0)
+
+#define __cim_input_data_format_select_YUV444()         \
+        do {                                            \
+                REG_CIM_CFG &= ~CIM_CFG_DF_MASK;                \
+                REG_CIM_CFG |= CIM_CFG_DF_YUV444;       \
+        } while (0)
+
+#define __cim_input_data_format_select_YUV422()         \
+        do {                                            \
+                REG_CIM_CFG &= ~CIM_CFG_DF_MASK;                \
+                REG_CIM_CFG |= CIM_CFG_DF_YUV422;       \
+        } while (0)
+
+#define __cim_input_data_format_select_ITU656()         \
+        do {                                            \
+                REG_CIM_CFG &= ~CIM_CFG_DF_MASK;                \
+                REG_CIM_CFG |= CIM_CFG_DF_ITU656;       \
+        } while (0)
+
+#define __cim_input_data_inverse()      ( REG_CIM_CFG |= CIM_CFG_INV_DAT )
+#define __cim_input_data_normal()       ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )
+
+#define __cim_vsync_active_low()        ( REG_CIM_CFG |= CIM_CFG_VSP )
+#define __cim_vsync_active_high()       ( REG_CIM_CFG &= ~CIM_CFG_VSP )
+
+#define __cim_hsync_active_low()        ( REG_CIM_CFG |= CIM_CFG_HSP )
+#define __cim_hsync_active_high()       ( REG_CIM_CFG &= ~CIM_CFG_HSP )
+
+#define __cim_sample_data_at_pclk_falling_edge() \
+        ( REG_CIM_CFG |= CIM_CFG_PCP )
+#define __cim_sample_data_at_pclk_rising_edge() \
+        ( REG_CIM_CFG &= ~CIM_CFG_PCP )
+
+#define __cim_enable_dummy_zero()       ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )
+#define __cim_disable_dummy_zero()      ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )
+
+#define __cim_select_external_vsync()   ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )
+#define __cim_select_internal_vsync()   ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )
+
+/* n=0-7 */
+#define __cim_set_data_packing_mode(n)          \
+        do {                                            \
+                REG_CIM_CFG &= ~CIM_CFG_PACK_MASK;      \
+                REG_CIM_CFG |= (CIM_CFG_PACK_##n);      \
+        } while (0)
+
+#define __cim_enable_bypass_func()      (REG_CIM_CFG &= ~CIM_CFG_BYPASS)
+#define __cim_disable_bypass_func()     (REG_CIM_CFG |= CIM_CFG_BYPASS)
+
+#define __cim_enable_ccir656_progressive_mode() \
+        do {                                            \
+                REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;       \
+                REG_CIM_CFG |= CIM_CFG_DSM_CPM;         \
+        } while (0)
+
+#define __cim_enable_ccir656_interlace_mode()   \
+        do {                                            \
+                REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;       \
+                REG_CIM_CFG |= CIM_CFG_DSM_CIM;         \
+        } while (0)
+
+#define __cim_enable_gated_clock_mode()         \
+        do {                                            \
+                REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;       \
+                REG_CIM_CFG |= CIM_CFG_DSM_GCM;         \
+        } while (0)
+
+#define __cim_enable_nongated_clock_mode()      \
+        do {                                            \
+                REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;       \
+                REG_CIM_CFG |= CIM_CFG_DSM_NGCM;        \
+        } while (0)
+
+/* n=1-16 */
+#define __cim_set_frame_rate(n)                 \
+        do {                                            \
+                REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK;     \
+                REG_CIM_CTRL |= CIM_CTRL_FRC_##n;       \
+        } while (0)
+
+#define __cim_enable_size_func() \
+        ( REG_CIM_CTRL |= CIM_CTRL_WIN_EN)
+#define __cim_disable_size_func() \
+        ( REG_CIM_CTRL &= ~CIM_CTRL_WIN_EN )
+
+#define __cim_enable_vdd_intr() \
+        ( REG_CIM_CTRL |= CIM_CTRL_VDDM )
+#define __cim_disable_vdd_intr() \
+        ( REG_CIM_CTRL &= ~CIM_CTRL_VDDM )
+
+#define __cim_enable_sof_intr() \
+        ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )
+#define __cim_disable_sof_intr() \
+        ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )
+
+#define __cim_enable_eof_intr() \
+        ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )
+#define __cim_disable_eof_intr() \
+        ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )
+
+#define __cim_enable_eeof_intr() \
+        ( REG_CIM_CTRL |= CIM_CTRL_DMA_EEOFM )
+#define __cim_disable_eeof_intr() \
+        ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EEOFM )
+
+#define __cim_enable_stop_intr() \
+        ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )
+#define __cim_disable_stop_intr() \
+        ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )
+
+#define __cim_enable_trig_intr() \
+        ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )
+#define __cim_disable_trig_intr() \
+        ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )
+
+#define __cim_enable_rxfifo_overflow_intr()     \
+        ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )
+#define __cim_disable_rxfifo_overflow_intr()    \
+        ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )
+
+#define __cim_enable_dma()   ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )
+#define __cim_disable_dma()  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )
+#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )
+#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )
+
+/* cim control2 */
+#define __cim_enable_priority_control()         ( REG_CIM_CTRL2 |= CIM_CTRL2_OPE)
+#define __cim_disable_priority_control()        ( REG_CIM_CTRL2 &= ~CIM_CTRL2_OPE)
+#define __cim_enable_auto_priority()            ( REG_CIM_CTRL2 |= CIM_CTRL2_APM)
+#define __cim_disable_auto_priority()           ( REG_CIM_CTRL2 &= ~CIM_CTRL2_APM)
+#define __cim_enable_emergency()                ( REG_CIM_CTRL2 |= CIM_CTRL2_EME)
+#define __cim_disable_emergency()               ( REG_CIM_CTRL2 &= ~CIM_CTRL2_EME);
+/* 0, 1, 2, 3
+ ** 0: highest priority
+ ** 3: lowest priority
+ ** 1 maybe best for SEP=1
+ ** 3 maybe best for SEP=0
+ **/
+#define __cim_set_opg(n)                                \
+        do {                                                            \
+                REG_CIM_CTRL2 &= ~CIM_CTRL2_OPG_MASK;                   \
+                REG_CIM_CTRL2 |= ((n) << CIM_CTRL2_OPG_BIT) & CIM_CTRL2_OPG_MASK; \
+        } while (0)
+
+#define __cim_clear_state()          ( REG_CIM_STATE = 0 )
+
+#define __cim_disable_done()         ( REG_CIM_STATE & CIM_STATE_VDD )
+#define __cim_rxfifo_empty()         ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )
+#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )
+#define __cim_rxfifo_overflow()      ( REG_CIM_STATE & CIM_STATE_RXF_OF )
+#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )
+#define __cim_dma_stop()             ( REG_CIM_STATE & CIM_STATE_DMA_STOP )
+#define __cim_dma_eof()              ( REG_CIM_STATE & CIM_STATE_DMA_EOF )
+#define __cim_dma_sof()              ( REG_CIM_STATE & CIM_STATE_DMA_SOF )
+
+#define __cim_get_iid()              ( REG_CIM_IID )
+#define __cim_get_fid()              ( REG_CIM_FID )
+//#define __cim_get_image_data()       ( REG_CIM_RXFIFO )
+#define __cim_get_dma_cmd()          ( REG_CIM_CMD )
+
+#define __cim_set_da(a)              ( REG_CIM_DA = (a) )
+
+#define __cim_set_line(a)       ( REG_CIM_SIZE = (REG_CIM_SIZE&(~CIM_SIZE_LPF_MASK))|((a)<<CIM_SIZE_LPF_BIT) )
+#define __cim_set_pixel(a)      ( REG_CIM_SIZE = (REG_CIM_SIZE&(~CIM_SIZE_PPL_MASK))|((a)<<CIM_SIZE_PPL_BIT) )
+#define __cim_get_line()        ((REG_CIM_SIZE&CIM_SIZE_LPF_MASK)>>CIM_SIZE_LPF_BIT)
+#define __cim_get_pixel()       ((REG_CIM_SIZE&CIM_SIZE_PPL_MASK)>>CIM_SIZE_PPL_BIT)
+
+#define __cim_set_v_offset(a)   ( REG_CIM_OFFSET = (REG_CIM_OFFSET&(~CIM_OFFSET_V_MASK)) | ((a)<<CIM_OFFSET_V_BIT) )
+#define __cim_set_h_offset(a)   ( REG_CIM_OFFSET = (REG_CIM_OFFSET&(~CIM_OFFSET_H_MASK)) | ((a)<<CIM_OFFSET_H_BIT) )
+#define __cim_get_v_offset()    ((REG_CIM_OFFSET&CIM_OFFSET_V_MASK)>>CIM_OFFSET_V_BIT)
+#define __cim_get_h_offset()    ((REG_CIM_OFFSET&CIM_OFFSET_H_MASK)>>CIM_OFFSET_H_BIT)
+
+#endif /* __MIPS_ASSEMBLER */
+
+/*
+ * Clock reset and power controller module(CPM) address definition
+ */
+#define CPM_BASE        0xb0000000
+
+/*
+ * CPM registers offset address definition
+ */
+#define CPM_CPCCR_OFFSET        (0x00)  /* rw, 32, 0x01011100 */
+#define CPM_LCR_OFFSET          (0x04)  /* rw, 32, 0x000000f8 */
+#define CPM_RSR_OFFSET          (0x08)  /* rw, 32, 0x???????? */
+#define CPM_CPPCR0_OFFSET       (0x10)  /* rw, 32, 0x28080011 */
+#define CPM_CPPSR_OFFSET        (0x14)  /* rw, 32, 0x80000000 */
+#define CPM_CLKGR0_OFFSET       (0x20)  /* rw, 32, 0x3fffffe0 */
+#define CPM_OPCR_OFFSET         (0x24)  /* rw, 32, 0x00001570 */
+#define CPM_CLKGR1_OFFSET       (0x28)  /* rw, 32, 0x0000017f */
+#define CPM_CPPCR1_OFFSET       (0x30)  /* rw, 32, 0x28080002 */
+#define CPM_CPSPR_OFFSET        (0x34)  /* rw, 32, 0x???????? */
+#define CPM_CPSPPR_OFFSET       (0x38)  /* rw, 32, 0x0000a5a5 */
+#define CPM_USBPCR_OFFSET       (0x3c)  /* rw, 32, 0x42992198 */
+#define CPM_USBRDT_OFFSET       (0x40)  /* rw, 32, 0x00000096 */
+#define CPM_USBVBFIL_OFFSET     (0x44)  /* rw, 32, 0x00000080 */
+#define CPM_USBCDR_OFFSET       (0x50)  /* rw, 32, 0x00000000 */
+#define CPM_I2SCDR_OFFSET       (0x60)  /* rw, 32, 0x00000000 */
+#define CPM_LPCDR_OFFSET        (0x64)  /* rw, 32, 0x00000000 */
+#define CPM_MSCCDR_OFFSET       (0x68)  /* rw, 32, 0x00000000 */
+#define CPM_UHCCDR_OFFSET       (0x6c)  /* rw, 32, 0x00000000 */
+#define CPM_SSICDR_OFFSET       (0x74)  /* rw, 32, 0x00000000 */
+#define CPM_CIMCDR_OFFSET       (0x7c)  /* rw, 32, 0x00000000 */
+#define CPM_GPSCDR_OFFSET       (0x80)  /* rw, 32, 0x00000000 */
+#define CPM_PCMCDR_OFFSET       (0x84)  /* rw, 32, 0x00000000 */
+#define CPM_GPUCDR_OFFSET       (0x88)  /* rw, 32, 0x00000000 */
+#define CPM_PSWC0ST_OFFSET      (0x90)  /* rw, 32, 0x00000000 */
+#define CPM_PSWC1ST_OFFSET      (0x94)  /* rw, 32, 0x00000000 */
+#define CPM_PSWC2ST_OFFSET      (0x98)  /* rw, 32, 0x00000000 */
+#define CPM_PSWC3ST_OFFSET      (0x9c)  /* rw, 32, 0x00000000 */
+
+/*
+ * CPM registers address definition
+ */
+#define CPM_CPCCR        (CPM_BASE + CPM_CPCCR_OFFSET)
+#define CPM_LCR          (CPM_BASE + CPM_LCR_OFFSET)
+#define CPM_RSR          (CPM_BASE + CPM_RSR_OFFSET)
+#define CPM_CPPCR0       (CPM_BASE + CPM_CPPCR0_OFFSET)
+#define CPM_CPPSR        (CPM_BASE + CPM_CPPSR_OFFSET)
+#define CPM_CLKGR0       (CPM_BASE + CPM_CLKGR0_OFFSET)
+#define CPM_OPCR         (CPM_BASE + CPM_OPCR_OFFSET)
+#define CPM_CLKGR1       (CPM_BASE + CPM_CLKGR1_OFFSET)
+#define CPM_CPPCR1       (CPM_BASE + CPM_CPPCR1_OFFSET)
+#define CPM_CPSPR        (CPM_BASE + CPM_CPSPR_OFFSET)
+#define CPM_CPSPPR       (CPM_BASE + CPM_CPSPPR_OFFSET)
+#define CPM_USBPCR       (CPM_BASE + CPM_USBPCR_OFFSET)
+#define CPM_USBRDT       (CPM_BASE + CPM_USBRDT_OFFSET)
+#define CPM_USBVBFIL     (CPM_BASE + CPM_USBVBFIL_OFFSET)
+#define CPM_USBCDR       (CPM_BASE + CPM_USBCDR_OFFSET)
+#define CPM_I2SCDR       (CPM_BASE + CPM_I2SCDR_OFFSET)
+#define CPM_LPCDR        (CPM_BASE + CPM_LPCDR_OFFSET)
+#define CPM_MSCCDR       (CPM_BASE + CPM_MSCCDR_OFFSET)
+#define CPM_UHCCDR       (CPM_BASE + CPM_UHCCDR_OFFSET)
+#define CPM_SSICDR       (CPM_BASE + CPM_SSICDR_OFFSET)
+#define CPM_CIMCDR       (CPM_BASE + CPM_CIMCDR_OFFSET)
+#define CPM_GPSCDR       (CPM_BASE + CPM_GPSCDR_OFFSET)
+#define CPM_PCMCDR       (CPM_BASE + CPM_PCMCDR_OFFSET)
+#define CPM_GPUCDR       (CPM_BASE + CPM_GPUCDR_OFFSET)
+#define CPM_PSWC0ST      (CPM_BASE + CPM_PSWC0ST_OFFSET)
+#define CPM_PSWC1ST      (CPM_BASE + CPM_PSWC1ST_OFFSET)
+#define CPM_PSWC2ST      (CPM_BASE + CPM_PSWC2ST_OFFSET)
+#define CPM_PSWC3ST      (CPM_BASE + CPM_PSWC3ST_OFFSET)
+
+/*
+ * CPM registers common define
+ */
+
+/* Clock control register(CPCCR) */
+#define CPCCR_ECS               BIT31
+#define CPCCR_MEM               BIT30
+#define CPCCR_CE                BIT22
+#define CPCCR_PCS               BIT21
+
+#define CPCCR_SDIV_LSB          24
+#define CPCCR_SDIV_MASK         BITS_H2L(27, CPCCR_SDIV_LSB)
+
+#define CPCCR_H2DIV_LSB         16
+#define CPCCR_H2DIV_MASK        BITS_H2L(19, CPCCR_H2DIV_LSB)
+
+#define CPCCR_MDIV_LSB          12
+#define CPCCR_MDIV_MASK         BITS_H2L(15, CPCCR_MDIV_LSB)
+
+#define CPCCR_PDIV_LSB          8
+#define CPCCR_PDIV_MASK         BITS_H2L(11, CPCCR_PDIV_LSB)
+
+#define CPCCR_HDIV_LSB          4
+#define CPCCR_HDIV_MASK         BITS_H2L(7, CPCCR_HDIV_LSB)
+
+#define CPCCR_CDIV_LSB          0
+#define CPCCR_CDIV_MASK         BITS_H2L(3, CPCCR_CDIV_LSB)
+
+/* Low power control register(LCR) */
+#define LCR_PDAHB1              BIT30
+#define LCR_PDAHB1S             BIT26
+#define LCR_DOZE                BIT2
+
+#define LCR_PST_LSB             8
+#define LCR_PST_MASK            BITS_H2L(19, LCR_PST_LSB)
+
+#define LCR_DUTY_LSB            3
+#define LCR_DUTY_MASK           BITS_H2L(7, LCR_DUTY_LSB)
+
+#define LCR_LPM_LSB             0
+#define LCR_LPM_MASK            BITS_H2L(1, LCR_LPM_LSB)
+#define LCR_LPM_IDLE            (0x0 << LCR_LPM_LSB)
+#define LCR_LPM_SLEEP           (0x1 << LCR_LPM_LSB)
+
+/* Reset status register(RSR) */
+#define RSR_P0R         BIT2
+#define RSR_WR          BIT1
+#define RSR_PR          BIT0
+
+/* PLL control register 0(CPPCR0) */
+#define CPPCR0_LOCK             BIT15   /* LOCK0 bit */
+#define CPPCR0_PLLS             BIT10
+#define CPPCR0_PLLBP            BIT9
+#define CPPCR0_PLLEN            BIT8
+
+#define CPPCR0_PLLM_LSB         24
+#define CPPCR0_PLLM_MASK        BITS_H2L(30, CPPCR0_PLLM_LSB)
+
+#define CPPCR0_PLLN_LSB         18
+#define CPPCR0_PLLN_MASK        BITS_H2L(21, CPPCR0_PLLN_LSB)
+
+#define CPPCR0_PLLOD_LSB        16
+#define CPPCR0_PLLOD_MASK       BITS_H2L(17, CPPCR0_PLLOD_LSB)
+
+#define CPPCR0_PLLST_LSB        0
+#define CPPCR0_PLLST_MASK       BITS_H2L(7, CPPCR0_PLLST_LSB)
+
+/* PLL switch and status register(CPPSR) */
+#define CPPSR_PLLOFF            BIT31
+#define CPPSR_PLLBP             BIT30
+#define CPPSR_PLLON             BIT29
+#define CPPSR_PS                BIT28
+#define CPPSR_FS                BIT27
+#define CPPSR_CS                BIT26
+#define CPPSR_SM                BIT2
+#define CPPSR_PM                BIT1
+#define CPPSR_FM                BIT0
+
+/* Clock gate register 0(CGR0) */
+#define CLKGR0_AHB_MON          BIT31
+#define CLKGR0_DDR              BIT30
+#define CLKGR0_IPU              BIT29
+#define CLKGR0_LCD              BIT28
+#define CLKGR0_TVE              BIT27
+#define CLKGR0_CIM              BIT26
+#define CLKGR0_MDMA             BIT25
+#define CLKGR0_UHC              BIT24
+#define CLKGR0_MAC              BIT23
+#define CLKGR0_GPS              BIT22
+#define CLKGR0_DMAC             BIT21
+#define CLKGR0_SSI2             BIT20
+#define CLKGR0_SSI1             BIT19
+#define CLKGR0_UART3            BIT18
+#define CLKGR0_UART2            BIT17
+#define CLKGR0_UART1            BIT16
+#define CLKGR0_UART0            BIT15
+#define CLKGR0_SADC             BIT14
+#define CLKGR0_KBC              BIT13
+#define CLKGR0_MSC2             BIT12
+#define CLKGR0_MSC1             BIT11
+#define CLKGR0_OWI              BIT10
+#define CLKGR0_TSSI             BIT9
+#define CLKGR0_AIC              BIT8
+#define CLKGR0_SCC              BIT7
+#define CLKGR0_I2C1             BIT6
+#define CLKGR0_I2C0             BIT5
+#define CLKGR0_SSI0             BIT4
+#define CLKGR0_MSC0             BIT3
+#define CLKGR0_OTG              BIT2
+#define CLKGR0_BCH              BIT1
+#define CLKGR0_NEMC             BIT0
+
+/* Oscillator and power control register(OPCR) */
+#define OPCR_OTGPHY_ENABLE      BIT7    /* SPENDN bit */
+#define OPCR_GPSEN              BIT6
+#define OPCR_UHCPHY_DISABLE     BIT5    /* SPENDH bit */
+#define OPCR_O1SE               BIT4
+#define OPCR_PD                 BIT3
+#define OPCR_ERCS               BIT2
+
+#define OPCR_O1ST_LSB           8
+#define OPCR_O1ST_MASK          BITS_H2L(15, OPCR_O1ST_LSB)
+
+/* Clock gate register 1(CGR1) */
+#define CLKGR1_AUX              BIT11
+#define CLKGR1_OSD              BIT10
+#define CLKGR1_GPU              BIT9
+#define CLKGR1_PCM              BIT8
+#define CLKGR1_AHB1             BIT7
+#define CLKGR1_CABAC            BIT6
+#define CLKGR1_SRAM             BIT5
+#define CLKGR1_DCT              BIT4
+#define CLKGR1_ME               BIT3
+#define CLKGR1_DBLK             BIT2
+#define CLKGR1_MC               BIT1
+#define CLKGR1_BDMA             BIT0
+
+/* PLL control register 1(CPPCR1) */
+#define CPPCR1_P1SCS            BIT15
+#define CPPCR1_PLL1EN           BIT7
+#define CPPCR1_PLL1S            BIT6
+#define CPPCR1_LOCK             BIT2    /* LOCK1 bit */
+#define CPPCR1_PLL1OFF          BIT1
+#define CPPCR1_PLL1ON           BIT0
+
+#define CPPCR1_PLL1M_LSB        24
+#define CPPCR1_PLL1M_MASK       BITS_H2L(30, CPPCR1_PLL1M_LSB)
+
+#define CPPCR1_PLL1N_LSB        18
+#define CPPCR1_PLL1N_MASK       BITS_H2L(21, CPPCR1_PLL1N_LSB)
+
+#define CPPCR1_PLL1OD_LSB       16
+#define CPPCR1_PLL1OD_MASK      BITS_H2L(17, CPPCR1_PLL1OD_LSB)
+
+#define CPPCR1_P1SDIV_LSB       9
+#define CPPCR1_P1SDIV_MASK      BITS_H2L(14, CPPCR1_P1SDIV_LSB)
+
+/* CPM scratch pad protected register(CPSPPR) */
+#define CPSPPR_CPSPR_WRITABLE   (0x00005a5a)
+
+/* OTG parameter control register(USBPCR) */
+#define USBPCR_USB_MODE         BIT31
+#define USBPCR_AVLD_REG         BIT30
+#define USBPCR_INCRM            BIT27   /* INCR_MASK bit */
+#define USBPCR_CLK12_EN         BIT26
+#define USBPCR_COMMONONN        BIT25
+#define USBPCR_VBUSVLDEXT       BIT24
+#define USBPCR_VBUSVLDEXTSEL    BIT23
+#define USBPCR_POR              BIT22
+#define USBPCR_SIDDQ            BIT21
+#define USBPCR_OTG_DISABLE      BIT20
+#define USBPCR_TXPREEMPHTUNE    BIT6
+
+#define USBPCR_IDPULLUP_LSB             28   /* IDPULLUP_MASK bit */
+#define USBPCR_IDPULLUP_MASK            BITS_H2L(29, USBPCR_USBPCR_IDPULLUP_LSB)
+
+#define USBPCR_COMPDISTUNE_LSB          17
+#define USBPCR_COMPDISTUNE_MASK         BITS_H2L(19, USBPCR_COMPDISTUNE_LSB)
+
+#define USBPCR_OTGTUNE_LSB              14
+#define USBPCR_OTGTUNE_MASK             BITS_H2L(16, USBPCR_OTGTUNE_LSB)
+
+#define USBPCR_SQRXTUNE_LSB             11
+#define USBPCR_SQRXTUNE_MASK            BITS_H2L(13, USBPCR_SQRXTUNE_LSB)
+
+#define USBPCR_TXFSLSTUNE_LSB           7
+#define USBPCR_TXFSLSTUNE_MASK          BITS_H2L(10, USBPCR_TXFSLSTUNE_LSB)
+
+#define USBPCR_TXRISETUNE_LSB           4
+#define USBPCR_TXRISETUNE_MASK          BITS_H2L(5, USBPCR_TXRISETUNE_LSB)
+
+#define USBPCR_TXVREFTUNE_LSB           0
+#define USBPCR_TXVREFTUNE_MASK          BITS_H2L(3, USBPCR_TXVREFTUNE_LSB)
+
+/* OTG reset detect timer register(USBRDT) */
+#define USBRDT_HB_MASK          BIT26
+#define USBRDT_VBFIL_LD_EN      BIT25
+#define USBRDT_IDDIG_EN         BIT24
+#define USBRDT_IDDIG_REG        BIT23
+
+#define USBRDT_USBRDT_LSB       0
+#define USBRDT_USBRDT_MASK      BITS_H2L(22, USBRDT_USBRDT_LSB)
+
+/* OTG PHY clock divider register(USBCDR) */
+#define USBCDR_UCS              BIT31
+#define USBCDR_UPCS             BIT30
+
+#define USBCDR_OTGDIV_LSB       0       /* USBCDR bit */
+#define USBCDR_OTGDIV_MASK      BITS_H2L(5, USBCDR_OTGDIV_LSB)
+
+/* I2S device clock divider register(I2SCDR) */ 
+#define I2SCDR_I2CS             BIT31
+#define I2SCDR_I2PCS            BIT30
+
+#define I2SCDR_I2SDIV_LSB       0       /* I2SCDR bit */
+#define I2SCDR_I2SDIV_MASK      BITS_H2L(8, I2SCDR_I2SDIV_LSB)
+
+/* LCD pix clock divider register(LPCDR) */
+//#define LPCDR_LSCS              BIT31
+#define LPCDR_LTCS              BIT30
+#define LPCDR_LPCS              BIT29
+
+#define LPCDR_PIXDIV_LSB        0       /* LPCDR bit */
+#define LPCDR_PIXDIV_MASK       BITS_H2L(10, LPCDR_PIXDIV_LSB)
+
+/* MSC clock divider register(MSCCDR) */
+#define MSCCDR_MCS              BIT31
+
+#define MSCCDR_MSCDIV_LSB       0       /* MSCCDR bit */
+#define MSCCDR_MSCDIV_MASK      BITS_H2L(4, MSCCDR_MSCDIV_LSB)
+
+/* UHC device clock divider register(UHCCDR) */
+#define UHCCDR_UHPCS            BIT31
+
+#define UHCCDR_UHCDIV_LSB       0       /* UHCCDR bit */
+#define UHCCDR_UHCDIV_MASK      BITS_H2L(3, UHCCDR_UHCDIV_LSB)
+
+/* SSI clock divider register(SSICDR) */
+#define SSICDR_SCS              BIT31
+
+#define SSICDR_SSIDIV_LSB       0       /* SSICDR bit */
+#define SSICDR_SSIDIV_MASK      BITS_H2L(3, SSICDR_SSIDIV_LSB)
+
+/* CIM mclk clock divider register(CIMCDR) */
+#define CIMCDR_CIMDIV_LSB       0       /* CIMCDR bit */
+#define CIMCDR_CIMDIV_MASK      BITS_H2L(7, CIMCDR_CIMDIV_LSB)
+
+/* GPS clock divider register(GPSCDR) */
+#define GPSCDR_GPCS             BIT31
+
+#define GPSCDR_GPSDIV_LSB       0       /* GPSCDR bit */
+#define GSPCDR_GPSDIV_MASK      BITS_H2L(3, GPSCDR_GPSDIV_LSB)
+
+/* PCM device clock divider register(PCMCDR) */
+#define PCMCDR_PCMS             BIT31
+#define PCMCDR_PCMPCS           BIT30
+
+#define PCMCDR_PCMDIV_LSB       0       /* PCMCDR bit */
+#define PCMCDR_PCMDIV_MASK      BITS_H2L(8, PCMCDR_PCMDIV_LSB)
+
+/* GPU clock divider register */
+#define GPUCDR_GPCS             BIT31
+#define GPUCDR_GPUDIV_LSB       0       /* GPUCDR bit */
+#define GPUCDR_GPUDIV_MASK      BITS_H2L(2, GPUCDR_GPUDIV_LSB)
+
+#ifndef __MIPS_ASSEMBLER
+
+#define REG_CPM_CPCCR           REG32(CPM_CPCCR)
+#define REG_CPM_RSR             REG32(CPM_RSR)
+#define REG_CPM_CPPCR0          REG32(CPM_CPPCR0)
+#define REG_CPM_CPPSR           REG32(CPM_CPPSR)
+#define REG_CPM_CPPCR1          REG32(CPM_CPPCR1)
+#define REG_CPM_CPSPR           REG32(CPM_CPSPR)
+#define REG_CPM_CPSPPR          REG32(CPM_CPSPPR)
+#define REG_CPM_USBPCR          REG32(CPM_USBPCR)
+#define REG_CPM_USBRDT          REG32(CPM_USBRDT)
+#define REG_CPM_USBVBFIL        REG32(CPM_USBVBFIL)
+#define REG_CPM_USBCDR          REG32(CPM_USBCDR)
+#define REG_CPM_I2SCDR          REG32(CPM_I2SCDR)
+#define REG_CPM_LPCDR           REG32(CPM_LPCDR)
+#define REG_CPM_MSCCDR          REG32(CPM_MSCCDR)
+#define REG_CPM_UHCCDR          REG32(CPM_UHCCDR)
+#define REG_CPM_SSICDR          REG32(CPM_SSICDR)
+#define REG_CPM_CIMCDR          REG32(CPM_CIMCDR)
+#define REG_CPM_GPSCDR          REG32(CPM_GPSCDR)
+#define REG_CPM_PCMCDR          REG32(CPM_PCMCDR)
+#define REG_CPM_GPUCDR          REG32(CPM_GPUCDR)
+
+#define REG_CPM_PSWC0ST         REG32(CPM_PSWC0ST)
+#define REG_CPM_PSWC1ST         REG32(CPM_PSWC1ST)
+#define REG_CPM_PSWC2ST         REG32(CPM_PSWC2ST)
+#define REG_CPM_PSWC3ST         REG32(CPM_PSWC3ST)
+
+#define REG_CPM_LCR             REG32(CPM_LCR)
+#define REG_CPM_CLKGR0          REG32(CPM_CLKGR0)
+#define REG_CPM_OPCR            REG32(CPM_OPCR)
+#define REG_CPM_CLKGR1          REG32(CPM_CLKGR1)
+#define REG_CPM_CLKGR           REG32(CPM_CLKGR0)
+
+#define cpm_get_scrpad()        INREG32(CPM_CPSPR)
+#define cpm_set_scrpad(data)                            \
+do {                                                    \
+        OUTREG32(CPM_CPSPPR, CPSPPR_CPSPR_WRITABLE);    \
+        OUTREG32(CPM_CPSPR, data);                      \
+        OUTREG32(CPM_CPSPPR, ~CPSPPR_CPSPR_WRITABLE);   \
+} while (0)
+
+#define CPM_POWER_ON    1
+#define CPM_POWER_OFF   0
+
+/***************************************************************************
+ * CPM                                                                     *
+ ***************************************************************************/
+#define __cpm_get_pllm() \
+        ((REG_CPM_CPPCR0 & CPPCR0_PLLM_MASK) >> CPPCR0_PLLM_LSB)
+#define __cpm_get_plln() \
+        ((REG_CPM_CPPCR0 & CPPCR0_PLLN_MASK) >> CPPCR0_PLLN_LSB)
+#define __cpm_get_pllod() \
+        ((REG_CPM_CPPCR0 & CPPCR0_PLLOD_MASK) >> CPPCR0_PLLOD_LSB)
+
+#define __cpm_get_pll1m() \
+        ((REG_CPM_CPPCR1 & CPPCR1_PLL1M_MASK) >> CPPCR1_PLL1M_LSB)
+#define __cpm_get_pll1n() \
+        ((REG_CPM_CPPCR1 & CPPCR1_PLL1N_MASK) >> CPPCR1_PLL1N_LSB)
+#define __cpm_get_pll1od() \
+        ((REG_CPM_CPPCR1 & CPPCR1_PLL1OD_MASK) >> CPPCR1_PLL1OD_LSB)
+
+#define __cpm_get_cdiv() \
+        ((REG_CPM_CPCCR & CPCCR_CDIV_MASK) >> CPCCR_CDIV_LSB)
+#define __cpm_get_hdiv() \
+        ((REG_CPM_CPCCR & CPCCR_HDIV_MASK) >> CPCCR_HDIV_LSB)
+#define __cpm_get_h2div() \
+        ((REG_CPM_CPCCR & CPCCR_H2DIV_MASK) >> CPCCR_H2DIV_LSB)
+#define __cpm_get_pdiv() \
+        ((REG_CPM_CPCCR & CPCCR_PDIV_MASK) >> CPCCR_PDIV_LSB)
+#define __cpm_get_mdiv() \
+        ((REG_CPM_CPCCR & CPCCR_MDIV_MASK) >> CPCCR_MDIV_LSB)
+#define __cpm_get_sdiv() \
+        ((REG_CPM_CPCCR & CPCCR_SDIV_MASK) >> CPCCR_SDIV_LSB)
+#define __cpm_get_i2sdiv() \
+        ((REG_CPM_I2SCDR & I2SCDR_I2SDIV_MASK) >> I2SCDR_I2SDIV_LSB)
+#define __cpm_get_pixdiv() \
+        ((REG_CPM_LPCDR & LPCDR_PIXDIV_MASK) >> LPCDR_PIXDIV_LSB)
+#define __cpm_get_mscdiv() \
+        ((REG_CPM_MSCCDR & MSCCDR_MSCDIV_MASK) >> MSCCDR_MSCDIV_LSB)
+#define __cpm_get_ssidiv() \
+        ((REG_CPM_SSICCDR & SSICDR_SSICDIV_MASK) >> SSICDR_SSIDIV_LSB)
+#define __cpm_get_pcmdiv() \
+        ((REG_CPM_PCMCDR & PCMCDR_PCMCD_MASK) >> PCMCDR_PCMCD_LSB)
+#define __cpm_get_pll1div() \
+        ((REG_CPM_CPPCR1 & CPCCR1_P1SDIV_MASK) >> CPCCR1_P1SDIV_LSB)
+
+#define __cpm_set_cdiv(v) \
+        (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_CDIV_MASK) | ((v) << (CPCCR_CDIV_LSB)))
+#define __cpm_set_hdiv(v) \
+        (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_HDIV_MASK) | ((v) << (CPCCR_HDIV_LSB)))
+#define __cpm_set_pdiv(v) \
+        (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_PDIV_MASK) | ((v) << (CPCCR_PDIV_LSB)))
+#define __cpm_set_mdiv(v) \
+        (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_MDIV_MASK) | ((v) << (CPCCR_MDIV_LSB)))
+#define __cpm_set_h1div(v) \
+        (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_H1DIV_MASK) | ((v) << (CPCCR_H1DIV_LSB)))
+#define __cpm_set_udiv(v) \
+        (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_UDIV_MASK) | ((v) << (CPCCR_UDIV_LSB)))
+#define __cpm_set_i2sdiv(v) \
+        (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~I2SCDR_I2SDIV_MASK) | ((v) << (I2SCDR_I2SDIV_LSB)))
+#define __cpm_set_pixdiv(v) \
+        (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~LPCDR_PIXDIV_MASK) | ((v) << (LPCDR_PIXDIV_LSB)))
+#define __cpm_set_mscdiv(v) \
+        (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~MSCCDR_MSCDIV_MASK) | ((v) << (MSCCDR_MSCDIV_LSB)))
+#define __cpm_set_ssidiv(v) \
+        (REG_CPM_SSICDR = (REG_CPM_SSICDR & ~SSICDR_SSIDIV_MASK) | ((v) << (SSICDR_SSIDIV_LSB)))
+#define __cpm_set_pcmdiv(v) \
+        (REG_CPM_PCMCDR = (REG_CPM_PCMCDR & ~PCMCDR_PCMCD_MASK) | ((v) << (PCMCDR_PCMCD_LSB)))
+#define __cpm_set_pll1div(v) \
+        (REG_CPM_CPPCR1 = (REG_CPM_CPPCR1 & ~CPCCR1_P1SDIV_MASK) | ((v) << (CPCCR1_P1SDIV_LSB)))
+
+#define __cpm_select_i2sclk_pll1()      (REG_CPM_I2SCDR |= I2SCDR_I2PCS)
+#define __cpm_select_i2sclk_pll0()      (REG_CPM_I2SCDR &= ~I2SCDR_I2PCS)
+#define __cpm_select_otgclk_pll1()      (REG_CPM_USBCDR |= USBCDR_UPCS)
+#define __cpm_select_otgclk_pll0()      (REG_CPM_USBCDR &= ~USBCDR_UPCS)
+#define __cpm_select_lcdpclk_pll1()     (REG_CPM_LPCDR |= LPCDR_LPCS)
+#define __cpm_select_lcdpclk_pll0()     (REG_CPM_LPCDR &= ~LPCDR_LPCS)
+#define __cpm_select_uhcclk_pll1()      (REG_CPM_UHCCDR |= UHCCDR_UHPCS)
+#define __cpm_select_uhcclk_pll0()      (REG_CPM_UHCCDR &= ~UHCCDR_UHPCS)
+#define __cpm_select_gpsclk_pll1()      (REG_CPM_GPSCDR |= GPSCDR_GPCS)
+#define __cpm_select_gpsclk_pll0()      (REG_CPM_GPSCDR &= ~GPSCDR_GPCS)
+#define __cpm_select_pcmclk_pll1()      (REG_CPM_PCMCDR |= PCMCDR_PCMPCS)
+#define __cpm_select_pcmclk_pll0()      (REG_CPM_PCMCDR &= ~PCMCDR_PCMPCS)
+#define __cpm_select_gpuclk_pll1()      (REG_CPM_GPUCDR |= GPUCDR_GPCS)
+#define __cpm_select_gpuclk_pll0()      (REG_CPM_GPUCDR &= ~GPUCDR_GPCS)
+#define __cpm_select_clk_pll1()         (REG_CPM_CDR |= CDR_PCS)
+#define __cpm_select_clk_pll0()         (REG_CPM_CDR &= ~CDR_PCS)
+
+
+#define __cpm_select_pcmclk_pll()       (REG_CPM_PCMCDR |= PCMCDR_PCMS)
+#define __cpm_select_pcmclk_exclk()     (REG_CPM_PCMCDR &= ~PCMCDR_PCMS)
+#define __cpm_select_pixclk_ext()       (REG_CPM_LPCDR |= LPCDR_LPCS)
+#define __cpm_select_pixclk_pll()       (REG_CPM_LPCDR &= ~LPCDR_LPCS)
+#define __cpm_select_tveclk_exclk()     (REG_CPM_LPCDR |= CPCCR_LSCS)
+#define __cpm_select_tveclk_pll()       (REG_CPM_LPCDR &= ~LPCDR_LSCS)
+#define __cpm_select_pixclk_lcd()       (REG_CPM_LPCDR &= ~LPCDR_LTCS)
+#define __cpm_select_pixclk_tve()       (REG_CPM_LPCDR |= LPCDR_LTCS)
+#define __cpm_select_i2sclk_exclk()     (REG_CPM_I2SCDR &= ~I2SCDR_I2CS)
+#define __cpm_select_i2sclk_pll()       (REG_CPM_I2SCDR |= I2SCDR_I2CS)
+//#define __cpm_select_usbclk_exclk()   (REG_CPM_CPCCR &= ~CPCCR_UCS)
+//#define __cpm_select_usbclk_pll()     (REG_CPM_CPCCR |= CPCCR_UCS)
+
+#define __cpm_enable_cko()
+#define __cpm_exclk_direct()            (REG_CPM_CPCCR &= ~CPCCR_ECS)
+#define __cpm_exclk_div2()              (REG_CPM_CPCCR |= CPCCR_ECS)
+#define __cpm_enable_pll_change()       (REG_CPM_CPCCR |= CPCCR_CE)
+
+#define __cpm_pllout_div2()             (REG_CPM_CPCCR &= ~CPCCR_PCS)
+#define __cpm_pll_enable()              (REG_CPM_CPPCR0 |= CPPCR0_PLLEN)
+
+#define __cpm_pll1_enable()             (REG_CPM_CPPCR1 |= CPPCR1_PLL1EN)
+
+#define __cpm_pll_is_off()              (REG_CPM_CPPSR & CPPSR_PLLOFF)
+#define __cpm_pll_is_on()               (REG_CPM_CPPSR & CPPSR_PLLON)
+#define __cpm_pll_bypass()              (REG_CPM_CPPSR |= CPPSR_PLLBP)
+
+#define __cpm_get_cclk_doze_duty() \
+        ((REG_CPM_LCR & LCR_DOZE_DUTY_MASK) >> LCR_DOZE_DUTY_LSB)
+#define __cpm_set_cclk_doze_duty(v) \
+        (REG_CPM_LCR = (REG_CPM_LCR & ~LCR_DOZE_DUTY_MASK) | ((v) << (LCR_DOZE_DUTY_LSB)))
+
+#define __cpm_doze_mode()               (REG_CPM_LCR |= LCR_DOZE_ON)
+#define __cpm_idle_mode() \
+        (REG_CPM_LCR = (REG_CPM_LCR & ~LCR_LPM_MASK) | LCR_LPM_IDLE)
+#define __cpm_sleep_mode() \
+        (REG_CPM_LCR = (REG_CPM_LCR & ~LCR_LPM_MASK) | LCR_LPM_SLEEP)
+
+#define __cpm_stop_all()        \
+        do {\
+                (REG_CPM_CLKGR0 = 0xffffffff);\
+                (REG_CPM_CLKGR1 = 0x3ff);\
+        }while(0)
+#define __cpm_stop_emc()        (REG_CPM_CLKGR0 |= CLKGR0_EMC)
+#define __cpm_stop_ddr()        (REG_CPM_CLKGR0 |= CLKGR0_DDR)
+#define __cpm_stop_ipu()        (REG_CPM_CLKGR0 |= CLKGR0_IPU)
+#define __cpm_stop_lcd()        (REG_CPM_CLKGR0 |= CLKGR0_LCD)
+#define __cpm_stop_tve()        (REG_CPM_CLKGR0 |= CLKGR0_TVE)
+#define __cpm_stop_Cim()        (REG_CPM_CLKGR0 |= CLKGR0_CIM)
+#define __cpm_stop_mdma()       (REG_CPM_CLKGR0 |= CLKGR0_MDMA)
+#define __cpm_stop_uhc()        (REG_CPM_CLKGR0 |= CLKGR0_UHC)
+#define __cpm_stop_mac()        (REG_CPM_CLKGR0 |= CLKGR0_MAC)
+#define __cpm_stop_gps()        (REG_CPM_CLKGR0 |= CLKGR0_GPS)
+#define __cpm_stop_dmac()       (REG_CPM_CLKGR0 |= CLKGR0_DMAC)
+#define __cpm_stop_ssi2()       (REG_CPM_CLKGR0 |= CLKGR0_SSI2)
+#define __cpm_stop_ssi1()       (REG_CPM_CLKGR0 |= CLKGR0_SSI1)
+#define __cpm_stop_uart3()      (REG_CPM_CLKGR0 |= CLKGR0_UART3)
+#define __cpm_stop_uart2()      (REG_CPM_CLKGR0 |= CLKGR0_UART2)
+#define __cpm_stop_uart1()      (REG_CPM_CLKGR0 |= CLKGR0_UART1)
+#define __cpm_stop_uart0()      (REG_CPM_CLKGR0 |= CLKGR0_UART0)
+#define __cpm_stop_sadc()       (REG_CPM_CLKGR0 |= CLKGR0_SADC)
+#define __cpm_stop_kbc()        (REG_CPM_CLKGR0 |= CLKGR0_KBC)
+#define __cpm_stop_msc2()       (REG_CPM_CLKGR0 |= CLKGR0_MSC2)
+#define __cpm_stop_msc1()       (REG_CPM_CLKGR0 |= CLKGR0_MSC1)
+#define __cpm_stop_owi()        (REG_CPM_CLKGR0 |= CLKGR0_OWI)
+#define __cpm_stop_tssi()       (REG_CPM_CLKGR0 |= CLKGR0_TSSI)
+#define __cpm_stop_aic()        (REG_CPM_CLKGR0 |= CLKGR0_AIC)
+#define __cpm_stop_scc()        (REG_CPM_CLKGR0 |= CLKGR0_SCC)
+#define __cpm_stop_i2c1()       (REG_CPM_CLKGR0 |= CLKGR0_I2C1)
+#define __cpm_stop_i2c0()       (REG_CPM_CLKGR0 |= CLKGR0_I2C0)
+#define __cpm_stop_ssi0()       (REG_CPM_CLKGR0 |= CLKGR0_SSI0)
+#define __cpm_stop_msc0()       (REG_CPM_CLKGR0 |= CLKGR0_MSC0)
+#define __cpm_stop_otg()        (REG_CPM_CLKGR0 |= CLKGR0_OTG)
+#define __cpm_stop_bch()        (REG_CPM_CLKGR0 |= CLKGR0_BCH)
+#define __cpm_stop_nemc()       (REG_CPM_CLKGR0 |= CLKGR0_NEMC)
+#define __cpm_stop_gpu()        (REG_CPM_CLKGR1 |= CLKGR1_GPU)
+#define __cpm_stop_pcm()        (REG_CPM_CLKGR1 |= CLKGR1_PCM)
+#define __cpm_stop_ahb1()       (REG_CPM_CLKGR1 |= CLKGR1_AHB1)
+#define __cpm_stop_cabac()      (REG_CPM_CLKGR1 |= CLKGR1_CABAC)
+#define __cpm_stop_sram()       (REG_CPM_CLKGR1 |= CLKGR1_SRAM)
+#define __cpm_stop_dct()        (REG_CPM_CLKGR1 |= CLKGR1_DCT)
+#define __cpm_stop_me()         (REG_CPM_CLKGR1 |= CLKGR1_ME)
+#define __cpm_stop_dblk()       (REG_CPM_CLKGR1 |= CLKGR1_DBLK)
+#define __cpm_stop_mc()         (REG_CPM_CLKGR1 |= CLKGR1_MC)
+#define __cpm_stop_bdma()       (REG_CPM_CLKGR1 |= CLKGR1_BDMA)
+
+#define __cpm_start_all()       \
+        do {\
+                REG_CPM_CLKGR0 = 0x0;\
+                REG_CPM_CLKGR1 = 0x0;\
+        } while(0)
+#define __cpm_start_emc()       (REG_CPM_CLKGR0 &= ~CLKGR0_EMC)
+#define __cpm_start_ddr()       (REG_CPM_CLKGR0 &= ~CLKGR0_DDR)
+#define __cpm_start_ipu()       (REG_CPM_CLKGR0 &= ~CLKGR0_IPU)
+#define __cpm_start_lcd()       (REG_CPM_CLKGR0 &= ~CLKGR0_LCD)
+#define __cpm_start_tve()       (REG_CPM_CLKGR0 &= ~CLKGR0_TVE)
+#define __cpm_start_Cim()       (REG_CPM_CLKGR0 &= ~CLKGR0_CIM)
+#define __cpm_start_mdma()      (REG_CPM_CLKGR0 &= ~CLKGR0_MDMA)
+#define __cpm_start_uhc()       (REG_CPM_CLKGR0 &= ~CLKGR0_UHC)
+#define __cpm_start_mac()       (REG_CPM_CLKGR0 &= ~CLKGR0_MAC)
+#define __cpm_start_gps()       (REG_CPM_CLKGR0 &= ~CLKGR0_GPS)
+#define __cpm_start_dmac()      (REG_CPM_CLKGR0 &= ~CLKGR0_DMAC)
+#define __cpm_start_ssi2()      (REG_CPM_CLKGR0 &= ~CLKGR0_SSI2)
+#define __cpm_start_ssi1()      (REG_CPM_CLKGR0 &= ~CLKGR0_SSI1)
+#define __cpm_start_uart3()     (REG_CPM_CLKGR0 &= ~CLKGR0_UART3)
+#define __cpm_start_uart2()     (REG_CPM_CLKGR0 &= ~CLKGR0_UART2)
+#define __cpm_start_uart1()     (REG_CPM_CLKGR0 &= ~CLKGR0_UART1)
+#define __cpm_start_uart0()     (REG_CPM_CLKGR0 &= ~CLKGR0_UART0)
+#define __cpm_start_sadc()      (REG_CPM_CLKGR0 &= ~CLKGR0_SADC)
+#define __cpm_start_kbc()       (REG_CPM_CLKGR0 &= ~CLKGR0_KBC)
+#define __cpm_start_msc2()      (REG_CPM_CLKGR0 &= ~CLKGR0_MSC2)
+#define __cpm_start_msc1()      (REG_CPM_CLKGR0 &= ~CLKGR0_MSC1)
+#define __cpm_start_owi()       (REG_CPM_CLKGR0 &= ~CLKGR0_OWI)
+#define __cpm_start_tssi()      (REG_CPM_CLKGR0 &= ~CLKGR0_TSSI)
+#define __cpm_start_aic()       (REG_CPM_CLKGR0 &= ~CLKGR0_AIC)
+#define __cpm_start_scc()       (REG_CPM_CLKGR0 &= ~CLKGR0_SCC)
+#define __cpm_start_i2c1()      (REG_CPM_CLKGR0 &= ~CLKGR0_I2C1)
+#define __cpm_start_i2c0()      (REG_CPM_CLKGR0 &= ~CLKGR0_I2C0)
+#define __cpm_start_ssi0()      (REG_CPM_CLKGR0 &= ~CLKGR0_SSI0)
+#define __cpm_start_msc0()      (REG_CPM_CLKGR0 &= ~CLKGR0_MSC0)
+#define __cpm_start_otg()       (REG_CPM_CLKGR0 &= ~CLKGR0_OTG)
+#define __cpm_start_bch()       (REG_CPM_CLKGR0 &= ~CLKGR0_BCH)
+#define __cpm_start_nemc()      (REG_CPM_CLKGR0 &= ~CLKGR0_NEMC)
+#define __cpm_start_gpu()       (REG_CPM_CLKGR1 &= ~CLKGR1_GPU)
+#define __cpm_start_pcm()       (REG_CPM_CLKGR1 &= ~CLKGR1_PCM)
+#define __cpm_start_ahb1()      (REG_CPM_CLKGR1 &= ~CLKGR1_AHB1)
+#define __cpm_start_cabac()     (REG_CPM_CLKGR1 &= ~CLKGR1_CABAC)
+#define __cpm_start_sram()      (REG_CPM_CLKGR1 &= ~CLKGR1_SRAM)
+#define __cpm_start_dct()       (REG_CPM_CLKGR1 &= ~CLKGR1_DCT)
+#define __cpm_start_me()        (REG_CPM_CLKGR1 &= ~CLKGR1_ME)
+#define __cpm_start_dblk()      (REG_CPM_CLKGR1 &= ~CLKGR1_DBLK)
+#define __cpm_start_mc()        (REG_CPM_CLKGR1 &= ~CLKGR1_MC)
+#define __cpm_start_bdma()      (REG_CPM_CLKGR1 &= ~CLKGR1_BDMA)
+
+#define __cpm_get_o1st() \
+        ((REG_CPM_OPCR & OPCR_O1ST_MASK) >> OPCR_O1ST_LSB)
+#define __cpm_set_o1st(v) \
+        (REG_CPM_OPCR = (REG_CPM_OPCR & ~OPCR_O1ST_MASK) | ((v) << (OPCR_O1ST_LSB)))
+#define __cpm_suspend_otgphy()          (REG_CPM_OPCR &= ~OPCR_OTGPHY_ENABLE)
+#define __cpm_resume_otgphy()           (REG_CPM_OPCR |= OPCR_OTGPHY_ENABLE)
+#define __cpm_enable_osc_in_sleep()     (REG_CPM_OPCR |= OPCR_OSC_ENABLE)
+#define __cpm_select_rtcclk_rtc()       (REG_CPM_OPCR |= OPCR_ERCS)
+#define __cpm_select_rtcclk_exclk()     (REG_CPM_OPCR &= ~OPCR_ERCS)
+
+#ifdef CFG_EXTAL
+#define JZ_EXTAL                CFG_EXTAL
+#else
+#define JZ_EXTAL                12000000
+#endif
+#define JZ_EXTAL2               32768 /* RTC clock */
+
+/* PLL output frequency */
+static __inline__ unsigned int __cpm_get_pllout(void)
+{
+        unsigned long m, n, no, pllout;
+        unsigned long cppcr = REG_CPM_CPPCR0;
+        unsigned long od[4] = {1, 2, 4, 8};
+        if ((cppcr & CPPCR0_PLLEN) && (!(cppcr & CPPCR0_PLLBP))) {
+                m = __cpm_get_pllm() * 2;
+                n = __cpm_get_plln();
+                no = od[__cpm_get_pllod()];
+                pllout = ((JZ_EXTAL) * m / (n * no));
+        } else
+                pllout = JZ_EXTAL;
+        return pllout;
+}
+
+/* PLL output frequency */
+static __inline__ unsigned int __cpm_get_pll1out(void)
+{
+        unsigned long m, n, no, pllout;
+        unsigned long cppcr1 = REG_CPM_CPPCR1;
+        unsigned long od[4] = {1, 2, 4, 8};
+        if (cppcr1 & CPPCR1_PLL1EN)
+        {
+                m = __cpm_get_pll1m() * 2;
+                n = __cpm_get_pll1n();
+                no = od[__cpm_get_pll1od()];
+                if (cppcr1 & CPPCR1_P1SCS)
+                        pllout = ((__cpm_get_pllout()) * m / (n * no));
+                else
+                        pllout = ((JZ_EXTAL) * m / (n * no));
+
+        } else
+                pllout = JZ_EXTAL;
+        return pllout;
+}
+
+/* PLL output frequency for MSC/I2S/LCD/USB */
+static __inline__ unsigned int __cpm_get_pllout2(void)
+{
+        if (REG_CPM_CPCCR & CPCCR_PCS)
+                return __cpm_get_pllout();
+        else
+                return __cpm_get_pllout()/2;
+}
+
+/* CPU core clock */
+static __inline__ unsigned int __cpm_get_cclk(void)
+{
+        int div[] = {1, 2, 3, 4, 6, 8};
+
+        return __cpm_get_pllout() / div[__cpm_get_cdiv()];
+}
+
+/* AHB system bus clock */
+static __inline__ unsigned int __cpm_get_hclk(void)
+{
+        int div[] = {1, 2, 3, 4, 6, 8};
+
+        return __cpm_get_pllout() / div[__cpm_get_hdiv()];
+}
+
+/* Memory bus clock */
+static __inline__ unsigned int __cpm_get_mclk(void)
+{
+        int div[] = {1, 2, 3, 4, 6, 8};
+
+        return __cpm_get_pllout() / div[__cpm_get_mdiv()];
+}
+
+/* APB peripheral bus clock */
+static __inline__ unsigned int __cpm_get_pclk(void)
+{
+        int div[] = {1, 2, 3, 4, 6, 8};
+
+        return __cpm_get_pllout() / div[__cpm_get_pdiv()];
+}
+
+/* AHB1 module clock */
+static __inline__ unsigned int __cpm_get_h2clk(void)
+{
+        int div[] = {1, 2, 3, 4, 6, 8};
+
+        return __cpm_get_pllout() / div[__cpm_get_h2div()];
+}
+
+/* LCD pixel clock */
+static __inline__ unsigned int __cpm_get_pixclk(void)
+{
+        return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
+}
+
+/* I2S clock */
+static __inline__ unsigned int __cpm_get_i2sclk(void)
+{
+        if (REG_CPM_I2SCDR & I2SCDR_I2CS) {
+                return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
+        }
+        else {
+                return JZ_EXTAL;
+        }
+}
+
+/* USB clock */
+/*
+static __inline__ unsigned int __cpm_get_usbclk(void)
+{
+        if (REG_CPM_CPCCR & CPCCR_UCS) {
+                return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
+        }
+        else {
+                return JZ_EXTAL;
+        }
+}
+*/
+/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
+static __inline__ unsigned int __cpm_get_extalclk(void)
+{
+        return JZ_EXTAL;
+}
+
+/* RTC clock for CPM,INTC,RTC,TCU,WDT */
+static __inline__ unsigned int __cpm_get_rtcclk(void)
+{
+        return JZ_EXTAL2;
+}
+
+/*
+ * Output 24MHz for SD and 16MHz for MMC.
+ */
+static inline void __cpm_select_msc_clk(int sd)
+{
+        unsigned int pllout2 = __cpm_get_pllout2();
+        unsigned int div = 0;
+
+        if (sd) {
+                div = pllout2 / 24000000;
+        }
+        else {
+                div = pllout2 / 16000000;
+        }
+
+        REG_CPM_MSCCDR = (div - 1)|(1<<31);
+        REG_CPM_CPCCR |= CPCCR_CE;
+}
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define DDRC_BASE       0xB3020000
+
+/*************************************************************************
+ * DDRC (DDR Controller)
+ *************************************************************************/
+#define DDRC_ST                 (DDRC_BASE + 0x0) /* DDR Status Register */
+#define DDRC_CFG                (DDRC_BASE + 0x4) /* DDR Configure Register */
+#define DDRC_CTRL               (DDRC_BASE + 0x8) /* DDR Control Register */
+#define DDRC_LMR                (DDRC_BASE + 0xc) /* DDR Load-Mode-Register */
+#define DDRC_TIMING1            (DDRC_BASE + 0x10) /* DDR Timing Config Register 1 */
+#define DDRC_TIMING2            (DDRC_BASE + 0x14) /* DDR Timing Config Register 2 */
+#define DDRC_REFCNT             (DDRC_BASE + 0x18) /* DDR  Auto-Refresh Counter */
+#define DDRC_DQS                (DDRC_BASE + 0x1c) /* DDR DQS Delay Control Register */
+#define DDRC_DQS_ADJ            (DDRC_BASE + 0x20) /* DDR DQS Delay Adjust Register */
+#define DDRC_MMAP0              (DDRC_BASE + 0x24) /* DDR Memory Map Config Register */
+#define DDRC_MMAP1              (DDRC_BASE + 0x28) /* DDR Memory Map Config Register */
+#define DDRC_DDELAYCTRL1        (DDRC_BASE + 0x2c)
+#define DDRC_DDELAYCTRL2        (DDRC_BASE + 0x30)
+#define DDRC_DSTRB              (DDRC_BASE + 0x34)
+#define DDRC_PMEMBS0            (DDRC_BASE + 0x50)
+#define DDRC_PMEMBS1            (DDRC_BASE + 0x54)
+#define DDRC_PMEMOSEL           (DDRC_BASE + 0x58)
+#define DDRC_PMEMOEN            (DDRC_BASE + 0x5c)
+
+/* DDRC Register */
+#define REG_DDRC_ST             REG32(DDRC_ST)
+#define REG_DDRC_CFG            REG32(DDRC_CFG)
+#define REG_DDRC_CTRL           REG32(DDRC_CTRL)
+#define REG_DDRC_LMR            REG32(DDRC_LMR)
+#define REG_DDRC_TIMING1        REG32(DDRC_TIMING1)
+#define REG_DDRC_TIMING2        REG32(DDRC_TIMING2)
+#define REG_DDRC_REFCNT         REG32(DDRC_REFCNT)
+#define REG_DDRC_DQS            REG32(DDRC_DQS)
+#define REG_DDRC_DQS_ADJ        REG32(DDRC_DQS_ADJ)
+#define REG_DDRC_MMAP0          REG32(DDRC_MMAP0)
+#define REG_DDRC_MMAP1          REG32(DDRC_MMAP1)
+#define REG_DDRC_DDELAYCTRL1    REG32(DDRC_DDELAYCTRL1)
+#define REG_DDRC_DDELAYCTRL2    REG32(DDRC_DDELAYCTRL2)
+#define REG_DDRC_DSTRB          REG32(DDRC_DSTRB)
+#define REG_DDRC_PMEMBS0        REG32(DDRC_PMEMBS0)
+#define REG_DDRC_PMEMBS1        REG32(DDRC_PMEMBS1)
+#define REG_DDRC_PMEMOSEL       REG32(DDRC_PMEMOSEL)
+#define REG_DDRC_PMEMOEN        REG32(DDRC_PMEMOEN)
+
+/* DDRC Status Register */
+#define DDRC_ST_ENDIAN          (1 << 7) /* 0 Little data endian
+                                            1 Big data endian */
+#define DDRC_ST_MISS            (1 << 6) 
+
+#define DDRC_ST_DPDN            (1 << 5) /* 0 DDR memory is NOT in deep-power-down state
+                                            1 DDR memory is in deep-power-down state */
+#define DDRC_ST_PDN             (1 << 4) /* 0 DDR memory is NOT in power-down state
+                                            1 DDR memory is in power-down state */
+#define DDRC_ST_AREF            (1 << 3) /* 0 DDR memory is NOT in auto-refresh state
+                                            1 DDR memory is in auto-refresh state */
+#define DDRC_ST_SREF            (1 << 2) /* 0 DDR memory is NOT in self-refresh state
+                                            1 DDR memory is in self-refresh state */
+#define DDRC_ST_CKE1            (1 << 1) /* 0 CKE1 Pin is low
+                                            1 CKE1 Pin is high */
+#define DDRC_ST_CKE0            (1 << 0) /* 0 CKE0 Pin is low
+                                            1 CKE0 Pin is high */
+
+/* DDRC Configure Register */
+#define DDRC_CFG_RDPRI          (1 << 29)
+#define DDRC_CFG_ROW1_BIT       27 /* Row Address width. */
+#define DDRC_CFG_COL1_BIT       25 /* Row Address width. */
+#define DDRC_CFG_BA1            (1 << 24)
+#define DDRC_CFG_IMBA           (1 << 23)
+#define DDRC_CFG_DQSMD          (1 << 22)
+#define DDRC_CFG_BTRUN          (1 << 21)
+
+#define DDRC_CFG_MISPE          (1 << 15)
+
+#define DDRC_CFG_TYPE_BIT       12
+#define DDRC_CFG_TYPE_MASK      (0x7 << DDRC_CFG_TYPE_BIT)
+#define DDRC_CFG_TYPE_DDR1      (2 << DDRC_CFG_TYPE_BIT)
+#define DDRC_CFG_TYPE_MDDR      (3 << DDRC_CFG_TYPE_BIT)
+#define DDRC_CFG_TYPE_DDR2      (4 << DDRC_CFG_TYPE_BIT)
+
+#define DDRC_CFG_ROW_BIT        10 /* Row Address width. */
+#define DDRC_CFG_ROW_MASK       (0x3 << DDRC_CFG_ROW_BIT)
+#define DDRC_CFG_ROW_12         (0 << DDRC_CFG_ROW_BIT) /* 12-bit row address is used */
+#define DDRC_CFG_ROW_13         (1 << DDRC_CFG_ROW_BIT) /* 13-bit row address is used */
+#define DDRC_CFG_ROW_14         (2 << DDRC_CFG_ROW_BIT) /* 14-bit row address is used */
+
+#define DDRC_CFG_COL_BIT        8 /* Column Address width.
+                                     Specify the Column address width of external DDR. */
+#define DDRC_CFG_COL_MASK       (0x3 << DDRC_CFG_COL_BIT)
+#define DDRC_CFG_COL_8          (0 << DDRC_CFG_COL_BIT) /* 8-bit Column address is used */
+#define DDRC_CFG_COL_9          (1 << DDRC_CFG_COL_BIT) /* 9-bit Column address is used */
+#define DDRC_CFG_COL_10         (2 << DDRC_CFG_COL_BIT) /* 10-bit Column address is used */
+#define DDRC_CFG_COL_11         (3 << DDRC_CFG_COL_BIT) /* 11-bit Column address is used */
+
+#define DDRC_CFG_CS1EN          (1 << 7) /* 0 DDR Pin CS1 un-used
+                                            1 There're DDR memory connected to CS1 */
+#define DDRC_CFG_CS0EN          (1 << 6) /* 0 DDR Pin CS0 un-used
+                                            1 There're DDR memory connected to CS0 */
+
+#define DDRC_CFG_CL_BIT         2 /* CAS Latency */
+#define DDRC_CFG_CL_MASK        (0xf << DDRC_CFG_CL_BIT)
+#define DDRC_CFG_CL_3           (0x0a << DDRC_CFG_CL_BIT) /* CL = 3 tCK */
+#define DDRC_CFG_CL_4           (0x0b << DDRC_CFG_CL_BIT) /* CL = 4 tCK */
+#define DDRC_CFG_CL_5           (0x0c << DDRC_CFG_CL_BIT) /* CL = 5 tCK */
+#define DDRC_CFG_CL_6           (0x0d << DDRC_CFG_CL_BIT) /* CL = 6 tCK */
+#define DDRC_CFG_CL_7           (0x0e << DDRC_CFG_CL_BIT) /* CL = 7 tCK */
+
+#define DDRC_CFG_BA             (1 << 1) /* 0 4 bank device, Pin ba[1:0] valid, ba[2] un-used
+                                            1 8 bank device, Pin ba[2:0] valid*/
+#define DDRC_CFG_DW             (1 << 0) /*0 External memory data width is 16-bit
+                                           1 External memory data width is 32-bit */
+
+/* DDRC Control Register */
+#define DDRC_CTRL_ACTPD         (1 << 15) /* 0 Precharge all banks before entering power-down
+                                             1 Do not precharge banks before entering power-down */
+#define DDRC_CTRL_PDT_BIT       12 /* Power-Down Timer */
+#define DDRC_CTRL_PDT_MASK      (0x7 << DDRC_CTRL_PDT_BIT)
+#define DDRC_CTRL_PDT_DIS       (0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */
+#define DDRC_CTRL_PDT_8         (1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */
+#define DDRC_CTRL_PDT_16        (2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */
+#define DDRC_CTRL_PDT_32        (3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */
+#define DDRC_CTRL_PDT_64        (4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */
+#define DDRC_CTRL_PDT_128       (5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */
+
+#define DDRC_CTRL_PRET_BIT      8 /* Precharge Timer */
+#define DDRC_CTRL_PRET_MASK     (0x7 << DDRC_CTRL_PRET_BIT) /*  */
+  #define DDRC_CTRL_PRET_DIS    (0 << DDRC_CTRL_PRET_BIT) /* PRET function Disabled */
+  #define DDRC_CTRL_PRET_8      (1 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 8 tCK idle */
+  #define DDRC_CTRL_PRET_16     (2 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 16 tCK idle */
+  #define DDRC_CTRL_PRET_32     (3 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 32 tCK idle */
+  #define DDRC_CTRL_PRET_64     (4 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 64 tCK idle */
+  #define DDRC_CTRL_PRET_128    (5 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 128 tCK idle */
+
+#define DDRC_CTRL_SR            (1 << 5) /* 1 Drive external DDR device entering self-refresh mode
+                                            0 Drive external DDR device exiting self-refresh mode */
+#define DDRC_CTRL_UNALIGN       (1 << 4) /* 0 Disable unaligned transfer on AXI BUS
+                                            1 Enable unaligned transfer on AXI BUS */
+#define DDRC_CTRL_ALH           (1 << 3) /* Advanced Latency Hiding:
+                                            0 Disable ALH
+                                            1 Enable ALH */
+#define DDRC_CTRL_CKE           (1 << 1) /* 0 Not set CKE Pin High
+                                            1 Set CKE Pin HIGH */
+#define DDRC_CTRL_RESET         (1 << 0) /* 0 End resetting ddrc_controller
+                                            1 Resetting ddrc_controller */
+
+/* DDRC Load-Mode-Register */
+#define DDRC_LMR_DDR_ADDR_BIT   16 /* When performing a DDR command, DDRC_ADDR[13:0]
+                                      corresponding to external DDR address Pin A[13:0] */
+#define DDRC_LMR_DDR_ADDR_MASK  (0x3fff << DDRC_LMR_DDR_ADDR_BIT)
+
+#define DDRC_LMR_BA_BIT         8 /* When performing a DDR command, BA[2:0]
+                                     corresponding to external DDR address Pin BA[2:0]. */
+#define DDRC_LMR_BA_MASK        (0x7 << DDRC_LMR_BA_BIT)
+/* For DDR2 */
+#define DDRC_LMR_BA_MRS         (0 << DDRC_LMR_BA_BIT) /* Mode Register set */
+#define DDRC_LMR_BA_EMRS1       (1 << DDRC_LMR_BA_BIT) /* Extended Mode Register1 set */
+#define DDRC_LMR_BA_EMRS2       (2 << DDRC_LMR_BA_BIT) /* Extended Mode Register2 set */
+#define DDRC_LMR_BA_EMRS3       (3 << DDRC_LMR_BA_BIT) /* Extended Mode Register3 set */
+/* For mobile DDR */
+#define DDRC_LMR_BA_M_MRS       (0 << DDRC_LMR_BA_BIT) /* Mode Register set */
+#define DDRC_LMR_BA_M_EMRS      (2 << DDRC_LMR_BA_BIT) /* Extended Mode Register set */
+#define DDRC_LMR_BA_M_SR        (1 << DDRC_LMR_BA_BIT) /* Status Register set */
+
+#define DDRC_LMR_CMD_BIT        4
+#define DDRC_LMR_CMD_MASK       (0x3 << DDRC_LMR_CMD_BIT)
+#define DDRC_LMR_CMD_PREC       (0 << DDRC_LMR_CMD_BIT)/* Precharge one bank/All banks */
+#define DDRC_LMR_CMD_AUREF      (1 << DDRC_LMR_CMD_BIT)/* Auto-Refresh */
+#define DDRC_LMR_CMD_LMR        (2 << DDRC_LMR_CMD_BIT)/* Load Mode Register */
+
+#define DDRC_LMR_START          (1 << 0) /* 0 No command is performed
+                                            1 On the posedge of START, perform a command
+                                            defined by CMD field */
+/* DDRC Mode Register Set */
+#define DDR_MRS_PD_BIT          (1 << 10) /* Active power down exit time */
+#define DDR_MRS_PD_MASK         (1 << DDR_MRS_PD_BIT) 
+#define DDR_MRS_PD_FAST_EXIT    (0 << 10)
+#define DDR_MRS_PD_SLOW_EXIT    (1 << 10)
+#define DDR_MRS_WR_BIT          (1 << 9) /* Write Recovery for autoprecharge */
+#define DDR_MRS_WR_MASK         (7 << DDR_MRS_WR_BIT)
+#define DDR_MRS_DLL_RST         (1 << 8) /* DLL Reset */
+#define DDR_MRS_TM_BIT          7        /* Operating Mode */
+#define DDR_MRS_TM_MASK         (1 << DDR_MRS_OM_BIT) 
+#define DDR_MRS_TM_NORMAL       (0 << DDR_MRS_OM_BIT)
+#define DDR_MRS_TM_TEST (1 << DDR_MRS_OM_BIT)
+#define DDR_MRS_CAS_BIT         4        /* CAS Latency */
+#define DDR_MRS_CAS_MASK        (7 << DDR_MRS_CAS_BIT)
+#define DDR_MRS_BT_BIT          3        /* Burst Type */
+#define DDR_MRS_BT_MASK         (1 << DDR_MRS_BT_BIT)
+#define DDR_MRS_BT_SEQ  (0 << DDR_MRS_BT_BIT) /* Sequential */
+#define DDR_MRS_BT_INT  (1 << DDR_MRS_BT_BIT) /* Interleave */
+#define DDR_MRS_BL_BIT          0        /* Burst Length */
+#define DDR_MRS_BL_MASK         (7 << DDR_MRS_BL_BIT)
+#define DDR_MRS_BL_4            (2 << DDR_MRS_BL_BIT)
+#define DDR_MRS_BL_8            (3 << DDR_MRS_BL_BIT)
+
+/* DDRC Extended Mode Register1 Set */
+#define DDR_EMRS1_QOFF          (1<<12) /* 0 Output buffer enabled
+                                           1 Output buffer disabled */
+#define DDR_EMRS1_RDQS_EN       (1<<11) /* 0 Disable
+                                           1 Enable */
+#define DDR_EMRS1_DQS_DIS       (1<<10) /* 0 Enable
+                                           1 Disable */
+#define DDR_EMRS1_OCD_BIT       7 /* Additive Latency 0 -> 6 */
+#define DDR_EMRS1_OCD_MASK      (0x7 << DDR_EMRS1_OCD_BIT)
+#define DDR_EMRS1_OCD_EXIT              (0 << DDR_EMRS1_OCD_BIT)
+#define DDR_EMRS1_OCD_D0                (1 << DDR_EMRS1_OCD_BIT)
+#define DDR_EMRS1_OCD_D1                (2 << DDR_EMRS1_OCD_BIT)
+#define DDR_EMRS1_OCD_ADJ               (4 << DDR_EMRS1_OCD_BIT)
+#define DDR_EMRS1_OCD_DFLT              (7 << DDR_EMRS1_OCD_BIT)
+#define DDR_EMRS1_AL_BIT        3 /* Additive Latency 0 -> 6 */
+#define DDR_EMRS1_AL_MASK       (7 << DDR_EMRS1_AL_BIT)
+#define DDR_EMRS1_RTT_BIT       2 /*  */
+#define DDR_EMRS1_RTT_MASK      (0x11 << DDR_EMRS1_DIC_BIT) /* Bit 6, Bit 2 */
+#define DDR_EMRS1_DIC_BIT       1        /* Output Driver Impedence Control */
+#define DDR_EMRS1_DIC_MASK      (1 << DDR_EMRS1_DIC_BIT) /* 100% */
+#define DDR_EMRS1_DIC_NORMAL    (0 << DDR_EMRS1_DIC_BIT) /* 60% */
+#define DDR_EMRS1_DIC_HALF      (1 << DDR_EMRS1_DIC_BIT)
+#define DDR_EMRS1_DLL_BIT       0        /* DLL Enable  */
+#define DDR_EMRS1_DLL_MASK      (1 << DDR_EMRS1_DLL_BIT)
+#define DDR_EMRS1_DLL_EN        (0 << DDR_EMRS1_DLL_BIT)
+#define DDR_EMRS1_DLL_DIS       (1 << DDR_EMRS1_DLL_BIT)
+
+/* Mobile SDRAM Extended Mode Register */
+#define DDR_EMRS_DS_BIT         5       /* Driver strength */
+#define DDR_EMRS_DS_MASK        (7 << DDR_EMRS_DS_BIT)
+#define DDR_EMRS_DS_FULL        (0 << DDR_EMRS_DS_BIT)  /*Full*/
+#define DDR_EMRS_DS_HALF        (1 << DDR_EMRS_DS_BIT)  /*1/2 Strength*/
+#define DDR_EMRS_DS_QUTR        (2 << DDR_EMRS_DS_BIT)  /*1/4 Strength*/
+#define DDR_EMRS_DS_OCTANT      (3 << DDR_EMRS_DS_BIT)  /*1/8 Strength*/
+#define DDR_EMRS_DS_QUTR3       (4 << DDR_EMRS_DS_BIT)  /*3/4 Strength*/
+
+#define DDR_EMRS_PRSR_BIT       0       /* Partial Array Self Refresh */
+#define DDR_EMRS_PRSR_MASK      (7 << DDR_EMRS_PRSR_BIT)
+#define DDR_EMRS_PRSR_ALL       (0 << DDR_EMRS_PRSR_BIT) /*All Banks*/
+#define DDR_EMRS_PRSR_HALF_TL   (1 << DDR_EMRS_PRSR_BIT) /*Half of Total Bank*/
+#define DDR_EMRS_PRSR_QUTR_TL   (2 << DDR_EMRS_PRSR_BIT) /*Quarter of Total Bank*/
+#define DDR_EMRS_PRSR_HALF_B0   (5 << DDR_EMRS_PRSR_BIT) /*Half of Bank0*/
+#define DDR_EMRS_PRSR_QUTR_B0   (6 << DDR_EMRS_PRSR_BIT) /*Quarter of Bank0*/
+
+/* DDRC Timing Config Register 1 */
+#define DDRC_TIMING1_TRAS_BIT   28 /* ACTIVE to PRECHARGE command period (2 * tRAS + 1) */
+#define DDRC_TIMING1_TRAS_MASK  (0xf << DDRC_TIMING1_TRAS_BIT)
+
+#define DDRC_TIMING1_TRTP_BIT           24 /* READ to PRECHARGE command period. */
+#define DDRC_TIMING1_TRTP_MASK  (0x3 << DDRC_TIMING1_TRTP_BIT)
+
+#define DDRC_TIMING1_TRP_BIT            20 /* PRECHARGE command period. */
+#define DDRC_TIMING1_TRP_MASK   (0x7 << DDRC_TIMING1_TRP_BIT)
+
+#define DDRC_TIMING1_TRCD_BIT           16 /* ACTIVE to READ or WRITE command period. */
+#define DDRC_TIMING1_TRCD_MASK  (0x7 << DDRC_TIMING1_TRCD_BIT)
+
+#define DDRC_TIMING1_TRC_BIT            12 /* ACTIVE to ACTIVE command period. */
+#define DDRC_TIMING1_TRC_MASK   (0xf << DDRC_TIMING1_TRC_BIT)
+
+#define DDRC_TIMING1_TRRD_BIT           8 /* ACTIVE bank A to ACTIVE bank B command period. */
+#define DDRC_TIMING1_TRRD_MASK  (0x3 << DDRC_TIMING1_TRRD_BIT)
+#define DDRC_TIMING1_TRRD_DISABLE       (0 << DDRC_TIMING1_TRRD_BIT)
+#define DDRC_TIMING1_TRRD_2             (1 << DDRC_TIMING1_TRRD_BIT)
+#define DDRC_TIMING1_TRRD_3             (2 << DDRC_TIMING1_TRRD_BIT)
+#define DDRC_TIMING1_TRRD_4             (3 << DDRC_TIMING1_TRRD_BIT)
+
+#define DDRC_TIMING1_TWR_BIT            4 /* WRITE Recovery Time defined by register MR of DDR2 memory */
+#define DDRC_TIMING1_TWR_MASK           (0x7 << DDRC_TIMING1_TWR_BIT)
+#define DDRC_TIMING1_TWR_1              (0 << DDRC_TIMING1_TWR_BIT)
+#define DDRC_TIMING1_TWR_2              (1 << DDRC_TIMING1_TWR_BIT)
+#define DDRC_TIMING1_TWR_3              (2 << DDRC_TIMING1_TWR_BIT)
+#define DDRC_TIMING1_TWR_4              (3 << DDRC_TIMING1_TWR_BIT)
+#define DDRC_TIMING1_TWR_5              (4 << DDRC_TIMING1_TWR_BIT)
+#define DDRC_TIMING1_TWR_6              (5 << DDRC_TIMING1_TWR_BIT)
+
+#define DDRC_TIMING1_TWTR_BIT           0 /* WRITE to READ command delay. */
+#define DDRC_TIMING1_TWTR_MASK  (0x3 << DDRC_TIMING1_TWTR_BIT)
+#define DDRC_TIMING1_TWTR_1             (0 << DDRC_TIMING1_TWTR_BIT)
+#define DDRC_TIMING1_TWTR_2             (1 << DDRC_TIMING1_TWTR_BIT)
+#define DDRC_TIMING1_TWTR_3             (2 << DDRC_TIMING1_TWTR_BIT)
+#define DDRC_TIMING1_TWTR_4             (3 << DDRC_TIMING1_TWTR_BIT)
+
+/* DDRC Timing Config Register 2 */
+#define DDRC_TIMING2_TRFC_BIT         24 /* AUTO-REFRESH command period. */
+#define DDRC_TIMING2_TRFC_MASK        (0xf << DDRC_TIMING2_TRFC_BIT)
+#define DDRC_TIMING2_RWCOV_BIT        19 /* Equal to Tsel of MDELAY. */
+#define DDRC_TIMING2_RWCOV_MASK       (0x3 << DDRC_TIMING2_RWCOV_BIT)
+#define DDRC_TIMING2_TCKE_BIT         16
+#define DDRC_TIMING2_TCKE_MASK        (0x7 << DDRC_TIMING2_TCKE_BIT)
+#define DDRC_TIMING2_TMINSR_BIT       8  /* Minimum Self-Refresh / Deep-Power-Down time */
+#define DDRC_TIMING2_TMINSR_MASK      (0xf << DDRC_TIMING2_TMINSR_BIT)
+#define DDRC_TIMING2_TXP_BIT          4  /* EXIT-POWER-DOWN to next valid command period. */
+#define DDRC_TIMING2_TXP_MASK         (0x7 << DDRC_TIMING2_TXP_BIT)
+#define DDRC_TIMING2_TMRD_BIT         0  /* Load-Mode-Register to next valid command period. */
+#define DDRC_TIMING2_TMRD_MASK        (0x3 << DDRC_TIMING2_TMRD_BIT)
+
+/* DDRC  Auto-Refresh Counter */
+#define DDRC_REFCNT_CON_BIT           16 /* Constant value used to compare with CNT value. */
+#define DDRC_REFCNT_CON_MASK          (0xff << DDRC_REFCNT_CON_BIT)
+#define DDRC_REFCNT_CNT_BIT           8  /* 8-bit counter */
+#define DDRC_REFCNT_CNT_MASK          (0xff << DDRC_REFCNT_CNT_BIT)
+#define DDRC_REFCNT_CLKDIV_BIT        1  /* Clock Divider for auto-refresh counter. */
+#define DDRC_REFCNT_CLKDIV_MASK       (0x7 << DDRC_REFCNT_CLKDIV_BIT)
+#define DDRC_REFCNT_REF_EN            (1 << 0) /* Enable Refresh Counter */
+
+/* DDRC DQS Delay Control Register */
+#define DDRC_DQS_ERROR                (1 << 29) /* ahb_clk Delay Detect ERROR, read-only. */
+#define DDRC_DQS_READY                (1 << 28) /* ahb_clk Delay Detect READY, read-only. */
+#define DDRC_DQS_SRDET                (1 << 25)
+#define DDRC_DQS_DET                  (1 << 24) /* Start delay detecting. */
+#define DDRC_DQS_AUTO                 (1 << 23) /* Hardware auto-detect & set delay line */
+#define DDRC_DQS_CLKD_BIT             16 /* CLKD is reference value for setting WDQS and RDQS.*/
+#define DDRC_DQS_CLKD_MASK            (0x3f << DDRC_DQS_CLKD_BIT) 
+#define DDRC_DQS_WDQS_BIT             8  /* Set delay element number to write DQS delay-line. */
+#define DDRC_DQS_WDQS_MASK            (0x3f << DDRC_DQS_WDQS_BIT) 
+#define DDRC_DQS_RDQS_BIT             0  /* Set delay element number to read DQS delay-line. */
+#define DDRC_DQS_RDQS_MASK            (0x3f << DDRC_DQS_RDQS_BIT) 
+
+/* DDRC DQS Delay Adjust Register */
+#define DDRC_DQS_ADJDQSCON_BIT        16
+#define DDRC_DQS_ADJDQSCON_MASK       (0xffff << DDRC_DQS_ADJDQSCON_BIT)
+#define DDRC_DQS_ADJWSIGN             (1 << 13)
+#define DDRC_DQS_ADJWDQS_BIT          8 /* The adjust value for WRITE DQS delay */
+#define DDRC_DQS_ADJWDQS_MASK         (0x1f << DDRC_DQS_ADJWDQS_BIT)
+#define DDRC_DQS_ADJRSIGN             (1 << 5)
+#define DDRC_DQS_ADJRDQS_BIT          0 /* The adjust value for READ DQS delay */
+#define DDRC_DQS_ADJRDQS_MASK         (0x1f << DDRC_DQS_ADJRDQS_BIT)
+
+/* DDRC Memory Map Config Register */
+#define DDRC_MMAP_BASE_BIT            8 /* base address */
+#define DDRC_MMAP_BASE_MASK           (0xff << DDRC_MMAP_BASE_BIT)
+#define DDRC_MMAP_MASK_BIT            0 /* address mask */
+#define DDRC_MMAP_MASK_MASK           (0xff << DDRC_MMAP_MASK_BIT)         
+
+#define DDRC_MMAP0_BASE              (0x20 << DDRC_MMAP_BASE_BIT)
+#define DDRC_MMAP1_BASE_64M     (0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
+#define DDRC_MMAP1_BASE_128M    (0x28 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
+#define DDRC_MMAP1_BASE_256M    (0x30 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
+
+#define DDRC_MMAP_MASK_64_64    (0xfc << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
+#define DDRC_MMAP_MASK_128_128  (0xf8 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
+#define DDRC_MMAP_MASK_256_256  (0xf0 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
+
+/* DDRC Timing Configure Register 1 */
+#define DDRC_DDELAYCTRL1_TSEL_BIT                       18
+#define DDRC_DDELAYCTRL1_TSEL_MASK                      (0x3 << DDRC_DDELAYCTRL1_TSEL_BIT)
+#define DDRC_DDELAYCTRL1_MSEL_BIT                       16
+#define DDRC_DDELAYCTRL1_MSEL_MASK                      (0x3 << DDRC_DDELAYCTRL1_MSEL_BIT)
+#define DDRC_DDELAYCTRL1_HL                             (1 << 15)
+#define DDRC_DDELAYCTRL1_QUAR                           (1 << 14)
+#define DDRC_DDELAYCTRL1_MAUTO                          (1 << 6)
+#define DDRC_DDELAYCTRL1_MSIGN                          (1 << 5)
+#define DDRC_DDELAYCTRL1_MASK_DELAY_SEL_ADJ_BIT         0
+#define DDRC_DDELAYCTRL1_MASK_DELAY_SEL_ADJ_MASK        (0x1f << DDRC_DDELAYCTRL1_MASK_DELAY_SEL_ADJ_BIT)
+
+/* DDRC Timing Configure Register 2 */
+#define DDRC_DDELAYCTRL2_MASK_DELAY_SEL_BIT             0
+#define DDRC_DDELAYCTRL2_MASK_DELAY_SEL_MASK            (0x3f << DDRC_DDELAYCTRL2_MASK_DELAY_SEL_BIT)
+
+/* DDRC Multi-media stride Register */
+#define DDRC_DSTRB_STRB0_BIT            16
+#define DDRC_DSTRB_STRB0_MASK           (0x1fff << DDRC_DSTRB_STRB0_BIT)
+#define DDRC_DSTRB_STRB1_BIT            0
+#define DDRC_DSTRB_STRB1_MASK           (0x1fff << DDRC_DSTRB_STRB1_BIT)
+/* DDRC IO pad control Register */
+#define DDRC_PMEMBS0_PDDQS3                     (1 << 31)
+#define DDRC_PMEMBS0_PDDQS2                     (1 << 30)
+#define DDRC_PMEMBS0_PDDQS1                     (1 << 29)
+#define DDRC_PMEMBS0_PDDQS0                     (1 << 28)
+#define DDRC_PMEMBS0_PDDQ3                      (1 << 27)
+#define DDRC_PMEMBS0_PDDQ2                      (1 << 26)
+#define DDRC_PMEMBS0_PDDQ1                      (1 << 25)
+#define DDRC_PMEMBS0_PDDQ0                      (1 << 24)
+#define DDRC_PMEMBS0_STDQS3                     (1 << 23)
+#define DDRC_PMEMBS0_STDQS2                     (1 << 22)
+#define DDRC_PMEMBS0_STDQS1                     (1 << 21)
+#define DDRC_PMEMBS0_STDQS0                     (1 << 20)
+#define DDRC_PMEMBS0_STDQ3                      (1 << 19)
+#define DDRC_PMEMBS0_STDQ2                      (1 << 18)
+#define DDRC_PMEMBS0_STDQ1                      (1 << 17)
+#define DDRC_PMEMBS0_STDQ0                      (1 << 16)
+#define DDRC_PMEMBS0_PEDQS3                     (1 << 15)
+#define DDRC_PMEMBS0_PEDQS2                     (1 << 14)
+#define DDRC_PMEMBS0_PEDQS1                     (1 << 13)
+#define DDRC_PMEMBS0_PEDQS0                     (1 << 12)
+#define DDRC_PMEMBS0_PEDQ3                      (1 << 11)
+#define DDRC_PMEMBS0_PEDQ2                      (1 << 10)
+#define DDRC_PMEMBS0_PEDQ1                      (1 << 9)
+#define DDRC_PMEMBS0_PEDQ0                      (1 << 8)
+#define DDRC_PMEMBS0_PSDQS3                     (1 << 7)
+#define DDRC_PMEMBS0_PSDQS2                     (1 << 6)
+#define DDRC_PMEMBS0_PSDQS1                     (1 << 5)
+#define DDRC_PMEMBS0_PSDQS0                     (1 << 4)
+#define DDRC_PMEMBS0_PSDQ3                      (1 << 3)
+#define DDRC_PMEMBS0_PSDQ2                      (1 << 2)
+#define DDRC_PMEMBS0_PSDQ1                      (1 << 1)
+#define DDRC_PMEMBS0_PSDQ0                      (1 << 0)
+/* DDRC IO pad control Register */
+#define DDRC_PMEMBS1_IENDQS3                    (1 << 31)
+#define DDRC_PMEMBS1_IENDQS2                    (1 << 30)
+#define DDRC_PMEMBS1_IENDQS1                    (1 << 29)
+#define DDRC_PMEMBS1_IENDQS0                    (1 << 28)
+#define DDRC_PMEMBS1_IENDQ3                     (1 << 27)
+#define DDRC_PMEMBS1_IENDQ2                     (1 << 26)
+#define DDRC_PMEMBS1_IENDQ1                     (1 << 25)
+#define DDRC_PMEMBS1_IENDQ0                     (1 << 24)
+#define DDRC_PMEMBS1_SSTL                       (1 << 16)
+
+#define DDRC_PMEMBS1_SSELDQS3_BIT               14
+#define DDRC_PMEMBS1_SSELDQS3_MASK              (0x3 << DDRC_PMEMBS1_SSELDQS3_BIT)
+
+#define DDRC_PMEMBS1_SSELDQS2_BIT               12
+#define DDRC_PMEMBS1_SSELDQS2_MASK              (0x3 << DDRC_PMEMBS1_SSELDQS2_BIT)
+
+#define DDRC_PMEMBS1_SSELDQS1_BIT               10
+#define DDRC_PMEMBS1_SSELDQS1_MASK              (0x3 << DDRC_PMEMBS1_SSELDQS1_BIT)
+
+#define DDRC_PMEMBS1_SSELDQS0_BIT               8
+#define DDRC_PMEMBS1_SSELDQS0_MASK              (0x3 << DDRC_PMEMBS1_SSELDQS0_BIT)
+
+#define DDRC_PMEMBS1_SSELDQ3_BIT                6
+#define DDRC_PMEMBS1_SSELDQ3_MASK               (0x3 << DDRC_PMEMBS1_SSELDQ3_BIT)
+
+#define DDRC_PMEMBS1_SSELDQ2_BIT                4
+#define DDRC_PMEMBS1_SSELDQ2_MASK               (0x3 << DDRC_PMEMBS1_SSELDQ2_BIT)
+
+#define DDRC_PMEMBS1_SSELDQ1_BIT                2
+#define DDRC_PMEMBS1_SSELDQ1_MASK               (0x3 << DDRC_PMEMBS1_SSELDQ1_BIT)
+
+#define DDRC_PMEMBS1_SSELDQ0_BIT                0
+#define DDRC_PMEMBS1_SSELDQ0_MASK               (0x3 << DDRC_PMEMBS1_SSELDQ0_BIT)
+
+/* DDRC IO pad control Register */
+#define DDRC_PMEMOSEL_CKSSEL_BIT                18
+#define DDRC_PMEMOSEL_CKSSEL_MASK               (0x3 << DDRC_PMEMOSEL_CKSSEL_BIT)
+
+#define DDRC_PMEMOSEL_CKESSEL_BIT               16
+#define DDRC_PMEMOSEL_CKESSEL_MASK              (0x3 << DDRC_PMEMOSEL_CKESSEL_BIT)
+
+#define DDRC_PMEMOSEL_ADDRSSEL_BIT              14
+#define DDRC_PMEMOSEL_ADDRSSEL_MASK             (0x3 << DDRC_PMEMOSEL_ADDRSSEL_BIT)
+
+#define DDRC_PMEMOSEL_DMSSEL3_BIT               12
+#define DDRC_PMEMOSEL_DMSSEL3_MASK              (0x3 << DDRC_PMEMOSEL_DMSSEL3_BIT)
+
+#define DDRC_PMEMOSEL_DMSSEL2_BIT               10
+#define DDRC_PMEMOSEL_DMSSEL2_MASK              (0x3 << DDRC_PMEMOSEL_DMSSEL2_BIT)
+
+#define DDRC_PMEMOSEL_DMSSEL1_BIT               8
+#define DDRC_PMEMOSEL_DMSSEL1_MASK              (0x3 << DDRC_PMEMOSEL_DMSSEL1_BIT)
+
+#define DDRC_PMEMOSEL_DMSSEL0_BIT               6
+#define DDRC_PMEMOSEL_DMSSEL0_MASK              (0x3 << DDRC_PMEMOSEL_DMSSEL0_BIT)
+
+#define DDRC_PMEMOSEL_CMDSSEL_BIT               4
+#define DDRC_PMEMOSEL_CMDSSEL_MASK              (0x3 << DDRC_PMEMOSEL_CMDSSEL_BIT)
+
+#define DDRC_PMEMOSEL_CSSSEL1_BIT               2
+#define DDRC_PMEMOSEL_CSSSEL1_MASK              (0x3 << DDRC_PMEMOSEL_CSSSEL1_BIT)
+
+#define DDRC_PMEMOSEL_CSSSEL0_BIT               0
+#define DDRC_PMEMOSEL_CSSSEL0_MASK              (0x3 << DDRC_PMEMOSEL_CSSSEL0_BIT)
+
+/* DDRC IO pad control Register */
+#define DDRC_PMEMOEN_CKOEN                      (1 << 14)
+#define DDRC_PMEMOEN_BAOEN2                     (1 << 13)
+#define DDRC_PMEMOEN_BAOEN1                     (1 << 12)
+#define DDRC_PMEMOEN_BAOEN0                     (1 << 11)
+#define DDRC_PMEMOEN_AOEN13                     (1 << 10)
+#define DDRC_PMEMOEN_AOEN12                     (1 << 9)
+#define DDRC_PMEMOEN_AOEN11_0                   (1 << 8)
+#define DDRC_PMEMOEN_DMOEN3                     (1 << 7)
+#define DDRC_PMEMOEN_DMOEN2                     (1 << 6)
+#define DDRC_PMEMOEN_DMOEN1                     (1 << 5)
+#define DDRC_PMEMOEN_DMOEN0                     (1 << 4)
+#define DDRC_PMEMOEN_CMDOEN                     (1 << 3)
+#define DDRC_PMEMOEN_CSOEN1                     (1 << 2)
+#define DDRC_PMEMOEN_CSOEN0                     (1 << 1)
+#define DDRC_PMEMOEN_CKEOEN                     (1 << 0)
+
+#ifndef __MIPS_ASSEMBLER
+
+#define DDR_GET_VALUE(x, y)                           \
+({                                                    \
+        unsigned long value, tmp;                     \
+        tmp = x * 1000;                               \
+        value = (tmp % y == 0) ? (tmp / y) : (tmp / y + 1); \
+                value;                                \
+})
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define EMC_BASE        0xB3410000
+
+/*************************************************************************
+ * EMC (External Memory Controller)
+ *************************************************************************/
+#define EMC_BCR         (EMC_BASE + 0x00)  /* Bus Control Register */
+#define EMC_PMEMBS1     (EMC_BASE + 0x6004) 
+#define EMC_PMEMBS0     (EMC_BASE + 0x6008) 
+#define EMC_SMCR0       (EMC_BASE + 0x10)  /* Static Memory Control Register 0 ??? */
+#define EMC_SMCR1       (EMC_BASE + 0x14)  /* Static Memory Control Register 1 */
+#define EMC_SMCR2       (EMC_BASE + 0x18)  /* Static Memory Control Register 2 */
+#define EMC_SMCR3       (EMC_BASE + 0x1c)  /* Static Memory Control Register 3 */
+#define EMC_SMCR4       (EMC_BASE + 0x20)  /* Static Memory Control Register 4 */
+#define EMC_SMCR5       (EMC_BASE + 0x24)  /* Static Memory Control Register 5 */
+#define EMC_SMCR6       (EMC_BASE + 0x28)  /* Static Memory Control Register 6 */
+#define EMC_SACR0       (EMC_BASE + 0x30)  /* Static Memory Bank 0 Addr Config Reg */
+#define EMC_SACR1       (EMC_BASE + 0x34)  /* Static Memory Bank 1 Addr Config Reg */
+#define EMC_SACR2       (EMC_BASE + 0x38)  /* Static Memory Bank 2 Addr Config Reg */
+#define EMC_SACR3       (EMC_BASE + 0x3c)  /* Static Memory Bank 3 Addr Config Reg */
+#define EMC_SACR4       (EMC_BASE + 0x40)  /* Static Memory Bank 4 Addr Config Reg */
+#define EMC_SACR5       (EMC_BASE + 0x44)  /* Static Memory Bank 5 Addr Config Reg */
+#define EMC_SACR6       (EMC_BASE + 0x48)  /* Static Memory Bank 6 Addr Config Reg */
+#define EMC_NFCSR       (EMC_BASE + 0x50)  /* NAND Flash Control/Status Register */
+#define EMC_DMCR        (EMC_BASE + 0x80)  /* DRAM Control Register */
+#define EMC_RTCSR       (EMC_BASE + 0x84)  /* Refresh Time Control/Status Register */
+#define EMC_RTCNT       (EMC_BASE + 0x88)  /* Refresh Timer Counter */
+#define EMC_RTCOR       (EMC_BASE + 0x8c)  /* Refresh Time Constant Register */
+#define EMC_DMAR0       (EMC_BASE + 0x90)  /* SDRAM Bank 0 Addr Config Register */
+#define EMC_DMAR1       (EMC_BASE + 0x94)  /* SDRAM Bank 1 Addr Config Register */
+#define EMC_SDMR0       (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
+
+#define REG_EMC_BCR     REG32(EMC_BCR)
+#define REG_EMC_PMEMBS1 REG32(EMC_PMEMBS1)
+#define REG_EMC_PMEMBS0 REG32(EMC_PMEMBS0)
+#define REG_EMC_SMCR0   REG32(EMC_SMCR0) // ???
+#define REG_EMC_SMCR1   REG32(EMC_SMCR1)
+#define REG_EMC_SMCR2   REG32(EMC_SMCR2)
+#define REG_EMC_SMCR3   REG32(EMC_SMCR3)
+#define REG_EMC_SMCR4   REG32(EMC_SMCR4)
+#define REG_EMC_SMCR5   REG32(EMC_SMCR5)
+#define REG_EMC_SMCR6   REG32(EMC_SMCR6)
+#define REG_EMC_SACR0   REG32(EMC_SACR0)
+#define REG_EMC_SACR1   REG32(EMC_SACR1)
+#define REG_EMC_SACR2   REG32(EMC_SACR2)
+#define REG_EMC_SACR3   REG32(EMC_SACR3)
+#define REG_EMC_SACR4   REG32(EMC_SACR4)
+
+#define REG_EMC_NFCSR   REG32(EMC_NFCSR)
+
+#define REG_EMC_DMCR    REG32(EMC_DMCR)
+#define REG_EMC_RTCSR   REG16(EMC_RTCSR)
+#define REG_EMC_RTCNT   REG16(EMC_RTCNT)
+#define REG_EMC_RTCOR   REG16(EMC_RTCOR)
+#define REG_EMC_DMAR0   REG32(EMC_DMAR0)
+#define REG_EMC_DMAR1   REG32(EMC_DMAR1)
+
+/* Bus Control Register */
+#define EMC_BCR_BT_SEL_BIT      30
+#define EMC_BCR_BT_SEL_MASK     (0x3 << EMC_BCR_BT_SEL_BIT)
+#define EMC_BCR_PK_SEL          (1 << 24)
+#define EMC_BCR_BSR_MASK          (1 << 2)  /* Nand and SDRAM Bus Share Select: 0, share; 1, unshare */
+  #define EMC_BCR_BSR_SHARE       (0 << 2)
+  #define EMC_BCR_BSR_UNSHARE     (1 << 2)
+#define EMC_BCR_BRE             (1 << 1)
+#define EMC_BCR_ENDIAN          (1 << 0)
+
+/* Static Memory Control Register */
+#define EMC_SMCR_STRV_BIT       24
+#define EMC_SMCR_STRV_MASK      (0x1f << EMC_SMCR_STRV_BIT)
+#define EMC_SMCR_TAW_BIT        20
+#define EMC_SMCR_TAW_MASK       (0x0f << EMC_SMCR_TAW_BIT)
+#define EMC_SMCR_TBP_BIT        16
+#define EMC_SMCR_TBP_MASK       (0x0f << EMC_SMCR_TBP_BIT)
+#define EMC_SMCR_TAH_BIT        12
+#define EMC_SMCR_TAH_MASK       (0x07 << EMC_SMCR_TAH_BIT)
+#define EMC_SMCR_TAS_BIT        8
+#define EMC_SMCR_TAS_MASK       (0x07 << EMC_SMCR_TAS_BIT)
+#define EMC_SMCR_BW_BIT         6
+#define EMC_SMCR_BW_MASK        (0x03 << EMC_SMCR_BW_BIT)
+  #define EMC_SMCR_BW_8BIT      (0 << EMC_SMCR_BW_BIT)
+  #define EMC_SMCR_BW_16BIT     (1 << EMC_SMCR_BW_BIT)
+  #define EMC_SMCR_BW_32BIT     (2 << EMC_SMCR_BW_BIT)
+#define EMC_SMCR_BCM            (1 << 3)
+#define EMC_SMCR_BL_BIT         1
+#define EMC_SMCR_BL_MASK        (0x03 << EMC_SMCR_BL_BIT)
+  #define EMC_SMCR_BL_4         (0 << EMC_SMCR_BL_BIT)
+  #define EMC_SMCR_BL_8         (1 << EMC_SMCR_BL_BIT)
+  #define EMC_SMCR_BL_16        (2 << EMC_SMCR_BL_BIT)
+  #define EMC_SMCR_BL_32        (3 << EMC_SMCR_BL_BIT)
+#define EMC_SMCR_SMT            (1 << 0)
+
+/* Static Memory Bank Addr Config Reg */
+#define EMC_SACR_BASE_BIT       8
+#define EMC_SACR_BASE_MASK      (0xff << EMC_SACR_BASE_BIT)
+#define EMC_SACR_MASK_BIT       0
+#define EMC_SACR_MASK_MASK      (0xff << EMC_SACR_MASK_BIT)
+
+/* NAND Flash Control/Status Register */
+#define EMC_NFCSR_NFCE4         (1 << 7) /* NAND Flash Enable */
+#define EMC_NFCSR_NFE4          (1 << 6) /* NAND Flash FCE# Assertion Enable */
+#define EMC_NFCSR_NFCE3         (1 << 5)
+#define EMC_NFCSR_NFE3          (1 << 4)
+#define EMC_NFCSR_NFCE2         (1 << 3)
+#define EMC_NFCSR_NFE2          (1 << 2)
+#define EMC_NFCSR_NFCE1         (1 << 1)
+#define EMC_NFCSR_NFE1          (1 << 0)
+#define EMC_NFCSR_NFE(n)        (1 << (((n)-1)*2))
+#define EMC_NFCSR_NFCE(n)       (1 << (((n)*2)-1))
+
+/* DRAM Control Register */
+#define EMC_DMCR_BW_BIT         31
+#define EMC_DMCR_BW             (1 << EMC_DMCR_BW_BIT)
+#define EMC_DMCR_CA_BIT         26
+#define EMC_DMCR_CA_MASK        (0x07 << EMC_DMCR_CA_BIT)
+  #define EMC_DMCR_CA_8         (0 << EMC_DMCR_CA_BIT)
+  #define EMC_DMCR_CA_9         (1 << EMC_DMCR_CA_BIT)
+  #define EMC_DMCR_CA_10        (2 << EMC_DMCR_CA_BIT)
+  #define EMC_DMCR_CA_11        (3 << EMC_DMCR_CA_BIT)
+  #define EMC_DMCR_CA_12        (4 << EMC_DMCR_CA_BIT)
+#define EMC_DMCR_RMODE          (1 << 25)
+#define EMC_DMCR_RFSH           (1 << 24)
+#define EMC_DMCR_MRSET          (1 << 23)
+#define EMC_DMCR_RA_BIT         20
+#define EMC_DMCR_RA_MASK        (0x03 << EMC_DMCR_RA_BIT)
+  #define EMC_DMCR_RA_11        (0 << EMC_DMCR_RA_BIT)
+  #define EMC_DMCR_RA_12        (1 << EMC_DMCR_RA_BIT)
+  #define EMC_DMCR_RA_13        (2 << EMC_DMCR_RA_BIT)
+#define EMC_DMCR_BA_BIT         19
+#define EMC_DMCR_BA             (1 << EMC_DMCR_BA_BIT)
+#define EMC_DMCR_PDM            (1 << 18)
+#define EMC_DMCR_EPIN           (1 << 17)
+#define EMC_DMCR_MBSEL          (1 << 16)
+#define EMC_DMCR_TRAS_BIT       13
+#define EMC_DMCR_TRAS_MASK      (0x07 << EMC_DMCR_TRAS_BIT)
+#define EMC_DMCR_RCD_BIT        11
+#define EMC_DMCR_RCD_MASK       (0x03 << EMC_DMCR_RCD_BIT)
+#define EMC_DMCR_TPC_BIT        8
+#define EMC_DMCR_TPC_MASK       (0x07 << EMC_DMCR_TPC_BIT)
+#define EMC_DMCR_TRWL_BIT       5
+#define EMC_DMCR_TRWL_MASK      (0x03 << EMC_DMCR_TRWL_BIT)
+#define EMC_DMCR_TRC_BIT        2
+#define EMC_DMCR_TRC_MASK       (0x07 << EMC_DMCR_TRC_BIT)
+#define EMC_DMCR_TCL_BIT        0
+#define EMC_DMCR_TCL_MASK       (0x03 << EMC_DMCR_TCL_BIT)
+
+/* Refresh Time Control/Status Register */
+#define EMC_RTCSR_SFR           (1 << 8)    /* self refresh flag */
+#define EMC_RTCSR_CMF           (1 << 7)
+#define EMC_RTCSR_CKS_BIT       0
+#define EMC_RTCSR_CKS_MASK      (0x07 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_4       (1 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_16      (2 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_64      (3 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_256     (4 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_1024    (5 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_2048    (6 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_4096    (7 << EMC_RTCSR_CKS_BIT)
+
+/* SDRAM Bank Address Configuration Register */
+#define EMC_DMAR_BASE_BIT       8
+#define EMC_DMAR_BASE_MASK      (0xff << EMC_DMAR_BASE_BIT)
+#define EMC_DMAR_MASK_BIT       0
+#define EMC_DMAR_MASK_MASK      (0xff << EMC_DMAR_MASK_BIT)
+
+/* Mode Register of SDRAM bank 0 */
+#define EMC_SDMR_BM             (1 << 9) /* Write Burst Mode */
+#define EMC_SDMR_OM_BIT         7        /* Operating Mode */
+#define EMC_SDMR_OM_MASK        (3 << EMC_SDMR_OM_BIT)
+  #define EMC_SDMR_OM_NORMAL    (0 << EMC_SDMR_OM_BIT)
+#define EMC_SDMR_CAS_BIT        4        /* CAS Latency */
+#define EMC_SDMR_CAS_MASK       (7 << EMC_SDMR_CAS_BIT)
+  #define EMC_SDMR_CAS_1        (1 << EMC_SDMR_CAS_BIT)
+  #define EMC_SDMR_CAS_2        (2 << EMC_SDMR_CAS_BIT)
+  #define EMC_SDMR_CAS_3        (3 << EMC_SDMR_CAS_BIT)
+#define EMC_SDMR_BT_BIT         3        /* Burst Type */
+#define EMC_SDMR_BT_MASK        (1 << EMC_SDMR_BT_BIT)
+  #define EMC_SDMR_BT_SEQ       (0 << EMC_SDMR_BT_BIT) /* Sequential */
+  #define EMC_SDMR_BT_INT       (1 << EMC_SDMR_BT_BIT) /* Interleave */
+#define EMC_SDMR_BL_BIT         0        /* Burst Length */
+#define EMC_SDMR_BL_MASK        (7 << EMC_SDMR_BL_BIT)
+  #define EMC_SDMR_BL_1         (0 << EMC_SDMR_BL_BIT)
+  #define EMC_SDMR_BL_2         (1 << EMC_SDMR_BL_BIT)
+  #define EMC_SDMR_BL_4         (2 << EMC_SDMR_BL_BIT)
+  #define EMC_SDMR_BL_8         (3 << EMC_SDMR_BL_BIT)
+
+#define EMC_SDMR_CAS2_16BIT \
+  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
+#define EMC_SDMR_CAS2_32BIT \
+  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
+#define EMC_SDMR_CAS3_16BIT \
+  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
+#define EMC_SDMR_CAS3_32BIT \
+  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
+
+#define I2C0_BASE       0xB0050000
+#define I2C1_BASE       0xB0051000
+
+/*************************************************************************
+ * I2C
+ *************************************************************************/
+#define I2C_CTRL(n)             (I2C0_BASE + (n)*0x1000 + 0x00)
+#define I2C_TAR(n)              (I2C0_BASE + (n)*0x1000 + 0x04)
+#define I2C_SAR(n)              (I2C0_BASE + (n)*0x1000 + 0x08)
+#define I2C_DC(n)               (I2C0_BASE + (n)*0x1000 + 0x10)
+#define I2C_SHCNT(n)            (I2C0_BASE + (n)*0x1000 + 0x14)
+#define I2C_SLCNT(n)            (I2C0_BASE + (n)*0x1000 + 0x18)
+#define I2C_FHCNT(n)            (I2C0_BASE + (n)*0x1000 + 0x1C)
+#define I2C_FLCNT(n)            (I2C0_BASE + (n)*0x1000 + 0x20)
+#define I2C_INTST(n)            (I2C0_BASE + (n)*0x1000 + 0x2C)
+#define I2C_INTM(n)             (I2C0_BASE + (n)*0x1000 + 0x30)
+#define I2C_RXTL(n)             (I2C0_BASE + (n)*0x1000 + 0x38)
+#define I2C_TXTL(n)             (I2C0_BASE + (n)*0x1000 + 0x3c)
+#define I2C_CINTR(n)            (I2C0_BASE + (n)*0x1000 + 0x40)
+#define I2C_CRXUF(n)            (I2C0_BASE + (n)*0x1000 + 0x44)
+#define I2C_CRXOF(n)            (I2C0_BASE + (n)*0x1000 + 0x48)
+#define I2C_CTXOF(n)            (I2C0_BASE + (n)*0x1000 + 0x4C)
+#define I2C_CRXREQ(n)           (I2C0_BASE + (n)*0x1000 + 0x50)
+#define I2C_CTXABRT(n)          (I2C0_BASE + (n)*0x1000 + 0x54)
+#define I2C_CRXDONE(n)          (I2C0_BASE + (n)*0x1000 + 0x58)
+#define I2C_CACT(n)             (I2C0_BASE + (n)*0x1000 + 0x5C)
+#define I2C_CSTP(n)             (I2C0_BASE + (n)*0x1000 + 0x60)
+#define I2C_CSTT(n)             (I2C0_BASE + (n)*0x1000 + 0x64)
+#define I2C_CGC(n)              (I2C0_BASE + (n)*0x1000 + 0x68)
+#define I2C_ENB(n)              (I2C0_BASE + (n)*0x1000 + 0x6C)
+#define I2C_STA(n)              (I2C0_BASE + (n)*0x1000 + 0x70)
+#define I2C_TXABRT(n)           (I2C0_BASE + (n)*0x1000 + 0x80)
+#define I2C_DMACR(n)            (I2C0_BASE + (n)*0x1000 + 0x88)
+#define I2C_DMATDLR(n)          (I2C0_BASE + (n)*0x1000 + 0x8c)
+#define I2C_DMARDLR(n)          (I2C0_BASE + (n)*0x1000 + 0x90)
+#define I2C_SDASU(n)            (I2C0_BASE + (n)*0x1000 + 0x94)
+#define I2C_ACKGC(n)            (I2C0_BASE + (n)*0x1000 + 0x98)
+#define I2C_ENSTA(n)            (I2C0_BASE + (n)*0x1000 + 0x9C)
+
+#define REG_I2C_CTRL(n)         REG8(I2C_CTRL(n)) /* I2C Control Register (I2C_CTRL) */
+#define REG_I2C_TAR(n)          REG16(I2C_TAR(n)) /* I2C target address (I2C_TAR) */
+#define REG_I2C_SAR(n)          REG16(I2C_SAR(n))
+#define REG_I2C_DC(n)           REG16(I2C_DC(n))
+#define REG_I2C_SHCNT(n)        REG16(I2C_SHCNT(n))
+#define REG_I2C_SLCNT(n)        REG16(I2C_SLCNT(n))
+#define REG_I2C_FHCNT(n)        REG16(I2C_FHCNT(n))
+#define REG_I2C_FLCNT(n)        REG16(I2C_FLCNT(n))
+#define REG_I2C_INTST(n)        REG16(I2C_INTST(n)) /* i2c interrupt status (I2C_INTST) */
+#define REG_I2C_INTM(n)         REG16(I2C_INTM(n)) /* i2c interrupt mask status (I2C_INTM) */
+#define REG_I2C_RXTL(n)         REG8(I2C_RXTL(n))
+#define REG_I2C_TXTL(n)         REG8(I2C_TXTL(n))
+#define REG_I2C_CINTR(n)        REG8(I2C_CINTR(n))
+#define REG_I2C_CRXUF(n)        REG8(I2C_CRXUF(n))
+#define REG_I2C_CRXOF(n)        REG8(I2C_CRXOF(n))
+#define REG_I2C_CTXOF(n)        REG8(I2C_CTXOF(n))
+#define REG_I2C_CRXREQ(n)       REG8(I2C_CRXREQ(n))
+#define REG_I2C_CTXABRT(n)      REG8(I2C_CTXABRT(n))
+#define REG_I2C_CRXDONE(n)      REG8(I2C_CRXDONE(n))
+#define REG_I2C_CACT(n)         REG8(I2C_CACT(n))
+#define REG_I2C_CSTP(n)         REG8(I2C_CSTP(n))
+#define REG_I2C_CSTT(n)         REG16(I2C_CSTT(n))
+#define REG_I2C_CGC(n)          REG8(I2C_CGC(n))
+#define REG_I2C_ENB(n)          REG8(I2C_ENB(n))
+#define REG_I2C_STA(n)          REG8(I2C_STA(n))
+#define REG_I2C_TXABRT(n)       REG16(I2C_TXABRT(n))
+#define REG_I2C_DMACR(n)        REG8(I2C_DMACR(n))
+#define REG_I2C_DMATDLR(n)      REG8(I2C_DMATDLR(n))
+#define REG_I2C_DMARDLR(n)      REG8(I2C_DMARDLR(n))
+#define REG_I2C_SDASU(n)        REG8(I2C_SDASU(n))
+#define REG_I2C_ACKGC(n)        REG8(I2C_ACKGC(n))
+#define REG_I2C_ENSTA(n)        REG8(I2C_ENSTA(n))
+
+/* I2C Control Register (I2C_CTRL) */
+
+#define I2C_CTRL_STPHLD         (1 << 7) /* Stop Hold Enable bit: when tx fifo empty, 0: send stop 1: never send stop*/
+#define I2C_CTRL_SLVDIS         (1 << 6) /* after reset slave is disabled*/
+#define I2C_CTRL_REST           (1 << 5)        
+#define I2C_CTRL_MATP           (1 << 4) /* 1: 10bit address 0: 7bit addressing*/
+#define I2C_CTRL_SATP           (1 << 3) /* 1: 10bit address 0: 7bit address*/
+#define I2C_CTRL_SPDF           (2 << 1) /* fast mode 400kbps */
+#define I2C_CTRL_SPDS           (1 << 1) /* standard mode 100kbps */
+#define I2C_CTRL_MD             (1 << 0) /* master enabled*/
+
+/* I2C target address (I2C_TAR) */
+
+#define I2C_TAR_MATP            (1 << 12)
+#define I2C_TAR_SPECIAL         (1 << 11)
+#define I2C_TAR_GC_OR_START     (1 << 10)
+#define I2C_TAR_I2CTAR_BIT      0
+#define I2C_TAR_I2CTAR_MASK     (0x3ff << I2C_TAR_I2CTAR_BIT)
+
+/* I2C slave address  */
+#define I2C_SAR_I2CSAR_BIT      0
+#define I2C_SAR_I2CSAR_MASK     (0x3ff << I2C_SAR_I2CSAR_BIT)
+
+/* I2C data buffer and command (I2C_DC) */
+
+#define I2C_DC_CMD                      (1 << 8) /* 1 read 0  write*/
+#define I2C_DC_DAT_BIT          0
+#define I2C_DC_DAT_MASK         (0xff << I2C_DC_DAT_BIT) /* 1 read 0  write*/
+
+/* i2c interrupt status (I2C_INTST) */
+
+#define I2C_INTST_IGC                   (1 << 11) /* */
+#define I2C_INTST_ISTT                  (1 << 10)
+#define I2C_INTST_ISTP                  (1 << 9)
+#define I2C_INTST_IACT                  (1 << 8)
+#define I2C_INTST_RXDN                  (1 << 7)
+#define I2C_INTST_TXABT                 (1 << 6) 
+#define I2C_INTST_RDREQ                 (1 << 5)
+#define I2C_INTST_TXEMP                 (1 << 4)
+#define I2C_INTST_TXOF                  (1 << 3)
+#define I2C_INTST_RXFL                  (1 << 2)
+#define I2C_INTST_RXOF                  (1 << 1)
+#define I2C_INTST_RXUF                  (1 << 0)
+
+/* i2c interrupt mask status (I2C_INTM) */
+
+#define I2C_INTM_MIGC                   (1 << 11) /* */
+#define I2C_INTM_MISTT                  (1 << 10)
+#define I2C_INTM_MISTP                  (1 << 9)
+#define I2C_INTM_MIACT                  (1 << 8)
+#define I2C_INTM_MRXDN                  (1 << 7)
+#define I2C_INTM_MTXABT                 (1 << 6)
+#define I2C_INTM_MRDREQ                 (1 << 5)
+#define I2C_INTM_MTXEMP                 (1 << 4)
+#define I2C_INTM_MTXOF                  (1 << 3)
+#define I2C_INTM_MRXFL                  (1 << 2)
+#define I2C_INTM_MRXOF                  (1 << 1)
+#define I2C_INTM_MRXUF                  (1 << 0)
+
+/* I2C Clear Combined and Individual Interrupts (I2C_CINTR) */
+
+#define I2C_CINTR_CINT                  (1 << 0)
+
+/* I2C Clear TX_OVER Interrupt */
+/* I2C Clear RDREQ Interrupt */
+/* I2C Clear TX_ABRT Interrupt */
+/* I2C Clear RX_DONE Interrupt */
+/* I2C Clear ACTIVITY Interrupt */
+/* I2C Clear STOP Interrupts */
+/* I2C Clear START Interrupts */
+/* I2C Clear GEN_CALL Interrupts */
+
+/* I2C Enable (I2C_ENB) */
+
+#define I2C_ENB_I2CENB          (1 << 0) /* Enable the i2c */   
+
+/* I2C Status Register (I2C_STA) */
+
+#define I2C_STA_SLVACT          (1 << 6) /* Slave FSM is not in IDLE state */
+#define I2C_STA_MSTACT          (1 << 5) /* Master FSM is not in IDLE state */
+#define I2C_STA_RFF             (1 << 4) /* RFIFO if full */
+#define I2C_STA_RFNE            (1 << 3) /* RFIFO is not empty */
+#define I2C_STA_TFE             (1 << 2) /* TFIFO is empty */
+#define I2C_STA_TFNF            (1 << 1) /* TFIFO is not full  */
+#define I2C_STA_ACT             (1 << 0) /* I2C Activity Status */
+
+/* I2C Transmit Abort Status Register (I2C_TXABRT) */
+
+#define I2C_TXABRT_SLVRD_INTX           (1 << 15)
+#define I2C_TXABRT_SLV_ARBLOST          (1 << 14)
+#define I2C_TXABRT_SLVFLUSH_TXFIFO      (1 << 13)
+#define I2C_TXABRT_ARB_LOST             (1 << 12)
+#define I2C_TXABRT_ABRT_MASTER_DIS      (1 << 11)
+#define I2C_TXABRT_ABRT_10B_RD_NORSTRT  (1 << 10)
+#define I2C_TXABRT_SBYTE_NORSTRT        (1 << 9)
+#define I2C_TXABRT_ABRT_HS_NORSTRT      (1 << 8)
+#define I2C_TXABRT_SBYTE_ACKDET         (1 << 7)
+#define I2C_TXABRT_ABRT_HS_ACKD         (1 << 6)
+#define I2C_TXABRT_ABRT_GCALL_READ      (1 << 5)
+#define I2C_TXABRT_ABRT_GCALL_NOACK     (1 << 4)
+#define I2C_TXABRT_ABRT_XDATA_NOACK     (1 << 3)
+#define I2C_TXABRT_ABRT_10ADDR2_NOACK   (1 << 2)
+#define I2C_TXABRT_ABRT_10ADDR1_NOACK   (1 << 1)
+#define I2C_TXABRT_ABRT_7B_ADDR_NOACK   (1 << 0)
+
+/* */
+#define I2C_DMACR_TDEN                  (1 << 1)
+#define I2C_DMACR_RDEN                  (1 << 0)
+
+/* */
+#define I2C_DMATDLR_TDLR_BIT            0
+#define I2C_DMATDLR_TDLR_MASK           (0x1f << I2C_DMATDLR_TDLR_BIT)
+
+/* */
+#define I2C_DMARDLR_RDLR_BIT            0
+#define I2C_DMARDLR_RDLR_MASK           (0x1f << I2C_DMARDLR_RDLR_BIT)
+
+/* I2C Enable Status Register (I2C_ENSTA) */
+
+#define I2C_ENSTA_SLVRDLST              (1 << 2)
+#define I2C_ENSTA_SLVDISB               (1 << 1)
+#define I2C_ENSTA_I2CEN                 (1 << 0) /* when read as 1, i2c is deemed to be in an enabled state
+                                                    when read as 0, i2c is deemed completely inactive. The cpu can 
+                                                 safely read this bit anytime .When this bit is read as 0 ,the cpu can 
+                                                 safely read SLVRDLST and SLVDISB */
+
+/* I2C standard mode high count register(I2CSHCNT) */
+#define I2CSHCNT_ADJUST(n)      (((n) - 8) < 6 ? 6 : ((n) - 8))
+
+/* I2C standard mode low count register(I2CSLCNT) */
+#define I2CSLCNT_ADJUST(n)      (((n) - 1) < 8 ? 8 : ((n) - 1))
+
+/* I2C fast mode high count register(I2CFHCNT) */
+#define I2CFHCNT_ADJUST(n)      (((n) - 8) < 6 ? 6 : ((n) - 8))
+
+/* I2C fast mode low count register(I2CFLCNT) */
+#define I2CFLCNT_ADJUST(n)      (((n) - 1) < 8 ? 8 : ((n) - 1))
+
+#ifndef __MIPS_ASSEMBLER
+
+/***************************************************************************
+ * I2C
+ ***************************************************************************/
+
+#define __i2c_enable(n)         ( REG_I2C_ENB(n) = 1 )
+#define __i2c_disable(n)        ( REG_I2C_ENB(n) = 0 )
+
+#define __i2c_is_enable(n)       ( REG_I2C_ENSTA(n) & I2C_ENB_I2CENB )
+#define __i2c_is_disable(n)      ( !(REG_I2C_ENSTA(n) & I2C_ENB_I2CENB) )
+
+#define __i2c_abrt(n)            ( REG_I2C_TXABRT(n) != 0 )
+#define __i2c_abrt_intr(n)       (REG_I2C_INTST(n) & I2C_INTST_TXABT)
+#define __i2c_master_active(n)   ( REG_I2C_STA(n) & I2C_STA_MSTACT )
+#define __i2c_abrt_7b_addr_nack(n)  ( REG_I2C_TXABRT(n) & I2C_TXABRT_ABRT_7B_ADDR_NOACK )
+#define __i2c_txfifo_is_empty(n)     ( REG_I2C_STA(n) & I2C_STA_TFE )
+#define __i2c_clear_interrupts(ret,n)    ( ret = REG_I2C_CINTR(n) )
+
+#define __i2c_dma_rd_enable(n)        SETREG8(I2C_DMACR(n),1 << 0)
+#define __i2c_dma_rd_disable(n)       CLRREG8(I2C_DMACR(n),1 << 0)
+#define __i2c_dma_td_enable(n)        SETREG8(I2C_DMACR(n),1 << 1)
+#define __i2c_dma_td_disable(n)       CLRREG8(I2C_DMACR(n),1 << 1)
+
+#define __i2c_send_stop(n)           CLRREG8(I2C_CTRL(n), I2C_CTRL_STPHLD)
+#define __i2c_nsend_stop(n)          SETREG8(I2C_CTRL(n), I2C_CTRL_STPHLD)
+
+#define __i2c_set_dma_td_level(n,data) OUTREG8(I2C_DMATDLR(n),data)
+#define __i2c_set_dma_rd_level(n,data) OUTREG8(I2C_DMARDLR(n),data)   
+
+/*
+#define __i2c_set_clk(dev_clk, i2c_clk) \
+  ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
+*/
+
+#define __i2c_read(n)           ( REG_I2C_DC(n) & 0xff )
+#define __i2c_write(val,n)      ( REG_I2C_DC(n) = (val) )
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define IPU_BASE        0xB3080000
+
+/*************************************************************************
+ * IPU (Image Processing Unit)
+ *************************************************************************/
+#define IPU_V_BASE              0xB3080000
+#define IPU_P_BASE              0x13080000
+
+/* Register offset */
+#define REG_CTRL                0x0  /* IPU Control Register */
+#define REG_STATUS              0x4  /* IPU Status Register */
+#define REG_D_FMT               0x8  /* Data Format Register */
+#define REG_Y_ADDR              0xc  /* Input Y or YUV422 Packaged Data Address Register */
+#define REG_U_ADDR              0x10 /* Input U Data Address Register */
+#define REG_V_ADDR              0x14 /* Input V Data Address Register */
+#define REG_IN_FM_GS            0x18 /* Input Geometric Size Register */
+#define REG_Y_STRIDE            0x1c /* Input Y Data Line Stride Register */
+#define REG_UV_STRIDE           0x20 /* Input UV Data Line Stride Register */
+#define REG_OUT_ADDR            0x24 /* Output Frame Start Address Register */
+#define REG_OUT_GS              0x28 /* Output Geometric Size Register */
+#define REG_OUT_STRIDE          0x2c /* Output Data Line Stride Register */
+#define REG_RSZ_COEF_INDEX      0x30 /* Resize Coefficients Table Index Register */
+#define REG_CSC_CO_COEF         0x34 /* CSC C0 Coefficient Register */
+#define REG_CSC_C1_COEF         0x38 /* CSC C1 Coefficient Register */
+#define REG_CSC_C2_COEF         0x3c /* CSC C2 Coefficient Register */
+#define REG_CSC_C3_COEF         0x40 /* CSC C3 Coefficient Register */
+#define REG_CSC_C4_COEF         0x44 /* CSC C4 Coefficient Register */
+#define HRSZ_LUT_BASE           0x48 /* Horizontal Resize Coefficients Look Up Table Register group */
+#define VRSZ_LUT_BASE           0x4c /* Virtical Resize Coefficients Look Up Table Register group */
+#define REG_CSC_OFSET_PARA      0x50 /* CSC Offset Parameter Register */
+#define REG_Y_PHY_T_ADDR        0x54 /* Input Y Physical Table Address Register */
+#define REG_U_PHY_T_ADDR        0x58 /* Input U Physical Table Address Register */
+#define REG_V_PHY_T_ADDR        0x5c /* Input V Physical Table Address Register */
+#define REG_OUT_PHY_T_ADDR      0x60 /* Output Physical Table Address Register */
+
+/* REG_CTRL: IPU Control Register */
+#define IPU_CE_SFT      0x0
+#define IPU_CE_MSK      0x1
+#define IPU_RUN_SFT     0x1
+#define IPU_RUN_MSK     0x1
+#define HRSZ_EN_SFT     0x2
+#define HRSZ_EN_MSK     0x1
+#define VRSZ_EN_SFT     0x3
+#define VRSZ_EN_MSK     0x1
+#define CSC_EN_SFT      0x4
+#define CSC_EN_MSK      0x1
+#define FM_IRQ_EN_SFT   0x5
+#define FM_IRQ_EN_MSK   0x1
+#define IPU_RST_SFT     0x6
+#define IPU_RST_MSK     0x1
+#define H_SCALE_SFT     0x8
+#define H_SCALE_MSK     0x1
+#define V_SCALE_SFT     0x9
+#define V_SCALE_MSK     0x1
+#define PKG_SEL_SFT     0xA
+#define PKG_SEL_MSK     0x1
+#define LCDC_SEL_SFT    0xB
+#define LCDC_SEL_MSK    0x1
+#define SPAGE_MAP_SFT   0xC
+#define SPAGE_MAP_MSK   0x1
+#define DPAGE_SEL_SFT   0xD
+#define DPAGE_SEL_MSK   0x1
+#define DISP_SEL_SFT    0xE
+#define DISP_SEL_MSK    0x1
+#define FIELD_CONF_EN_SFT 15
+#define FIELD_CONF_EN_MSK 1
+#define FIELD_SEL_SFT   16
+#define FIELD_SEL_MSK   1
+#define DFIX_SEL_SFT    17
+#define DFIX_SEL_MSK    1
+
+/* REG_STATUS: IPU Status Register */
+#define OUT_END_SFT     0x0
+#define OUT_END_MSK     0x1
+#define FMT_ERR_SFT     0x1
+#define FMT_ERR_MSK     0x1
+#define SIZE_ERR_SFT    0x2
+#define SIZE_ERR_MSK    0x1
+
+/* D_FMT: Data Format Register */
+#define IN_FMT_SFT      0x0
+#define IN_FMT_MSK      0x3
+#define IN_OFT_SFT      0x2
+#define IN_OFT_MSK      0x3
+#define YUV_PKG_OUT_SFT 0x10
+#define YUV_PKG_OUT_MSK 0x7
+#define OUT_FMT_SFT     0x13
+#define OUT_FMT_MSK     0x3
+#define RGB_OUT_OFT_SFT 0x15
+#define RGB_OUT_OFT_MSK 0x7
+#define RGB888_FMT_SFT  0x18
+#define RGB888_FMT_MSK  0x1
+
+/* IN_FM_GS: Input Geometric Size Register */
+#define IN_FM_H_SFT     0x0
+#define IN_FM_H_MSK     0xFFF
+#define IN_FM_W_SFT     0x10
+#define IN_FM_W_MSK     0xFFF
+
+/* Y_STRIDE: Input Y Data Line Stride Register */
+#define Y_S_SFT         0x0
+#define Y_S_MSK         0x3FFF
+
+/* UV_STRIDE: Input UV Data Line Stride Register */
+#define V_S_SFT         0x0
+#define V_S_MSK         0x1FFF
+#define U_S_SFT         0x10
+#define U_S_MSK         0x1FFF
+
+/* OUT_GS: Output Geometric Size Register */
+#define OUT_FM_H_SFT    0x0
+#define OUT_FM_H_MSK    0x1FFF
+#define OUT_FM_W_SFT    0x10
+#define OUT_FM_W_MSK    0x7FFF
+
+/* OUT_STRIDE: Output Data Line Stride Register */
+#define OUT_S_SFT       0x0
+#define OUT_S_MSK       0xFFFF
+
+/* RSZ_COEF_INDEX: Resize Coefficients Table Index Register */
+#define VE_IDX_SFT      0x0
+#define VE_IDX_MSK      0x1F
+#define HE_IDX_SFT      0x10
+#define HE_IDX_MSK      0x1F
+
+/* CSC_CX_COEF: CSC CX Coefficient Register */
+#define CX_COEF_SFT     0x0
+#define CX_COEF_MSK     0xFFF
+
+/* HRSZ_LUT_BASE, VRSZ_LUT_BASE: Resize Coefficients Look Up Table Register group */
+#define LUT_LEN         20
+
+#define OUT_N_SFT       0x0
+#define OUT_N_MSK       0x1
+#define IN_N_SFT        0x1
+#define IN_N_MSK        0x1
+#define W_COEF_SFT      0x2
+#define W_COEF_MSK      0x3FF
+
+/* CSC_OFSET_PARA: CSC Offset Parameter Register */
+#define CHROM_OF_SFT    0x10
+#define CHROM_OF_MSK    0xFF
+#define LUMA_OF_SFT     0x00
+#define LUMA_OF_MSK     0xFF
+
+#ifndef __MIPS_ASSEMBLER
+
+#if 0
+/*************************************************************************
+ * IPU (Image Processing Unit)
+ *************************************************************************/
+#define u32 volatile unsigned long
+
+#define write_reg(reg, val)     \
+do {                            \
+        *(u32 *)(reg) = (val);  \
+} while(0)
+
+#define read_reg(reg, off)      (*(u32 *)((reg)+(off)))
+
+#define set_ipu_fmt(rgb_888_out_fmt, rgb_out_oft, out_fmt, yuv_pkg_out, in_oft, in_fmt ) \
+({ write_reg( (IPU_V_BASE + REG_D_FMT), ((in_fmt) & IN_FMT_MSK)<<IN_FMT_SFT \
+| ((in_oft) & IN_OFT_MSK)<< IN_OFT_SFT \
+| ((out_fmt) & OUT_FMT_MSK)<<OUT_FMT_SFT \
+| ((yuv_pkg_out) & YUV_PKG_OUT_MSK ) << YUV_PKG_OUT_SFT \
+| ((rgb_888_out_fmt) & RGB888_FMT_MSK ) << RGB888_FMT_SFT \
+| ((rgb_out_oft) & RGB_OUT_OFT_MSK ) << RGB_OUT_OFT_SFT); \
+})
+#define set_y_addr(y_addr) \
+({ write_reg( (IPU_V_BASE + REG_Y_ADDR), y_addr); \
+})
+#define set_u_addr(u_addr) \
+({ write_reg( (IPU_V_BASE + REG_U_ADDR), u_addr); \
+})
+
+#define set_v_addr(v_addr) \
+({ write_reg( (IPU_V_BASE + REG_V_ADDR), v_addr); \
+})
+
+#define set_y_phy_t_addr(y_phy_t_addr) \
+({ write_reg( (IPU_V_BASE + REG_Y_PHY_T_ADDR), y_phy_t_addr); \
+})
+
+#define set_u_phy_t_addr(u_phy_t_addr) \
+({ write_reg( (IPU_V_BASE + REG_U_PHY_T_ADDR), u_phy_t_addr); \
+})
+
+#define set_v_phy_t_addr(v_phy_t_addr) \
+({ write_reg( (IPU_V_BASE + REG_V_PHY_T_ADDR), v_phy_t_addr); \
+})
+
+#define set_out_phy_t_addr(out_phy_t_addr) \
+({ write_reg( (IPU_V_BASE + REG_OUT_PHY_T_ADDR), out_phy_t_addr); \
+})
+
+#define set_inframe_gsize(width, height, y_stride, u_stride, v_stride) \
+({ write_reg( (IPU_V_BASE + REG_IN_FM_GS), ((width) & IN_FM_W_MSK)<<IN_FM_W_SFT \
+| ((height) & IN_FM_H_MSK)<<IN_FM_H_SFT); \
+ write_reg( (IPU_V_BASE + REG_Y_STRIDE), ((y_stride) & Y_S_MSK)<<Y_S_SFT); \
+ write_reg( (IPU_V_BASE + REG_UV_STRIDE), ((u_stride) & U_S_MSK)<<U_S_SFT \
+| ((v_stride) & V_S_MSK)<<V_S_SFT); \
+})
+#define set_out_addr(out_addr) \
+({ write_reg( (IPU_V_BASE + REG_OUT_ADDR), out_addr); \
+})
+#define set_outframe_gsize(width, height, o_stride) \
+({ write_reg( (IPU_V_BASE + REG_OUT_GS), ((width) & OUT_FM_W_MSK)<<OUT_FM_W_SFT \
+| ((height) & OUT_FM_H_MSK)<<OUT_FM_H_SFT); \
+ write_reg( (IPU_V_BASE + REG_OUT_STRIDE), ((o_stride) & OUT_S_MSK)<<OUT_S_SFT); \
+})
+#define set_rsz_lut_end(h_end, v_end) \
+({ write_reg( (IPU_V_BASE + REG_RSZ_COEF_INDEX), ((h_end) & HE_IDX_MSK)<<HE_IDX_SFT \
+| ((v_end) & VE_IDX_MSK)<<VE_IDX_SFT); \
+})
+#define set_csc_c0(c0_coeff) \
+({ write_reg( (IPU_V_BASE + REG_CSC_CO_COEF), ((c0_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \
+})
+#define set_csc_c1(c1_coeff) \
+({ write_reg( (IPU_V_BASE + REG_CSC_C1_COEF), ((c1_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \
+})
+#define set_csc_c2(c2_coeff) \
+({ write_reg( (IPU_V_BASE + REG_CSC_C2_COEF), ((c2_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \
+})
+#define set_csc_c3(c3_coeff) \
+({ write_reg( (IPU_V_BASE + REG_CSC_C3_COEF), ((c3_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \
+})
+#define set_csc_c4(c4_coeff) \
+({ write_reg( (IPU_V_BASE + REG_CSC_C4_COEF), ((c4_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \
+})
+#define set_hrsz_lut_coef(coef, in_n, out_n) \
+({ write_reg( (IPU_V_BASE + HRSZ_LUT_BASE ), ((coef) & W_COEF_MSK)<<W_COEF_SFT \
+| ((in_n) & IN_N_MSK)<<IN_N_SFT | ((out_n) & OUT_N_MSK)<<OUT_N_SFT); \
+})
+#define set_vrsz_lut_coef(coef, in_n, out_n) \
+({ write_reg( (IPU_V_BASE + VRSZ_LUT_BASE), ((coef) & W_COEF_MSK)<<W_COEF_SFT \
+| ((in_n) & IN_N_MSK)<<IN_N_SFT | ((out_n) & OUT_N_MSK)<<OUT_N_SFT); \
+})
+
+#define set_primary_ctrl(vrsz_en, hrsz_en,csc_en, irq_en) \
+({ write_reg( (IPU_V_BASE + REG_CTRL), ((irq_en) & FM_IRQ_EN_MSK)<<FM_IRQ_EN_SFT \
+| ((vrsz_en) & VRSZ_EN_MSK)<<VRSZ_EN_SFT \
+| ((hrsz_en) & HRSZ_EN_MSK)<<HRSZ_EN_SFT \
+| ((csc_en) & CSC_EN_MSK)<<CSC_EN_SFT \
+| (read_reg(IPU_V_BASE, REG_CTRL)) \
+& ~(CSC_EN_MSK<<CSC_EN_SFT | FM_IRQ_EN_MSK<<FM_IRQ_EN_SFT | VRSZ_EN_MSK<<VRSZ_EN_SFT | HRSZ_EN_MSK<<HRSZ_EN_SFT ) ); \
+})
+
+#define set_source_ctrl(pkg_sel, spage_sel) \
+({ write_reg( (IPU_V_BASE + REG_CTRL), ((pkg_sel) & PKG_SEL_MSK  )<< PKG_SEL_SFT \
+| ((spage_sel) & SPAGE_MAP_MSK )<< SPAGE_MAP_SFT \
+| (read_reg(IPU_V_BASE, REG_CTRL)) \
+& ~(SPAGE_MAP_MSK << SPAGE_MAP_SFT | PKG_SEL_MSK << PKG_SEL_SFT ) ) ; \
+})
+
+#define set_out_ctrl(lcdc_sel, dpage_sel, disp_sel) \
+({ write_reg( (IPU_V_BASE + REG_CTRL), ((lcdc_sel) & LCDC_SEL_MSK  )<< LCDC_SEL_SFT \
+| ((dpage_sel) & DPAGE_SEL_MSK )<< DPAGE_SEL_SFT \
+| ((disp_sel) & DISP_SEL_MSK )<< DISP_SEL_SFT \
+| (read_reg(IPU_V_BASE, REG_CTRL)) \
+& ~(LCDC_SEL_MSK<< LCDC_SEL_SFT | DPAGE_SEL_MSK << DPAGE_SEL_SFT | DISP_SEL_MSK << DISP_SEL_SFT ) ); \
+})
+
+#define set_scale_ctrl(v_scal, h_scal) \
+({ write_reg( (IPU_V_BASE + REG_CTRL), ((v_scal) & V_SCALE_MSK)<<V_SCALE_SFT \
+| ((h_scal) & H_SCALE_MSK)<<H_SCALE_SFT \
+| (read_reg(IPU_V_BASE, REG_CTRL)) & ~(V_SCALE_MSK<<V_SCALE_SFT | H_SCALE_MSK<<H_SCALE_SFT ) ); \
+})
+
+#define set_csc_ofset_para(chrom_oft, luma_oft) \
+({ write_reg( (IPU_V_BASE + REG_CSC_OFSET_PARA ), ((chrom_oft) & CHROM_OF_MSK ) << CHROM_OF_SFT \
+| ((luma_oft) & LUMA_OF_MSK ) << LUMA_OF_SFT ) ; \
+})
+
+#define sw_reset_ipu() \
+({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) \
+| IPU_RST_MSK<<IPU_RST_SFT); \
+})
+#define enable_ipu() \
+({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) | 0x1); \
+})
+#define disable_ipu() \
+({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) & ~0x1); \
+})
+#define run_ipu() \
+({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) | 0x2); \
+})
+#define stop_ipu() \
+({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) & ~0x2); \
+})
+
+#define polling_end_flag() \
+({ (read_reg(IPU_V_BASE, REG_STATUS)) & 0x01; \
+})
+
+#define start_vlut_coef_write() \
+({ write_reg( (IPU_V_BASE + VRSZ_LUT_BASE), ( 0x1<<12 ) ); \
+})
+
+#define start_hlut_coef_write() \
+({ write_reg( (IPU_V_BASE + HRSZ_LUT_BASE), ( 0x01<<12 ) ); \
+})
+
+#define clear_end_flag() \
+({ write_reg( (IPU_V_BASE + REG_STATUS), 0); \
+})
+#endif /* #if 0 */
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define LCD_BASE        0xB3050000
+#define SLCD_BASE       0xB3050000
+
+/*************************************************************************
+ * SLCD (Smart LCD Controller)
+ *************************************************************************/
+
+#define SLCD_CFG        (SLCD_BASE + 0xA0)  /* SLCD Configure Register */
+#define SLCD_CTRL       (SLCD_BASE + 0xA4)  /* SLCD Control Register */
+#define SLCD_STATE      (SLCD_BASE + 0xA8)  /* SLCD Status Register */
+#define SLCD_DATA       (SLCD_BASE + 0xAC)  /* SLCD Data Register */
+
+#define REG_SLCD_CFG    REG32(SLCD_CFG)
+#define REG_SLCD_CTRL   REG8(SLCD_CTRL)
+#define REG_SLCD_STATE  REG8(SLCD_STATE)
+#define REG_SLCD_DATA   REG32(SLCD_DATA)
+
+/* SLCD Configure Register */
+#define SLCD_CFG_DWIDTH_BIT     10
+#define SLCD_CFG_DWIDTH_MASK    (0x7 << SLCD_CFG_DWIDTH_BIT)
+  #define SLCD_CFG_DWIDTH_18BIT (0 << SLCD_CFG_DWIDTH_BIT)
+  #define SLCD_CFG_DWIDTH_16BIT (1 << SLCD_CFG_DWIDTH_BIT)
+  #define SLCD_CFG_DWIDTH_8BIT_x3       (2 << SLCD_CFG_DWIDTH_BIT)
+  #define SLCD_CFG_DWIDTH_8BIT_x2       (3 << SLCD_CFG_DWIDTH_BIT)
+  #define SLCD_CFG_DWIDTH_8BIT_x1       (4 << SLCD_CFG_DWIDTH_BIT)
+  #define SLCD_CFG_DWIDTH_24BIT (5 << SLCD_CFG_DWIDTH_BIT)
+  #define SLCD_CFG_DWIDTH_9BIT_x2       (7 << SLCD_CFG_DWIDTH_BIT)
+#define SLCD_CFG_CWIDTH_BIT     (8)
+#define SLCD_CFG_CWIDTH_MASK    (0x3 << SLCD_CFG_CWIDTH_BIT)
+#define SLCD_CFG_CWIDTH_16BIT   (0 << SLCD_CFG_CWIDTH_BIT)
+#define SLCD_CFG_CWIDTH_8BIT    (1 << SLCD_CFG_CWIDTH_BIT)
+#define SLCD_CFG_CWIDTH_18BIT   (2 << SLCD_CFG_CWIDTH_BIT)
+#define SLCD_CFG_CWIDTH_24BIT   (3 << SLCD_CFG_CWIDTH_BIT)
+#define SLCD_CFG_CS_ACTIVE_LOW  (0 << 4)
+#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
+#define SLCD_CFG_RS_CMD_LOW     (0 << 3)
+#define SLCD_CFG_RS_CMD_HIGH    (1 << 3)
+#define SLCD_CFG_CLK_ACTIVE_FALLING     (0 << 1)
+#define SLCD_CFG_CLK_ACTIVE_RISING      (1 << 1)
+#define SLCD_CFG_TYPE_PARALLEL  (0 << 0)
+#define SLCD_CFG_TYPE_SERIAL    (1 << 0)
+
+/* SLCD Control Register */
+#define SLCD_CTRL_DMA_MODE      (1 << 2)
+#define SLCD_CTRL_DMA_START     (1 << 1)
+#define SLCD_CTRL_DMA_EN        (1 << 0)
+
+/* SLCD Status Register */
+#define SLCD_STATE_BUSY         (1 << 0)
+
+/* SLCD Data Register */
+#define SLCD_DATA_RS_DATA       (0 << 31)
+#define SLCD_DATA_RS_COMMAND    (1 << 31)
+
+/*************************************************************************
+ * LCD (LCD Controller)
+ *************************************************************************/
+#define LCD_CFG         (LCD_BASE + 0x00) /* LCD Configure Register */
+#define LCD_CTRL        (LCD_BASE + 0x30) /* LCD Control Register */
+#define LCD_STATE       (LCD_BASE + 0x34) /* LCD Status Register */
+
+#define LCD_OSDC        (LCD_BASE + 0x100) /* LCD OSD Configure Register */
+#define LCD_OSDCTRL     (LCD_BASE + 0x104) /* LCD OSD Control Register */
+#define LCD_OSDS        (LCD_BASE + 0x108) /* LCD OSD Status Register */
+#define LCD_BGC         (LCD_BASE + 0x10C) /* LCD Background Color Register */
+#define LCD_KEY0        (LCD_BASE + 0x110) /* LCD Foreground Color Key Register 0 */
+#define LCD_KEY1        (LCD_BASE + 0x114) /* LCD Foreground Color Key Register 1 */
+#define LCD_ALPHA       (LCD_BASE + 0x118) /* LCD ALPHA Register */
+#define LCD_IPUR        (LCD_BASE + 0x11C) /* LCD IPU Restart Register */
+#define LCD_RGBC        (LCD_BASE + 0x90) /* RGB Controll Register */
+
+#define LCD_VAT         (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
+#define LCD_DAH         (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
+#define LCD_DAV         (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
+
+#define LCD_XYP0        (LCD_BASE + 0x120) /* Foreground 0 XY Position Register */
+#define LCD_XYP0_PART2  (LCD_BASE + 0x1F0) /* Foreground 0 PART2 XY Position Register */
+#define LCD_XYP1        (LCD_BASE + 0x124) /* Foreground 1 XY Position Register */
+#define LCD_SIZE0       (LCD_BASE + 0x128) /* Foreground 0 Size Register */
+#define LCD_SIZE0_PART2 (LCD_BASE + 0x1F4) /*Foreground 0 PART2 Size Register */
+#define LCD_SIZE1       (LCD_BASE + 0x12C) /* Foreground 1 Size Register */
+
+#define LCD_VSYNC       (LCD_BASE + 0x04) /* Vertical Synchronize Register */
+#define LCD_HSYNC       (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
+#define LCD_PS          (LCD_BASE + 0x18) /* PS Signal Setting */
+#define LCD_CLS         (LCD_BASE + 0x1c) /* CLS Signal Setting */
+#define LCD_SPL         (LCD_BASE + 0x20) /* SPL Signal Setting */
+#define LCD_REV         (LCD_BASE + 0x24) /* REV Signal Setting */
+#define LCD_IID         (LCD_BASE + 0x38) /* Interrupt ID Register */
+#define LCD_DA0         (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
+#define LCD_SA0         (LCD_BASE + 0x44) /* Source Address Register 0 */
+#define LCD_FID0        (LCD_BASE + 0x48) /* Frame ID Register 0 */
+#define LCD_CMD0        (LCD_BASE + 0x4c) /* DMA Command Register 0 */
+
+#define LCD_OFFS0       (LCD_BASE + 0x60) /* DMA Offsize Register 0 */
+#define LCD_PW0         (LCD_BASE + 0x64) /* DMA Page Width Register 0 */
+#define LCD_CNUM0       (LCD_BASE + 0x68) /* DMA Command Counter Register 0 */
+#define LCD_DESSIZE0    (LCD_BASE + 0x6C) /* Foreground Size in Descriptor 0 Register*/
+
+#define LCD_DA1         (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
+#define LCD_SA1         (LCD_BASE + 0x54) /* Source Address Register 1 */
+#define LCD_FID1        (LCD_BASE + 0x58) /* Frame ID Register 1 */
+#define LCD_CMD1        (LCD_BASE + 0x5c) /* DMA Command Register 1 */
+#define LCD_OFFS1       (LCD_BASE + 0x70) /* DMA Offsize Register 1 */
+#define LCD_PW1         (LCD_BASE + 0x74) /* DMA Page Width Register 1 */
+#define LCD_CNUM1       (LCD_BASE + 0x78) /* DMA Command Counter Register 1 */
+#define LCD_DESSIZE1    (LCD_BASE + 0x7C) /* Foreground Size in Descriptor 1 Register*/
+
+#define LCD_DA0_PART2   (LCD_BASE + 0x1C0) /* Descriptor Address Register PART2 */
+#define LCD_SA0_PART2   (LCD_BASE + 0x1C4) /* Source Address Register PART2 */
+#define LCD_FID0_PART2  (LCD_BASE + 0x1C8) /* Frame ID Register PART2 */
+#define LCD_CMD0_PART2  (LCD_BASE + 0x1CC) /* DMA Command Register PART2 */
+#define LCD_OFFS0_PART2 (LCD_BASE + 0x1E0) /* DMA Offsize Register PART2 */
+#define LCD_PW0_PART2   (LCD_BASE + 0x1E4) /* DMA Command Counter Register PART2 */
+#define LCD_CNUM0_PART2 (LCD_BASE + 0x1E8) /* Foreground Size in Descriptor PART2 Register */
+#define LCD_DESSIZE0_PART2      (LCD_BASE + 0x1EC) /*  */
+#define LCD_PCFG        (LCD_BASE + 0x2C0)
+
+#define REG_LCD_CFG     REG32(LCD_CFG)
+#define REG_LCD_CTRL    REG32(LCD_CTRL)
+#define REG_LCD_STATE   REG32(LCD_STATE)
+
+#define REG_LCD_OSDC    REG16(LCD_OSDC)
+#define REG_LCD_OSDCTRL REG16(LCD_OSDCTRL)
+#define REG_LCD_OSDS    REG16(LCD_OSDS)
+#define REG_LCD_BGC     REG32(LCD_BGC)
+#define REG_LCD_KEY0    REG32(LCD_KEY0)
+#define REG_LCD_KEY1    REG32(LCD_KEY1)
+#define REG_LCD_ALPHA   REG8(LCD_ALPHA)
+#define REG_LCD_IPUR    REG32(LCD_IPUR)
+
+#define REG_LCD_VAT     REG32(LCD_VAT)
+#define REG_LCD_DAH     REG32(LCD_DAH)
+#define REG_LCD_DAV     REG32(LCD_DAV)
+
+#define REG_LCD_XYP0            REG32(LCD_XYP0)
+#define REG_LCD_XYP0_PART2      REG32(LCD_XYP0_PART2)
+#define REG_LCD_XYP1            REG32(LCD_XYP1)
+#define REG_LCD_SIZE0           REG32(LCD_SIZE0)
+#define REG_LCD_SIZE0_PART2     REG32(LCD_SIZE0_PART2)
+#define REG_LCD_SIZE1           REG32(LCD_SIZE1)
+                        
+#define REG_LCD_RGBC            REG16(LCD_RGBC)
+                        
+#define REG_LCD_VSYNC           REG32(LCD_VSYNC)
+#define REG_LCD_HSYNC           REG32(LCD_HSYNC)
+#define REG_LCD_PS              REG32(LCD_PS)
+#define REG_LCD_CLS             REG32(LCD_CLS)
+#define REG_LCD_SPL             REG32(LCD_SPL)
+#define REG_LCD_REV             REG32(LCD_REV)
+#define REG_LCD_IID             REG32(LCD_IID)
+#define REG_LCD_DA0             REG32(LCD_DA0)
+#define REG_LCD_SA0             REG32(LCD_SA0)
+#define REG_LCD_FID0            REG32(LCD_FID0)
+#define REG_LCD_CMD0            REG32(LCD_CMD0)
+
+#define REG_LCD_OFFS0           REG32(LCD_OFFS0)
+#define REG_LCD_PW0             REG32(LCD_PW0)
+#define REG_LCD_CNUM0           REG32(LCD_CNUM0)
+#define REG_LCD_DESSIZE0        REG32(LCD_DESSIZE0)
+
+#define REG_LCD_DA0_PART2       REG32(LCD_DA0_PART2)
+#define REG_LCD_SA0_PART2       REG32(LCD_SA0_PART2)
+#define REG_LCD_FID0_PART2      REG32(LCD_FID0_PART2)
+#define REG_LCD_CMD0_PART2      REG32(LCD_CMD0_PART2)
+#define REG_LCD_OFFS0_PART2     REG32(LCD_OFFS0_PART2)
+#define REG_LCD_PW0_PART2       REG32(LCD_PW0_PART2)
+#define REG_LCD_CNUM0_PART2     REG32(LCD_CNUM0_PART2)
+#define REG_LCD_DESSIZE0_PART2  REG32(LCD_DESSIZE0_PART2)
+
+#define REG_LCD_DA1             REG32(LCD_DA1)
+#define REG_LCD_SA1             REG32(LCD_SA1)
+#define REG_LCD_FID1            REG32(LCD_FID1)
+#define REG_LCD_CMD1            REG32(LCD_CMD1)
+#define REG_LCD_OFFS1           REG32(LCD_OFFS1)
+#define REG_LCD_PW1             REG32(LCD_PW1)
+#define REG_LCD_CNUM1           REG32(LCD_CNUM1)
+#define REG_LCD_DESSIZE1        REG32(LCD_DESSIZE1)
+#define REG_LCD_PCFG            REG32(LCD_PCFG)
+
+/* LCD Configure Register */
+#define LCD_CFG_LCDPIN_BIT      31  /* LCD pins selection */
+#define LCD_CFG_LCDPIN_MASK     (0x1 << LCD_CFG_LCDPIN_BIT)
+  #define LCD_CFG_LCDPIN_LCD    (0x0 << LCD_CFG_LCDPIN_BIT)
+  #define LCD_CFG_LCDPIN_SLCD   (0x1 << LCD_CFG_LCDPIN_BIT)
+#define LCD_CFG_TVEPEH          (1 << 30) /* TVE PAL enable extra halfline signal */
+//#define LCD_CFG_FUHOLD                (1 << 29) /* hold pixel clock when outFIFO underrun */
+#define LCD_CFG_NEWDES          (1 << 28) /* use new descripter. old: 4words, new:8words */
+#define LCD_CFG_PALBP           (1 << 27) /* bypass data format and alpha blending */
+#define LCD_CFG_TVEN            (1 << 26) /* indicate the terminal is lcd or tv */
+#define LCD_CFG_RECOVER         (1 << 25) /* Auto recover when output fifo underrun */
+#define LCD_CFG_DITHER          (1 << 24) /* Dither function */
+#define LCD_CFG_PSM             (1 << 23) /* PS signal mode */
+#define LCD_CFG_CLSM            (1 << 22) /* CLS signal mode */
+#define LCD_CFG_SPLM            (1 << 21) /* SPL signal mode */
+#define LCD_CFG_REVM            (1 << 20) /* REV signal mode */
+#define LCD_CFG_HSYNM           (1 << 19) /* HSYNC signal mode */
+#define LCD_CFG_PCLKM           (1 << 18) /* PCLK signal mode */
+#define LCD_CFG_INVDAT          (1 << 17) /* Inverse output data */
+#define LCD_CFG_SYNDIR_IN       (1 << 16) /* VSYNC&HSYNC direction */
+#define LCD_CFG_PSP             (1 << 15) /* PS pin reset state */
+#define LCD_CFG_CLSP            (1 << 14) /* CLS pin reset state */
+#define LCD_CFG_SPLP            (1 << 13) /* SPL pin reset state */
+#define LCD_CFG_REVP            (1 << 12) /* REV pin reset state */
+#define LCD_CFG_HSP             (1 << 11) /* HSYNC polarity:0-active high,1-active low */
+#define LCD_CFG_PCP             (1 << 10) /* PCLK polarity:0-rising,1-falling */
+#define LCD_CFG_DEP             (1 << 9)  /* DE polarity:0-active high,1-active low */
+#define LCD_CFG_VSP             (1 << 8)  /* VSYNC polarity:0-rising,1-falling */
+#define LCD_CFG_MODE_TFT_18BIT  (1 << 7)  /* 18bit TFT */
+#define LCD_CFG_MODE_TFT_16BIT  (0 << 7)  /* 16bit TFT */
+#define LCD_CFG_MODE_TFT_24BIT  (1 << 6)  /* 24bit TFT */
+#define LCD_CFG_PDW_BIT         4  /* STN pins utilization */
+#define LCD_CFG_PDW_MASK        (0x3 << LCD_CFG_PDW_BIT)
+#define LCD_CFG_PDW_1           (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
+  #define LCD_CFG_PDW_2         (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
+  #define LCD_CFG_PDW_4         (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
+  #define LCD_CFG_PDW_8         (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
+#define LCD_CFG_MODE_BIT        0  /* Display Device Mode Select */
+#define LCD_CFG_MODE_MASK       (0x0f << LCD_CFG_MODE_BIT)
+  #define LCD_CFG_MODE_GENERIC_TFT      (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
+  #define LCD_CFG_MODE_SPECIAL_TFT_1    (1 << LCD_CFG_MODE_BIT)
+  #define LCD_CFG_MODE_SPECIAL_TFT_2    (2 << LCD_CFG_MODE_BIT)
+  #define LCD_CFG_MODE_SPECIAL_TFT_3    (3 << LCD_CFG_MODE_BIT)
+  #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
+  #define LCD_CFG_MODE_INTER_CCIR656    (6 << LCD_CFG_MODE_BIT)
+  #define LCD_CFG_MODE_SINGLE_CSTN      (8 << LCD_CFG_MODE_BIT)
+  #define LCD_CFG_MODE_SINGLE_MSTN      (9 << LCD_CFG_MODE_BIT)
+  #define LCD_CFG_MODE_DUAL_CSTN        (10 << LCD_CFG_MODE_BIT)
+  #define LCD_CFG_MODE_DUAL_MSTN        (11 << LCD_CFG_MODE_BIT)
+  #define LCD_CFG_MODE_SERIAL_TFT       (12 << LCD_CFG_MODE_BIT)
+  #define LCD_CFG_MODE_LCM              (13 << LCD_CFG_MODE_BIT)
+  #define LCD_CFG_MODE_SLCD             LCD_CFG_MODE_LCM
+
+/* LCD Control Register */
+#define LCD_CTRL_PINMD          (1 << 31) /* This register set Pin distribution in 16-bit parallel mode
+                                            0: 16-bit data correspond with LCD_D[15:0]
+                                            1: 16-bit data correspond with LCD_D[17:10], LCD_D[8:1] */
+#define LCD_CTRL_BST_BIT        28  /* Burst Length Selection */
+#define LCD_CTRL_BST_MASK       (0x7 << LCD_CTRL_BST_BIT)
+  #define LCD_CTRL_BST_4        (0 << LCD_CTRL_BST_BIT) /* 4-word */
+  #define LCD_CTRL_BST_8        (1 << LCD_CTRL_BST_BIT) /* 8-word */
+  #define LCD_CTRL_BST_16       (2 << LCD_CTRL_BST_BIT) /* 16-word */
+  #define LCD_CTRL_BST_32       (3 << LCD_CTRL_BST_BIT) /* 32-word */
+  #define LCD_CTRL_BST_C16      (5 << LCD_CTRL_BST_BIT) /* 32-word */
+  #define LCD_CTRL_BST_64       (4 << LCD_CTRL_BST_BIT) /* 32-word */
+#define LCD_CTRL_RGB565         (0 << 27) /* RGB565 mode(foreground 0 in OSD mode) */
+#define LCD_CTRL_RGB555         (1 << 27) /* RGB555 mode(foreground 0 in OSD mode) */
+#define LCD_CTRL_OFUP           (1 << 26) /* Output FIFO underrun protection enable */
+#define LCD_CTRL_FRC_BIT        24  /* STN FRC Algorithm Selection */
+#define LCD_CTRL_FRC_MASK       (0x03 << LCD_CTRL_FRC_BIT)
+  #define LCD_CTRL_FRC_16       (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
+  #define LCD_CTRL_FRC_4        (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
+  #define LCD_CTRL_FRC_2        (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
+#define LCD_CTRL_PDD_BIT        16  /* Load Palette Delay Counter */
+#define LCD_CTRL_PDD_MASK       (0xff << LCD_CTRL_PDD_BIT)
+//#define LCD_CTRL_VGA          (1 << 15) /* VGA interface enable */
+#define LCD_CTRL_DACTE          (1 << 14) /* DAC loop back test */
+#define LCD_CTRL_EOFM           (1 << 13) /* EOF interrupt mask */
+#define LCD_CTRL_SOFM           (1 << 12) /* SOF interrupt mask */
+#define LCD_CTRL_OFUM           (1 << 11) /* Output FIFO underrun interrupt mask */
+#define LCD_CTRL_IFUM0          (1 << 10) /* Input FIFO 0 underrun interrupt mask */
+#define LCD_CTRL_IFUM1          (1 << 9)  /* Input FIFO 1 underrun interrupt mask */
+#define LCD_CTRL_LDDM           (1 << 8)  /* LCD disable done interrupt mask */
+#define LCD_CTRL_QDM            (1 << 7)  /* LCD quick disable done interrupt mask */
+#define LCD_CTRL_BEDN           (1 << 6)  /* Endian selection */
+#define LCD_CTRL_PEDN           (1 << 5)  /* Endian in byte:0-msb first, 1-lsb first */
+#define LCD_CTRL_DIS            (1 << 4)  /* Disable indicate bit */
+#define LCD_CTRL_ENA            (1 << 3)  /* LCD enable bit */
+#define LCD_CTRL_BPP_BIT        0  /* Bits Per Pixel */
+#define LCD_CTRL_BPP_MASK       (0x07 << LCD_CTRL_BPP_BIT)
+  #define LCD_CTRL_BPP_1        (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
+  #define LCD_CTRL_BPP_2        (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
+  #define LCD_CTRL_BPP_4        (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
+  #define LCD_CTRL_BPP_8        (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
+  #define LCD_CTRL_BPP_16       (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
+  #define LCD_CTRL_BPP_18_24    (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
+  #define LCD_CTRL_BPP_CMPS_24  (6 << LCD_CTRL_BPP_BIT) /* 24 compress bpp */
+  #define LCD_CTRL_BPP_30       (7 << LCD_CTRL_BPP_BIT) /* 30 bpp */
+
+/* LCD Status Register */
+#define LCD_STATE_QD            (1 << 7) /* Quick Disable Done */
+#define LCD_STATE_EOF           (1 << 5) /* EOF Flag */
+#define LCD_STATE_SOF           (1 << 4) /* SOF Flag */
+#define LCD_STATE_OFU           (1 << 3) /* Output FIFO Underrun */
+#define LCD_STATE_IFU0          (1 << 2) /* Input FIFO 0 Underrun */
+#define LCD_STATE_IFU1          (1 << 1) /* Input FIFO 1 Underrun */
+#define LCD_STATE_LDD           (1 << 0) /* LCD Disabled */
+
+/* OSD Configure Register */
+#define LCD_OSDC_SOFM1          (1 << 15) /* Start of frame interrupt mask for foreground 1 */
+#define LCD_OSDC_EOFM1          (1 << 14) /* End of frame interrupt mask for foreground 1 */
+#define LCD_OSDC_OSDIV          (1 << 12)
+#define LCD_OSDC_SOFM0          (1 << 11) /* Start of frame interrupt mask for foreground 0 */
+#define LCD_OSDC_EOFM0          (1 << 10) /* End of frame interrupt mask for foreground 0 */
+#if 0
+#define LCD_OSDC_ENDM           (1 << 9) /* End of frame interrupt mask for panel. */
+#define LCD_OSDC_F0DIVMD        (1 << 8) /* Divide Foreground 0 into 2 parts.
+                                          * 0: Foreground 0 only has one part. */
+#define LCD_OSDC_F0P1EN         (1 << 7) /* 1: Foreground 0 PART1 is enabled.
+                                          * 0: Foreground 0 PART1 is disabled. */
+#define LCD_OSDC_F0P2MD         (1 << 6) /* 1: PART 1&2 same level and same heighth
+                                          * 0: PART 1&2 have no same line */
+#define LCD_OSDC_F0P2EN         (1 << 5) /* 1: Foreground 0 PART2 is enabled.
+                                          * 0: Foreground 0 PART2 is disabled.*/
+#endif
+#define LCD_OSDC_F1EN           (1 << 4) /* enable foreground 1 */
+#define LCD_OSDC_F0EN           (1 << 3) /* enable foreground 0 */
+#define LCD_OSDC_ALPHAEN                (1 << 2) /* enable alpha blending */
+#define LCD_OSDC_ALPHAMD                (1 << 1) /* alpha blending mode */
+#define LCD_OSDC_OSDEN          (1 << 0) /* OSD mode enable */
+
+/* OSD Controll Register */
+#define LCD_OSDCTRL_IPU         (1 << 15) /* input data from IPU */
+#define LCD_OSDCTRL_RGB565      (0 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */
+#define LCD_OSDCTRL_RGB555      (1 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */
+#define LCD_OSDCTRL_CHANGES     (1 << 3) /* Change size flag */
+#define LCD_OSDCTRL_OSDBPP_BIT  0        /* Bits Per Pixel of OSD Channel 1 */
+#define LCD_OSDCTRL_OSDBPP_MASK (0x7<<LCD_OSDCTRL_OSDBPP_BIT)    /* Bits Per Pixel of OSD Channel 1's MASK */
+  #define LCD_OSDCTRL_OSDBPP_16 (4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/
+  #define LCD_OSDCTRL_OSDBPP_15_16      (4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/
+  #define LCD_OSDCTRL_OSDBPP_18_24      (5 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 18,24 bit*/
+  #define LCD_OSDCTRL_OSDBPP_CMPS_24    (6 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB compress 24 bit*/
+  #define LCD_OSDCTRL_OSDBPP_30         (7 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 30 bit*/
+
+/* OSD State Register */
+#define LCD_OSDS_SOF1           (1 << 15) /* Start of frame flag for foreground 1 */
+#define LCD_OSDS_EOF1           (1 << 14) /* End of frame flag for foreground 1 */
+#define LCD_OSDS_SOF0           (1 << 11) /* Start of frame flag for foreground 0 */
+#define LCD_OSDS_EOF0           (1 << 10) /* End of frame flag for foreground 0 */
+#define LCD_OSDS_READY          (1 << 0)  /* Read for accept the change */
+
+/* Background Color Register */
+#define LCD_BGC_RED_OFFSET      (1 << 16)  /* Red color offset */
+#define LCD_BGC_RED_MASK        (0xFF<<LCD_BGC_RED_OFFSET)
+#define LCD_BGC_GREEN_OFFSET    (1 << 8)   /* Green color offset */
+#define LCD_BGC_GREEN_MASK      (0xFF<<LCD_BGC_GREEN_OFFSET)
+#define LCD_BGC_BLUE_OFFSET     (1 << 0)   /* Blue color offset */
+#define LCD_BGC_BLUE_MASK       (0xFF<<LCD_BGC_BLUE_OFFSET)
+
+/* Foreground Color Key Register 0,1(foreground 0, foreground 1) */
+#define LCD_KEY_KEYEN           (1 << 31)   /* enable color key */
+#define LCD_KEY_KEYMD           (1 << 30)   /* color key mode */
+#define LCD_KEY_RED_OFFSET      16  /* Red color offset */
+#define LCD_KEY_RED_MASK        (0xFF<<LCD_KEY_RED_OFFSET)
+#define LCD_KEY_GREEN_OFFSET    8   /* Green color offset */
+#define LCD_KEY_GREEN_MASK      (0xFF<<LCD_KEY_GREEN_OFFSET)
+#define LCD_KEY_BLUE_OFFSET     0   /* Blue color offset */
+#define LCD_KEY_BLUE_MASK       (0xFF<<LCD_KEY_BLUE_OFFSET)
+#define LCD_KEY_MASK            (LCD_KEY_RED_MASK|LCD_KEY_GREEN_MASK|LCD_KEY_BLUE_MASK)
+
+/* IPU Restart Register */
+#define LCD_IPUR_IPUREN         (1 << 31)   /* IPU restart function enable*/
+#define LCD_IPUR_IPURMASK       (0xFFFFFF)   /* IPU restart value mask*/
+
+/* RGB Control Register */
+#define LCD_RGBC_RGBDM          (1 << 15)   /* enable RGB Dummy data */
+#define LCD_RGBC_DMM            (1 << 14)   /* RGB Dummy mode */
+#define LCD_RGBC_YCC            (1 << 8)    /* RGB to YCC */
+#define LCD_RGBC_ODDRGB_BIT     4       /* odd line serial RGB data arrangement */
+#define LCD_RGBC_ODDRGB_MASK    (0x7<<LCD_RGBC_ODDRGB_BIT)
+  #define LCD_RGBC_ODD_RGB      0
+  #define LCD_RGBC_ODD_RBG      1
+  #define LCD_RGBC_ODD_GRB      2
+  #define LCD_RGBC_ODD_GBR      3
+  #define LCD_RGBC_ODD_BRG      4
+  #define LCD_RGBC_ODD_BGR      5
+#define LCD_RGBC_EVENRGB_BIT    0       /* even line serial RGB data arrangement */
+#define LCD_RGBC_EVENRGB_MASK   (0x7<<LCD_RGBC_EVENRGB_BIT)
+  #define LCD_RGBC_EVEN_RGB     0
+  #define LCD_RGBC_EVEN_RBG     1
+  #define LCD_RGBC_EVEN_GRB     2
+  #define LCD_RGBC_EVEN_GBR     3
+  #define LCD_RGBC_EVEN_BRG     4
+  #define LCD_RGBC_EVEN_BGR     5
+
+/* Vertical Synchronize Register */
+#define LCD_VSYNC_VPS_BIT       16  /* VSYNC pulse start in line clock, fixed to 0 */
+#define LCD_VSYNC_VPS_MASK      (0xffff << LCD_VSYNC_VPS_BIT)
+#define LCD_VSYNC_VPE_BIT       0   /* VSYNC pulse end in line clock */
+#define LCD_VSYNC_VPE_MASK      (0xffff << LCD_VSYNC_VPS_BIT)
+
+/* Horizontal Synchronize Register */
+#define LCD_HSYNC_HPS_BIT       16  /* HSYNC pulse start position in dot clock */
+#define LCD_HSYNC_HPS_MASK      (0xffff << LCD_HSYNC_HPS_BIT)
+#define LCD_HSYNC_HPE_BIT       0   /* HSYNC pulse end position in dot clock */
+#define LCD_HSYNC_HPE_MASK      (0xffff << LCD_HSYNC_HPE_BIT)
+
+/* Virtual Area Setting Register */
+#define LCD_VAT_HT_BIT          16  /* Horizontal Total size in dot clock */
+#define LCD_VAT_HT_MASK         (0xffff << LCD_VAT_HT_BIT)
+#define LCD_VAT_VT_BIT          0   /* Vertical Total size in dot clock */
+#define LCD_VAT_VT_MASK         (0xffff << LCD_VAT_VT_BIT)
+
+/* Display Area Horizontal Start/End Point Register */
+#define LCD_DAH_HDS_BIT         16  /* Horizontal display area start in dot clock */
+#define LCD_DAH_HDS_MASK        (0xffff << LCD_DAH_HDS_BIT)
+#define LCD_DAH_HDE_BIT         0   /* Horizontal display area end in dot clock */
+#define LCD_DAH_HDE_MASK        (0xffff << LCD_DAH_HDE_BIT)
+
+/* Display Area Vertical Start/End Point Register */
+#define LCD_DAV_VDS_BIT         16  /* Vertical display area start in line clock */
+#define LCD_DAV_VDS_MASK        (0xffff << LCD_DAV_VDS_BIT)
+#define LCD_DAV_VDE_BIT         0   /* Vertical display area end in line clock */
+#define LCD_DAV_VDE_MASK        (0xffff << LCD_DAV_VDE_BIT)
+
+/* Foreground XY Position Register */
+#define LCD_XYP_YPOS_BIT        16  /* Y position bit of foreground 0 or 1 */
+#define LCD_XYP_YPOS_MASK       (0xffff << LCD_XYP_YPOS_BIT)
+#define LCD_XYP_XPOS_BIT        0   /* X position bit of foreground 0 or 1 */
+#define LCD_XYP_XPOS_MASK       (0xffff << LCD_XYP_XPOS_BIT)
+
+/* PS Signal Setting */
+#define LCD_PS_PSS_BIT          16  /* PS signal start position in dot clock */
+#define LCD_PS_PSS_MASK         (0xffff << LCD_PS_PSS_BIT)
+#define LCD_PS_PSE_BIT          0   /* PS signal end position in dot clock */
+#define LCD_PS_PSE_MASK         (0xffff << LCD_PS_PSE_BIT)
+
+/* CLS Signal Setting */
+#define LCD_CLS_CLSS_BIT        16  /* CLS signal start position in dot clock */
+#define LCD_CLS_CLSS_MASK       (0xffff << LCD_CLS_CLSS_BIT)
+#define LCD_CLS_CLSE_BIT        0   /* CLS signal end position in dot clock */
+#define LCD_CLS_CLSE_MASK       (0xffff << LCD_CLS_CLSE_BIT)
+
+/* SPL Signal Setting */
+#define LCD_SPL_SPLS_BIT        16  /* SPL signal start position in dot clock */
+#define LCD_SPL_SPLS_MASK       (0xffff << LCD_SPL_SPLS_BIT)
+#define LCD_SPL_SPLE_BIT        0   /* SPL signal end position in dot clock */
+#define LCD_SPL_SPLE_MASK       (0xffff << LCD_SPL_SPLE_BIT)
+
+/* REV Signal Setting */
+#define LCD_REV_REVS_BIT        16  /* REV signal start position in dot clock */
+#define LCD_REV_REVS_MASK       (0xffff << LCD_REV_REVS_BIT)
+
+/* DMA Command Register */
+#define LCD_CMD_SOFINT          (1 << 31)
+#define LCD_CMD_EOFINT          (1 << 30)
+#define LCD_CMD_CMD             (1 << 29) /* indicate command in slcd mode */
+#define LCD_CMD_PAL             (1 << 28)
+#define LCD_CMD_UNCOMP_EN       (1 << 27)
+#define LCD_CMD_UNCOMPRESS_WITHOUT_ALPHA        (1 << 26)
+#define LCD_CMD_LEN_BIT         0
+#define LCD_CMD_LEN_MASK        (0xffffff << LCD_CMD_LEN_BIT)
+
+/* DMA Offsize Register 0,1 */
+
+/* DMA Page Width Register 0,1 */
+
+/* DMA Command Counter Register 0,1 */
+
+/* Foreground 0,1 Size Register */
+#define LCD_DESSIZE_HEIGHT_BIT  16  /* height of foreground 1 */
+#define LCD_DESSIZE_HEIGHT_MASK (0xffff << LCD_DESSIZE_HEIGHT_BIT)
+#define LCD_DESSIZE_WIDTH_BIT   0  /* width of foreground 1 */
+#define LCD_DESSIZE_WIDTH_MASK  (0xffff << LCD_DESSIZE_WIDTH_BIT)
+
+/* Priority level threshold configure Register */
+#define LCD_PCFG_LCD_PRI_MD     (1 << 31)
+#define LCD_PCFG_HP_BST_BIT     28
+#define LCD_PCFG_HP_BST_MASK    (0x7 << LCD_PCFG_HP_BST_BIT)
+#define LCD_PCFG_PCFG2_BIT      8
+#define LCD_PCFG_PCFG2_MASK     (0xf << LCD_PCFG_PCFG2_BIT)
+#define LCD_PCFG_PCFG1_BIT      4
+#define LCD_PCFG_PCFG1_MASK     (0xf << LCD_PCFG_PCFG1_BIT)
+#define LCD_PCFG_PCFG0_BIT      0
+#define LCD_PCFG_PCFG0_MASK     (0xf << LCD_PCFG_PCFG0_BIT)
+
+#ifndef __MIPS_ASSEMBLER
+
+/*************************************************************************
+ * SLCD (Smart LCD Controller)
+ *************************************************************************/
+#define __slcd_set_data_18bit() \
+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_18BIT )
+#define __slcd_set_data_16bit() \
+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_16BIT )
+#define __slcd_set_data_8bit_x3() \
+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_8BIT_x3 )
+#define __slcd_set_data_8bit_x2() \
+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_8BIT_x2 )
+#define __slcd_set_data_8bit_x1() \
+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_8BIT_x1 )
+#define __slcd_set_data_24bit() \
+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_24BIT )
+#define __slcd_set_data_9bit_x2() \
+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_9BIT_x2 )
+
+#define __slcd_set_cmd_16bit() \
+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_16BIT )
+#define __slcd_set_cmd_8bit() \
+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_8BIT )
+#define __slcd_set_cmd_18bit() \
+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_18BIT )
+#define __slcd_set_cmd_24bit() \
+  ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_24BIT )
+
+#define __slcd_set_cs_high()        ( REG_SLCD_CFG |= SLCD_CFG_CS_ACTIVE_HIGH )
+#define __slcd_set_cs_low()         ( REG_SLCD_CFG &= ~SLCD_CFG_CS_ACTIVE_HIGH )
+
+#define __slcd_set_rs_high()        ( REG_SLCD_CFG |= SLCD_CFG_RS_CMD_HIGH )
+#define __slcd_set_rs_low()         ( REG_SLCD_CFG &= ~SLCD_CFG_RS_CMD_HIGH )
+
+#define __slcd_set_clk_falling()    ( REG_SLCD_CFG &= ~SLCD_CFG_CLK_ACTIVE_RISING )
+#define __slcd_set_clk_rising()     ( REG_SLCD_CFG |= SLCD_CFG_CLK_ACTIVE_RISING )
+
+#define __slcd_set_parallel_type()  ( REG_SLCD_CFG &= ~SLCD_CFG_TYPE_SERIAL )
+#define __slcd_set_serial_type()    ( REG_SLCD_CFG |= SLCD_CFG_TYPE_SERIAL )
+
+/* SLCD Control Register */
+#define __slcd_enable_dma()         ( REG_SLCD_CTRL |= SLCD_CTRL_DMA_EN )
+#define __slcd_disable_dma()        ( REG_SLCD_CTRL &= ~SLCD_CTRL_DMA_EN )
+
+/* SLCD Status Register */
+#define __slcd_is_busy()            ( REG_SLCD_STATE & SLCD_STATE_BUSY )
+
+/* SLCD Data Register */
+#define __slcd_set_cmd_rs()         ( REG_SLCD_DATA |= SLCD_DATA_RS_COMMAND)
+#define __slcd_set_data_rs()        ( REG_SLCD_DATA &= ~SLCD_DATA_RS_COMMAND)
+
+/***************************************************************************
+ * LCD
+ ***************************************************************************/
+#define __lcd_as_smart_lcd()            ( REG_LCD_CFG |= ( LCD_CFG_LCDPIN_SLCD | LCD_CFG_MODE_SLCD))
+#define __lcd_as_general_lcd()          ( REG_LCD_CFG &= ~( LCD_CFG_LCDPIN_SLCD | LCD_CFG_MODE_SLCD))
+
+#define __lcd_enable_tvepeh()           ( REG_LCD_CFG |= LCD_CFG_TVEPEH )
+#define __lcd_disable_tvepeh()          ( REG_LCD_CFG &= ~LCD_CFG_TVEPEH )
+
+#define __lcd_enable_fuhold()           ( REG_LCD_CFG |= LCD_CFG_FUHOLD )
+#define __lcd_disable_fuhold()          ( REG_LCD_CFG &= ~LCD_CFG_FUHOLD )
+
+#define __lcd_des_8word()               ( REG_LCD_CFG |= LCD_CFG_NEWDES )
+#define __lcd_des_4word()               ( REG_LCD_CFG &= ~LCD_CFG_NEWDES )
+
+#define __lcd_enable_bypass_pal()       ( REG_LCD_CFG |= LCD_CFG_PALBP )
+#define __lcd_disable_bypass_pal()      ( REG_LCD_CFG &= ~LCD_CFG_PALBP )
+
+#define __lcd_set_lcdpnl_term()         ( REG_LCD_CFG |= LCD_CFG_TVEN )
+#define __lcd_set_tv_term()             ( REG_LCD_CFG &= ~LCD_CFG_TVEN )
+
+#define __lcd_enable_auto_recover()     ( REG_LCD_CFG |= LCD_CFG_RECOVER )
+#define __lcd_disable_auto_recover()    ( REG_LCD_CFG &= ~LCD_CFG_RECOVER )
+
+#define __lcd_enable_dither()           ( REG_LCD_CFG |= LCD_CFG_DITHER )
+#define __lcd_disable_dither()          ( REG_LCD_CFG &= ~LCD_CFG_DITHER )
+
+#define __lcd_disable_ps_mode()         ( REG_LCD_CFG |= LCD_CFG_PSM )
+#define __lcd_enable_ps_mode()          ( REG_LCD_CFG &= ~LCD_CFG_PSM )
+
+#define __lcd_disable_cls_mode()        ( REG_LCD_CFG |= LCD_CFG_CLSM )
+#define __lcd_enable_cls_mode()         ( REG_LCD_CFG &= ~LCD_CFG_CLSM )
+
+#define __lcd_disable_spl_mode()        ( REG_LCD_CFG |= LCD_CFG_SPLM )
+#define __lcd_enable_spl_mode()         ( REG_LCD_CFG &= ~LCD_CFG_SPLM )
+
+#define __lcd_disable_rev_mode()        ( REG_LCD_CFG |= LCD_CFG_REVM )
+#define __lcd_enable_rev_mode()         ( REG_LCD_CFG &= ~LCD_CFG_REVM )
+
+#define __lcd_disable_hsync_mode()      ( REG_LCD_CFG |= LCD_CFG_HSYNM )
+#define __lcd_enable_hsync_mode()       ( REG_LCD_CFG &= ~LCD_CFG_HSYNM )
+
+#define __lcd_disable_pclk_mode()       ( REG_LCD_CFG |= LCD_CFG_PCLKM )
+#define __lcd_enable_pclk_mode()        ( REG_LCD_CFG &= ~LCD_CFG_PCLKM )
+
+#define __lcd_normal_outdata()          ( REG_LCD_CFG &= ~LCD_CFG_INVDAT )
+#define __lcd_inverse_outdata()         ( REG_LCD_CFG |= LCD_CFG_INVDAT )
+
+#define __lcd_sync_input()              ( REG_LCD_CFG |= LCD_CFG_SYNDIR_IN )
+#define __lcd_sync_output()             ( REG_LCD_CFG &= ~LCD_CFG_SYNDIR_IN )
+
+#define __lcd_hsync_active_high()       ( REG_LCD_CFG &= ~LCD_CFG_HSP )
+#define __lcd_hsync_active_low()        ( REG_LCD_CFG |= LCD_CFG_HSP )
+
+#define __lcd_pclk_rising()             ( REG_LCD_CFG &= ~LCD_CFG_PCP )
+#define __lcd_pclk_falling()            ( REG_LCD_CFG |= LCD_CFG_PCP )
+
+#define __lcd_de_active_high()          ( REG_LCD_CFG &= ~LCD_CFG_DEP )
+#define __lcd_de_active_low()           ( REG_LCD_CFG |= LCD_CFG_DEP )
+
+#define __lcd_vsync_rising()            ( REG_LCD_CFG &= ~LCD_CFG_VSP )
+#define __lcd_vsync_falling()           ( REG_LCD_CFG |= LCD_CFG_VSP )
+
+#define __lcd_set_16_tftpnl() \
+  ( REG_LCD_CFG = (REG_LCD_CFG & ~LCD_CFG_MODE_TFT_MASK) | LCD_CFG_MODE_TFT_16BIT )
+
+#define __lcd_set_18_tftpnl() \
+  ( REG_LCD_CFG = (REG_LCD_CFG & ~LCD_CFG_MODE_TFT_MASK) | LCD_CFG_MODE_TFT_18BIT )
+
+#define __lcd_set_24_tftpnl()           ( REG_LCD_CFG |= LCD_CFG_MODE_TFT_24BIT )
+
+/* 
+ * n=1,2,4,8 for single mono-STN 
+ * n=4,8 for dual mono-STN
+ */
+#define __lcd_set_panel_datawidth(n)            \
+do {                                            \
+        REG_LCD_CFG &= ~LCD_CFG_PDW_MASK;       \
+        REG_LCD_CFG |= LCD_CFG_PDW_n##;         \
+} while (0)
+
+/* m = LCD_CFG_MODE_GENERUIC_TFT_xxx */
+#define __lcd_set_panel_mode(m)                 \
+do {                                            \
+        REG_LCD_CFG &= ~LCD_CFG_MODE_MASK;      \
+        REG_LCD_CFG |= (m);                     \
+} while(0)
+
+/* n=4,8,16 */
+#define __lcd_set_burst_length(n)               \
+do {                                            \
+        REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK;     \
+        REG_LCD_CTRL |= LCD_CTRL_BST_n##;       \
+} while (0)
+
+#define __lcd_select_rgb565()           ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
+#define __lcd_select_rgb555()           ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
+
+#define __lcd_set_ofup()                ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
+#define __lcd_clr_ofup()                ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
+
+/* n=2,4,16 */
+#define __lcd_set_stn_frc(n)                    \
+do {                                            \
+        REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK;     \
+        REG_LCD_CTRL |= LCD_CTRL_FRC_n##;       \
+} while (0)
+
+#define __lcd_enable_eof_intr()         ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
+#define __lcd_disable_eof_intr()        ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
+
+#define __lcd_enable_sof_intr()         ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
+#define __lcd_disable_sof_intr()        ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
+
+#define __lcd_enable_ofu_intr()         ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
+#define __lcd_disable_ofu_intr()        ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
+
+#define __lcd_enable_ifu0_intr()        ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
+#define __lcd_disable_ifu0_intr()       ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
+
+#define __lcd_enable_ifu1_intr()        ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
+#define __lcd_disable_ifu1_intr()       ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
+
+#define __lcd_enable_ldd_intr()         ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
+#define __lcd_disable_ldd_intr()        ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
+
+#define __lcd_enable_qd_intr()          ( REG_LCD_CTRL |= LCD_CTRL_QDM )
+#define __lcd_disable_qd_intr()         ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
+
+#define __lcd_reverse_byte_endian()     ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
+#define __lcd_normal_byte_endian()      ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
+
+#define __lcd_pixel_endian_little()     ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
+#define __lcd_pixel_endian_big()        ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
+
+#define __lcd_set_dis()                 ( REG_LCD_CTRL |= LCD_CTRL_DIS )
+#define __lcd_clr_dis()                 ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
+
+#define __lcd_set_ena()                 ( REG_LCD_CTRL |= LCD_CTRL_ENA )
+#define __lcd_clr_ena()                 ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
+
+/* n=1,2,4,8,16 */
+#define __lcd_set_bpp(n) \
+  ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
+
+/* LCD status register indication */
+
+#define __lcd_quick_disable_done()      ( REG_LCD_STATE & LCD_STATE_QD )
+#define __lcd_disable_done()            ( REG_LCD_STATE & LCD_STATE_LDD )
+#define __lcd_infifo0_underrun()        ( REG_LCD_STATE & LCD_STATE_IFU0 )
+#define __lcd_infifo1_underrun()        ( REG_LCD_STATE & LCD_STATE_IFU1 )
+#define __lcd_outfifo_underrun()        ( REG_LCD_STATE & LCD_STATE_OFU )
+#define __lcd_start_of_frame()          ( REG_LCD_STATE & LCD_STATE_SOF )
+#define __lcd_end_of_frame()            ( REG_LCD_STATE & LCD_STATE_EOF )
+
+#define __lcd_clr_outfifounderrun()     ( REG_LCD_STATE &= ~LCD_STATE_OFU )
+#define __lcd_clr_sof()                 ( REG_LCD_STATE &= ~LCD_STATE_SOF )
+#define __lcd_clr_eof()                 ( REG_LCD_STATE &= ~LCD_STATE_EOF )
+
+/* OSD functions */
+#define __lcd_enable_osd()      (REG_LCD_OSDC |= LCD_OSDC_OSDEN)
+#define __lcd_enable_f0()       (REG_LCD_OSDC |= LCD_OSDC_F0EN)
+#define __lcd_enable_f1()       (REG_LCD_OSDC |= LCD_OSDC_F1EN)
+#define __lcd_enable_alpha()    (REG_LCD_OSDC |= LCD_OSDC_ALPHAEN)
+#define __lcd_enable_alphamd()  (REG_LCD_OSDC |= LCD_OSDC_ALPHAMD)
+
+#define __lcd_disable_osd()     (REG_LCD_OSDC &= ~LCD_OSDC_OSDEN)
+#define __lcd_disable_f0()      (REG_LCD_OSDC &= ~LCD_OSDC_F0EN)
+#define __lcd_disable_f1()      (REG_LCD_OSDC &= ~LCD_OSDC_F1EN)
+#define __lcd_disable_alpha()   (REG_LCD_OSDC &= ~LCD_OSDC_ALPHAEN)
+#define __lcd_disable_alphamd() (REG_LCD_OSDC &= ~LCD_OSDC_ALPHAMD)
+
+/* OSD Controll Register */
+#define __lcd_fg1_use_ipu()             (REG_LCD_OSDCTRL |= LCD_OSDCTRL_IPU)
+#define __lcd_fg1_use_dma_chan1()       (REG_LCD_OSDCTRL &= ~LCD_OSDCTRL_IPU)
+#define __lcd_fg1_unuse_ipu()           __lcd_fg1_use_dma_chan1()
+#define __lcd_osd_rgb555_mode()         ( REG_LCD_OSDCTRL |= LCD_OSDCTRL_RGB555 )
+#define __lcd_osd_rgb565_mode()         ( REG_LCD_OSDCTRL &= ~LCD_OSDCTRL_RGB555 )
+#define __lcd_osd_change_size()         ( REG_LCD_OSDCTRL |= LCD_OSDCTRL_CHANGES )
+#define __lcd_osd_bpp_15_16() \
+  ( REG_LCD_OSDCTRL = (REG_LCD_OSDCTRL & ~LCD_OSDCTRL_OSDBPP_MASK) | LCD_OSDCTRL_OSDBPP_15_16 )
+#define __lcd_osd_bpp_18_24() \
+  ( REG_LCD_OSDCTRL = (REG_LCD_OSDCTRL & ~LCD_OSDCTRL_OSDBPP_MASK) | LCD_OSDCTRL_OSDBPP_18_24 )
+
+/* OSD State Register */
+#define __lcd_start_of_fg1()            ( REG_LCD_STATE & LCD_OSDS_SOF1 )
+#define __lcd_end_of_fg1()              ( REG_LCD_STATE & LCD_OSDS_EOF1 )
+#define __lcd_start_of_fg0()            ( REG_LCD_STATE & LCD_OSDS_SOF0 )
+#define __lcd_end_of_fg0()              ( REG_LCD_STATE & LCD_OSDS_EOF0 )
+#define __lcd_change_is_rdy()           ( REG_LCD_STATE & LCD_OSDS_READY )
+
+/* Foreground Color Key Register 0,1(foreground 0, foreground 1) */
+#define __lcd_enable_colorkey0()        (REG_LCD_KEY0 |= LCD_KEY_KEYEN)
+#define __lcd_enable_colorkey1()        (REG_LCD_KEY1 |= LCD_KEY_KEYEN)
+#define __lcd_enable_colorkey0_md()     (REG_LCD_KEY0 |= LCD_KEY_KEYMD)
+#define __lcd_enable_colorkey1_md()     (REG_LCD_KEY1 |= LCD_KEY_KEYMD)
+#define __lcd_set_colorkey0(key)        (REG_LCD_KEY0 = (REG_LCD_KEY0&~0xFFFFFF)|(key))
+#define __lcd_set_colorkey1(key)        (REG_LCD_KEY1 = (REG_LCD_KEY1&~0xFFFFFF)|(key))
+
+#define __lcd_disable_colorkey0()       (REG_LCD_KEY0 &= ~LCD_KEY_KEYEN)
+#define __lcd_disable_colorkey1()       (REG_LCD_KEY1 &= ~LCD_KEY_KEYEN)
+#define __lcd_disable_colorkey0_md()    (REG_LCD_KEY0 &= ~LCD_KEY_KEYMD)
+#define __lcd_disable_colorkey1_md()    (REG_LCD_KEY1 &= ~LCD_KEY_KEYMD)
+
+/* IPU Restart Register */
+#define __lcd_enable_ipu_restart()      (REG_LCD_IPUR |= LCD_IPUR_IPUREN)
+#define __lcd_disable_ipu_restart()     (REG_LCD_IPUR &= ~LCD_IPUR_IPUREN)
+#define __lcd_set_ipu_restart_triger(n) (REG_LCD_IPUR = (REG_LCD_IPUR&(~0xFFFFFF))|(n))
+
+/* RGB Control Register */
+#define __lcd_enable_rgb_dummy()        (REG_LCD_RGBC |= LCD_RGBC_RGBDM)
+#define __lcd_disable_rgb_dummy()       (REG_LCD_RGBC &= ~LCD_RGBC_RGBDM)
+
+#define __lcd_dummy_rgb()       (REG_LCD_RGBC |= LCD_RGBC_DMM)
+#define __lcd_rgb_dummy()       (REG_LCD_RGBC &= ~LCD_RGBC_DMM)
+
+#define __lcd_rgb2ycc()         (REG_LCD_RGBC |= LCD_RGBC_YCC)
+#define __lcd_notrgb2ycc()      (REG_LCD_RGBC &= ~LCD_RGBC_YCC)
+
+#define __lcd_odd_mode_rgb() \
+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_RGB )
+#define __lcd_odd_mode_rbg() \
+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_RBG )
+#define __lcd_odd_mode_grb() \
+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_GRB)
+
+#define __lcd_odd_mode_gbr() \
+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_GBR)
+#define __lcd_odd_mode_brg() \
+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_BRG)
+#define __lcd_odd_mode_bgr() \
+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_BGR)
+
+#define __lcd_even_mode_rgb() \
+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_RGB )
+#define __lcd_even_mode_rbg() \
+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_RBG )
+#define __lcd_even_mode_grb() \
+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_GRB)
+
+#define __lcd_even_mode_gbr() \
+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_GBR)
+#define __lcd_even_mode_brg() \
+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_BRG)
+#define __lcd_even_mode_bgr() \
+  ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_BGR)
+
+/* Vertical Synchronize Register */
+#define __lcd_vsync_get_vps() \
+  ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
+
+#define __lcd_vsync_get_vpe() \
+  ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
+#define __lcd_vsync_set_vpe(n)                          \
+do {                                                    \
+        REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK;           \
+        REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT;      \
+} while (0)
+
+#define __lcd_hsync_get_hps() \
+  ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
+#define __lcd_hsync_set_hps(n)                          \
+do {                                                    \
+        REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK;           \
+        REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT;      \
+} while (0)
+
+#define __lcd_hsync_get_hpe() \
+  ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
+#define __lcd_hsync_set_hpe(n)                          \
+do {                                                    \
+        REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK;           \
+        REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT;      \
+} while (0)
+
+#define __lcd_vat_get_ht() \
+  ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
+#define __lcd_vat_set_ht(n)                             \
+do {                                                    \
+        REG_LCD_VAT &= ~LCD_VAT_HT_MASK;                \
+        REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT;           \
+} while (0)
+
+#define __lcd_vat_get_vt() \
+  ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
+#define __lcd_vat_set_vt(n)                             \
+do {                                                    \
+        REG_LCD_VAT &= ~LCD_VAT_VT_MASK;                \
+        REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT;           \
+} while (0)
+
+#define __lcd_dah_get_hds() \
+  ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
+#define __lcd_dah_set_hds(n)                            \
+do {                                                    \
+        REG_LCD_DAH &= ~LCD_DAH_HDS_MASK;               \
+        REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT;          \
+} while (0)
+
+#define __lcd_dah_get_hde() \
+  ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
+#define __lcd_dah_set_hde(n)                            \
+do {                                                    \
+        REG_LCD_DAH &= ~LCD_DAH_HDE_MASK;               \
+        REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT;          \
+} while (0)
+
+#define __lcd_dav_get_vds() \
+  ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
+#define __lcd_dav_set_vds(n)                            \
+do {                                                    \
+        REG_LCD_DAV &= ~LCD_DAV_VDS_MASK;               \
+        REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT;          \
+} while (0)
+
+#define __lcd_dav_get_vde() \
+  ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
+#define __lcd_dav_set_vde(n)                            \
+do {                                                    \
+        REG_LCD_DAV &= ~LCD_DAV_VDE_MASK;               \
+        REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT;          \
+} while (0)
+
+/* DMA Command Register */
+#define __lcd_cmd0_set_sofint()         ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
+#define __lcd_cmd0_clr_sofint()         ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
+#define __lcd_cmd1_set_sofint()         ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
+#define __lcd_cmd1_clr_sofint()         ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
+
+#define __lcd_cmd0_set_eofint()         ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
+#define __lcd_cmd0_clr_eofint()         ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
+#define __lcd_cmd1_set_eofint()         ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
+#define __lcd_cmd1_clr_eofint()         ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
+
+#define __lcd_cmd0_set_pal()            ( REG_LCD_CMD0 |= LCD_CMD_PAL )
+#define __lcd_cmd0_clr_pal()            ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
+
+#define __lcd_cmd0_get_len() \
+  ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
+#define __lcd_cmd1_get_len() \
+  ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
+
+#endif /* __MIPS_ASSEMBLER */
+
+/*
+ * Motion compensation module(MC) address definition
+ */
+#define MC_BASE         0xb3250000
+
+/*
+ * MC registers offset address definition
+ */
+#define MC_MCCR_OFFSET          (0x00)  /* rw, 32, 0x???????? */
+#define MC_MCSR_OFFSET          (0x04)  /* rw, 32, 0x???????? */
+#define MC_MCRBAR_OFFSET        (0x08)  /* rw, 32, 0x???????? */
+#define MC_MCT1LFCR_OFFSET      (0x0c)  /* rw, 32, 0x???????? */
+#define MC_MCT2LFCR_OFFSET      (0x10)  /* rw, 32, 0x???????? */
+#define MC_MCCBAR_OFFSET        (0x14)  /* rw, 32, 0x???????? */
+#define MC_MCIIR_OFFSET         (0x18)  /* rw, 32, 0x???????? */
+#define MC_MCSIR_OFFSET         (0x1c)  /* rw, 32, 0x???????? */
+#define MC_MCT1MFCR_OFFSET      (0x20)  /* rw, 32, 0x???????? */
+#define MC_MCT2MFCR_OFFSET      (0x24)  /* rw, 32, 0x???????? */
+#define MC_MCFGIR_OFFSET        (0x28)  /* rw, 32, 0x???????? */
+#define MC_MCFCIR_OFFSET        (0x2c)  /* rw, 32, 0x???????? */
+#define MC_MCRNDTR_OFFSET       (0x40)  /* rw, 32, 0x???????? */
+
+#define MC_MC2CR_OFFSET         (0x8000)        /* rw, 32, 0x???????? */
+#define MC_MC2SR_OFFSET         (0x8004)        /* rw, 32, 0x???????? */
+#define MC_MC2RBAR_OFFSET       (0x8008)        /* rw, 32, 0x???????? */
+#define MC_MC2CBAR_OFFSET       (0x800c)        /* rw, 32, 0x???????? */
+#define MC_MC2IIR_OFFSET        (0x8010)        /* rw, 32, 0x???????? */
+#define MC_MC2TFCR_OFFSET       (0x8014)        /* rw, 32, 0x???????? */
+#define MC_MC2SIR_OFFSET        (0x8018)        /* rw, 32, 0x???????? */
+#define MC_MC2FCIR_OFFSET       (0x801c)        /* rw, 32, 0x???????? */
+#define MC_MC2RNDTR_OFFSET      (0x8040)        /* rw, 32, 0x???????? */
+
+/*
+ * MC registers address definition
+ */
+#define MC_MCCR         (MC_BASE + MC_MCCR_OFFSET)
+#define MC_MCSR         (MC_BASE + MC_MCSR_OFFSET)
+#define MC_MCRBAR       (MC_BASE + MC_MCRBAR_OFFSET)
+#define MC_MCT1LFCR     (MC_BASE + MC_MCT1LFCR_OFFSET)
+#define MC_MCT2LFCR     (MC_BASE + MC_MCT2LFCR_OFFSET)
+#define MC_MCCBAR       (MC_BASE + MC_MCCBAR_OFFSET)
+#define MC_MCIIR        (MC_BASE + MC_MCIIR_OFFSET)
+#define MC_MCSIR        (MC_BASE + MC_MCSIR_OFFSET)
+#define MC_MCT1MFCR     (MC_BASE + MC_MCT1MFCR_OFFSET)
+#define MC_MCT2MFCR     (MC_BASE + MC_MCT2MFCR_OFFSET)
+#define MC_MCFGIR       (MC_BASE + MC_MCFGIR_OFFSET)
+#define MC_MCFCIR       (MC_BASE + MC_MCFCIR_OFFSET)
+#define MC_MCRNDTR      (MC_BASE + MC_MCRNDTR_OFFSET)
+
+#define MC_MC2CR        (MC_BASE + MC_MC2CR_OFFSET)
+#define MC_MC2SR        (MC_BASE + MC_MC2SR_OFFSET)
+#define MC_MC2RBAR      (MC_BASE + MC_MC2RBAR_OFFSET)
+#define MC_MC2CBAR      (MC_BASE + MC_MC2CBAR_OFFSET)
+#define MC_MC2IIR       (MC_BASE + MC_MC2IIR_OFFSET)
+#define MC_MC2TFCR      (MC_BASE + MC_MC2TFCR_OFFSET)
+#define MC_MC2SIR       (MC_BASE + MC_MC2SIR_OFFSET)
+#define MC_MC2FCIR      (MC_BASE + MC_MC2FCIR_OFFSET)
+#define MC_MC2RNDTR     (MC_BASE + MC_MC2RNDTR_OFFSET)
+
+/*
+ * MC registers common define
+ */
+
+/* MC Control Register(MCCR) */
+#define MCCR_RETE               BIT16
+#define MCCR_DIPE               BIT7
+#define MCCR_CKGEN              BIT6
+#define MCCR_FDDEN              BIT5
+#define MCCR_DINSE              BIT3
+#define MCCR_FAE                BIT2
+#define MCCR_RST                BIT1
+#define MCCR_CHEN               BIT0
+
+#define MCCR_FDDPGN_LSB         8
+#define MCCR_FDDPGN_MASK        BITS_H2L(15, MCCR_FDDPGN_LSB)
+
+/* MC Status Register(MCSR) */
+#define MCSR_DLEND              BIT1
+#define MCSR_BKLEND             BIT0
+
+#ifndef __MIPS_ASSEMBLER
+
+#define REG_MC_MCCR             REG32(REG_MC_MCCR)
+#define REG_MC_MCSR             REG32(REG_MC_MCSR)
+#define REG_MC_MCRBAR           REG32(REG_MC_MCRBAR)
+#define REG_MC_MCT1LFCR         REG32(REG_MC_MCT1LFCR)
+#define REG_MC_MCT2LFCR         REG32(REG_MC_MCT2LFCR)
+#define REG_MC_MCCBAR           REG32(REG_MC_MCCBAR)
+#define REG_MC_MCIIR            REG32(REG_MC_MCIIR)
+#define REG_MC_MCSIR            REG32(REG_MC_MCSIR)
+#define REG_MC_MCT1MFCR         REG32(REG_MC_MCT1MFCR)
+#define REG_MC_MCT2MFCR         REG32(REG_MC_MCT2MFCR)
+#define REG_MC_MCFGIR           REG32(REG_MC_MCFGIR)
+#define REG_MC_MCFCIR           REG32(REG_MC_MCFCIR)
+#define REG_MC_MCRNDTR          REG32(REG_MC_MCRNDTR)
+
+#define REG_MC_MC2CR            REG32(REG_MC_MC2CR)
+#define REG_MC_MC2SR            REG32(REG_MC_MC2SR)
+#define REG_MC_MC2RBAR          REG32(REG_MC_MC2RBAR)
+#define REG_MC_MC2CBAR          REG32(REG_MC_MC2CBAR)
+#define REG_MC_MC2IIR           REG32(REG_MC_MC2IIR)
+#define REG_MC_MC2TFCR          REG32(REG_MC_MC2TFCR)
+#define REG_MC_MC2SIR           REG32(REG_MC_MC2SIR)
+#define REG_MC_MC2FCIR          REG32(REG_MC_MC2FCIR)
+#define REG_MC_MC2RNDTR         REG32(REG_MC_MC2RNDTR)
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define MDMAC_BASE      0xB3030000 /* Memory Copy DMAC */
+
+/*************************************************************************
+ * MDMAC (MEM Copy DMA Controller)
+ *************************************************************************/
+
+/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
+
+#define MDMAC_DSAR(n)           (MDMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
+#define MDMAC_DTAR(n)           (MDMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
+#define MDMAC_DTCR(n)           (MDMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
+#define MDMAC_DRSR(n)           (MDMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
+#define MDMAC_DCCSR(n)          (MDMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
+#define MDMAC_DCMD(n)           (MDMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
+#define MDMAC_DDA(n)            (MDMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
+#define MDMAC_DSD(n)            (MDMAC_BASE + (0x1c + (n) * 0x20)) /* DMA Stride Address */
+
+#define MDMAC_DMACR             (MDMAC_BASE + 0x0300) /* DMA control register */
+#define MDMAC_DMAIPR            (MDMAC_BASE + 0x0304) /* DMA interrupt pending */
+#define MDMAC_DMADBR            (MDMAC_BASE + 0x0308) /* DMA doorbell */
+#define MDMAC_DMADBSR           (MDMAC_BASE + 0x030C) /* DMA doorbell set */
+#define MDMAC_DMACKE            (MDMAC_BASE + 0x0310)
+#define MDMAC_DMACKES           (MDMAC_BASE + 0x0314)
+#define MDMAC_DMACKEC           (MDMAC_BASE + 0x0318)
+
+#define REG_MDMAC_DSAR(n)       REG32(MDMAC_DSAR((n)))
+#define REG_MDMAC_DTAR(n)       REG32(MDMAC_DTAR((n)))
+#define REG_MDMAC_DTCR(n)       REG32(MDMAC_DTCR((n)))
+#define REG_MDMAC_DRSR(n)       REG32(MDMAC_DRSR((n)))
+#define REG_MDMAC_DCCSR(n)      REG32(MDMAC_DCCSR((n)))
+#define REG_MDMAC_DCMD(n)       REG32(MDMAC_DCMD((n)))
+#define REG_MDMAC_DDA(n)        REG32(MDMAC_DDA((n)))
+#define REG_MDMAC_DSD(n)        REG32(MDMAC_DSD(n))
+#define REG_MDMAC_DMACR         REG32(MDMAC_DMACR)
+#define REG_MDMAC_DMAIPR        REG32(MDMAC_DMAIPR)
+#define REG_MDMAC_DMADBR        REG32(MDMAC_DMADBR)
+#define REG_MDMAC_DMADBSR       REG32(MDMAC_DMADBSR)
+#define REG_MDMAC_DMACKE        REG32(MDMAC_DMACKE)
+#define REG_MDMAC_DMACKES       REG32(MDMAC_DMACKES)
+#define REG_MDMAC_DMACKEC       REG32(MDMAC_DMACKEC)
+
+// DMA control register
+#define DMAC_MDMACR_HLT         (1 << 3)  /* DMA halt flag */
+#define DMAC_MDMACR_AR          (1 << 2)  /* address error flag */
+#define DMAC_MDMACR_DMAE        (1 << 0)  /* DMA enable bit */
+
+#ifndef __MIPS_ASSEMBLER
+
+/***************************************************************************
+ * Mem Copy DMAC
+ ***************************************************************************/
+
+#define __mdmac_enable_module() \
+        ( REG_MDMAC_DMACR |= DMAC_MDMACR_DMAE )
+#define __mdmac_disable_module() \
+        ( REG_MDMAC_DMACR &= ~DMAC_MDMACR_DMAE )
+
+#define __mdmac_test_halt_error ( REG_MDMAC_DMACR & DMAC_MDMACR_HLT )
+#define __mdmac_test_addr_error ( REG_MDMAC_DMACR & DMAC_MDMACR_AR )
+
+#define __mdmac_channel_enable_clk \
+        REG_MDMAC_DMACKES = 1 << (n);
+
+#define __mdmac_channel_disable_clk \
+        REG_MDMAC_DMACKEC = 1 << (n);
+
+#define __mdmac_enable_descriptor(n) \
+  ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
+#define __mdmac_disable_descriptor(n) \
+  ( REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
+
+#define __mdmac_enable_channel(n)                 \
+do {                                             \
+        REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_EN;    \
+} while (0)
+#define __mdmac_disable_channel(n)                \
+do {                                             \
+        REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN;   \
+} while (0)
+#define __mdmac_channel_enabled(n) \
+  ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_EN )
+
+#define __mdmac_channel_enable_irq(n) \
+  ( REG_MDMAC_DCMD((n)) |= DMAC_DCMD_TIE )
+#define __mdmac_channel_disable_irq(n) \
+  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
+
+#define __mdmac_channel_transmit_halt_detected(n) \
+  (  REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
+#define __mdmac_channel_transmit_end_detected(n) \
+  (  REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_TT )
+#define __mdmac_channel_address_error_detected(n) \
+  (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
+#define __mdmac_channel_count_terminated_detected(n) \
+  (  REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_CT )
+#define __mdmac_channel_descriptor_invalid_detected(n) \
+  (  REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_INV )
+
+#define __mdmac_channel_clear_transmit_halt(n)                          \
+        do {                                                            \
+                /* clear both channel halt error and globle halt error */ \
+                REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT;                  \
+                REG_MDMAC_DMACR &= ~DMAC_DMACR_HLT;     \
+        } while (0)
+#define __mdmac_channel_clear_transmit_end(n) \
+  (  REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
+#define __mdmac_channel_clear_address_error(n)                          \
+        do {                                                            \
+                REG_MDMAC_DDA(n) = 0; /* clear descriptor address register */ \
+                REG_MDMAC_DSAR(n) = 0; /* clear source address register */ \
+                REG_MDMAC_DTAR(n) = 0; /* clear target address register */ \
+                /* clear both channel addr error and globle address error */ \
+                REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_AR;                   \
+                REG_MDMAC_DMACR &= ~DMAC_DMACR_AR;      \
+        } while (0)
+#define __mdmac_channel_clear_count_terminated(n) \
+  (  REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
+#define __mdmac_channel_clear_descriptor_invalid(n) \
+  (  REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
+
+#define __mdmac_channel_set_transfer_unit_32bit(n)      \
+do {                                                    \
+        REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;      \
+        REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT;      \
+} while (0)
+
+#define __mdmac_channel_set_transfer_unit_16bit(n)      \
+do {                                                    \
+        REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;      \
+        REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT;      \
+} while (0)
+
+#define __mdmac_channel_set_transfer_unit_8bit(n)       \
+do {                                                    \
+        REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;      \
+        REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT;       \
+} while (0)
+
+#define __mdmac_channel_set_transfer_unit_16byte(n)     \
+do {                                                    \
+        REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;      \
+        REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE;     \
+} while (0)
+
+#define __mdmac_channel_set_transfer_unit_32byte(n)     \
+do {                                                    \
+        REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;      \
+        REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE;     \
+} while (0)
+
+/* w=8,16,32 */
+#define __mdmac_channel_set_dest_port_width(n,w)                \
+do {                                                    \
+        REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK;    \
+        REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w;      \
+} while (0)
+
+/* w=8,16,32 */
+#define __mdmac_channel_set_src_port_width(n,w)         \
+do {                                                    \
+        REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK;    \
+        REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w;      \
+} while (0)
+
+/* v=0-15 */
+#define __mdmac_channel_set_rdil(n,v)                           \
+do {                                                            \
+        REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK;            \
+        REG_MDMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT);      \
+} while (0)
+
+#define __mdmac_channel_dest_addr_fixed(n) \
+        (REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DAI)
+#define __mdmac_channel_dest_addr_increment(n) \
+        (REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DAI)
+
+#define __mdmac_channel_src_addr_fixed(n) \
+        (REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SAI)
+#define __mdmac_channel_src_addr_increment(n) \
+        (REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SAI)
+
+#define __mdmac_channel_set_doorbell(n) \
+        (REG_MDMAC_DMADBSR = (1 << (n)))
+
+#define __mdmac_channel_irq_detected(n)  (REG_MDMAC_DMAIPR & (1 << (n)))
+#define __mdmac_channel_ack_irq(n)       (REG_MDMAC_DMAIPR &= ~(1 <<(n)))
+
+static __inline__ int __mdmac_get_irq(void)
+{
+        int i;
+        for (i = 0; i < MAX_MDMA_NUM; i++)
+                if (__mdmac_channel_irq_detected(i))
+                        return i;
+        return -1;
+}
+
+#endif /* __MIPS_ASSEMBLER */
+
+/*
+ * Motion estimation module(ME) address definition
+ */
+#define ME_BASE         0xb3260000
+
+/*
+ * ME registers offset address definition
+ */
+#define ME_MECR_OFFSET          (0x00)  /* rw, 32, 0x???????0 */
+#define ME_MERBAR_OFFSET        (0x04)  /* rw, 32, 0x???????? */
+#define ME_MECBAR_OFFSET        (0x08)  /* rw, 32, 0x???????? */
+#define ME_MEDAR_OFFSET         (0x0c)  /* rw, 32, 0x???????? */
+#define ME_MERFSR_OFFSET        (0x10)  /* rw, 32, 0x???????? */
+#define ME_MECFSR_OFFSET        (0x14)  /* rw, 32, 0x???????? */
+#define ME_MEDFSR_OFFSET        (0x18)  /* rw, 32, 0x???????? */
+#define ME_MESR_OFFSET          (0x1c)  /* rw, 32, 0x???????? */
+#define ME_MEMR_OFFSET          (0x20)  /* rw, 32, 0x???????? */
+#define ME_MEFR_OFFSET          (0x24)  /* rw, 32, 0x???????? */
+
+/*
+ * ME registers address definition
+ */
+#define ME_MECR         (ME_BASE + ME_MECR_OFFSET)
+#define ME_MERBAR       (ME_BASE + ME_MERBAR_OFFSET)
+#define ME_MECBAR       (ME_BASE + ME_MECBAR_OFFSET)
+#define ME_MEDAR        (ME_BASE + ME_MEDAR_OFFSET)
+#define ME_MERFSR       (ME_BASE + ME_MERFSR_OFFSET)
+#define ME_MECFSR       (ME_BASE + ME_MECFSR_OFFSET)
+#define ME_MEDFSR       (ME_BASE + ME_MEDFSR_OFFSET)
+#define ME_MESR         (ME_BASE + ME_MESR_OFFSET)
+#define ME_MEMR         (ME_BASE + ME_MEMR_OFFSET)
+#define ME_MEFR         (ME_BASE + ME_MEFR_OFFSET)
+
+/*
+ * ME registers common define
+ */
+
+/* ME control register(MECR) */
+#define MECR_FLUSH              BIT2
+#define MECR_RESET              BIT1
+#define MECR_ENABLE             BIT0
+
+/* ME settings register(MESR) */
+#define MESR_GATE_LSB           16
+#define MESR_GATE_MASK          BITS_H2L(31, MESR_GATE_LSB)
+
+#define MESR_NUM_LSB            0
+#define MESR_NUM_MASK           BITS_H2L(5, MESR_NUM_LSB)
+
+/* ME MVD register(MEMR) */
+#define MEMR_MVDY_LSB           16
+#define MESR_MVDY_MASK          BITS_H2L(31, MEMR_MVDY_LSB)
+
+#define MEMR_MVDX_LSB           0
+#define MESR_MVDX_MASK          BITS_H2L(15, MEMR_MVDX_LSB)
+
+/* ME flag register(MEFR) */
+#define MEFR_INTRA              BIT1
+#define MEFR_COMPLETED          BIT0
+
+#ifndef __MIPS_ASSEMBLER
+
+#define REG_ME_MECR     REG32(ME_MECR)
+#define REG_ME_MERBAR   REG32(ME_MERBAR)
+#define REG_ME_MECBAR   REG32(ME_MECBAR)
+#define REG_ME_MEDAR    REG32(ME_MEDAR)
+#define REG_ME_MERFSR   REG32(ME_MERFSR)
+#define REG_ME_MECFSR   REG32(ME_MECFSR)
+#define REG_ME_MEDFSR   REG32(ME_MEDFSR)
+#define REG_ME_MESR     REG32(ME_MESR)
+#define REG_ME_MEMR     REG32(ME_MEMR)
+#define REG_ME_MEFR     REG32(ME_MEFR)
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define MSC0_BASE       0xB0021000
+#define MSC1_BASE       0xB0022000
+#define MSC2_BASE       0xB0023000
+
+/*************************************************************************
+ * MSC
+ ************************************************************************/
+/* n = 0, 1 (MSC0, MSC1) */
+#define MSC_STRPCL(n)           (MSC0_BASE + (n)*0x1000 + 0x000)
+#define MSC_STAT(n)             (MSC0_BASE + (n)*0x1000 + 0x004)
+#define MSC_CLKRT(n)            (MSC0_BASE + (n)*0x1000 + 0x008)
+#define MSC_CMDAT(n)            (MSC0_BASE + (n)*0x1000 + 0x00C)
+#define MSC_RESTO(n)            (MSC0_BASE + (n)*0x1000 + 0x010)
+#define MSC_RDTO(n)             (MSC0_BASE + (n)*0x1000 + 0x014)
+#define MSC_BLKLEN(n)           (MSC0_BASE + (n)*0x1000 + 0x018)
+#define MSC_NOB(n)              (MSC0_BASE + (n)*0x1000 + 0x01C)
+#define MSC_SNOB(n)             (MSC0_BASE + (n)*0x1000 + 0x020)
+#define MSC_IMASK(n)            (MSC0_BASE + (n)*0x1000 + 0x024)
+#define MSC_IREG(n)             (MSC0_BASE + (n)*0x1000 + 0x028)
+#define MSC_CMD(n)              (MSC0_BASE + (n)*0x1000 + 0x02C)
+#define MSC_ARG(n)              (MSC0_BASE + (n)*0x1000 + 0x030)
+#define MSC_RES(n)              (MSC0_BASE + (n)*0x1000 + 0x034)
+#define MSC_RXFIFO(n)           (MSC0_BASE + (n)*0x1000 + 0x038)
+#define MSC_TXFIFO(n)           (MSC0_BASE + (n)*0x1000 + 0x03C)
+#define MSC_LPM(n)              (MSC0_BASE + (n)*0x1000 + 0x040)
+
+#define REG_MSC_STRPCL(n)       REG16(MSC_STRPCL(n))
+#define REG_MSC_STAT(n)         REG32(MSC_STAT(n))
+#define REG_MSC_CLKRT(n)        REG16(MSC_CLKRT(n))
+#define REG_MSC_CMDAT(n)        REG32(MSC_CMDAT(n))
+#define REG_MSC_RESTO(n)        REG16(MSC_RESTO(n))
+#define REG_MSC_RDTO(n)         REG32(MSC_RDTO(n))
+#define REG_MSC_BLKLEN(n)       REG16(MSC_BLKLEN(n))
+#define REG_MSC_NOB(n)          REG16(MSC_NOB(n))
+#define REG_MSC_SNOB(n)         REG16(MSC_SNOB(n))
+#define REG_MSC_IMASK(n)        REG32(MSC_IMASK(n))
+#define REG_MSC_IREG(n)         REG16(MSC_IREG(n))
+#define REG_MSC_CMD(n)          REG8(MSC_CMD(n))
+#define REG_MSC_ARG(n)          REG32(MSC_ARG(n))
+#define REG_MSC_RES(n)          REG16(MSC_RES(n))
+#define REG_MSC_RXFIFO(n)       REG32(MSC_RXFIFO(n))
+#define REG_MSC_TXFIFO(n)       REG32(MSC_TXFIFO(n))
+#define REG_MSC_LPM(n)          REG32(MSC_LPM(n))
+
+/* MSC Clock and Control Register (MSC_STRPCL) */
+#define MSC_STRPCL_SEND_CCSD            (1 << 15) /*send command completion signal disable to ceata */
+#define MSC_STRPCL_SEND_AS_CCSD         (1 << 14) /*send internally generated stop after sending ccsd */
+#define MSC_STRPCL_EXIT_MULTIPLE        (1 << 7)
+#define MSC_STRPCL_EXIT_TRANSFER        (1 << 6)
+#define MSC_STRPCL_START_READWAIT       (1 << 5)
+#define MSC_STRPCL_STOP_READWAIT        (1 << 4)
+#define MSC_STRPCL_RESET                (1 << 3)
+#define MSC_STRPCL_START_OP             (1 << 2)
+#define MSC_STRPCL_CLOCK_CONTROL_BIT    0
+#define MSC_STRPCL_CLOCK_CONTROL_MASK   (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
+  #define MSC_STRPCL_CLOCK_CONTROL_STOP   (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
+  #define MSC_STRPCL_CLOCK_CONTROL_START  (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
+
+/* MSC Status Register (MSC_STAT) */
+#define MSC_STAT_AUTO_CMD_DONE          (1 << 31) /*12 is internally generated by controller has finished */
+#define MSC_STAT_IS_RESETTING           (1 << 15)
+#define MSC_STAT_SDIO_INT_ACTIVE        (1 << 14)
+#define MSC_STAT_PRG_DONE               (1 << 13)
+#define MSC_STAT_DATA_TRAN_DONE         (1 << 12)
+#define MSC_STAT_END_CMD_RES            (1 << 11)
+#define MSC_STAT_DATA_FIFO_AFULL        (1 << 10)
+#define MSC_STAT_IS_READWAIT            (1 << 9)
+#define MSC_STAT_CLK_EN                 (1 << 8)
+#define MSC_STAT_DATA_FIFO_FULL         (1 << 7)
+#define MSC_STAT_DATA_FIFO_EMPTY        (1 << 6)
+#define MSC_STAT_CRC_RES_ERR            (1 << 5)
+#define MSC_STAT_CRC_READ_ERROR         (1 << 4)
+#define MSC_STAT_CRC_WRITE_ERROR_BIT    2
+#define MSC_STAT_CRC_WRITE_ERROR_MASK   (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
+  #define MSC_STAT_CRC_WRITE_ERROR_NO           (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
+  #define MSC_STAT_CRC_WRITE_ERROR              (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
+  #define MSC_STAT_CRC_WRITE_ERROR_NOSTS        (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
+#define MSC_STAT_TIME_OUT_RES           (1 << 1)
+#define MSC_STAT_TIME_OUT_READ          (1 << 0)
+
+/* MSC Bus Clock Control Register (MSC_CLKRT) */
+#define MSC_CLKRT_CLK_DIV_BIT           14
+#define MSC_CLKRT_CLK_DIV_MASK          (0x3 << MSC_CLKRT_CLK_DIV_BIT)
+#define MSC_CLKRT_CLK_SRC_DIV_1         (0x0 << MSC_CLKRT_CLK_DIV_BIT) /* CLK_SRC */
+#define MSC_CLKRT_CLK_SRC_DIV_2         (0x1 << MSC_CLKRT_CLK_DIV_BIT) /* 1/2 of CLK_SRC */
+#define MSC_CLKRT_CLK_SRC_DIV_3         (0x2 << MSC_CLKRT_CLK_DIV_BIT) /* 1/3 of CLK_SRC */
+#define MSC_CLKRT_CLK_SRC_DIV_4         (0x3 << MSC_CLKRT_CLK_DIV_BIT) /* 1/4 of CLK_SRC */
+
+#define MSC_CLKRT_CLK_RATE_BIT          0
+#define MSC_CLKRT_CLK_RATE_MASK         (0x7 << MSC_CLKRT_CLK_RATE_BIT)
+#define MSC_CLKRT_CLK_RATE_DIV_1        (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
+#define MSC_CLKRT_CLK_RATE_DIV_2        (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
+#define MSC_CLKRT_CLK_RATE_DIV_4        (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
+#define MSC_CLKRT_CLK_RATE_DIV_8        (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
+#define MSC_CLKRT_CLK_RATE_DIV_16       (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
+#define MSC_CLKRT_CLK_RATE_DIV_32       (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
+#define MSC_CLKRT_CLK_RATE_DIV_64       (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
+#define MSC_CLKRT_CLK_RATE_DIV_128      (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
+
+/* MSC Command Sequence Control Register (MSC_CMDAT) */
+#define MSC_CMDAT_CCS_EXPECTED          (1 << 31) /* interrupts are enabled in ce-ata */
+#define MSC_CMDAT_READ_CEATA            (1 << 30)
+#define MSC_CMDAT_SDIO_PRDT             (1 << 17) /* exact 2 cycle */
+#define MSC_CMDAT_SEND_AS_STOP          (1 << 16)
+#define MSC_CMDAT_RTRG_BIT              14
+#define MSC_CMDAT_RTRG_EQUALT_8         (0x0 << MSC_CMDAT_RTRG_BIT) /*reset value*/
+  #define MSC_CMDAT_RTRG_EQUALT_16      (0x1 << MSC_CMDAT_RTRG_BIT) 
+  #define MSC_CMDAT_RTRG_EQUALT_24      (0x2 << MSC_CMDAT_RTRG_BIT)
+
+#define MSC_CMDAT_TTRG_BIT              12
+#define MSC_CMDAT_TTRG_LESS_8           (0x0 << MSC_CMDAT_TTRG_BIT) /*reset value*/
+  #define MSC_CMDAT_TTRG_LESS_16        (0x1 << MSC_CMDAT_TTRG_BIT) 
+  #define MSC_CMDAT_TTRG_LESS_24        (0x2 << MSC_CMDAT_TTRG_BIT)
+#define MSC_CMDAT_STOP_ABORT            (1 << 11)
+#define MSC_CMDAT_BUS_WIDTH_BIT         9
+#define MSC_CMDAT_BUS_WIDTH_MASK        (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
+  #define MSC_CMDAT_BUS_WIDTH_1BIT      (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
+  #define MSC_CMDAT_BUS_WIDTH_4BIT      (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
+  #define MSC_CMDAT_BUS_WIDTH_8BIT      (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) /* 8-bit data bus */
+#define MSC_CMDAT_DMA_EN                (1 << 8)
+#define MSC_CMDAT_INIT                  (1 << 7)
+#define MSC_CMDAT_BUSY                  (1 << 6)
+#define MSC_CMDAT_STREAM_BLOCK          (1 << 5)
+#define MSC_CMDAT_WRITE                 (1 << 4)
+#define MSC_CMDAT_READ                  (0 << 4)
+#define MSC_CMDAT_DATA_EN               (1 << 3)
+#define MSC_CMDAT_RESPONSE_BIT  0
+#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
+  #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
+  #define MSC_CMDAT_RESPONSE_R1   (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
+  #define MSC_CMDAT_RESPONSE_R2   (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
+  #define MSC_CMDAT_RESPONSE_R3   (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
+  #define MSC_CMDAT_RESPONSE_R4   (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
+  #define MSC_CMDAT_RESPONSE_R5   (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
+  #define MSC_CMDAT_RESPONSE_R6   (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
+  #define MSC_CMDAT_RESRONSE_R7   (0x7 << MSC_CMDAT_RESPONSE_BIT) /* Format R7 */
+
+#define CMDAT_DMA_EN    (1 << 8)
+#define CMDAT_INIT      (1 << 7)
+#define CMDAT_BUSY      (1 << 6)
+#define CMDAT_STREAM    (1 << 5)
+#define CMDAT_WRITE     (1 << 4)
+#define CMDAT_DATA_EN   (1 << 3)
+
+/* MSC Interrupts Mask Register (MSC_IMASK) */
+#define MSC_IMASK_AUTO_CMD_DONE         (1 << 15)
+#define MSC_IMASK_DATA_FIFO_FULL        (1 << 14)
+#define MSC_IMASK_DATA_FIFO_EMP         (1 << 13)
+#define MSC_IMASK_CRC_RES_ERR           (1 << 12)
+#define MSC_IMASK_CRC_READ_ERR          (1 << 11)
+#define MSC_IMASK_CRC_WRITE_ERR         (1 << 10)
+#define MSC_IMASK_TIME_OUT_RES          (1 << 9)
+#define MSC_IMASK_TIME_OUT_READ         (1 << 8)
+#define MSC_IMASK_SDIO                  (1 << 7)
+#define MSC_IMASK_TXFIFO_WR_REQ         (1 << 6)
+#define MSC_IMASK_RXFIFO_RD_REQ         (1 << 5)
+#define MSC_IMASK_END_CMD_RES           (1 << 2)
+#define MSC_IMASK_PRG_DONE              (1 << 1)
+#define MSC_IMASK_DATA_TRAN_DONE        (1 << 0)
+
+/* MSC Interrupts Status Register (MSC_IREG) */
+#define MSC_IREG_AUTO_CMD_DONE          (1 << 15)
+#define MSC_IREG_DATA_FIFO_FULL         (1 << 14)
+#define MSC_IREG_DATA_FIFO_EMP          (1 << 13)
+#define MSC_IREG_CRC_RES_ERR            (1 << 12)
+#define MSC_IREG_CRC_READ_ERR           (1 << 11)
+#define MSC_IREG_CRC_WRITE_ERR          (1 << 10)
+#define MSC_IREG_TIMEOUT_RES            (1 << 9)
+#define MSC_IREG_TIMEOUT_READ           (1 << 8)
+#define MSC_IREG_SDIO                   (1 << 7)
+#define MSC_IREG_TXFIFO_WR_REQ          (1 << 6)
+#define MSC_IREG_RXFIFO_RD_REQ          (1 << 5)
+#define MSC_IREG_END_CMD_RES            (1 << 2)
+#define MSC_IREG_PRG_DONE               (1 << 1)
+#define MSC_IREG_DATA_TRAN_DONE         (1 << 0)
+
+/* MSC Low Power Mode Register (MSC_LPM) */
+#define MSC_SET_HISPD                   (1 << 31)
+#define MSC_SET_LPM                     (1 << 0)
+
+#ifndef __MIPS_ASSEMBLER
+
+/***************************************************************************
+ * MSC
+ ***************************************************************************/
+/* n = 0, 1 (MSC0, MSC1) */
+
+#define __msc_start_op(n) \
+        ( REG_MSC_STRPCL(n) = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
+
+#define __msc_set_resto(n, to)          ( REG_MSC_RESTO(n) = to )
+#define __msc_set_rdto(n, to)           ( REG_MSC_RDTO(n) = to )
+#define __msc_set_cmd(n, cmd)           ( REG_MSC_CMD(n) = cmd )
+#define __msc_set_arg(n, arg)           ( REG_MSC_ARG(n) = arg )
+#define __msc_set_nob(n, nob)           ( REG_MSC_NOB(n) = nob )
+#define __msc_get_nob(n)                ( REG_MSC_NOB(n) )
+#define __msc_set_blklen(n, len)        ( REG_MSC_BLKLEN(n) = len )
+#define __msc_set_cmdat(n, cmdat)       ( REG_MSC_CMDAT(n) = cmdat )
+
+#define __msc_set_cmdat_bus_width1(n)                   \
+do {                                                    \
+        REG_MSC_CMDAT(n) &= ~MSC_CMDAT_BUS_WIDTH_MASK;  \
+        REG_MSC_CMDAT(n) |= MSC_CMDAT_BUS_WIDTH_1BIT;   \
+} while(0)
+
+#define __msc_set_cmdat_bus_width4(n)                   \
+do {                                                    \
+        REG_MSC_CMDAT(n) &= ~MSC_CMDAT_BUS_WIDTH_MASK;  \
+        REG_MSC_CMDAT(n) |= MSC_CMDAT_BUS_WIDTH_4BIT;   \
+} while(0)
+
+#define __msc_set_cmdat_dma_en(n)       ( REG_MSC_CMDAT(n) |= MSC_CMDAT_DMA_EN )
+#define __msc_set_cmdat_init(n)         ( REG_MSC_CMDAT(n) |= MSC_CMDAT_INIT )
+#define __msc_set_cmdat_busy(n)         ( REG_MSC_CMDAT(n) |= MSC_CMDAT_BUSY )
+#define __msc_set_cmdat_stream(n)       ( REG_MSC_CMDAT(n) |= MSC_CMDAT_STREAM_BLOCK )
+#define __msc_set_cmdat_block(n)        ( REG_MSC_CMDAT(n) &= ~MSC_CMDAT_STREAM_BLOCK )
+#define __msc_set_cmdat_read(n)         ( REG_MSC_CMDAT(n) &= ~MSC_CMDAT_WRITE )
+#define __msc_set_cmdat_write(n)        ( REG_MSC_CMDAT(n) |= MSC_CMDAT_WRITE )
+#define __msc_set_cmdat_data_en(n)      ( REG_MSC_CMDAT(n) |= MSC_CMDAT_DATA_EN )
+
+/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
+#define __msc_set_cmdat_res_format(n, r)                                \
+do {                                                            \
+        REG_MSC_CMDAT(n) &= ~MSC_CMDAT_RESPONSE_MASK;   \
+        REG_MSC_CMDAT(n) |= (r);                                        \
+} while(0)
+
+#define __msc_clear_cmdat(n) \
+  REG_MSC_CMDAT(n) &= ~( MSC_CMDAT_STOP_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
+  MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE | \
+  MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_MASK )
+
+#define __msc_get_imask(n)              ( REG_MSC_IMASK(n) )
+#define __msc_mask_all_intrs(n)         ( REG_MSC_IMASK(n) = 0xff )
+#define __msc_unmask_all_intrs(n)       ( REG_MSC_IMASK(n) = 0x00 )
+#define __msc_mask_rd(n)                ( REG_MSC_IMASK(n) |= MSC_IMASK_RXFIFO_RD_REQ )
+#define __msc_unmask_rd(n)              ( REG_MSC_IMASK(n) &= ~MSC_IMASK_RXFIFO_RD_REQ )
+#define __msc_mask_wr(n)                ( REG_MSC_IMASK(n) |= MSC_IMASK_TXFIFO_WR_REQ )
+#define __msc_unmask_wr(n)              ( REG_MSC_IMASK(n) &= ~MSC_IMASK_TXFIFO_WR_REQ )
+#define __msc_mask_endcmdres(n)         ( REG_MSC_IMASK(n) |= MSC_IMASK_END_CMD_RES )
+#define __msc_unmask_endcmdres(n)       ( REG_MSC_IMASK(n) &= ~MSC_IMASK_END_CMD_RES )
+#define __msc_mask_datatrandone(n)      ( REG_MSC_IMASK(n) |= MSC_IMASK_DATA_TRAN_DONE )
+#define __msc_unmask_datatrandone(n)    ( REG_MSC_IMASK(n) &= ~MSC_IMASK_DATA_TRAN_DONE )
+#define __msc_mask_prgdone(n)           ( REG_MSC_IMASK(n) |= MSC_IMASK_PRG_DONE )
+#define __msc_unmask_prgdone(n)         ( REG_MSC_IMASK(n) &= ~MSC_IMASK_PRG_DONE )
+
+/* m=0,1,2,3,4,5,6,7 */
+#define __msc_set_clkrt(n, m)   \
+do {                            \
+        REG_MSC_CLKRT(n) = m;   \
+} while(0)
+
+#define __msc_get_ireg(n)                       ( REG_MSC_IREG(n) )
+#define __msc_ireg_rd(n)                        ( REG_MSC_IREG(n) & MSC_IREG_RXFIFO_RD_REQ )
+#define __msc_ireg_wr(n)                        ( REG_MSC_IREG(n) & MSC_IREG_TXFIFO_WR_REQ )
+#define __msc_ireg_end_cmd_res(n)               ( REG_MSC_IREG(n) & MSC_IREG_END_CMD_RES )
+#define __msc_ireg_data_tran_done(n)            ( REG_MSC_IREG(n) & MSC_IREG_DATA_TRAN_DONE )
+#define __msc_ireg_prg_done(n)                  ( REG_MSC_IREG(n) & MSC_IREG_PRG_DONE )
+#define __msc_ireg_clear_end_cmd_res(n)         ( REG_MSC_IREG(n) = MSC_IREG_END_CMD_RES )
+#define __msc_ireg_clear_data_tran_done(n)      ( REG_MSC_IREG(n) = MSC_IREG_DATA_TRAN_DONE )
+#define __msc_ireg_clear_prg_done(n)            ( REG_MSC_IREG(n) = MSC_IREG_PRG_DONE )
+
+#define __msc_get_stat(n)               ( REG_MSC_STAT(n) )
+#define __msc_stat_not_end_cmd_res(n)   ( (REG_MSC_STAT(n) & MSC_STAT_END_CMD_RES) == 0)
+#define __msc_stat_crc_err(n) \
+  ( REG_MSC_STAT(n) & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
+#define __msc_stat_res_crc_err(n)       ( REG_MSC_STAT(n) & MSC_STAT_CRC_RES_ERR )
+#define __msc_stat_rd_crc_err(n)        ( REG_MSC_STAT(n) & MSC_STAT_CRC_READ_ERROR )
+#define __msc_stat_wr_crc_err(n)        ( REG_MSC_STAT(n) & MSC_STAT_CRC_WRITE_ERROR_YES )
+#define __msc_stat_resto_err(n)         ( REG_MSC_STAT(n) & MSC_STAT_TIME_OUT_RES )
+#define __msc_stat_rdto_err(n)          ( REG_MSC_STAT(n) & MSC_STAT_TIME_OUT_READ )
+
+#define __msc_rd_resfifo(n)             ( REG_MSC_RES(n) )
+#define __msc_rd_rxfifo(n)              ( REG_MSC_RXFIFO(n) )
+#define __msc_wr_txfifo(n, v)           ( REG_MSC_TXFIFO(n) = v )
+
+#define __msc_reset(n)                                          \
+do {                                                            \
+        REG_MSC_STRPCL(n) = MSC_STRPCL_RESET;                   \
+        while (REG_MSC_STAT(n) & MSC_STAT_IS_RESETTING);                \
+} while (0)
+
+#define __msc_start_clk(n)                                      \
+do {                                                            \
+        REG_MSC_STRPCL(n) = MSC_STRPCL_CLOCK_CONTROL_START;     \
+} while (0)
+
+#define __msc_stop_clk(n)                                       \
+do {                                                            \
+        REG_MSC_STRPCL(n) = MSC_STRPCL_CLOCK_CONTROL_STOP;      \
+} while (0)
+
+#define MMC_CLK 19169200
+#define SD_CLK  24576000
+
+/* msc_clk should little than pclk and little than clk retrieve from card */
+#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv)         \
+do {                                                            \
+        unsigned int rate, pclk, i;                             \
+        pclk = dev_clk;                                         \
+        rate = type?SD_CLK:MMC_CLK;                             \
+        if (msc_clk && msc_clk < pclk)                          \
+                pclk = msc_clk;                                 \
+        i = 0;                                                  \
+        while (pclk < rate)                                     \
+        {                                                       \
+                i ++;                                           \
+                rate >>= 1;                                     \
+        }                                                       \
+        lv = i;                                                 \
+} while(0)
+
+/* divide rate to little than or equal to 400kHz */
+#define __msc_calc_slow_clk_divisor(type, lv)                   \
+do {                                                            \
+        unsigned int rate, i;                                   \
+        rate = (type?SD_CLK:MMC_CLK)/1000/400;                  \
+        i = 0;                                                  \
+        while (rate > 0)                                        \
+        {                                                       \
+                rate >>= 1;                                     \
+                i ++;                                           \
+        }                                                       \
+        lv = i;                                                 \
+} while(0)
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define NEMC_BASE       0xB3410000
+
+/*************************************************************************
+ * NEMC (External Memory Controller for NAND)
+ *************************************************************************/
+
+#define NEMC_NFCSR      (NEMC_BASE + 0x50) /* NAND Flash Control/Status Register */
+#define NEMC_SMCR       (NEMC_BASE + 0x14)  /* Static Memory Control Register 1 */
+#define NEMC_PNCR       (NEMC_BASE + 0x100)
+#define NEMC_PNDR       (NEMC_BASE + 0x104)
+#define NEMC_BITCNT     (NEMC_BASE + 0x108)
+
+#define REG_NEMC_NFCSR  REG32(NEMC_NFCSR)
+#define REG_NEMC_SMCR1  REG32(NEMC_SMCR)
+#define REG_NEMC_PNCR   REG32(NEMC_PNCR)
+#define REG_NEMC_PNDR   REG32(NEMC_PNDR)
+#define REG_NEMC_BITCNT REG32(NEMC_BITCNT)
+
+/* NAND Flash Control/Status Register */
+#define NEMC_NFCSR_NFCE4        (1 << 7) /* NAND Flash Enable */
+#define NEMC_NFCSR_NFE4         (1 << 6) /* NAND Flash FCE# Assertion Enable */
+#define NEMC_NFCSR_NFCE3        (1 << 5)
+#define NEMC_NFCSR_NFE3         (1 << 4)
+#define NEMC_NFCSR_NFCE2        (1 << 3)
+#define NEMC_NFCSR_NFE2         (1 << 2)
+#define NEMC_NFCSR_NFCE1        (1 << 1)
+#define NEMC_NFCSR_NFE1         (1 << 0)
+
+#define UDC_BASE        0xB3440000
+
+/*************************************************************************
+ * USB Device
+ *************************************************************************/
+#define USB_BASE  UDC_BASE
+
+#define USB_FADDR               (USB_BASE + 0x00) /* Function Address 8-bit */
+#define USB_POWER               (USB_BASE + 0x01) /* Power Managemetn 8-bit */
+#define USB_INTRIN              (USB_BASE + 0x02) /* Interrupt IN 16-bit */
+#define USB_INTROUT             (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
+#define USB_INTRINE             (USB_BASE + 0x06) /* Intr IN enable 16-bit */
+#define USB_INTROUTE            (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
+#define USB_INTRUSB             (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
+#define USB_INTRUSBE            (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
+#define USB_FRAME               (USB_BASE + 0x0c) /* Frame number 16-bit */
+#define USB_INDEX               (USB_BASE + 0x0e) /* Index register 8-bit */
+#define USB_TESTMODE            (USB_BASE + 0x0f) /* USB test mode 8-bit */
+
+#define USB_CSR0                (USB_BASE + 0x12) /* EP0 CSR 16-bit */
+#define USB_COUNT0              (USB_BASE + 0x18) /* EP0 OUT FIFO count 8-bit */
+
+#define USB_INMAXP              (USB_BASE + 0x10) /* EP1-15 IN Max Pkt Size 16-bit */
+#define USB_INCSR               (USB_BASE + 0x12) /* EP1-15 IN CSR LSB 8/16bit */
+#define USB_INCSRH              (USB_BASE + 0x13) /* EP1-15 IN CSR MSB 8-bit */
+#define USB_OUTMAXP             (USB_BASE + 0x14) /* EP1-15 OUT Max Pkt Size 16-bit */
+#define USB_OUTCSR              (USB_BASE + 0x16) /* EP1-15 OUT CSR LSB 8/16bit */
+#define USB_OUTCSRH             (USB_BASE + 0x17) /* EP1-15 OUT CSR MSB 8-bit */
+#define USB_OUTCOUNT            (USB_BASE + 0x18) /* EP1-15 OUT FIFO count 16-bit */
+
+#define USB_FIFO_EP(n)          (USB_BASE + (n)*4 + 0x20)
+
+#define USB_EPINFO              (USB_BASE + 0x78) /* Endpoint information */
+#define USB_RAMINFO             (USB_BASE + 0x79) /* RAM information */
+
+#define USB_INTR                (USB_BASE + 0x200) /* DMA pending interrupts */
+#define USB_CNTL(n)             (USB_BASE + (n)*0x10 + 0x204) /* DMA channel n control */
+#define USB_ADDR(n)             (USB_BASE + (n)*0x10 + 0x208) /* DMA channel n AHB memory addr */
+#define USB_COUNT(n)            (USB_BASE + (n)*0x10 + 0x20c) /* DMA channel n byte count */
+
+/* Power register bit masks */
+#define USB_POWER_SUSPENDM      0x01
+#define USB_POWER_RESUME        0x04
+#define USB_POWER_HSMODE        0x10
+#define USB_POWER_HSENAB        0x20
+#define USB_POWER_SOFTCONN      0x40
+
+/* Interrupt register bit masks */
+#define USB_INTR_SUSPEND        0x01
+#define USB_INTR_RESUME         0x02
+#define USB_INTR_RESET          0x04
+
+#define USB_INTR_EP(n)          (1 << (n))
+
+/* CSR0 bit masks */
+#define USB_CSR0_OUTPKTRDY      0x01
+#define USB_CSR0_INPKTRDY       0x02
+#define USB_CSR0_SENTSTALL      0x04
+#define USB_CSR0_DATAEND        0x08
+#define USB_CSR0_SETUPEND       0x10
+#define USB_CSR0_SENDSTALL      0x20
+#define USB_CSR0_SVDOUTPKTRDY   0x40
+#define USB_CSR0_SVDSETUPEND    0x80
+#define USB_CSR0_FLUSHFIFO      0x100
+
+/* Endpoint CSR register bits */
+#define USB_INCSRH_AUTOSET      0x80
+#define USB_INCSRH_ISO          0x40
+#define USB_INCSRH_MODE         0x20
+#define USB_INCSRH_DMAREQENAB   0x10
+#define USB_INCSRH_FRCDATATOG   0x08
+#define USB_INCSRH_DMAREQMODE   0x04
+#define USB_INCSR_CDT           0x40
+#define USB_INCSR_SENTSTALL     0x20
+#define USB_INCSR_SENDSTALL     0x10
+#define USB_INCSR_FF            0x08
+#define USB_INCSR_UNDERRUN      0x04
+#define USB_INCSR_FFNOTEMPT     0x02
+#define USB_INCSR_INPKTRDY      0x01
+#define USB_OUTCSRH_AUTOCLR     0x80
+#define USB_OUTCSRH_ISO         0x40
+#define USB_OUTCSRH_DMAREQENAB  0x20
+#define USB_OUTCSRH_DNYT        0x10
+#define USB_OUTCSRH_DMAREQMODE  0x08
+#define USB_OUTCSR_CDT          0x80
+#define USB_OUTCSR_SENTSTALL    0x40
+#define USB_OUTCSR_SENDSTALL    0x20
+#define USB_OUTCSR_FF           0x10
+#define USB_OUTCSR_DATAERR      0x08
+#define USB_OUTCSR_OVERRUN      0x04
+#define USB_OUTCSR_FFFULL       0x02
+#define USB_OUTCSR_OUTPKTRDY    0x01
+
+/* Testmode register bits */
+#define USB_TEST_SE0NAK         0x01
+#define USB_TEST_J              0x02
+#define USB_TEST_K              0x04
+#define USB_TEST_PACKET         0x08
+#define USB_TEST_FORCE_HS       0x10
+#define USB_TEST_FORCE_FS       0x20
+#define USB_TEST_ALL            ( USB_TEST_SE0NAK | USB_TEST_J         \
+                                | USB_TEST_K | USB_TEST_PACKET         \
+                                | USB_TEST_FORCE_HS | USB_TEST_FORCE_FS)
+
+/* DMA control bits */
+#define USB_CNTL_ENA            0x01
+#define USB_CNTL_DIR_IN         0x02
+#define USB_CNTL_MODE_1         0x04
+#define USB_CNTL_INTR_EN        0x08
+#define USB_CNTL_EP(n)          ((n) << 4)
+#define USB_CNTL_BURST_0        (0 << 9)
+#define USB_CNTL_BURST_4        (1 << 9)
+#define USB_CNTL_BURST_8        (2 << 9)
+#define USB_CNTL_BURST_16       (3 << 9)
+
+/* DMA interrupt bits */
+#define USB_INTR_DMA_BULKIN     1
+#define USB_INTR_DMA_BULKOUT    2
+
+#define REG_USB_FADDR           REG8(USB_FADDR)
+#define REG_USB_POWER           REG8(USB_POWER)
+#define REG_USB_INTRIN          REG16(USB_INTRIN)
+#define REG_USB_INTROUT         REG16(USB_INTROUT)
+#define REG_USB_INTRINE         REG16(USB_INTRINE)
+#define REG_USB_INTROUTE        REG16(USB_INTROUTE)
+#define REG_USB_INTRUSB         REG8(USB_INTRUSB)
+#define REG_USB_INTRUSBE        REG8(USB_INTRUSBE)
+#define REG_USB_FRAME           REG16(USB_FRAME)
+#define REG_USB_INDEX           REG8(USB_INDEX)
+#define REG_USB_TESTMODE        REG8(USB_TESTMODE)
+
+#define REG_USB_CSR0            REG16(USB_CSR0)
+#define REG_USB_COUNT0          REG8(USB_COUNT0)
+
+#define REG_USB_INMAXP          REG16(USB_INMAXP)
+#define REG_USB_INCSR           REG16(USB_INCSR)
+#define REG_USB_INCSRH          REG8(USB_INCSRH)
+#define REG_USB_OUTMAXP         REG16(USB_OUTMAXP)
+#define REG_USB_OUTCSR          REG16(USB_OUTCSR)
+#define REG_USB_OUTCSRH         REG8(USB_OUTCSRH)
+#define REG_USB_OUTCOUNT        REG16(USB_OUTCOUNT)
+
+#define REG_USB_FIFO_EP(n)      REG32(USB_FIFO_EP(n))
+
+#define REG_USB_INTR            REG8(USB_INTR)
+#define REG_USB_CNTL(n)         REG16(USB_CNTL(n))
+#define REG_USB_ADDR(n)         REG32(USB_ADDR(n))
+#define REG_USB_COUNT(n)        REG32(USB_COUNT(n))
+
+#define REG_USB_EPINFO          REG8(USB_EPINFO)
+#define REG_USB_RAMINFO         REG8(USB_RAMINFO)
+
+/*
+ * One wire bus interface(OWI) address definition
+ */
+#define OWI_BASE        0xb0072000
+
+/*
+ * OWI registers offset address definition
+ */
+#define OWI_OWICFG_OFFSET       (0x00)  /* rw, 8, 0x00 */
+#define OWI_OWICTL_OFFSET       (0x04)  /* rw, 8, 0x00 */
+#define OWI_OWISTS_OFFSET       (0x08)  /* rw, 8, 0x00 */
+#define OWI_OWIDAT_OFFSET       (0x0c)  /* rw, 8, 0x00 */
+#define OWI_OWIDIV_OFFSET       (0x10)  /* rw, 8, 0x00 */
+
+/*
+ * OWI registers address definition
+ */
+#define OWI_OWICFG      (OWI_BASE + OWI_OWICFG_OFFSET)
+#define OWI_OWICTL      (OWI_BASE + OWI_OWICTL_OFFSET)
+#define OWI_OWISTS      (OWI_BASE + OWI_OWISTS_OFFSET)
+#define OWI_OWIDAT      (OWI_BASE + OWI_OWIDAT_OFFSET)
+#define OWI_OWIDIV      (OWI_BASE + OWI_OWIDIV_OFFSET)
+
+/*
+ * OWI registers common define
+ */
+
+/* OWI configure register(OWICFG) */
+#define OWICFG_MODE     BIT7
+#define OWICFG_RDDATA   BIT6
+#define OWICFG_WRDATA   BIT5
+#define OWICFG_RDST     BIT4
+#define OWICFG_WR1RD    BIT3
+#define OWICFG_WR0      BIT2
+#define OWICFG_RST      BIT1
+#define OWICFG_ENA      BIT0
+
+/* OWI control register(OWICTL) */
+#define OWICTL_EBYTE    BIT2
+#define OWICTL_EBIT     BIT1
+#define OWICTL_ERST     BIT0
+
+/* OWI status register(OWISTS) */
+#define OWISTS_PST              BIT7
+#define OWISTS_BYTE_RDY         BIT2
+#define OWISTS_BIT_RDY          BIT1
+#define OWISTS_PST_RDY          BIT0
+
+/* OWI clock divide register(OWIDIV) */
+#define OWIDIV_CLKDIV_LSB       0
+#define OWIDIV_CLKDIV_MASK      BITS_H2L(5, OWIDIV_CLKDIV_LSB)
+
+#ifndef __MIPS_ASSEMBLER
+
+/* Basic ops */
+#define REG_OWI_OWICFG  REG8(OWI_OWICFG)
+#define REG_OWI_OWICTL  REG8(OWI_OWICTL)
+#define REG_OWI_OWISTS  REG8(OWI_OWISTS)
+#define REG_OWI_OWIDAT  REG8(OWI_OWIDAT)
+#define REG_OWI_OWIDIV  REG8(OWI_OWIDIV)
+
+#endif /* __MIPS_ASSEMBLER */
+
+/*
+ * Pulse-code modulation module(PCM) address definition
+ */
+#define PCM_BASE        0xb0071000
+
+/*
+ * pcm number, jz4760x has only PCM0
+ */
+
+#define PCM0            0
+#define PCM1            1
+
+/* PCM groups offset */
+#define PCM_GOS         0x3000
+
+/*
+ * PCM registers offset address definition
+ */
+#define PCM_PCTL_OFFSET         (0x00)  /* rw, 32, 0x00000000 */
+#define PCM_PCFG_OFFSET         (0x04)  /* rw, 32, 0x00000110 */
+#define PCM_PDP_OFFSET          (0x08)  /* rw, 32, 0x00000000 */
+#define PCM_PINTC_OFFSET        (0x0c)  /* rw, 32, 0x00000000 */
+#define PCM_PINTS_OFFSET        (0x10)  /* rw, 32, 0x00000100 */
+#define PCM_PDIV_OFFSET         (0x14)  /* rw, 32, 0x00000001 */
+
+/*
+ * PCM registers address definition
+ */
+#define PCM_PCTL(n)     (PCM_BASE + (n) * PCM_GOS + PCM_PCTL_OFFSET)
+#define PCM_PCFG(n)     (PCM_BASE + (n) * PCM_GOS + PCM_PCFG_OFFSET)
+#define PCM_PDP(n)      (PCM_BASE + (n) * PCM_GOS + PCM_PDP_OFFSET)
+#define PCM_PINTC(n)    (PCM_BASE + (n) * PCM_GOS + PCM_PINTC_OFFSET)
+#define PCM_PINTS(n)    (PCM_BASE + (n) * PCM_GOS + PCM_PINTS_OFFSET)
+#define PCM_PDIV(n)     (PCM_BASE + (n) * PCM_GOS + PCM_PDIV_OFFSET)
+
+/*
+ * CPM registers common define
+ */
+
+/* PCM controller control register (PCTL) */
+#define PCTL_ERDMA      BIT9
+#define PCTL_ETDMA      BIT8
+#define PCTL_LSMP       BIT7
+#define PCTL_ERPL       BIT6
+#define PCTL_EREC       BIT5
+#define PCTL_FLUSH      BIT4
+#define PCTL_RST        BIT3
+#define PCTL_CLKEN      BIT1
+#define PCTL_PCMEN      BIT0
+
+/* PCM controller configure register (PCFG) */
+#define PCFG_ISS_16BIT          BIT12
+#define PCFG_OSS_16BIT          BIT11
+#define PCFG_IMSBPOS            BIT10
+#define PCFG_OMSBPOS            BIT9
+#define PCFG_MODE_SLAVE         BIT0
+
+#define PCFG_SLOT_LSB           13
+#define PCFG_SLOT_MASK          BITS_H2L(14, PCFG_SLOT_LSB)
+#define PCFG_SLOT(val)          ((val) << PCFG_SLOT_LSB)
+
+#define PCFG_RFTH_LSB           5
+#define PCFG_RFTH_MASK          BITS_H2L(8, PCFG_RFTH_LSB)
+
+#define PCFG_TFTH_LSB           1
+#define PCFG_TFTH_MASK          BITS_H2L(4, PCFG_TFTH_LSB)
+
+/* PCM controller interrupt control register(PINTC) */
+#define PINTC_ETFS      BIT3
+#define PINTC_ETUR      BIT2
+#define PINTC_ERFS      BIT1
+#define PINTC_EROR      BIT0
+
+/* PCM controller interrupt status register(PINTS) */
+#define PINTS_RSTS      BIT14
+#define PINTS_TFS       BIT8
+#define PINTS_TUR       BIT7
+#define PINTS_RFS       BIT1
+#define PINTS_ROR       BIT0
+
+#define PINTS_TFL_LSB           9
+#define PINTS_TFL_MASK          BITS_H2L(13, PINTS_TFL_LSB)
+
+#define PINTS_RFL_LSB           2
+#define PINTS_RFL_MASK          BITS_H2L(6, PINTS_RFL_LSB)
+
+/* PCM controller clock division register(PDIV) */
+#define PDIV_SYNL_LSB           11
+#define PDIV_SYNL_MASK          BITS_H2L(16, PDIV_SYNL_LSB)
+
+#define PDIV_SYNDIV_LSB         6
+#define PDIV_SYNDIV_MASK        BITS_H2L(10, PDIV_SYNDIV_LSB)
+
+#define PDIV_CLKDIV_LSB         0
+#define PDIV_CLKDIV_MASK        BITS_H2L(5, PDIV_CLKDIV_LSB)
+
+#ifndef __MIPS_ASSEMBLER
+
+#define REG_PCM_PCTL(n)         REG32(PCM_PCTL(n))
+#define REG_PCM_PCFG(n)         REG32(PCM_PCFG(n))
+#define REG_PCM_PDP(n)          REG32(PCM_PDP(n))
+#define REG_PCM_PINTC(n)        REG32(PCM_PINTC(n))
+#define REG_PCM_PINTS(n)        REG32(PCM_PINTS(n))
+#define REG_PCM_PDIV(n)         REG32(PCM_PDIV(n))
+
+/*
+ * PCM_DIN, PCM_DOUT, PCM_CLK, PCM_SYN
+ */
+#define __gpio_as_pcm(n)                                                \
+do {                                                                    \
+        switch(n) {                                                     \
+        case PCM0:              __gpio_as_pcm0();break;                 \
+        case PCM1:              __gpio_as_pcm1();break;                 \
+        }                                                               \
+                                                                        \
+} while (0)
+
+#define __pcm_enable(n)                 (REG_PCM_PCTL(n) |= PCTL_PCMEN)
+#define __pcm_disable(n)                (REG_PCM_PCTL(n) &= ~PCTL_PCMEN)
+
+#define __pcm_clk_enable(n)             (REG_PCM_PCTL(n) |= PCTL_CLKEN)
+#define __pcm_clk_disable(n)            (REG_PCM_PCTL(n) &= ~PCTL_CLKEN)
+
+#define __pcm_reset(n)                  (REG_PCM_PCTL(n) |= PCTL_RST)
+#define __pcm_flush_fifo(n)             (REG_PCM_PCTL(n) |= PCTL_FLUSH)
+
+#define __pcm_enable_record(n)          (REG_PCM_PCTL(n) |= PCTL_EREC)
+#define __pcm_disable_record(n)         (REG_PCM_PCTL(n) &= ~PCTL_EREC)
+#define __pcm_enable_playback(n)        (REG_PCM_PCTL(n) |= PCTL_ERPL)
+#define __pcm_disable_playback(n)       (REG_PCM_PCTL(n) &= ~PCTL_ERPL)
+
+#define __pcm_enable_rxfifo(n)          __pcm_enable_record(n)
+#define __pcm_disable_rxfifo(n)         __pcm_disable_record(n)
+#define __pcm_enable_txfifo(n)          __pcm_enable_playback(n)
+#define __pcm_disable_txfifo(n)         __pcm_disable_playback(n)
+
+#define __pcm_last_sample(n)            (REG_PCM_PCTL(n) |= PCTL_LSMP)
+#define __pcm_zero_sample(n)            (REG_PCM_PCTL(n) &= ~PCTL_LSMP)
+
+#define __pcm_enable_transmit_dma(n)    (REG_PCM_PCTL(n) |= PCTL_ETDMA)
+#define __pcm_disable_transmit_dma(n)   (REG_PCM_PCTL(n) &= ~PCTL_ETDMA)
+#define __pcm_enable_receive_dma(n)     (REG_PCM_PCTL(n) |= PCTL_ERDMA)
+#define __pcm_disable_receive_dma(n)    (REG_PCM_PCTL(n) &= ~PCTL_ERDMA)
+
+#define __pcm_as_master(n)              (REG_PCM_PCFG(n) &= ~PCFG_MODE_SLAVE)
+#define __pcm_as_slave(n)               (REG_PCM_PCFG(n) |= PCFG_MODE_SLAVE)
+
+#define __pcm_set_transmit_trigger(n, val)              \
+do {                                                    \
+        REG_PCM_PCFG(n) &= ~PCFG_TFTH_MASK;             \
+        REG_PCM_PCFG(n) |= ((val) << PCFG_TFTH_LSB);    \
+                                                        \
+} while(0)
+
+#define __pcm_set_receive_trigger(n, val)               \
+do {                                                    \
+        REG_PCM_PCFG(n) &= ~PCFG_RFTH_MASK;             \
+        REG_PCM_PCFG(n) |= ((val) << PCFG_RFTH_LSB);    \
+                                                        \
+} while(0)
+
+#define __pcm_omsb_same_sync(n)         (REG_PCM_PCFG(n) &= ~PCFG_OMSBPOS)
+#define __pcm_omsb_next_sync(n)         (REG_PCM_PCFG(n) |= PCFG_OMSBPOS)
+
+#define __pcm_imsb_same_sync(n)         (REG_PCM_PCFG(n) &= ~PCFG_IMSBPOS)
+#define __pcm_imsb_next_sync(n)         (REG_PCM_PCFG(n) |= PCFG_IMSBPOS)
+
+#define __pcm_set_iss(n, val)                           \
+do {                                                    \
+        if ((val) == 16)                                \
+                REG_PCM_PCFG(n) |= PCFG_ISS_16BIT;      \
+        else                                            \
+                REG_PCM_PCFG(n) &= ~PCFG_ISS_16BIT;     \
+                                                        \
+} while (0)
+
+#define __pcm_set_oss(n, val)                           \
+do {                                                    \
+        if ((val) == 16)                                \
+                REG_PCM_PCFG(n) |= PCFG_OSS_16BIT;      \
+        else                                            \
+                REG_PCM_PCFG(n) &= ~PCFG_OSS_16BIT;     \
+                                                        \
+} while (0)                                             \
+
+#define __pcm_set_valid_slot(n, val)                                    \
+        (REG_PCM_PCFG(n) = (REG_PCM_PCFG(n) & ~PCFG_SLOT_MASK) | PCFG_SLOT(val))
+
+#define __pcm_write_data(n, val)        (REG_PCM_PDP(n) = (val))
+#define __pcm_read_data(n)              (REG_PCM_PDP(n))
+
+#define __pcm_enable_tfs_intr(n)        (REG_PCM_PINTC(n) |= PINTC_ETFS)
+#define __pcm_disable_tfs_intr(n)       (REG_PCM_PINTC(n) &= ~PINTC_ETFS)
+
+#define __pcm_enable_tur_intr(n)        (REG_PCM_PINTC(n) |= PINTC_ETUR)
+#define __pcm_disable_tur_intr(n)       (REG_PCM_PINTC(n) &= ~PINTC_ETUR)
+
+#define __pcm_enable_rfs_intr(n)        (REG_PCM_PINTC(n) |= PINTC_ERFS)
+#define __pcm_disable_rfs_intr(n)       (REG_PCM_PINTC(n) &= ~PINTC_ERFS)
+
+#define __pcm_enable_ror_intr(n)        (REG_PCM_PINTC(n) |= PINTC_EROR)
+#define __pcm_disable_ror_intr(n)       (REG_PCM_PINTC(n) &= ~PINTC_EROR)
+
+#define __pcm_ints_valid_tx(n)          (((REG_PCM_PINTS(n) & PINTS_TFL_MASK) >> PINTS_TFL_LSB))
+#define __pcm_ints_valid_rx(n)          (((REG_PCM_PINTS(n) & PINTS_RFL_MASK) >> PINTS_RFL_LSB))
+
+#define __pcm_set_clk_div(n, val)                                       \
+        (REG_PCM_PDIV(n) = (REG_PCM_PDIV(n) & ~PDIV_CLKDIV_MASK) | ((val) << PDIV_CLKDIV_LSB))
+
+#define __pcm_set_clk_rate(n, sysclk, pcmclk)                           \
+        __pcm_set_clk_div((n), ((sysclk) / (pcmclk) - 1))
+
+#define __pcm_set_sync_div(n, val)                                      \
+        (REG_PCM_PDIV(n) = (REG_PCM_PDIV(n) & ~PDIV_SYNDIV_MASK) | ((val) << PDIV_SYNDIV_LSB))
+
+#define __pcm_set_sync_rate(n, pcmclk, sync)                            \
+        __pcm_set_sync_div((n), ((pcmclk) / (8 * (sync)) - 1))
+
+#define __pcm_set_sync_len(n, val)                                      \
+        (REG_PCM_PDIV(n) = (REG_PCM_PDIV(n) & ~PDIV_SYNL_MASK) | ((val) << PDIV_SYNL_LSB))
+
+#endif /* __MIPS_ASSEMBLER */
+
+/*
+ * Real time clock module(RTC) address definition
+ */
+#define RTC_BASE        0xb0003000
+
+/*
+ * RTC registers offset address definition
+ */
+#define RTC_RTCCR_OFFSET        (0x00)  /* rw, 32, 0x00000081 */
+#define RTC_RTCSR_OFFSET        (0x04)  /* rw, 32, 0x???????? */
+#define RTC_RTCSAR_OFFSET       (0x08)  /* rw, 32, 0x???????? */
+#define RTC_RTCGR_OFFSET        (0x0c)  /* rw, 32, 0x0??????? */
+
+#define RTC_HCR_OFFSET          (0x20)  /* rw, 32, 0x00000000 */
+#define RTC_HWFCR_OFFSET        (0x24)  /* rw, 32, 0x0000???0 */
+#define RTC_HRCR_OFFSET         (0x28)  /* rw, 32, 0x00000??0 */
+#define RTC_HWCR_OFFSET         (0x2c)  /* rw, 32, 0x00000008 */
+#define RTC_HWRSR_OFFSET        (0x30)  /* rw, 32, 0x00000000 */
+#define RTC_HSPR_OFFSET         (0x34)  /* rw, 32, 0x???????? */
+#define RTC_WENR_OFFSET         (0x3c)  /* rw, 32, 0x00000000 */
+
+/*
+ * RTC registers address definition
+ */
+#define RTC_RTCCR       (RTC_BASE + RTC_RTCCR_OFFSET)
+#define RTC_RTCSR       (RTC_BASE + RTC_RTCSR_OFFSET)
+#define RTC_RTCSAR      (RTC_BASE + RTC_RTCSAR_OFFSET)
+#define RTC_RTCGR       (RTC_BASE + RTC_RTCGR_OFFSET)
+
+#define RTC_HCR         (RTC_BASE + RTC_HCR_OFFSET)
+#define RTC_HWFCR       (RTC_BASE + RTC_HWFCR_OFFSET)
+#define RTC_HRCR        (RTC_BASE + RTC_HRCR_OFFSET)
+#define RTC_HWCR        (RTC_BASE + RTC_HWCR_OFFSET)
+#define RTC_HWRSR       (RTC_BASE + RTC_HWRSR_OFFSET)
+#define RTC_HSPR        (RTC_BASE + RTC_HSPR_OFFSET)
+#define RTC_WENR        (RTC_BASE + RTC_WENR_OFFSET)
+
+/*
+ * RTC registers common define
+ */
+
+/* RTC control register(RTCCR) */
+#define RTCCR_WRDY              BIT7
+#define RTCCR_1HZ               BIT6
+#define RTCCR_1HZIE             BIT5
+#define RTCCR_AF                BIT4
+#define RTCCR_AIE               BIT3
+#define RTCCR_AE                BIT2
+#define RTCCR_SELEXC            BIT1
+#define RTCCR_RTCE              BIT0
+
+/* RTC regulator register(RTCGR) */
+#define RTCGR_LOCK              BIT31
+
+#define RTCGR_ADJC_LSB          16
+#define RTCGR_ADJC_MASK         BITS_H2L(25, RTCGR_ADJC_LSB)
+
+#define RTCGR_NC1HZ_LSB         0
+#define RTCGR_NC1HZ_MASK        BITS_H2L(15, RTCGR_NC1HZ_LSB)
+
+/* Hibernate control register(HCR) */
+#define HCR_PD                  BIT0
+
+/* Hibernate wakeup filter counter register(HWFCR) */
+#define HWFCR_LSB               5
+#define HWFCR_MASK              BITS_H2L(15, HWFCR_LSB)
+#define HWFCR_WAIT_TIME(ms)     (((ms) << HWFCR_LSB) > HWFCR_MASK ? HWFCR_MASK : ((ms) << HWFCR_LSB))
+
+/* Hibernate reset counter register(HRCR) */
+#define HRCR_LSB                5
+#define HRCR_MASK               BITS_H2L(11, HRCR_LSB)
+#define HRCR_WAIT_TIME(ms)     (((ms) << HRCR_LSB) > HRCR_MASK ? HRCR_MASK : ((ms) << HRCR_LSB))
+
+/* Hibernate wakeup control register(HWCR) */
+#define HWCR_EPDET              BIT3
+#define HWCR_WKUPVL             BIT2
+#define HWCR_EALM               BIT0
+
+/* Hibernate wakeup status register(HWRSR) */
+#define HWRSR_APD               BIT8
+#define HWRSR_HR                BIT5
+#define HWRSR_PPR               BIT4
+#define HWRSR_PIN               BIT1
+#define HWRSR_ALM               BIT0
+
+/* write enable pattern register(WENR) */
+#define WENR_WEN                BIT31
+
+#define WENR_WENPAT_LSB         0
+#define WENR_WENPAT_MASK        BITS_H2L(15, WENR_WENPAT_LSB)
+#define WENR_WENPAT_WRITABLE    (0xa55a)
+
+/* Hibernate scratch pattern register(HSPR) */
+#define HSPR_RTCV               0x52544356      /* The value is 'RTCV', means rtc is valid */ 
+
+#ifndef __MIPS_ASSEMBLER
+
+/* Waiting for the RTC register writing finish */
+#define __wait_write_ready()                                            \
+do {                                                                    \
+        int timeout = 0x1000;                                           \
+        while (!(rtc_read_reg(RTC_RTCCR) & RTCCR_WRDY) && timeout--);   \
+}while(0);
+
+/* Waiting for the RTC register writable */
+#define __wait_writable()                                               \
+do {                                                                    \
+        int timeout = 0x1000;                                           \
+        __wait_write_ready();                                           \
+        OUTREG32(RTC_WENR, WENR_WENPAT_WRITABLE);                       \
+        __wait_write_ready();                                           \
+        while (!(rtc_read_reg(RTC_WENR) & WENR_WEN) && timeout--);      \
+}while(0);
+
+/* Basic RTC ops */
+#define rtc_read_reg(reg)                               \
+({                                                      \
+        unsigned int data, timeout = 0x10000;           \
+        do {                                            \
+                data = INREG32(reg);                    \
+        } while (INREG32(reg) != data && timeout--);    \
+        data;                                           \
+})
+
+#define rtc_write_reg(reg, data)                        \
+do {                                                    \
+        __wait_writable();                              \
+        OUTREG32(reg, data);                            \
+        __wait_write_ready();                           \
+}while(0);
+
+#define rtc_set_reg(reg, data)  rtc_write_reg(reg, rtc_read_reg(reg) | (data))
+#define rtc_clr_reg(reg, data)  rtc_write_reg(reg, rtc_read_reg(reg) & ~(data))
+
+#endif /* __MIPS_ASSEMBLER */
+
+/*
+ * SAR A/D Controller(SADC) address definition
+ */
+#define SADC_BASE               0xb0070000
+
+/*
+ * SADC registers offset definition
+ */
+#define SADC_ADENA_OFFSET       (0x00)  /* rw,  8, 0x00 */
+#define SADC_ADCFG_OFFSET       (0x04)  /* rw, 32, 0x0002000c */
+#define SADC_ADCTRL_OFFSET      (0x08)  /* rw,  8, 0x3f */
+#define SADC_ADSTATE_OFFSET     (0x0c)  /* rw,  8, 0x00 */
+#define SADC_ADSAME_OFFSET      (0x10)  /* rw, 16, 0x0000 */
+#define SADC_ADWAIT_OFFSET      (0x14)  /* rw, 16, 0x0000 */
+#define SADC_ADTCH_OFFSET       (0x18)  /* rw, 32, 0x00000000 */
+#define SADC_ADVDAT_OFFSET      (0x1c)  /* rw, 16, 0x0000 */
+#define SADC_ADADAT_OFFSET      (0x20)  /* rw, 16, 0x0000 */
+#define SADC_ADFLT_OFFSET       (0x24)  /* rw, 16, 0x0000 */
+#define SADC_ADCLK_OFFSET       (0x28)  /* rw, 32, 0x00000000 */
+
+/*
+ * SADC registers address definition
+ */
+#define SADC_ADENA              (SADC_BASE + SADC_ADENA_OFFSET)  /* ADC Enable Register */
+#define SADC_ADCFG              (SADC_BASE + SADC_ADCFG_OFFSET)  /* ADC Configure Register */
+#define SADC_ADCTRL             (SADC_BASE + SADC_ADCTRL_OFFSET) /* ADC Control Register */
+#define SADC_ADSTATE            (SADC_BASE + SADC_ADSTATE_OFFSET)/* ADC Status Register*/
+#define SADC_ADSAME             (SADC_BASE + SADC_ADSAME_OFFSET) /* ADC Same Point Time Register */
+#define SADC_ADWAIT             (SADC_BASE + SADC_ADWAIT_OFFSET) /* ADC Wait Time Register */
+#define SADC_ADTCH              (SADC_BASE + SADC_ADTCH_OFFSET)  /* ADC Touch Screen Data Register */
+#define SADC_ADVDAT             (SADC_BASE + SADC_ADVDAT_OFFSET) /* ADC VBAT Data Register */
+#define SADC_ADADAT             (SADC_BASE + SADC_ADADAT_OFFSET) /* ADC AUX Data Register */
+#define SADC_ADFLT              (SADC_BASE + SADC_ADFLT_OFFSET)  /* ADC Filter Register */
+#define SADC_ADCLK              (SADC_BASE + SADC_ADCLK_OFFSET)  /* ADC Clock Divide Register */
+
+/*
+ * SADC registers common define
+ */
+
+/* ADC Enable Register (ADENA) */
+#define ADENA_POWER             BIT7
+#define ADENA_SLP_MD            BIT6
+#define ADENA_PENDEN            BIT3
+#define ADENA_TCHEN             BIT2
+#define ADENA_VBATEN            BIT1
+#define ADENA_AUXEN             BIT0
+
+/* ADC Configure Register (ADCFG) */
+#define ADCFG_SPZZ              BIT31
+#define ADCFG_VBAT_SEL          BIT30
+#define ADCFG_DMA_EN            BIT15
+
+#define ADCFG_XYZ_LSB           13
+#define ADCFG_XYZ_MASK          BITS_H2L(14, ADCFG_XYZ_LSB)
+ #define ADCFG_XYZ_XYS          (0x0 << ADCFG_XYZ_LSB)
+ #define ADCFG_XYZ_XYD          (0x1 << ADCFG_XYZ_LSB)
+ #define ADCFG_XYZ_XYZ1Z2       (0x2 << ADCFG_XYZ_LSB)
+
+#define ADCFG_SNUM_LSB          10
+#define ADCFG_SNUM_MASK         BITS_H2L(12, ADCFG_SNUM_LSB)
+ #define ADCFG_SNUM(n)          (((n) <= 6 ? ((n)-1) : ((n)-2)) << ADCFG_SNUM_LSB)
+
+#define ADCFG_CMD_LSB           0
+#define ADCFG_CMD_MASK          BITS_H2L(1, ADCFG_CMD_LSB)
+ #define ADCFG_CMD_AUX(n)       ((n) << ADCFG_CMD_LSB)
+
+/* ADC Control Register (ADCCTRL) */
+#define ADCTRL_SLPENDM          BIT5
+#define ADCTRL_PENDM            BIT4
+#define ADCTRL_PENUM            BIT3
+#define ADCTRL_DTCHM            BIT2
+#define ADCTRL_VRDYM            BIT1
+#define ADCTRL_ARDYM            BIT0
+#define ADCTRL_MASK_ALL         (ADCTRL_SLPENDM | ADCTRL_PENDM | ADCTRL_PENUM \
+                                | ADCTRL_DTCHM | ADCTRL_VRDYM | ADCTRL_ARDYM)
+
+/*  ADC Status Register  (ADSTATE) */
+#define ADSTATE_SLP_RDY         BIT7
+#define ADSTATE_SLPEND          BIT5
+#define ADSTATE_PEND            BIT4
+#define ADSTATE_PENU            BIT3
+#define ADSTATE_DTCH            BIT2
+#define ADSTATE_VRDY            BIT1
+#define ADSTATE_ARDY            BIT0
+
+/* ADC Same Point Time Register (ADSAME) */
+#define ADSAME_SCNT_LSB         0
+#define ADSAME_SCNT_MASK        BITS_H2L(15, ADSAME_SCNT_LSB)
+
+/* ADC Wait Pen Down Time Register (ADWAIT) */
+#define ADWAIT_WCNT_LSB         0
+#define ADWAIT_WCNT_MASK        BITS_H2L(15, ADWAIT_WCNT_LSB)
+
+/* ADC Touch Screen Data Register (ADTCH) */
+#define ADTCH_TYPE1             BIT31
+#define ADTCH_TYPE0             BIT15
+
+#define ADTCH_DATA1_LSB         16
+#define ADTCH_DATA1_MASK        BITS_H2L(27, ADTCH_DATA1_LSB)
+
+#define ADTCH_DATA0_LSB         0
+#define ADTCH_DATA0_MASK        BITS_H2L(11, ADTCH_DATA0_LSB)
+
+/* ADC VBAT Date Register (ADVDAT) */
+#define ADVDAT_VDATA_LSB        0
+#define ADVDAT_VDATA_MASK       BITS_H2L(11, ADVDAT_VDATA_LSB)
+
+/* ADC AUX Data Register (ADADAT) */
+#define ADADAT_ADATA_LSB        0
+#define ADADAT_ADATA_MASK       BITS_H2L(11, ADADAT_ADATA_LSB)
+
+/*  ADC Clock Divide Register (ADCLK) */
+#define ADCLK_CLKDIV_MS_LSB     16
+#define ADCLK_CLKDIV_MS_MASK    BITS_H2L(31, ADCLK_CLKDIV_MS_LSB)
+
+#define ADCLK_CLKDIV_US_LSB     8
+#define ADCLK_CLKDIV_US_MASK    BITS_H2L(15, ADCLK_CLKDIV_US_LSB)
+
+#define ADCLK_CLKDIV_LSB        0
+#define ADCLK_CLKDIV_MASK       BITS_H2L(7, ADCLK_CLKDIV_LSB)
+
+/* ADC Filter Register (ADFLT) */
+#define ADFLT_FLT_EN            BIT15
+
+#define ADFLT_FLT_D_LSB         0
+#define ADFLT_FLT_D_MASK        BITS_H2L(11, ADFLT_FLT_D_LSB)
+
+#ifndef __MIPS_ASSEMBLER
+
+#define REG_SADC_ADENA          REG8(SADC_ADENA)
+#define REG_SADC_ADCFG          REG32(SADC_ADCFG)
+#define REG_SADC_ADCTRL         REG8(SADC_ADCTRL)
+#define REG_SADC_ADSTATE        REG8(SADC_ADSTATE)
+#define REG_SADC_ADSAME         REG16(SADC_ADSAME)
+#define REG_SADC_ADWAIT         REG16(SADC_ADWAIT)
+#define REG_SADC_ADTCH          REG32(SADC_ADTCH)
+#define REG_SADC_ADVDAT         REG16(SADC_ADVDAT)
+#define REG_SADC_ADADAT         REG16(SADC_ADADAT)
+#define REG_SADC_ADFLT          REG16(SADC_ADFLT)
+#define REG_SADC_ADCLK          REG32(SADC_ADCLK)
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define SCC_BASE        0xB0040000
+
+/*************************************************************************
+ * SCC
+ *************************************************************************/
+#define SCC_DR                  (SCC_BASE + 0x000)
+#define SCC_FDR                 (SCC_BASE + 0x004)
+#define SCC_CR                  (SCC_BASE + 0x008)
+#define SCC_SR                  (SCC_BASE + 0x00C)
+#define SCC_TFR                 (SCC_BASE + 0x010)
+#define SCC_EGTR                (SCC_BASE + 0x014)
+#define SCC_ECR                 (SCC_BASE + 0x018)
+#define SCC_RTOR                (SCC_BASE + 0x01C)
+
+#define REG_SCC_DR              REG8(SCC_DR)
+#define REG_SCC_FDR             REG8(SCC_FDR)
+#define REG_SCC_CR              REG32(SCC_CR)
+#define REG_SCC_SR              REG16(SCC_SR)
+#define REG_SCC_TFR             REG16(SCC_TFR)
+#define REG_SCC_EGTR            REG8(SCC_EGTR)
+#define REG_SCC_ECR             REG32(SCC_ECR)
+#define REG_SCC_RTOR            REG8(SCC_RTOR)
+
+/* SCC FIFO Data Count Register (SCC_FDR) */
+
+#define SCC_FDR_EMPTY           0x00
+#define SCC_FDR_FULL            0x10
+
+/* SCC Control Register (SCC_CR) */
+
+#define SCC_CR_SCCE             (1 << 31)
+#define SCC_CR_TRS              (1 << 30)
+#define SCC_CR_T2R              (1 << 29)
+#define SCC_CR_FDIV_BIT         24
+#define SCC_CR_FDIV_MASK        (0x3 << SCC_CR_FDIV_BIT)
+  #define SCC_CR_FDIV_1         (0 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is the same as device clock */
+  #define SCC_CR_FDIV_2         (1 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is half of device clock */
+#define SCC_CR_FLUSH            (1 << 23)
+#define SCC_CR_TRIG_BIT         16
+#define SCC_CR_TRIG_MASK        (0x3 << SCC_CR_TRIG_BIT)
+  #define SCC_CR_TRIG_1         (0 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 1 */
+  #define SCC_CR_TRIG_4         (1 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 4 */
+  #define SCC_CR_TRIG_8         (2 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 8 */
+  #define SCC_CR_TRIG_14        (3 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 14 */
+#define SCC_CR_TP               (1 << 15)
+#define SCC_CR_CONV             (1 << 14)
+#define SCC_CR_TXIE             (1 << 13)
+#define SCC_CR_RXIE             (1 << 12)
+#define SCC_CR_TENDIE           (1 << 11)
+#define SCC_CR_RTOIE            (1 << 10)
+#define SCC_CR_ECIE             (1 << 9)
+#define SCC_CR_EPIE             (1 << 8)
+#define SCC_CR_RETIE            (1 << 7)
+#define SCC_CR_EOIE             (1 << 6)
+#define SCC_CR_TSEND            (1 << 3)
+#define SCC_CR_PX_BIT           1
+#define SCC_CR_PX_MASK          (0x3 << SCC_CR_PX_BIT)
+  #define SCC_CR_PX_NOT_SUPPORT (0 << SCC_CR_PX_BIT) /* SCC does not support clock stop */
+  #define SCC_CR_PX_STOP_LOW    (1 << SCC_CR_PX_BIT) /* SCC_CLK stops at state low */
+  #define SCC_CR_PX_STOP_HIGH   (2 << SCC_CR_PX_BIT) /* SCC_CLK stops at state high */
+#define SCC_CR_CLKSTP           (1 << 0)
+
+/* SCC Status Register (SCC_SR) */
+
+#define SCC_SR_TRANS            (1 << 15)
+#define SCC_SR_ORER             (1 << 12)
+#define SCC_SR_RTO              (1 << 11)
+#define SCC_SR_PER              (1 << 10)
+#define SCC_SR_TFTG             (1 << 9)
+#define SCC_SR_RFTG             (1 << 8)
+#define SCC_SR_TEND             (1 << 7)
+#define SCC_SR_RETR_3           (1 << 4)
+#define SCC_SR_ECNTO            (1 << 0)
+
+#ifndef __MIPS_ASSEMBLER
+
+/***************************************************************************
+ * SCC
+ ***************************************************************************/
+
+#define __scc_enable()                  ( REG_SCC_CR |= SCC_CR_SCCE )
+#define __scc_disable()                 ( REG_SCC_CR &= ~SCC_CR_SCCE )
+
+#define __scc_set_tx_mode()             ( REG_SCC_CR |= SCC_CR_TRS )
+#define __scc_set_rx_mode()             ( REG_SCC_CR &= ~SCC_CR_TRS )
+
+#define __scc_enable_t2r()              ( REG_SCC_CR |= SCC_CR_T2R )
+#define __scc_disable_t2r()             ( REG_SCC_CR &= ~SCC_CR_T2R )
+
+#define __scc_clk_as_devclk()                   \
+do {                                            \
+  REG_SCC_CR &= ~SCC_CR_FDIV_MASK;              \
+  REG_SCC_CR |= SCC_CR_FDIV_1;                  \
+} while (0)
+
+#define __scc_clk_as_half_devclk()              \
+do {                                            \
+  REG_SCC_CR &= ~SCC_CR_FDIV_MASK;              \
+  REG_SCC_CR |= SCC_CR_FDIV_2;                  \
+} while (0)
+
+/* n=1,4,8,14 */
+#define __scc_set_fifo_trigger(n)               \
+do {                                            \
+  REG_SCC_CR &= ~SCC_CR_TRIG_MASK;              \
+  REG_SCC_CR |= SCC_CR_TRIG_##n;                \
+} while (0)
+
+#define __scc_set_protocol(p)                   \
+do {                                            \
+        if (p)                                  \
+                REG_SCC_CR |= SCC_CR_TP;        \
+        else                                    \
+                REG_SCC_CR &= ~SCC_CR_TP;       \
+} while (0)
+
+#define __scc_flush_fifo()              ( REG_SCC_CR |= SCC_CR_FLUSH )
+
+#define __scc_set_invert_mode()         ( REG_SCC_CR |= SCC_CR_CONV )
+#define __scc_set_direct_mode()         ( REG_SCC_CR &= ~SCC_CR_CONV )
+
+#define SCC_ERR_INTRS \
+    ( SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE )
+#define SCC_ALL_INTRS \
+    ( SCC_CR_TXIE | SCC_CR_RXIE | SCC_CR_TENDIE | SCC_CR_RTOIE | \
+      SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE )
+
+#define __scc_enable_err_intrs()        ( REG_SCC_CR |= SCC_ERR_INTRS )
+#define __scc_disable_err_intrs()       ( REG_SCC_CR &= ~SCC_ERR_INTRS )
+
+#define SCC_ALL_ERRORS \
+    ( SCC_SR_ORER | SCC_SR_RTO | SCC_SR_PER | SCC_SR_RETR_3 | SCC_SR_ECNTO)
+
+#define __scc_clear_errors()            ( REG_SCC_SR &= ~SCC_ALL_ERRORS )
+
+#define __scc_enable_all_intrs()        ( REG_SCC_CR |= SCC_ALL_INTRS )
+#define __scc_disable_all_intrs()       ( REG_SCC_CR &= ~SCC_ALL_INTRS )
+
+#define __scc_enable_tx_intr()          ( REG_SCC_CR |= SCC_CR_TXIE | SCC_CR_TENDIE )
+#define __scc_disable_tx_intr()         ( REG_SCC_CR &= ~(SCC_CR_TXIE | SCC_CR_TENDIE) )
+
+#define __scc_enable_rx_intr()          ( REG_SCC_CR |= SCC_CR_RXIE)
+#define __scc_disable_rx_intr()         ( REG_SCC_CR &= ~SCC_CR_RXIE)
+
+#define __scc_set_tsend()               ( REG_SCC_CR |= SCC_CR_TSEND )
+#define __scc_clear_tsend()             ( REG_SCC_CR &= ~SCC_CR_TSEND )
+
+#define __scc_set_clockstop()           ( REG_SCC_CR |= SCC_CR_CLKSTP )
+#define __scc_clear_clockstop()         ( REG_SCC_CR &= ~SCC_CR_CLKSTP )
+
+#define __scc_clockstop_low()                   \
+do {                                            \
+  REG_SCC_CR &= ~SCC_CR_PX_MASK;                \
+  REG_SCC_CR |= SCC_CR_PX_STOP_LOW;             \
+} while (0)
+
+#define __scc_clockstop_high()                  \
+do {                                            \
+  REG_SCC_CR &= ~SCC_CR_PX_MASK;                \
+  REG_SCC_CR |= SCC_CR_PX_STOP_HIGH;            \
+} while (0)
+
+/* SCC status checking */
+#define __scc_check_transfer_status()           ( REG_SCC_SR & SCC_SR_TRANS )
+#define __scc_check_rx_overrun_error()          ( REG_SCC_SR & SCC_SR_ORER )
+#define __scc_check_rx_timeout()                ( REG_SCC_SR & SCC_SR_RTO )
+#define __scc_check_parity_error()              ( REG_SCC_SR & SCC_SR_PER )
+#define __scc_check_txfifo_trigger()            ( REG_SCC_SR & SCC_SR_TFTG )
+#define __scc_check_rxfifo_trigger()            ( REG_SCC_SR & SCC_SR_RFTG )
+#define __scc_check_tx_end()                    ( REG_SCC_SR & SCC_SR_TEND )
+#define __scc_check_retx_3()                    ( REG_SCC_SR & SCC_SR_RETR_3 )
+#define __scc_check_ecnt_overflow()             ( REG_SCC_SR & SCC_SR_ECNTO )
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define SSI0_BASE       0xB0043000
+#define SSI1_BASE       0xB0044000
+#define SSI2_BASE       0xB0045000
+
+/*************************************************************************
+ * SSI (Synchronous Serial Interface)
+ *************************************************************************/
+/* n = 0, 1 (SSI0, SSI1) */
+#define SSI_DR(n)               (SSI0_BASE + 0x000 + (n)*0x1000)
+#define SSI_CR0(n)              (SSI0_BASE + 0x004 + (n)*0x1000)
+#define SSI_CR1(n)              (SSI0_BASE + 0x008 + (n)*0x1000)
+#define SSI_SR(n)               (SSI0_BASE + 0x00C + (n)*0x1000)
+#define SSI_ITR(n)              (SSI0_BASE + 0x010 + (n)*0x1000)
+#define SSI_ICR(n)              (SSI0_BASE + 0x014 + (n)*0x1000)
+#define SSI_GR(n)               (SSI0_BASE + 0x018 + (n)*0x1000)
+
+#define REG_SSI_DR(n)           REG32(SSI_DR(n))
+#define REG_SSI_CR0(n)          REG16(SSI_CR0(n))
+#define REG_SSI_CR1(n)          REG32(SSI_CR1(n))
+#define REG_SSI_SR(n)           REG32(SSI_SR(n))
+#define REG_SSI_ITR(n)          REG16(SSI_ITR(n))
+#define REG_SSI_ICR(n)          REG8(SSI_ICR(n))
+#define REG_SSI_GR(n)           REG16(SSI_GR(n))
+
+/* SSI Data Register (SSI_DR) */
+
+#define SSI_DR_GPC_BIT          0
+#define SSI_DR_GPC_MASK         (0x1ff << SSI_DR_GPC_BIT)
+
+#define SSI_MAX_FIFO_ENTRIES    128 /* 128 txfifo and 128 rxfifo */
+
+/* SSI Control Register 0 (SSI_CR0) */
+
+#define SSI_CR0_SSIE            (1 << 15)
+#define SSI_CR0_TIE             (1 << 14)
+#define SSI_CR0_RIE             (1 << 13)
+#define SSI_CR0_TEIE            (1 << 12)
+#define SSI_CR0_REIE            (1 << 11)
+#define SSI_CR0_LOOP            (1 << 10)
+#define SSI_CR0_RFINE           (1 << 9)
+#define SSI_CR0_RFINC           (1 << 8)
+#define SSI_CR0_EACLRUN         (1 << 7) /* hardware auto clear underrun when TxFifo no empty */
+#define SSI_CR0_FSEL            (1 << 6)
+#define SSI_CR0_TFLUSH          (1 << 2)
+#define SSI_CR0_RFLUSH          (1 << 1)
+#define SSI_CR0_DISREV          (1 << 0)
+
+/* SSI Control Register 1 (SSI_CR1) */
+
+#define SSI_CR1_FRMHL_BIT       30
+#define SSI_CR1_FRMHL_MASK      (0x3 << SSI_CR1_FRMHL_BIT)
+  #define SSI_CR1_FRMHL_CELOW_CE2LOW    (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
+  #define SSI_CR1_FRMHL_CEHIGH_CE2LOW   (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
+  #define SSI_CR1_FRMHL_CELOW_CE2HIGH   (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid  and SSI_CE2_ is high valid */
+  #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH  (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
+#define SSI_CR1_TFVCK_BIT       28
+#define SSI_CR1_TFVCK_MASK      (0x3 << SSI_CR1_TFVCK_BIT)
+  #define SSI_CR1_TFVCK_0         (0 << SSI_CR1_TFVCK_BIT)
+  #define SSI_CR1_TFVCK_1         (1 << SSI_CR1_TFVCK_BIT)
+  #define SSI_CR1_TFVCK_2         (2 << SSI_CR1_TFVCK_BIT)
+  #define SSI_CR1_TFVCK_3         (3 << SSI_CR1_TFVCK_BIT)
+#define SSI_CR1_TCKFI_BIT       26
+#define SSI_CR1_TCKFI_MASK      (0x3 << SSI_CR1_TCKFI_BIT)
+  #define SSI_CR1_TCKFI_0         (0 << SSI_CR1_TCKFI_BIT)
+  #define SSI_CR1_TCKFI_1         (1 << SSI_CR1_TCKFI_BIT)
+  #define SSI_CR1_TCKFI_2         (2 << SSI_CR1_TCKFI_BIT)
+  #define SSI_CR1_TCKFI_3         (3 << SSI_CR1_TCKFI_BIT)
+#define SSI_CR1_LFST            (1 << 25)
+#define SSI_CR1_ITFRM           (1 << 24)
+#define SSI_CR1_UNFIN           (1 << 23)
+#define SSI_CR1_MULTS           (1 << 22)
+#define SSI_CR1_FMAT_BIT        20
+#define SSI_CR1_FMAT_MASK       (0x3 << SSI_CR1_FMAT_BIT)
+  #define SSI_CR1_FMAT_SPI        (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
+  #define SSI_CR1_FMAT_SSP        (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
+  #define SSI_CR1_FMAT_MW1        (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
+  #define SSI_CR1_FMAT_MW2        (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
+#define SSI_CR1_TTRG_BIT        16 /* SSI1 TX trigger */
+#define SSI_CR1_TTRG_MASK       (0xf << SSI_CR1_TTRG_BIT) 
+#define SSI_CR1_MCOM_BIT        12
+#define SSI_CR1_MCOM_MASK       (0xf << SSI_CR1_MCOM_BIT)
+  #define SSI_CR1_MCOM_1BIT       (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
+  #define SSI_CR1_MCOM_2BIT       (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
+  #define SSI_CR1_MCOM_3BIT       (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
+  #define SSI_CR1_MCOM_4BIT       (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
+  #define SSI_CR1_MCOM_5BIT       (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
+  #define SSI_CR1_MCOM_6BIT       (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
+  #define SSI_CR1_MCOM_7BIT       (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
+  #define SSI_CR1_MCOM_8BIT       (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
+  #define SSI_CR1_MCOM_9BIT       (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
+  #define SSI_CR1_MCOM_10BIT      (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
+  #define SSI_CR1_MCOM_11BIT      (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
+  #define SSI_CR1_MCOM_12BIT      (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
+  #define SSI_CR1_MCOM_13BIT      (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
+  #define SSI_CR1_MCOM_14BIT      (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
+  #define SSI_CR1_MCOM_15BIT      (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
+  #define SSI_CR1_MCOM_16BIT      (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
+#define SSI_CR1_RTRG_BIT        8 /* SSI RX trigger */
+#define SSI_CR1_RTRG_MASK       (0xf << SSI_CR1_RTRG_BIT)
+#define SSI_CR1_FLEN_BIT        4
+#define SSI_CR1_FLEN_MASK       (0xf << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_2BIT       (0x0 << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_3BIT       (0x1 << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_4BIT       (0x2 << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_5BIT       (0x3 << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_6BIT       (0x4 << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_7BIT       (0x5 << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_8BIT       (0x6 << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_9BIT       (0x7 << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_10BIT      (0x8 << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_11BIT      (0x9 << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_12BIT      (0xA << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_13BIT      (0xB << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_14BIT      (0xC << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_15BIT      (0xD << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_16BIT      (0xE << SSI_CR1_FLEN_BIT)
+  #define SSI_CR1_FLEN_17BIT      (0xF << SSI_CR1_FLEN_BIT)
+#define SSI_CR1_PHA             (1 << 1)
+#define SSI_CR1_POL             (1 << 0)
+
+/* SSI Status Register (SSI_SR) */
+
+#define SSI_SR_TFIFONUM_BIT     16
+#define SSI_SR_TFIFONUM_MASK    (0xff << SSI_SR_TFIFONUM_BIT)
+#define SSI_SR_RFIFONUM_BIT     8
+#define SSI_SR_RFIFONUM_MASK    (0xff << SSI_SR_RFIFONUM_BIT)
+#define SSI_SR_END              (1 << 7)
+#define SSI_SR_BUSY             (1 << 6)
+#define SSI_SR_TFF              (1 << 5)
+#define SSI_SR_RFE              (1 << 4)
+#define SSI_SR_TFHE             (1 << 3)
+#define SSI_SR_RFHF             (1 << 2)
+#define SSI_SR_UNDR             (1 << 1)
+#define SSI_SR_OVER             (1 << 0)
+
+/* SSI Interval Time Control Register (SSI_ITR) */
+
+#define SSI_ITR_CNTCLK          (1 << 15)
+#define SSI_ITR_IVLTM_BIT       0
+#define SSI_ITR_IVLTM_MASK      (0x7fff << SSI_ITR_IVLTM_BIT)
+
+/*
+ * SSI Character-per-frame Control Register (SSI_ICR)
+ * SSI_ICR is ignored for SSI_ICR1.FMT != 00b
+*/
+
+#ifndef __MIPS_ASSEMBLER
+
+/***************************************************************************
+ * SSI (Synchronous Serial Interface)
+ ***************************************************************************/
+/* n = 0, 1 (SSI0, SSI1) */
+#define __ssi_enable(n)         ( REG_SSI_CR0(n) |= SSI_CR0_SSIE )
+#define __ssi_disable(n)        ( REG_SSI_CR0(n) &= ~SSI_CR0_SSIE )
+#define __ssi_select_ce(n)      ( REG_SSI_CR0(n) &= ~SSI_CR0_FSEL )
+
+#define __ssi_normal_mode(n) ( REG_SSI_ITR(n) &= ~SSI_ITR_IVLTM_MASK )
+
+#define __ssi_select_ce2(n)             \
+do {                                    \
+        REG_SSI_CR0(n) |= SSI_CR0_FSEL;         \
+        REG_SSI_CR1(n) &= ~SSI_CR1_MULTS;       \
+} while (0)
+
+#define __ssi_select_gpc(n)                     \
+do {                                            \
+        REG_SSI_CR0(n) &= ~SSI_CR0_FSEL;        \
+        REG_SSI_CR1(n) |= SSI_CR1_MULTS;        \
+} while (0)
+
+#define __ssi_underrun_auto_clear(n)            \
+do {                                            \
+        REG_SSI_CR0(n) |= SSI_CR0_EACLRUN;      \
+} while (0)
+
+#define __ssi_underrun_clear_manually(n)        \
+do {                                            \
+        REG_SSI_CR0(n) &= ~SSI_CR0_EACLRUN;     \
+} while (0)
+
+#define __ssi_enable_tx_intr(n)                                 \
+        ( REG_SSI_CR0(n) |= SSI_CR0_TIE | SSI_CR0_TEIE )
+
+#define __ssi_disable_tx_intr(n)                                \
+        ( REG_SSI_CR0(n) &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
+
+#define __ssi_enable_rx_intr(n)                                 \
+        ( REG_SSI_CR0(n) |= SSI_CR0_RIE | SSI_CR0_REIE )
+
+#define __ssi_disable_rx_intr(n)                                \
+        ( REG_SSI_CR0(n) &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )
+
+#define __ssi_enable_txfifo_half_empty_intr(n)  \
+        ( REG_SSI_CR0(n) |= SSI_CR0_TIE )
+#define __ssi_disable_txfifo_half_empty_intr(n) \
+        ( REG_SSI_CR0(n) &= ~SSI_CR0_TIE )
+#define __ssi_enable_tx_error_intr(n)           \
+        ( REG_SSI_CR0(n) |= SSI_CR0_TEIE )
+#define __ssi_disable_tx_error_intr(n)          \
+        ( REG_SSI_CR0(n) &= ~SSI_CR0_TEIE )
+#define __ssi_enable_rxfifo_half_full_intr(n)   \
+        ( REG_SSI_CR0(n) |= SSI_CR0_RIE )
+#define __ssi_disable_rxfifo_half_full_intr(n)  \
+        ( REG_SSI_CR0(n) &= ~SSI_CR0_RIE )
+#define __ssi_enable_rx_error_intr(n)           \
+        ( REG_SSI_CR0(n) |= SSI_CR0_REIE )
+#define __ssi_disable_rx_error_intr(n)          \
+        ( REG_SSI_CR0(n) &= ~SSI_CR0_REIE )
+
+#define __ssi_enable_loopback(n)  ( REG_SSI_CR0(n) |= SSI_CR0_LOOP )
+#define __ssi_disable_loopback(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_LOOP )
+
+#define __ssi_enable_receive(n)   ( REG_SSI_CR0(n) &= ~SSI_CR0_DISREV )
+#define __ssi_disable_receive(n)  ( REG_SSI_CR0(n) |= SSI_CR0_DISREV )
+
+#define __ssi_finish_receive(n)                                 \
+        ( REG_SSI_CR0(n) |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )
+
+#define __ssi_disable_recvfinish(n)                             \
+        ( REG_SSI_CR0(n) &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )
+
+#define __ssi_flush_txfifo(n)           ( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH )
+#define __ssi_flush_rxfifo(n)           ( REG_SSI_CR0(n) |= SSI_CR0_RFLUSH )
+
+#define __ssi_flush_fifo(n)                                     \
+        ( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )
+
+#define __ssi_finish_transmit(n)        ( REG_SSI_CR1(n) &= ~SSI_CR1_UNFIN )
+#define __ssi_wait_transmit(n)          ( REG_SSI_CR1(n) |= SSI_CR1_UNFIN )
+#define __ssi_use_busy_wait_mode(n)     __ssi_wait_transmit(n)
+#define __ssi_unset_busy_wait_mode(n)   __ssi_finish_transmit(n)
+
+#define __ssi_spi_format(n)                                             \
+        do {                                                            \
+                REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK;                   \
+                REG_SSI_CR1(n) |= SSI_CR1_FMAT_SPI;                     \
+                REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \
+                REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1);  \
+        } while (0)
+
+/* TI's SSP format, must clear SSI_CR1.UNFIN */
+#define __ssi_ssp_format(n)                                             \
+        do {                                                            \
+                REG_SSI_CR1(n) &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \
+                REG_SSI_CR1(n) |= SSI_CR1_FMAT_SSP;                     \
+        } while (0)
+
+/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */
+#define __ssi_microwire_format(n)                                       \
+        do {                                                            \
+                REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK;                   \
+                REG_SSI_CR1(n) |= SSI_CR1_FMAT_MW1;                     \
+                REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \
+                REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3);  \
+                REG_SSI_CR0(n) &= ~SSI_CR0_RFINE;                       \
+        } while (0)
+
+/* CE# level (FRMHL), CE# in interval time (ITFRM),
+   clock phase and polarity (PHA POL),
+   interval time (SSIITR), interval characters/frame (SSIICR) */
+
+/* frmhl,endian,mcom,flen,pha,pol MASK */
+#define SSICR1_MISC_MASK                                        \
+        ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \
+          | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL )     
+
+#define __ssi_spi_set_misc(n,frmhl,endian,flen,mcom,pha,pol)            \
+        do {                                                            \
+                REG_SSI_CR1(n) &= ~SSICR1_MISC_MASK;                    \
+                REG_SSI_CR1(n) |= ((frmhl) << 30) | ((endian) << 25) |  \
+                        (((mcom) - 1) << 12) | (((flen) - 2) << 4) |    \
+                        ((pha) << 1) | (pol);                           \
+        } while(0)
+
+/* Transfer with MSB or LSB first */
+#define __ssi_set_msb(n) ( REG_SSI_CR1(n) &= ~SSI_CR1_LFST )
+#define __ssi_set_lsb(n) ( REG_SSI_CR1(n) |= SSI_CR1_LFST )
+
+#define __ssi_set_frame_length(n, m)                                    \
+        REG_SSI_CR1(n) = (REG_SSI_CR1(n) & ~SSI_CR1_FLEN_MASK) | (((m) - 2) << 4) 
+
+/* m = 1 - 16 */
+#define __ssi_set_microwire_command_length(n,m)                         \
+        ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##m##BIT) )
+
+/* Set the clock phase for SPI */
+#define __ssi_set_spi_clock_phase(n, m)                                 \
+        ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_PHA) | (((m)&0x1)<< 1)))
+
+/* Set the clock polarity for SPI */
+#define __ssi_set_spi_clock_polarity(n, p)                              \
+        ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_POL) | ((p)&0x1)) )
+
+/* SSI tx trigger, m = i x 8 */
+#define __ssi_set_tx_trigger(n, m)                              \
+        do {                                                    \
+                REG_SSI_CR1(n) &= ~SSI_CR1_TTRG_MASK;           \
+                REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_TTRG_BIT;    \
+        } while (0)
+
+/* SSI rx trigger, m = i x 8 */
+#define __ssi_set_rx_trigger(n, m)                              \
+        do {                                                    \
+                REG_SSI_CR1(n) &= ~SSI_CR1_RTRG_MASK;           \
+                REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_RTRG_BIT;    \
+        } while (0)
+
+#define __ssi_get_txfifo_count(n)                                       \
+        ( (REG_SSI_SR(n) & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )
+
+#define __ssi_get_rxfifo_count(n)                                       \
+        ( (REG_SSI_SR(n) & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )
+
+#define __ssi_transfer_end(n)           ( REG_SSI_SR(n) & SSI_SR_END )
+#define __ssi_is_busy(n)                ( REG_SSI_SR(n) & SSI_SR_BUSY )
+
+#define __ssi_txfifo_full(n)            ( REG_SSI_SR(n) & SSI_SR_TFF )
+#define __ssi_rxfifo_empty(n)           ( REG_SSI_SR(n) & SSI_SR_RFE )
+#define __ssi_rxfifo_half_full(n)       ( REG_SSI_SR(n) & SSI_SR_RFHF )
+#define __ssi_txfifo_half_empty(n)      ( REG_SSI_SR(n) & SSI_SR_TFHE )
+#define __ssi_underrun(n)               ( REG_SSI_SR(n) & SSI_SR_UNDR )
+#define __ssi_overrun(n)                ( REG_SSI_SR(n) & SSI_SR_OVER )
+#define __ssi_clear_underrun(n)         ( REG_SSI_SR(n) = ~SSI_SR_UNDR )
+#define __ssi_clear_overrun(n)          ( REG_SSI_SR(n) = ~SSI_SR_OVER )
+#define __ssi_clear_errors(n)           ( REG_SSI_SR(n) &= ~(SSI_SR_UNDR | SSI_SR_OVER) )
+
+#define __ssi_set_clk(n, dev_clk, ssi_clk)                      \
+        ( REG_SSI_GR(n) = (dev_clk) / (2*(ssi_clk)) - 1 )
+
+#define __ssi_receive_data(n)           REG_SSI_DR(n)
+#define __ssi_transmit_data(n, v)       (REG_SSI_DR(n) = (v))
+
+#endif /* __MIPS_ASSEMBLER */
+
+/*
+ * Timer and counter unit module(TCU) address definition
+ */
+#define TCU_BASE                0xb0002000
+
+/* TCU group offset */
+#define TCU_GOS                 0x10
+
+/* TCU total channel number */
+#define TCU_CHANNEL_NUM         8
+
+/*
+ * TCU registers offset definition
+ */
+#define TCU_TER_OFFSET          (0x10)  /* r, 16, 0x0000     */
+#define TCU_TESR_OFFSET         (0x14)  /* w, 16, 0x????     */
+#define TCU_TECR_OFFSET         (0x18)  /* w, 16, 0x????     */
+
+#define TCU_TSR_OFFSET          (0x1c)  /* r, 32, 0x00000000 */
+#define TCU_TSSR_OFFSET         (0x2c)  /* w, 32, 0x00000000 */
+#define TCU_TSCR_OFFSET         (0x3c)  /* w, 32, 0x0000     */
+
+#define TCU_TFR_OFFSET          (0x20)  /* r, 32, 0x003F003F */
+#define TCU_TFSR_OFFSET         (0x24)  /* w, 32, 0x???????? */
+#define TCU_TFCR_OFFSET         (0x28)  /* w, 32, 0x???????? */
+
+#define TCU_TMR_OFFSET          (0x30)  /* r, 32, 0x00000000 */
+#define TCU_TMSR_OFFSET         (0x34)  /* w, 32, 0x???????? */
+#define TCU_TMCR_OFFSET         (0x38)  /* w, 32, 0x???????? */
+
+#define TCU_TSTR_OFFSET         (0xf0)  /* r, 32, 0x00000000 */
+#define TCU_TSTSR_OFFSET        (0xf4)  /* w, 32, 0x???????? */
+#define TCU_TSTCR_OFFSET        (0xf8)  /* w, 32, 0x???????? */
+
+#define TCU_TDFR_OFFSET         (0x40)  /* rw,16, 0x????     */
+#define TCU_TDHR_OFFSET         (0x44)  /* rw,16, 0x????     */
+#define TCU_TCNT_OFFSET         (0x48)  /* rw,16, 0x????     */
+#define TCU_TCSR_OFFSET         (0x4c)  /* rw,16, 0x0000     */
+
+/*
+ * TCU registers address definition
+ */
+#define TCU_TER         (TCU_BASE + TCU_TER_OFFSET)
+#define TCU_TESR        (TCU_BASE + TCU_TESR_OFFSET)
+#define TCU_TECR        (TCU_BASE + TCU_TECR_OFFSET)
+#define TCU_TSR         (TCU_BASE + TCU_TSR_OFFSET)
+#define TCU_TFR         (TCU_BASE + TCU_TFR_OFFSET)
+#define TCU_TFSR        (TCU_BASE + TCU_TFSR_OFFSET)
+#define TCU_TFCR        (TCU_BASE + TCU_TFCR_OFFSET)
+#define TCU_TSSR        (TCU_BASE + TCU_TSSR_OFFSET)
+#define TCU_TMR         (TCU_BASE + TCU_TMR_OFFSET)
+#define TCU_TMSR        (TCU_BASE + TCU_TMSR_OFFSET)
+#define TCU_TMCR        (TCU_BASE + TCU_TMCR_OFFSET)
+#define TCU_TSCR        (TCU_BASE + TCU_TSCR_OFFSET)
+#define TCU_TSTR        (TCU_BASE + TCU_TSTR_OFFSET)
+#define TCU_TSTSR       (TCU_BASE + TCU_TSTSR_OFFSET)
+#define TCU_TSTCR       (TCU_BASE + TCU_TSTCR_OFFSET)
+
+/* n is the TCU channel index (0 - 7) */
+#define TCU_TDFR(n)     (TCU_BASE + (n) * TCU_GOS + TCU_TDFR_OFFSET)
+#define TCU_TDHR(n)     (TCU_BASE + (n) * TCU_GOS + TCU_TDHR_OFFSET)
+#define TCU_TCNT(n)     (TCU_BASE + (n) * TCU_GOS + TCU_TCNT_OFFSET)
+#define TCU_TCSR(n)     (TCU_BASE + (n) * TCU_GOS + TCU_TCSR_OFFSET)
+
+/*
+ * TCU registers bit field common define
+ */
+
+/* When n is NOT less than TCU_CHANNEL_NUM, change to TCU_CHANNEL_NUM - 1 */
+#define __TIMER(n)      (1 << ((n) < TCU_CHANNEL_NUM ? (n) : (TCU_CHANNEL_NUM - 1))
+
+/* Timer counter enable register(TER) */
+#define TER_OSTEN       BIT15
+#define TER_TCEN(n)     __TIMER(n)
+
+/* Timer counter enable set register(TESR) */
+#define TESR_OST        BIT15
+#define TESR_TIMER(n)   __TIMER(n)
+
+/* Timer counter enable clear register(TECR) */
+#define TECR_OST        BIT15
+#define TECR_TIMER(n)   __TIMER(n)
+
+/* Timer stop register(TSR) */
+#define TSR_WDT_STOP            BIT16
+#define TSR_OST_STOP            BIT15
+#define TSR_TIMER_STOP(n)       __TIMER(n)
+
+/* Timer stop set register(TSSR) */
+#define TSSR_WDT                BIT16
+#define TSSR_OST                BIT15
+#define TSSR_TIMER(n)           __TIMER(n)
+
+/* Timer stop clear register(TSCR) */
+#define TSCR_WDT                BIT16
+#define TSCR_OST                BIT15
+#define TSSR_TIMER(n)           __TIMER(n)
+
+/* Timer flag register(TFR) */
+#define TFR_HFLAG(n)    (__TIMER(n) << 16)
+#define TFR_OSTFLAG     BIT15
+#define TFR_FFLAG(n)    __TIMER(n)
+
+/* Timer flag set register(TFSR) */
+#define TFSR_HFLAG(n)   (__TIMER(n) << 16)
+#define TFSR_OSTFLAG    BIT15
+#define TFSR_FFLAG(n)   __TIMER(n)
+
+/* Timer flag clear register(TFCR) */
+#define TFCR_HFLAG(n)   (__TIMER(n) << 16)
+#define TFCR_OSTFLAG    BIT15
+#define TFCR_FFLAG(n)   (__TIMER(n))
+
+/* Timer mast register(TMR) */
+#define TMR_HMASK(n)    (__TIMER(n) << 16)
+#define TMR_OSTMASK     BIT15
+#define TMR_FMASK(n)    (__TIMER(n))
+
+/* Timer mask set register(TMSR) */
+#define TMSR_HMASK(n)   (__TIMER(n) << 16)
+#define TMSR_OSTMASK    BIT15
+#define TMSR_FMASK(n)   (__TIMER(n))
+
+/* Timer mask clear register(TMCR) */
+#define TMCR_HMASK(n)   (__TIMER(n) << 16)
+#define TMCR_OSTMASK    BIT15
+#define TMCR_FMASK(n)   (__TIMER(n))
+
+/* Timer control register(TCSR) */
+#define TCSR_BYPASS             BIT11
+#define TCSR_CLRZ               BIT10
+#define TCSR_SD_ABRUPT          BIT9
+#define TCSR_INITL_HIGH         BIT8
+#define TCSR_PWM_EN             BIT7
+#define TCSR_PWM_IN_EN          BIT6
+#define TCSR_EXT_EN             BIT2
+#define TCSR_RTC_EN             BIT1
+#define TCSR_PCK_EN             BIT0
+
+#define TCSR_PRESCALE_LSB       3
+#define TCSR_PRESCALE_MASK      BITS_H2L(5, TCSR_PRESCALE_LSB)
+#define TCSR_PRESCALE1          (0x0 << TCSR_PRESCALE_LSB)
+#define TCSR_PRESCALE4          (0x1 << TCSR_PRESCALE_LSB)
+#define TCSR_PRESCALE16         (0x2 << TCSR_PRESCALE_LSB)
+#define TCSR_PRESCALE64         (0x3 << TCSR_PRESCALE_LSB)
+#define TCSR_PRESCALE256        (0x4 << TCSR_PRESCALE_LSB)
+#define TCSR_PRESCALE1024       (0x5 << TCSR_PRESCALE_LSB)
+
+/* Timer data full register(TDFR) */
+#define TDFR_TDFR_LSB           0
+#define TDFR_TDFR_MASK          BITS_H2L(15, TDFR_TDFR_LSB)
+
+/* Timer data half register(TDHR) */
+#define TDHR_TDHR_LSB           0
+#define TDHR_TDHR_MASK          BITS_H2L(15, TDHR_TDHR_LSB)
+
+/* Timer counter register(TCNT) */
+#define TCNT_TCNT_LSB           0
+#define TCNT_TCNT_MASK          BITS_H2L(15, TCNT_TCNT_LSB)
+
+/* Timer status register(TSTR) */
+#define TSTR_REAL2      BIT18
+#define TSTR_REAL1      BIT17
+#define TSTR_BUSY2      BIT2
+#define TSTR_BUSY1      BIT1
+
+/* Timer status set register(TSTSR) */
+#define TSTSR_REALS2    BIT18
+#define TSTSR_REALS1    BIT17
+#define TSTSR_BUSYS2    BIT2
+#define TSTSR_BUSYS1    BIT1
+
+/* Timer status clear register(TSTCR) */
+#define TSTCR_REALC2    BIT18
+#define TSTCR_REALC1    BIT17
+#define TSTCR_BUSYC2    BIT2
+#define TSTCR_BUSYC1    BIT1
+
+#ifndef __MIPS_ASSEMBLER
+
+#define REG_TCU_TER     REG16(TCU_TER)
+#define REG_TCU_TESR    REG16(TCU_TESR)
+#define REG_TCU_TECR    REG16(TCU_TECR)
+#define REG_TCU_TSR     REG32(TCU_TSR)
+#define REG_TCU_TFR     REG32(TCU_TFR)
+#define REG_TCU_TFSR    REG32(TCU_TFSR)
+#define REG_TCU_TFCR    REG32(TCU_TFCR)
+#define REG_TCU_TSSR    REG32(TCU_TSSR)
+#define REG_TCU_TMR     REG32(TCU_TMR)
+#define REG_TCU_TMSR    REG32(TCU_TMSR)
+#define REG_TCU_TMCR    REG32(TCU_TMCR)
+#define REG_TCU_TSCR    REG32(TCU_TSCR)
+#define REG_TCU_TSTR    REG32(TCU_TSTR)
+#define REG_TCU_TSTSR   REG32(TCU_TSTSR)
+#define REG_TCU_TSTCR   REG32(TCU_TSTCR)
+
+#define REG_TCU_TDFR(n) REG16(TCU_TDFR(n))
+#define REG_TCU_TDHR(n) REG16(TCU_TDHR(n))
+#define REG_TCU_TCNT(n) REG16(TCU_TCNT(n))
+#define REG_TCU_TCSR(n) REG16(TCU_TCSR(n))
+
+// where 'n' is the TCU channel
+#define __tcu_select_extalclk(n) \
+        (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCSR_EXT_EN | TCSR_RTC_EN | TCSR_PCK_EN)) | TCSR_EXT_EN)
+#define __tcu_select_rtcclk(n) \
+        (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCSR_EXT_EN | TCSR_RTC_EN | TCSR_PCK_EN)) | TCSR_RTC_EN)
+#define __tcu_select_pclk(n) \
+        (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCSR_EXT_EN | TCSR_RTC_EN | TCSR_PCK_EN)) | TCSR_PCK_EN)
+#define __tcu_disable_pclk(n) \
+        REG_TCU_TCSR(n) = (REG_TCU_TCSR((n)) & ~TCSR_PCK_EN);
+#define __tcu_select_clk_div1(n) \
+        (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE1)
+#define __tcu_select_clk_div4(n) \
+        (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE4)
+#define __tcu_select_clk_div16(n) \
+        (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE16)
+#define __tcu_select_clk_div64(n) \
+        (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE64)
+#define __tcu_select_clk_div256(n) \
+        (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE256)
+#define __tcu_select_clk_div1024(n) \
+        (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE1024)
+
+#define __tcu_enable_pwm_output(n)      (REG_TCU_TCSR((n)) |= TCSR_PWM_EN)
+#define __tcu_disable_pwm_output(n)     (REG_TCU_TCSR((n)) &= ~TCSR_PWM_EN)
+
+#define __tcu_init_pwm_output_high(n)   (REG_TCU_TCSR((n)) |= TCSR_INITL_HIGH)
+#define __tcu_init_pwm_output_low(n)    (REG_TCU_TCSR((n)) &= ~TCSR_INITL_HIGH)
+
+#define __tcu_set_pwm_output_shutdown_graceful(n)       (REG_TCU_TCSR((n)) &= ~TCSR_SD_ABRUPT)
+#define __tcu_set_pwm_output_shutdown_abrupt(n)         (REG_TCU_TCSR((n)) |= TCSR_SD_ABRUPT)
+
+#define __tcu_clear_counter_to_zero(n)  (REG_TCU_TCSR((n)) |= TCSR_CLRZ)
+
+#define __tcu_ost_enabled()             (REG_TCU_TER & TER_OSTEN)
+#define __tcu_enable_ost()              (REG_TCU_TESR = TESR_OST)
+#define __tcu_disable_ost()             (REG_TCU_TECR = TECR_OST)
+
+#define __tcu_counter_enabled(n)        (REG_TCU_TER & (1 << (n)))
+#define __tcu_start_counter(n)          (REG_TCU_TESR |= (1 << (n)))
+#define __tcu_stop_counter(n)           (REG_TCU_TECR |= (1 << (n)))
+
+#define __tcu_half_match_flag(n)        (REG_TCU_TFR & (1 << ((n) + 16)))
+#define __tcu_full_match_flag(n)        (REG_TCU_TFR & (1 << (n)))
+#define __tcu_set_half_match_flag(n)    (REG_TCU_TFSR = (1 << ((n) + 16)))
+#define __tcu_set_full_match_flag(n)    (REG_TCU_TFSR = (1 << (n)))
+#define __tcu_clear_half_match_flag(n)  (REG_TCU_TFCR = (1 << ((n) + 16)))
+#define __tcu_clear_full_match_flag(n)  (REG_TCU_TFCR = (1 << (n)))
+#define __tcu_mask_half_match_irq(n)    (REG_TCU_TMSR = (1 << ((n) + 16)))
+#define __tcu_mask_full_match_irq(n)    (REG_TCU_TMSR = (1 << (n)))
+#define __tcu_unmask_half_match_irq(n)  (REG_TCU_TMCR = (1 << ((n) + 16)))
+#define __tcu_unmask_full_match_irq(n)  (REG_TCU_TMCR = (1 << (n)))
+
+#define __tcu_ost_match_flag()          (REG_TCU_TFR & TFR_OSTFLAG)
+#define __tcu_set_ost_match_flag()      (REG_TCU_TFSR = TFSR_OSTFLAG)
+#define __tcu_clear_ost_match_flag()    (REG_TCU_TFCR = TFCR_OSTFLAG)
+#define __tcu_ost_match_irq_masked()    (REG_TCU_TMR & TMR_OSTMASK)
+#define __tcu_mask_ost_match_irq()      (REG_TCU_TMSR = TMSR_OSTMASK)
+#define __tcu_unmask_ost_match_irq()    (REG_TCU_TMCR = TMCR_OSTMASK)
+
+#define __tcu_wdt_clock_stopped()       (REG_TCU_TSR & TSR_WDT_STOP)
+#define __tcu_ost_clock_stopped()       (REG_TCU_TSR & TSR_OST_STOP)
+#define __tcu_timer_clock_stopped(n)    (REG_TCU_TSR & (1 << (n)))
+
+#define __tcu_start_wdt_clock()         (REG_TCU_TSCR = TSCR_WDT)
+#define __tcu_start_ost_clock()         (REG_TCU_TSCR = TSCR_OST)
+#define __tcu_start_timer_clock(n)      (REG_TCU_TSCR = (1 << (n)))
+
+#define __tcu_stop_wdt_clock()          (REG_TCU_TSSR = TSSR_WDT)
+#define __tcu_stop_ost_clock()          (REG_TCU_TSSR = TSSR_OST)
+#define __tcu_stop_timer_clock(n)       (REG_TCU_TSSR = (1 << (n)))
+
+#define __tcu_get_count(n)              (REG_TCU_TCNT((n)))
+#define __tcu_set_count(n,v)            (REG_TCU_TCNT((n)) = (v))
+#define __tcu_set_full_data(n,v)        (REG_TCU_TDFR((n)) = (v))
+#define __tcu_set_half_data(n,v)        (REG_TCU_TDHR((n)) = (v))
+
+/* TCU2, counter 1, 2*/
+#define __tcu_read_real_value(n)        (REG_TCU_TSTR & (1 << ((n) + 16)))
+#define __tcu_read_false_value(n)       (REG_TCU_TSTR & (1 << ((n) + 16)))
+#define __tcu_counter_busy(n)           (REG_TCU_TSTR & (1 << (n)))
+#define __tcu_counter_ready(n)          (REG_TCU_TSTR & (1 << (n)))
+
+#define __tcu_set_read_real_value(n)    (REG_TCU_TSTSR = (1 << ((n) + 16)))
+#define __tcu_set_read_false_value(n)   (REG_TCU_TSTCR = (1 << ((n) + 16)))
+#define __tcu_set_counter_busy(n)       (REG_TCU_TSTSR = (1 << (n)))
+#define __tcu_set_counter_ready(n)      (REG_TCU_TSTCR = (1 << (n)))
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define TSSI0_BASE      0xB0073000
+
+/*************************************************************************
+ * TSSI MPEG 2-TS slave interface
+ *************************************************************************/
+#define TSSI_ENA       ( TSSI0_BASE + 0x00 )   /* TSSI enable register */
+#define TSSI_CFG       ( TSSI0_BASE + 0x04 )   /* TSSI configure register */
+#define TSSI_CTRL      ( TSSI0_BASE + 0x08 )   /* TSSI control register */
+#define TSSI_STAT      ( TSSI0_BASE + 0x0c )   /* TSSI state register */
+#define TSSI_FIFO      ( TSSI0_BASE + 0x10 )   /* TSSI FIFO register */
+#define TSSI_PEN       ( TSSI0_BASE + 0x14 )   /* TSSI PID enable register */
+#define TSSI_NUM       ( TSSI0_BASE + 0x18 )
+#define TSSI_DTR       ( TSSI0_BASE + 0x1c )
+#define TSSI_PID(n)    ( TSSI0_BASE + 0x20 + 4*(n) )   /* TSSI PID filter register */
+#define TSSI_PID0      ( TSSI0_BASE + 0x20 )
+#define TSSI_PID1      ( TSSI0_BASE + 0x24 )
+#define TSSI_PID2      ( TSSI0_BASE + 0x28 )
+#define TSSI_PID3      ( TSSI0_BASE + 0x2c )
+#define TSSI_PID4      ( TSSI0_BASE + 0x30 )
+#define TSSI_PID5      ( TSSI0_BASE + 0x34 )
+#define TSSI_PID6      ( TSSI0_BASE + 0x38 )
+#define TSSI_PID7      ( TSSI0_BASE + 0x3c )
+#define TSSI_PID8      ( TSSI0_BASE + 0x40 )
+#define TSSI_PID9      ( TSSI0_BASE + 0x44 )
+#define TSSI_PID10     ( TSSI0_BASE + 0x48 )
+#define TSSI_PID11     ( TSSI0_BASE + 0x4c )
+#define TSSI_PID12     ( TSSI0_BASE + 0x50 )
+#define TSSI_PID13     ( TSSI0_BASE + 0x54 )
+#define TSSI_PID14     ( TSSI0_BASE + 0x58 )
+#define TSSI_PID15     ( TSSI0_BASE + 0x5c )
+#define TSSI_PID_MAX   16       /* max PID: 15 */
+
+#define TSSI_DDA        ( TSSI0_BASE + 0x60 )
+#define TSSI_DTA        ( TSSI0_BASE + 0x64 )
+#define TSSI_DID        ( TSSI0_BASE + 0x68 )
+#define TSSI_DCMD       ( TSSI0_BASE + 0x6c )
+#define TSSI_DST        ( TSSI0_BASE + 0x70 )
+#define TSSI_TC         ( TSSI0_BASE + 0x74 )
+ 
+#define REG_TSSI_ENA       REG8( TSSI_ENA )
+#define REG_TSSI_CFG       REG16( TSSI_CFG )
+#define REG_TSSI_CTRL      REG8( TSSI_CTRL )
+#define REG_TSSI_STAT      REG8( TSSI_STAT )
+#define REG_TSSI_FIFO      REG32( TSSI_FIFO )
+#define REG_TSSI_PEN       REG32( TSSI_PEN )
+#define REG_TSSI_NUM       REG32( TSSI_NUM )
+#define REG_TSSI_DTR       REG32( TSSI_DTR )
+#define REG_TSSI_PID(n)    REG32( TSSI_PID(n) )
+#define REG_TSSI_PID0      REG32( TSSI_PID0 )
+#define REG_TSSI_PID1      REG32( TSSI_PID1 )
+#define REG_TSSI_PID2      REG32( TSSI_PID2 )
+#define REG_TSSI_PID3      REG32( TSSI_PID3 )
+#define REG_TSSI_PID4      REG32( TSSI_PID4 )
+#define REG_TSSI_PID5      REG32( TSSI_PID5 )
+#define REG_TSSI_PID6      REG32( TSSI_PID6 )
+#define REG_TSSI_PID7      REG32( TSSI_PID7 )
+#define REG_TSSI_PID8      REG32( TSSI_PID8 )
+#define REG_TSSI_PID9      REG32( TSSI_PID9 )
+#define REG_TSSI_PID10     REG32( TSSI_PID10 )
+#define REG_TSSI_PID11     REG32( TSSI_PID11 )
+#define REG_TSSI_PID12     REG32( TSSI_PID12 )
+#define REG_TSSI_PID13     REG32( TSSI_PID13 )
+#define REG_TSSI_PID14     REG32( TSSI_PID14 )
+#define REG_TSSI_PID15     REG32( TSSI_PID15 )
+
+/* TSSI enable register */
+#define TSSI_ENA_SFT_RST        ( 1 << 7 )      /* soft reset bit */
+#define TSSI_ENA_PID_EN         ( 1 << 2 )      /* soft filtering function enable bit */
+#define TSSI_ENA_FAIL           ( 1 << 4 )      /* fail signal bit */
+#define TSSI_ENA_PEN_0          ( 1 << 3 )      /* PID filter enable bit for PID */
+#define TSSI_ENA_DMA_EN         ( 1 << 1 )      /* DMA enable bit */
+#define TSSI_ENA_ENA            ( 1 << 0 )      /* TSSI enable bit */
+
+/* TSSI configure register */
+#define TSSI_CFG_TRIG_BIT       14 /* fifo trig number */
+#define TSSI_CFG_TRIG_MASK      ( 0x7 << TSSI_CFG_TRIG_BIT)
+#define TSSI_CFG_TRIG_4         ( 0 << TSSI_CFG_TRIG_BIT)
+#define TSSI_CFG_TRIG_8         ( 1 << TSSI_CFG_TRIG_BIT)
+#define TSSI_CFG_TRIG_16        ( 2 << TSSI_CFG_TRIG_BIT)
+#define TSSI_CFG_TRIG_32        ( 3 << TSSI_CFG_TRIG_BIT)
+#define TSSI_CFG_TRIG_48        ( 4 << TSSI_CFG_TRIG_BIT)
+#define TSSI_CFG_TRIG_64        ( 5 << TSSI_CFG_TRIG_BIT)
+#define TSSI_CFG_TRIG_80        ( 6 << TSSI_CFG_TRIG_BIT)
+#define TSSI_CFG_TRIG_96        ( 7 << TSSI_CFG_TRIG_BIT)
+
+/* mode of adding data 0 select bit */
+#define TSSI_CFG_TRANS_MD_BIT   10
+#define TSSI_CFG_TRANS_MD_MASK  ( 0x3 << TSSI_CFG_TRANS_MD_BIT) 
+#define TSSI_CFG_TRANS_MD_0     (0 << TSSI_CFG_TRANS_MD_BIT)
+#define TSSI_CFG_TRANS_MD_1     (1 << TSSI_CFG_TRANS_MD_BIT)
+#define TSSI_CFG_TRANS_MD_2     (2 << TSSI_CFG_TRANS_MD_BIT)
+
+#define TSSI_CFG_END_WD         ( 1 << 9 )      /* order of data in word */
+#define TSSI_CFG_END_BT         ( 1 << 8 )      /* order of data in byte */
+
+#define TSSI_CFG_TSDI_H         ( 1 << 7 )      /* data pin polarity */
+#define TSSI_CFG_USE_0          ( 1 << 6 )      /* serial mode data pin select */
+#define TSSI_CFG_USE_TSDI0      ( 1 << 6 )      /* TSDI0 as serial mode data pin */
+#define TSSI_CFG_USE_TSDI7      ( 0 << 6 )      /* TSDI7 as serial mode data pin */
+#define TSSI_CFG_TSCLK_CH       ( 1 << 5 )      /* clk channel select */
+#define TSSI_CFG_PARAL          ( 1 << 4 )      /* mode select */
+#define TSSI_CFG_PARAL_MODE     ( 1 << 4 )      /* parallel select */
+#define TSSI_CFG_SERIAL_MODE    ( 0 << 4 )      /* serial select */
+#define TSSI_CFG_TSCLK_P        ( 1 << 3 )      /* clk edge select */
+#define TSSI_CFG_TSFRM_H        ( 1 << 2 )      /* TSFRM polarity select */
+#define TSSI_CFG_TSSTR_H        ( 1 << 1 )      /* TSSTR polarity select */
+#define TSSI_CFG_TSFAIL_H       ( 1 << 0 )      /* TSFAIL polarity select */
+
+/* TSSI control register */
+#define TSSI_CTRL_DTRM          ( 1 << 2 )      /* FIFO data trigger interrupt mask bit */
+#define TSSI_CTRL_OVRNM         ( 1 << 1 )      /* FIFO overrun interrupt mask bit */
+#define TSSI_CTRL_TRIGM         ( 1 << 0 )      /* FIFO trigger interrupt mask bit */
+
+/* TSSI state register */
+#define TSSI_STAT_DTR           ( 1 << 2 )      /* FIFO data trigger interrupt flag bit */
+#define TSSI_STAT_OVRN          ( 1 << 1 )      /* FIFO overrun interrupt flag bit */
+#define TSSI_STAT_TRIG          ( 1 << 0 )      /* FIFO trigger interrupt flag bit */
+
+/* TSSI PID enable register */
+#define TSSI_PEN_EN00   ( 1 << 0 )      /* enable PID n */
+#define TSSI_PEN_EN10   ( 1 << 1 )      
+#define TSSI_PEN_EN20   ( 1 << 2 )      
+#define TSSI_PEN_EN30   ( 1 << 3 )      
+#define TSSI_PEN_EN40   ( 1 << 4 )      
+#define TSSI_PEN_EN50   ( 1 << 5 )      
+#define TSSI_PEN_EN60   ( 1 << 6 )      
+#define TSSI_PEN_EN70   ( 1 << 7 )      
+#define TSSI_PEN_EN80   ( 1 << 8 )      
+#define TSSI_PEN_EN90   ( 1 << 9 )      
+#define TSSI_PEN_EN100  ( 1 << 10 )      
+#define TSSI_PEN_EN110  ( 1 << 11 )      
+#define TSSI_PEN_EN120  ( 1 << 12 )      
+#define TSSI_PEN_EN130  ( 1 << 13 )      
+#define TSSI_PEN_EN140  ( 1 << 14 )      
+#define TSSI_PEN_EN150  ( 1 << 15 )      
+#define TSSI_PEN_EN01   ( 1 << 16 )      
+#define TSSI_PEN_EN11   ( 1 << 17 )      
+#define TSSI_PEN_EN21   ( 1 << 18 )     
+#define TSSI_PEN_EN31   ( 1 << 19 )      
+#define TSSI_PEN_EN41   ( 1 << 20 )     
+#define TSSI_PEN_EN51   ( 1 << 21 )      
+#define TSSI_PEN_EN61   ( 1 << 22 )     
+#define TSSI_PEN_EN71   ( 1 << 23 )      
+#define TSSI_PEN_EN81   ( 1 << 24 )      
+#define TSSI_PEN_EN91   ( 1 << 25 )      
+#define TSSI_PEN_EN101  ( 1 << 26 )      
+#define TSSI_PEN_EN111  ( 1 << 27 )      
+#define TSSI_PEN_EN121  ( 1 << 28 )      
+#define TSSI_PEN_EN131  ( 1 << 29 )      
+#define TSSI_PEN_EN141  ( 1 << 30 )      
+#define TSSI_PEN_EN151  ( 1 << 31 )      
+//#define TSSI_PEN_PID0         ( 1 << 31 ) /* PID filter enable PID0 */
+
+/* TSSI Data Number Registers */
+#define TSSI_DNUM_BIT   0
+#define TSSI_DNUM_MASK  (0x7f << TSSI_DNUM_BIT)
+
+/* TSSI Data Trigger Register */
+#define TSSI_DTRG_BIT   0
+#define TSSI_DTRG_MASK  (0x7f << TSSI_DTRG_BIT)
+
+/* TSSI PID Filter Registers */
+#define TSSI_PID_PID1_BIT       16
+#define TSSI_PID_PID1_MASK      (0x1fff<<TSSI_PID_PID1_BIT)
+#define TSSI_PID_PID0_BIT       0
+#define TSSI_PID_PID0_MASK      (0x1fff<<TSSI_PID_PID0_BIT)
+
+/* TSSI DMA Identifier Registers */
+#define TSSI_DMA_ID_BIT         0
+#define TSSI_DMA_ID_MASK        (0xffff << TSSI_DMA_ID_BIT)
+
+/* TSSI DMA Command Registers */
+#define TSSI_DCMD_TLEN_BIT      8
+#define TSSI_DCMD_TLEN_MASK     (0xff << TSSI_DCMD_TLEN_BIT)
+#define TSSI_DCMD_TEFE          (1 << 4)
+#define TSSI_DCMD_TSZ_BIT       2
+#define TSSI_DCMD_TSZ_MASK      (0x3 << TSSI_DCMD_TSZ_BIT)
+#define TSSI_DCMD_TSZ_4         (0 << TSSI_DCMD_TSZ_BIT)
+#define TSSI_DCMD_TSZ_8         (1 << TSSI_DCMD_TSZ_BIT)
+#define TSSI_DCMD_TSZ_16        (2 << TSSI_DCMD_TSZ_BIT)
+#define TSSI_DCMD_TSZ_32        (3 << TSSI_DCMD_TSZ_BIT)
+#define TSSI_DCMD_TEIE          (1 << 1)
+#define TSSI_DCMD_LINK          (1 << 0)
+
+/* TSSI DMA Status Registers */
+#define TSSI_DST_DID_BIT        16
+#define TSSI_DST_DID_MASK       (0xffff << 16)
+#define TSSI_DST_TEND           (1 << 0)
+
+/* TSSI Transfer Control Registers */
+#define TSSI_TC_OP_BIT          4
+#define TSSI_TC_OP_MASK         (0x3 << TSSI_TC_OP_BIT)
+//////////////////#define TSSI_TC_OP_0          ( 
+#define TSSI_TC_OPE             (1 << 2)
+#define TSSI_TC_EME             (1 << 1)
+#define TSSI_TC_APM             (1 << 0)
+#ifndef __MIPS_ASSEMBLER
+
+/*************************************************************************
+ * TSSI MPEG 2-TS slave interface operation
+ *************************************************************************/
+#define __tssi_enable()                       ( REG_TSSI_ENA |= TSSI_ENA_ENA )
+#define __tssi_disable()                      ( REG_TSSI_ENA &= ~TSSI_ENA_ENA )
+#define __tssi_soft_reset()                   ( REG_TSSI_ENA |= TSSI_ENA_SFT_RST )
+#define __tssi_filter_enable_pid0()           ( REG_TSSI_ENA |= TSSI_ENA_PEN_0)
+#define __tssi_filter_disable_pid0()          ( REG_TSSI_ENA &= ~TSSI_ENA_PEN_0)
+#define __tssi_dma_enable()                   ( REG_TSSI_ENA |= TSSI_ENA_DMA_EN )
+#define __tssi_dma_disable()                  ( REG_TSSI_ENA &= ~TSSI_ENA_DMA_EN )
+#define __tssi_filter_enable()                ( REG_TSSI_ENA |= TSSI_ENA_PID_EN )
+#define __tssi_filter_disable()               ( REG_TSSI_ENA &= ~TSSI_ENA_PID_EN )
+
+/* n = 4, 8, 16 */
+#define __tssi_set_tigger_num(n)                        \
+        do {                                            \
+                REG_TSSI_CFG &= ~TSSI_CFG_TRIG_MASK;    \
+                REG_TSSI_CFG |= TSSI_CFG_TRIG_##n;      \
+        } while (0)
+
+#define __tssi_set_data0_mode(n)                                \
+        do {                                                    \
+                REG_TSSI_CFG &= ~ TSSI_CFG_TRANS_MD_MASK;       \
+                REG_TSSI_CFG |= TSSI_CFG_TRANS_MD_##n;          \
+        }  while(0)
+
+#define __tssi_set_wd_1()                     ( REG_TSSI_CFG |= TSSI_CFG_END_WD )
+#define __tssi_set_wd_0()                     ( REG_TSSI_CFG &= ~TSSI_CFG_END_WD )
+
+#define __tssi_set_bt_1()                     ( REG_TSSI_CFG |= TSSI_CFG_END_BD )
+#define __tssi_set_bt_0()                     ( REG_TSSI_CFG &= ~TSSI_CFG_END_BD )
+
+#define __tssi_set_data_pola_high()           ( REG_TSSI_CFG |= TSSI_CFG_TSDI_H )
+#define __tssi_set_data_pola_low()            ( REG_TSSI_CFG &= ~TSSI_CFG_TSDI_H )
+
+#define __tssi_set_data_use_data0()           ( REG_TSSI_CFG |= TSSI_CFG_USE_0 )
+#define __tssi_set_data_use_data7()           ( REG_TSSI_CFG &= ~TSSI_CFG_USE_0 )
+
+#define __tssi_select_clk_fast()              ( REG_TSSI_CFG &= ~TSSI_CFG_TSCLK_CH )
+#define __tssi_select_clk_slow()              ( REG_TSSI_CFG |= TSSI_CFG_TSCLK_CH )
+
+#define __tssi_select_serail_mode()           ( REG_TSSI_CFG &= ~TSSI_CFG_PARAL )
+#define __tssi_select_paral_mode()            ( REG_TSSI_CFG |= TSSI_CFG_PARAL )
+
+#define __tssi_select_clk_nega_edge()         ( REG_TSSI_CFG &= ~TSSI_CFG_TSCLK_P )
+#define __tssi_select_clk_posi_edge()         ( REG_TSSI_CFG |= TSSI_CFG_TSCLK_P )
+
+#define __tssi_select_frm_act_high()          ( REG_TSSI_CFG |= TSSI_CFG_TSFRM_H )
+#define __tssi_select_frm_act_low()           ( REG_TSSI_CFG &= ~TSSI_CFG_TSFRM_H )
+
+#define __tssi_select_str_act_high()          ( REG_TSSI_CFG |= TSSI_CFG_TSSTR_H )
+#define __tssi_select_str_act_low()           ( REG_TSSI_CFG &= ~TSSI_CFG_TSSTR_H )
+
+#define __tssi_select_fail_act_high()         ( REG_TSSI_CFG |= TSSI_CFG_TSFAIL_H )
+#define __tssi_select_fail_act_low()          ( REG_TSSI_CFG &= ~TSSI_CFG_TSFAIL_H )
+
+#define __tssi_enable_data_trigger_irq()      (REG_TSSI_CTRL &= ~TSSI_CTRL_DTRM)
+#define __tssi_disable_data_trigger_irq()     (REG_TSSI_CTRL |= TSSI_CTRL_DTRM)
+
+#define __tssi_enable_ovrn_irq()              ( REG_TSSI_CTRL &= ~TSSI_CTRL_OVRNM )
+#define __tssi_disable_ovrn_irq()             ( REG_TSSI_CTRL |= TSSI_CTRL_OVRNM )
+
+#define __tssi_enable_trig_irq()              ( REG_TSSI_CTRL &= ~TSSI_CTRL_TRIGM )
+#define __tssi_disable_trig_irq()             ( REG_TSSI_CTRL |= TSSI_CTRL_TRIGM ) 
+
+#define __tssi_state_is_dtr()                 ( REG_TSSI_STAT & TSSI_STAT_DTR )
+#define __tssi_state_is_overrun()             ( REG_TSSI_STAT & TSSI_STAT_OVRN )
+#define __tssi_state_trigger_meet()           ( REG_TSSI_STAT & TSSI_STAT_TRIG )
+#define __tssi_clear_state()                  ( REG_TSSI_STAT = 0 ) /* write 0??? */
+#define __tssi_state_clear_overrun()          ( REG_TSSI_STAT = TSSI_STAT_OVRN )   //??????? xyma
+
+//#define __tssi_enable_filte_pid0()            ( REG_TSSI_PEN |= TSSI_PEN_PID0 )
+//#define __tssi_disable_filte_pid0()           ( REG_TSSI_PEN &= ~TSSI_PEN_PID0 )
+
+/* m = 0, ..., 31 */
+////////////////???????????????????????????????????????????????????????????
+
+#define __tssi_enable_pid_filter(m)                             \
+        do {                                                    \
+                int n = (m);                                    \
+                if ( n>=0 && n <(TSSI_PID_MAX*2) ) {            \
+                        REG_TSSI_PEN |= ( 1 << n );             \
+                }                                               \
+        } while (0)
+
+/* m = 0, ..., 31 */
+#define __tssi_disable_pid_filter(m)                                   \
+        do {                                                           \
+                int n = (m);                                           \
+                if ( n>=0 && n <(TSSI_PID_MAX*2) ) {                   \
+                        REG_TSSI_PEN &= ~( 1 << n );                   \
+                }                                                      \
+        } while (0)
+
+/* n = 0, ..., 15 */
+#define __tssi_set_pid0(n, pid0)                                        \
+        do {                                                            \
+                REG_TSSI_PID(n) &= ~TSSI_PID_PID0_MASK;                 \
+                REG_TSSI_PID(n) |= ((pid0)<<TSSI_PID_PID0_BIT)&TSSI_PID_PID0_MASK; \
+        }while (0)
+/* n = 0, ..., 15 */
+#define __tssi_set_pid1(n, pid1)                                        \
+        do {                                                            \
+                REG_TSSI_PID(n) &= ~TSSI_PID_PID1_MASK;                 \
+                REG_TSSI_PID(n) |= ((pid1)<<TSSI_PID_PID1_BIT)&TSSI_PID_PID1_MASK; \
+        }while (0)
+
+/* n = 0, ..., 15 */
+#define __tssi_set_pid(n, pid)                                          \
+        do {                                                            \
+                if ( n>=0 && n < TSSI_PID_MAX*2) {                      \
+                        if ( n < TSSI_PID_MAX )                         \
+                                __tssi_set_pid0(n, pid);                \
+                        else                                            \
+                                __tssi_set_pid1(n-TSSI_PID_MAX, pid);   \
+                }                                                       \
+        }while (0)
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define TVE_BASE        0xB3050100 
+
+/*************************************************************************
+ * TVE (TV Encoder Controller)
+ *************************************************************************/
+#define TVE_CTRL        (TVE_BASE + 0x40) /* TV Encoder Control register */
+#define TVE_FRCFG       (TVE_BASE + 0x44) /* Frame configure register */
+#define TVE_SLCFG1      (TVE_BASE + 0x50) /* TV signal level configure register 1 */
+#define TVE_SLCFG2      (TVE_BASE + 0x54) /* TV signal level configure register 2*/
+#define TVE_SLCFG3      (TVE_BASE + 0x58) /* TV signal level configure register 3*/
+#define TVE_LTCFG1      (TVE_BASE + 0x60) /* Line timing configure register 1 */
+#define TVE_LTCFG2      (TVE_BASE + 0x64) /* Line timing configure register 2 */
+#define TVE_CFREQ       (TVE_BASE + 0x70) /* Chrominance sub-carrier frequency configure register */
+#define TVE_CPHASE      (TVE_BASE + 0x74) /* Chrominance sub-carrier phase configure register */
+#define TVE_CBCRCFG     (TVE_BASE + 0x78) /* Chrominance filter configure register */
+#define TVE_WSSCR       (TVE_BASE + 0x80) /* Wide screen signal control register */
+#define TVE_WSSCFG1     (TVE_BASE + 0x84) /* Wide screen signal configure register 1 */
+#define TVE_WSSCFG2     (TVE_BASE + 0x88) /* Wide screen signal configure register 2 */
+#define TVE_WSSCFG3     (TVE_BASE + 0x8c) /* Wide screen signal configure register 3 */
+
+#define REG_TVE_CTRL     REG32(TVE_CTRL)
+#define REG_TVE_FRCFG    REG32(TVE_FRCFG)
+#define REG_TVE_SLCFG1   REG32(TVE_SLCFG1)
+#define REG_TVE_SLCFG2   REG32(TVE_SLCFG2)
+#define REG_TVE_SLCFG3   REG32(TVE_SLCFG3)
+#define REG_TVE_LTCFG1   REG32(TVE_LTCFG1)
+#define REG_TVE_LTCFG2   REG32(TVE_LTCFG2)
+#define REG_TVE_CFREQ    REG32(TVE_CFREQ)
+#define REG_TVE_CPHASE   REG32(TVE_CPHASE)
+#define REG_TVE_CBCRCFG  REG32(TVE_CBCRCFG)
+#define REG_TVE_WSSCR    REG32(TVE_WSSCR)
+#define REG_TVE_WSSCFG1  REG32(TVE_WSSCFG1)
+#define REG_TVE_WSSCFG2  REG32(TVE_WSSCFG2)
+#define REG_TVE_WSSCFG3  REG32(TVE_WSSCFG3)
+
+/* TV Encoder Control register */
+#define TVE_CTRL_EYCBCR         (1 << 25)    /* YCbCr_enable */
+#define TVE_CTRL_ECVBS          (1 << 24)    /* 1: cvbs_enable 0: s-video*/
+#define TVE_CTRL_DAPD3          (1 << 23)    /* DAC 3 power down */
+#define TVE_CTRL_DAPD2          (1 << 22)    /* DAC 2 power down */     
+#define TVE_CTRL_DAPD1          (1 << 21)    /* DAC 1 power down */     
+#define TVE_CTRL_DAPD           (1 << 20)    /* power down all DACs */
+#define TVE_CTRL_YCDLY_BIT      16
+#define TVE_CTRL_YCDLY_MASK     (0x7 << TVE_CTRL_YCDLY_BIT)
+#define TVE_CTRL_CGAIN_BIT      14
+#define TVE_CTRL_CGAIN_MASK     (0x3 << TVE_CTRL_CGAIN_BIT)
+  #define TVE_CTRL_CGAIN_FULL           (0 << TVE_CTRL_CGAIN_BIT) /* gain = 1 */
+  #define TVE_CTRL_CGAIN_QUTR           (1 << TVE_CTRL_CGAIN_BIT) /* gain = 1/4 */
+  #define TVE_CTRL_CGAIN_HALF           (2 << TVE_CTRL_CGAIN_BIT) /* gain = 1/2 */
+  #define TVE_CTRL_CGAIN_THREE_QURT     (3 << TVE_CTRL_CGAIN_BIT) /* gain = 3/4 */
+#define TVE_CTRL_CBW_BIT        12
+#define TVE_CTRL_CBW_MASK       (0x3 << TVE_CTRL_CBW_BIT)
+  #define TVE_CTRL_CBW_NARROW   (0 << TVE_CTRL_CBW_BIT) /* Narrow band */
+  #define TVE_CTRL_CBW_WIDE     (1 << TVE_CTRL_CBW_BIT) /* Wide band */
+  #define TVE_CTRL_CBW_EXTRA    (2 << TVE_CTRL_CBW_BIT) /* Extra wide band */
+  #define TVE_CTRL_CBW_ULTRA    (3 << TVE_CTRL_CBW_BIT) /* Ultra wide band */
+#define TVE_CTRL_SYNCT          (1 << 9)
+#define TVE_CTRL_PAL            (1 << 8) /* 1: PAL, 0: NTSC */
+#define TVE_CTRL_FINV           (1 << 7) /* invert_top:1-invert top and bottom fields. */
+#define TVE_CTRL_ZBLACK         (1 << 6) /* bypass_yclamp:1-Black of luminance (Y) input is 0.*/
+#define TVE_CTRL_CR1ST          (1 << 5) /* uv_order:0-Cb before Cr,1-Cr before Cb */
+#define TVE_CTRL_CLBAR          (1 << 4) /* Color bar mode:0-Output input video to TV,1-Output color bar to TV */
+#define TVE_CTRL_SWRST          (1 << 0) /* Software reset:1-TVE is reset */
+
+/* Signal level configure register 1 */
+#define TVE_SLCFG1_BLACKL_BIT   0
+#define TVE_SLCFG1_BLACKL_MASK  (0x3ff << TVE_SLCFG1_BLACKL_BIT)
+#define TVE_SLCFG1_WHITEL_BIT   16
+#define TVE_SLCFG1_WHITEL_MASK  (0x3ff << TVE_SLCFG1_WHITEL_BIT)
+
+/* Signal level configure register 2 */
+#define TVE_SLCFG2_BLANKL_BIT    0
+#define TVE_SLCFG2_BLANKL_MASK   (0x3ff << TVE_SLCFG2_BLANKL_BIT)
+#define TVE_SLCFG2_VBLANKL_BIT   16
+#define TVE_SLCFG2_VBLANKL_MASK  (0x3ff << TVE_SLCFG2_VBLANKL_BIT)
+
+/* Signal level configure register 3 */
+#define TVE_SLCFG3_SYNCL_BIT   0
+#define TVE_SLCFG3_SYNCL_MASK  (0xff << TVE_SLCFG3_SYNCL_BIT)
+
+/* Line timing configure register 1 */
+#define TVE_LTCFG1_BACKP_BIT   0
+#define TVE_LTCFG1_BACKP_MASK  (0x7f << TVE_LTCFG1_BACKP_BIT)
+#define TVE_LTCFG1_HSYNCW_BIT   8
+#define TVE_LTCFG1_HSYNCW_MASK  (0x7f << TVE_LTCFG1_HSYNCW_BIT)
+#define TVE_LTCFG1_FRONTP_BIT   16
+#define TVE_LTCFG1_FRONTP_MASK  (0x1f << TVE_LTCFG1_FRONTP_BIT)
+
+/* Line timing configure register 2 */
+#define TVE_LTCFG2_BURSTW_BIT    0
+#define TVE_LTCFG2_BURSTW_MASK   (0x3f << TVE_LTCFG2_BURSTW_BIT)
+#define TVE_LTCFG2_PREBW_BIT     8
+#define TVE_LTCFG2_PREBW_MASK    (0x1f << TVE_LTCFG2_PREBW_BIT)
+#define TVE_LTCFG2_ACTLIN_BIT    16
+#define TVE_LTCFG2_ACTLIN_MASK  (0x7ff << TVE_LTCFG2_ACTLIN_BIT)
+
+/* Chrominance sub-carrier phase configure register */
+#define TVE_CPHASE_CCRSTP_BIT    0
+#define TVE_CPHASE_CCRSTP_MASK   (0x3 << TVE_CPHASE_CCRSTP_BIT)
+  #define TVE_CPHASE_CCRSTP_8   (0 << TVE_CPHASE_CCRSTP_BIT) /* Every 8 field */
+  #define TVE_CPHASE_CCRSTP_4   (1 << TVE_CPHASE_CCRSTP_BIT) /* Every 4 field */
+  #define TVE_CPHASE_CCRSTP_2   (2 << TVE_CPHASE_CCRSTP_BIT) /* Every 2 lines */
+  #define TVE_CPHASE_CCRSTP_0   (3 << TVE_CPHASE_CCRSTP_BIT) /* Never */
+#define TVE_CPHASE_ACTPH_BIT     16
+#define TVE_CPHASE_ACTPH_MASK    (0xff << TVE_CPHASE_ACTPH_BIT)
+#define TVE_CPHASE_INITPH_BIT    24
+#define TVE_CPHASE_INITPH_MASK   (0xff << TVE_CPHASE_INITPH_BIT)
+
+/* Chrominance filter configure register */
+#define TVE_CBCRCFG_CRGAIN_BIT       0
+#define TVE_CBCRCFG_CRGAIN_MASK      (0xff << TVE_CBCRCFG_CRGAIN_BIT)
+#define TVE_CBCRCFG_CBGAIN_BIT       8
+#define TVE_CBCRCFG_CBGAIN_MASK      (0xff << TVE_CBCRCFG_CBGAIN_BIT)
+#define TVE_CBCRCFG_CRBA_BIT         16
+#define TVE_CBCRCFG_CRBA_MASK        (0xff << TVE_CBCRCFG_CRBA_BIT)
+#define TVE_CBCRCFG_CBBA_BIT         24
+#define TVE_CBCRCFG_CBBA_MASK        (0xff << TVE_CBCRCFG_CBBA_BIT)
+
+/* Frame configure register */
+#define TVE_FRCFG_NLINE_BIT          0
+#define TVE_FRCFG_NLINE_MASK         (0x3ff << TVE_FRCFG_NLINE_BIT)
+#define TVE_FRCFG_L1ST_BIT           16
+#define TVE_FRCFG_L1ST_MASK          (0xff << TVE_FRCFG_L1ST_BIT)
+
+/* Wide screen signal control register */
+#define TVE_WSSCR_EWSS0_BIT     0
+#define TVE_WSSCR_EWSS1_BIT     1
+#define TVE_WSSCR_WSSTP_BIT     2
+#define TVE_WSSCR_WSSCKBP_BIT   3
+#define TVE_WSSCR_WSSEDGE_BIT   4
+#define TVE_WSSCR_WSSEDGE_MASK  (0x7 << TVE_WSSCR_WSSEDGE_BIT)
+#define TVE_WSSCR_ENCH_BIT      8
+#define TVE_WSSCR_NCHW_BIT      9
+#define TVE_WSSCR_NCHFREQ_BIT   12
+#define TVE_WSSCR_NCHFREQ_MASK  (0x7 << TVE_WSSCR_NCHFREQ_BIT)
+
+#ifndef __MIPS_ASSEMBLER
+
+/*************************************************************************
+ * TVE (TV Encoder Controller) ops
+ *************************************************************************/
+/* TV Encoder Control register ops */
+#define __tve_soft_reset()              (REG_TVE_CTRL |= TVE_CTRL_SWRST)
+
+#define __tve_output_colorbar()         (REG_TVE_CTRL |= TVE_CTRL_CLBAR)
+#define __tve_output_video()            (REG_TVE_CTRL &= ~TVE_CTRL_CLBAR)
+
+#define __tve_input_cr_first()          (REG_TVE_CTRL |= TVE_CTRL_CR1ST)
+#define __tve_input_cb_first()          (REG_TVE_CTRL &= ~TVE_CTRL_CR1ST)
+
+#define __tve_set_0_as_black()          (REG_TVE_CTRL |= TVE_CTRL_ZBLACK)
+#define __tve_set_16_as_black()         (REG_TVE_CTRL &= ~TVE_CTRL_ZBLACK)
+
+#define __tve_ena_invert_top_bottom()   (REG_TVE_CTRL |= TVE_CTRL_FINV)
+#define __tve_dis_invert_top_bottom()   (REG_TVE_CTRL &= ~TVE_CTRL_FINV)
+
+#define __tve_set_pal_mode()            (REG_TVE_CTRL |= TVE_CTRL_PAL)
+#define __tve_set_ntsc_mode()           (REG_TVE_CTRL &= ~TVE_CTRL_PAL)
+
+#define __tve_set_pal_dura()            (REG_TVE_CTRL |= TVE_CTRL_SYNCT)
+#define __tve_set_ntsc_dura()           (REG_TVE_CTRL &= ~TVE_CTRL_SYNCT)
+
+/* n = 0 ~ 3 */
+#define __tve_set_c_bandwidth(n) \
+do {\
+        REG_TVE_CTRL &= ~TVE_CTRL_CBW_MASK;\
+        REG_TVE_CTRL |= (n) << TVE_CTRL_CBW_BIT;        \
+}while(0)
+
+/* n = 0 ~ 3 */
+#define __tve_set_c_gain(n) \
+do {\
+        REG_TVE_CTRL &= ~TVE_CTRL_CGAIN_MASK;\
+        (REG_TVE_CTRL |= (n) << TVE_CTRL_CGAIN_BIT;     \
+}while(0)
+
+/* n = 0 ~ 7 */
+#define __tve_set_yc_delay(n)                           \
+do {                                                    \
+        REG_TVE_CTRL &= ~TVE_CTRL_YCDLY_MASK            \
+        REG_TVE_CTRL |= ((n) << TVE_CTRL_YCDLY_BIT);    \
+} while(0)
+
+#define __tve_disable_all_dacs()        (REG_TVE_CTRL |= TVE_CTRL_DAPD)
+#define __tve_disable_dac1()            (REG_TVE_CTRL |= TVE_CTRL_DAPD1)
+#define __tve_enable_dac1()             (REG_TVE_CTRL &= ~TVE_CTRL_DAPD1)
+#define __tve_disable_dac2()            (REG_TVE_CTRL |= TVE_CTRL_DAPD2)
+#define __tve_enable_dac2()             (REG_TVE_CTRL &= ~TVE_CTRL_DAPD2)
+#define __tve_disable_dac3()            (REG_TVE_CTRL |= TVE_CTRL_DAPD3)
+#define __tve_enable_dac3()             (REG_TVE_CTRL &= ~TVE_CTRL_DAPD3)
+
+#define __tve_enable_svideo_fmt()       (REG_TVE_CTRL |= TVE_CTRL_ECVBS)
+#define __tve_enable_cvbs_fmt()         (REG_TVE_CTRL &= ~TVE_CTRL_ECVBS)
+
+/* TV Encoder Frame Configure register ops */
+/* n = 0 ~ 255 */
+#define __tve_set_first_video_line(n)           \
+do {\
+                REG_TVE_FRCFG &= ~TVE_FRCFG_L1ST_MASK;\
+                REG_TVE_FRCFG |= (n) << TVE_FRCFG_L1ST_BIT;\
+} while(0)
+/* n = 0 ~ 1023 */
+#define __tve_set_line_num_per_frm(n)           \
+do {\
+                REG_TVE_FRCFG &= ~TVE_FRCFG_NLINE_MASK;\
+                REG_TVE_CFG |= (n) << TVE_FRCFG_NLINE_BIT;\
+} while(0)
+#define __tve_get_video_line_num()\
+        (((REG_TVE_FRCFG & TVE_FRCFG_NLINE_MASK) >> TVE_FRCFG_NLINE_BIT) - 1 - 2 * ((REG_TVE_FRCFG & TVE_FRCFG_L1ST_MASK) >> TVE_FRCFG_L1ST_BIT))
+
+/* TV Encoder Signal Level Configure register ops */
+/* n = 0 ~ 1023 */
+#define __tve_set_white_level(n)                \
+do {\
+                REG_TVE_SLCFG1 &= ~TVE_SLCFG1_WHITEL_MASK;\
+                REG_TVE_SLCFG1 |= (n) << TVE_SLCFG1_WHITEL_BIT;\
+} while(0)
+/* n = 0 ~ 1023 */
+#define __tve_set_black_level(n)                \
+do {\
+                REG_TVE_SLCFG1 &= ~TVE_SLCFG1_BLACKL_MASK;\
+                REG_TVE_SLCFG1 |= (n) << TVE_SLCFG1_BLACKL_BIT;\
+} while(0)
+/* n = 0 ~ 1023 */
+#define __tve_set_blank_level(n)                \
+do {\
+                REG_TVE_SLCFG2 &= ~TVE_SLCFG2_BLANKL_MASK;\
+                REG_TVE_SLCFG2 |= (n) << TVE_SLCFG2_BLANKL_BIT;\
+} while(0)
+/* n = 0 ~ 1023 */
+#define __tve_set_vbi_blank_level(n)            \
+do {\
+                REG_TVE_SLCFG2 &= ~TVE_SLCFG2_VBLANKL_MASK;\
+                REG_TVE_SLCFG2 |= (n) << TVE_SLCFG2_VBLANKL_BIT;\
+} while(0)
+/* n = 0 ~ 1023 */
+#define __tve_set_sync_level(n)         \
+do {\
+                REG_TVE_SLCFG3 &= ~TVE_SLCFG3_SYNCL_MASK;\
+                REG_TVE_SLCFG3 |= (n) << TVE_SLCFG3_SYNCL_BIT;\
+} while(0)
+
+/* TV Encoder Signal Level Configure register ops */
+/* n = 0 ~ 31 */
+#define __tve_set_front_porch(n)                \
+do {\
+                REG_TVE_LTCFG1 &= ~TVE_LTCFG1_FRONTP_MASK;\
+                REG_TVE_LTCFG1 |= (n) << TVE_LTCFG1_FRONTP_BIT; \
+} while(0)
+/* n = 0 ~ 127 */
+#define __tve_set_hsync_width(n)                \
+do {\
+                REG_TVE_LTCFG1 &= ~TVE_LTCFG1_HSYNCW_MASK;\
+                REG_TVE_LTCFG1 |= (n) << TVE_LTCFG1_HSYNCW_BIT; \
+} while(0)
+/* n = 0 ~ 127 */
+#define __tve_set_back_porch(n)         \
+do {\
+                REG_TVE_LTCFG1 &= ~TVE_LTCFG1_BACKP_MASK;\
+                REG_TVE_LTCFG1 |= (n) << TVE_LTCFG1_BACKP_BIT;  \
+} while(0)
+/* n = 0 ~ 2047 */
+#define __tve_set_active_linec(n)               \
+do {\
+                REG_TVE_LTCFG2 &= ~TVE_LTCFG2_ACTLIN_MASK;\
+                REG_TVE_LTCFG2 |= (n) << TVE_LTCFG2_ACTLIN_BIT; \
+} while(0)
+/* n = 0 ~ 31 */
+#define __tve_set_breezy_way(n)         \
+do {\
+                REG_TVE_LTCFG2 &= ~TVE_LTCFG2_PREBW_MASK;\
+                REG_TVE_LTCFG2 |= (n) << TVE_LTCFG2_PREBW_BIT;  \
+} while(0)
+
+/* n = 0 ~ 127 */
+#define __tve_set_burst_width(n)                \
+do {\
+                REG_TVE_LTCFG2 &= ~TVE_LTCFG2_BURSTW_MASK;\
+                REG_TVE_LTCFG2 |= (n) << TVE_LTCFG2_BURSTW_BIT; \
+} while(0)
+
+/* TV Encoder Chrominance filter and Modulation register ops */
+/* n = 0 ~ (2^32-1) */
+#define __tve_set_c_sub_carrier_freq(n)  REG_TVE_CFREQ = (n)
+/* n = 0 ~ 255 */
+#define __tve_set_c_sub_carrier_init_phase(n) \
+do {   \
+        REG_TVE_CPHASE &= ~TVE_CPHASE_INITPH_MASK;      \
+        REG_TVE_CPHASE |= (n) << TVE_CPHASE_INITPH_BIT; \
+} while(0)
+/* n = 0 ~ 255 */
+#define __tve_set_c_sub_carrier_act_phase(n) \
+do {   \
+        REG_TVE_CPHASE &= ~TVE_CPHASE_ACTPH_MASK;       \
+        REG_TVE_CPHASE |= (n) << TVE_CPHASE_ACTPH_BIT;  \
+} while(0)
+/* n = 0 ~ 255 */
+#define __tve_set_c_phase_rst_period(n) \
+do {   \
+        REG_TVE_CPHASE &= ~TVE_CPHASE_CCRSTP_MASK;      \
+        REG_TVE_CPHASE |= (n) << TVE_CPHASE_CCRSTP_BIT; \
+} while(0)
+/* n = 0 ~ 255 */
+#define __tve_set_cb_burst_amp(n) \
+do {   \
+        REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CBBA_MASK;      \
+        REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CBBA_BIT; \
+} while(0)
+/* n = 0 ~ 255 */
+#define __tve_set_cr_burst_amp(n) \
+do {   \
+        REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CRBA_MASK;      \
+        REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CRBA_BIT; \
+} while(0)
+/* n = 0 ~ 255 */
+#define __tve_set_cb_gain_amp(n) \
+do {   \
+        REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CBGAIN_MASK;    \
+        REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CBGAIN_BIT;       \
+} while(0)
+/* n = 0 ~ 255 */
+#define __tve_set_cr_gain_amp(n) \
+do {   \
+        REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CRGAIN_MASK;    \
+        REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CRGAIN_BIT;       \
+} while(0)
+
+/* TV Encoder Wide Screen Signal Control register ops */
+/* n = 0 ~ 7 */
+#define __tve_set_notch_freq(n) \
+do {   \
+        REG_TVE_WSSCR &= ~TVE_WSSCR_NCHFREQ_MASK;       \
+        REG_TVE_WSSCR |= (n) << TVE_WSSCR_NCHFREQ_BIT;  \
+} while(0)
+/* n = 0 ~ 7 */
+#define __tve_set_notch_width() (REG_TVE_WSSCR |= TVE_WSSCR_NCHW_BIT)
+#define __tve_clear_notch_width()       (REG_TVE_WSSCR &= ~TVE_WSSCR_NCHW_BIT)
+#define __tve_enable_notch()            (REG_TVE_WSSCR |= TVE_WSSCR_ENCH_BIT)
+#define __tve_disable_notch()           (REG_TVE_WSSCR &= ~TVE_WSSCR_ENCH_BIT)
+/* n = 0 ~ 7 */
+#define __tve_set_wss_edge(n) \
+do {   \
+        REG_TVE_WSSCR &= ~TVE_WSSCR_WSSEDGE_MASK;       \
+        REG_TVE_WSSCR |= (n) << TVE_WSSCR_WSSEDGE_BIT;  \
+} while(0)
+#define __tve_set_wss_clkbyp()          (REG_TVE_WSSCR |= TVE_WSSCR_WSSCKBP_BIT)
+#define __tve_set_wss_type()            (REG_TVE_WSSCR |= TVE_WSSCR_WSSTP_BIT)
+#define __tve_enable_wssf1()            (REG_TVE_WSSCR |= TVE_WSSCR_EWSS1_BIT)
+#define __tve_enable_wssf0()            (REG_TVE_WSSCR |= TVE_WSSCR_EWSS0_BIT)
+
+/* TV Encoder Wide Screen Signal Configure register 1, 2 and 3 ops */
+/* n = 0 ~ 1023 */
+#define __tve_set_wss_level(n) \
+do {   \
+        REG_TVE_WSSCFG1 &= ~TVE_WSSCFG1_WSSL_MASK;      \
+        REG_TVE_WSSCFG1 |= (n) << TVE_WSSCFG1_WSSL_BIT; \
+} while(0)
+/* n = 0 ~ 4095 */
+#define __tve_set_wss_freq(n) \
+do {   \
+        REG_TVE_WSSCFG1 &= ~TVE_WSSCFG1_WSSFREQ_MASK;   \
+        REG_TVE_WSSCFG1 |= (n) << TVE_WSSCFG1_WSSFREQ_BIT;      \
+} while(0)
+/* n = 0, 1; l = 0 ~ 255 */
+#define __tve_set_wss_line(n,v)                 \
+do {   \
+        REG_TVE_WSSCFG##n &= ~TVE_WSSCFG_WSSLINE_MASK;  \
+        REG_TVE_WSSCFG##n |= (v) << TVE_WSSCFG_WSSLINE_BIT;     \
+} while(0)
+/* n = 0, 1; d = 0 ~ (2^20-1) */
+#define __tve_set_wss_data(n, v)                        \
+do {   \
+        REG_TVE_WSSCFG##n &= ~TVE_WSSCFG_WSSLINE_MASK;  \
+        REG_TVE_WSSCFG##n |= (v) << TVE_WSSCFG_WSSLINE_BIT;     \
+} while(0)
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define UART0_BASE      0xB0030000
+#define UART1_BASE      0xB0031000
+#define UART2_BASE      0xB0032000
+#define UART3_BASE      0xB0033000
+
+/*************************************************************************
+ * UART
+ *************************************************************************/
+
+#define IRDA_BASE       UART0_BASE
+#define UART_BASE       UART0_BASE
+#define UART_OFF        0x1000
+
+/* Register Offset */
+#define OFF_RDR         (0x00)  /* R  8b H'xx */
+#define OFF_TDR         (0x00)  /* W  8b H'xx */
+#define OFF_DLLR        (0x00)  /* RW 8b H'00 */
+#define OFF_DLHR        (0x04)  /* RW 8b H'00 */
+#define OFF_IER         (0x04)  /* RW 8b H'00 */
+#define OFF_ISR         (0x08)  /* R  8b H'01 */
+#define OFF_FCR         (0x08)  /* W  8b H'00 */
+#define OFF_LCR         (0x0C)  /* RW 8b H'00 */
+#define OFF_MCR         (0x10)  /* RW 8b H'00 */
+#define OFF_LSR         (0x14)  /* R  8b H'00 */
+#define OFF_MSR         (0x18)  /* R  8b H'00 */
+#define OFF_SPR         (0x1C)  /* RW 8b H'00 */
+#define OFF_SIRCR       (0x20)  /* RW 8b H'00, UART0 */
+#define OFF_UMR         (0x24)  /* RW 8b H'00, UART M Register */
+#define OFF_UACR        (0x28)  /* RW 8b H'00, UART Add Cycle Register */
+
+/* Register Address */
+#define UART0_RDR       (UART0_BASE + OFF_RDR)
+#define UART0_TDR       (UART0_BASE + OFF_TDR)
+#define UART0_DLLR      (UART0_BASE + OFF_DLLR)
+#define UART0_DLHR      (UART0_BASE + OFF_DLHR)
+#define UART0_IER       (UART0_BASE + OFF_IER)
+#define UART0_ISR       (UART0_BASE + OFF_ISR)
+#define UART0_FCR       (UART0_BASE + OFF_FCR)
+#define UART0_LCR       (UART0_BASE + OFF_LCR)
+#define UART0_MCR       (UART0_BASE + OFF_MCR)
+#define UART0_LSR       (UART0_BASE + OFF_LSR)
+#define UART0_MSR       (UART0_BASE + OFF_MSR)
+#define UART0_SPR       (UART0_BASE + OFF_SPR)
+#define UART0_SIRCR     (UART0_BASE + OFF_SIRCR)
+#define UART0_UMR       (UART0_BASE + OFF_UMR)
+#define UART0_UACR      (UART0_BASE + OFF_UACR)
+
+#define UART1_RDR       (UART1_BASE + OFF_RDR)
+#define UART1_TDR       (UART1_BASE + OFF_TDR)
+#define UART1_DLLR      (UART1_BASE + OFF_DLLR)
+#define UART1_DLHR      (UART1_BASE + OFF_DLHR)
+#define UART1_IER       (UART1_BASE + OFF_IER)
+#define UART1_ISR       (UART1_BASE + OFF_ISR)
+#define UART1_FCR       (UART1_BASE + OFF_FCR)
+#define UART1_LCR       (UART1_BASE + OFF_LCR)
+#define UART1_MCR       (UART1_BASE + OFF_MCR)
+#define UART1_LSR       (UART1_BASE + OFF_LSR)
+#define UART1_MSR       (UART1_BASE + OFF_MSR)
+#define UART1_SPR       (UART1_BASE + OFF_SPR)
+#define UART1_SIRCR     (UART1_BASE + OFF_SIRCR)
+
+#define UART2_RDR       (UART2_BASE + OFF_RDR)
+#define UART2_TDR       (UART2_BASE + OFF_TDR)
+#define UART2_DLLR      (UART2_BASE + OFF_DLLR)
+#define UART2_DLHR      (UART2_BASE + OFF_DLHR)
+#define UART2_IER       (UART2_BASE + OFF_IER)
+#define UART2_ISR       (UART2_BASE + OFF_ISR)
+#define UART2_FCR       (UART2_BASE + OFF_FCR)
+#define UART2_LCR       (UART2_BASE + OFF_LCR)
+#define UART2_MCR       (UART2_BASE + OFF_MCR)
+#define UART2_LSR       (UART2_BASE + OFF_LSR)
+#define UART2_MSR       (UART2_BASE + OFF_MSR)
+#define UART2_SPR       (UART2_BASE + OFF_SPR)
+#define UART2_SIRCR     (UART2_BASE + OFF_SIRCR)
+
+#define UART3_RDR       (UART3_BASE + OFF_RDR)
+#define UART3_TDR       (UART3_BASE + OFF_TDR)
+#define UART3_DLLR      (UART3_BASE + OFF_DLLR)
+#define UART3_DLHR      (UART3_BASE + OFF_DLHR)
+#define UART3_IER       (UART3_BASE + OFF_IER)
+#define UART3_ISR       (UART3_BASE + OFF_ISR)
+#define UART3_FCR       (UART3_BASE + OFF_FCR)
+#define UART3_LCR       (UART3_BASE + OFF_LCR)
+#define UART3_MCR       (UART3_BASE + OFF_MCR)
+#define UART3_LSR       (UART3_BASE + OFF_LSR)
+#define UART3_MSR       (UART3_BASE + OFF_MSR)
+#define UART3_SPR       (UART3_BASE + OFF_SPR)
+#define UART3_SIRCR     (UART3_BASE + OFF_SIRCR)
+
+/*
+ * Define macros for UARTIER
+ * UART Interrupt Enable Register
+ */
+#define UARTIER_RIE     (1 << 0)        /* 0: receive fifo full interrupt disable */
+#define UARTIER_TIE     (1 << 1)        /* 0: transmit fifo empty interrupt disable */
+#define UARTIER_RLIE    (1 << 2)        /* 0: receive line status interrupt disable */
+#define UARTIER_MIE     (1 << 3)        /* 0: modem status interrupt disable */
+#define UARTIER_RTIE    (1 << 4)        /* 0: receive timeout interrupt disable */
+
+/*
+ * Define macros for UARTISR
+ * UART Interrupt Status Register
+ */
+#define UARTISR_IP      (1 << 0)        /* 0: interrupt is pending  1: no interrupt */
+#define UARTISR_IID     (7 << 1)        /* Source of Interrupt */
+#define UARTISR_IID_MSI         (0 << 1)  /* Modem status interrupt */
+#define UARTISR_IID_THRI        (1 << 1)  /* Transmitter holding register empty */
+#define UARTISR_IID_RDI         (2 << 1)  /* Receiver data interrupt */
+#define UARTISR_IID_RLSI        (3 << 1)  /* Receiver line status interrupt */
+#define UARTISR_IID_RTO         (6 << 1)  /* Receive timeout */
+#define UARTISR_FFMS            (3 << 6)  /* FIFO mode select, set when UARTFCR.FE is set to 1 */
+#define UARTISR_FFMS_NO_FIFO    (0 << 6)
+#define UARTISR_FFMS_FIFO_MODE  (3 << 6)
+
+/*
+ * Define macros for UARTFCR
+ * UART FIFO Control Register
+ */
+#define UARTFCR_FE      (1 << 0)        /* 0: non-FIFO mode  1: FIFO mode */
+#define UARTFCR_RFLS    (1 << 1)        /* write 1 to flush receive FIFO */
+#define UARTFCR_TFLS    (1 << 2)        /* write 1 to flush transmit FIFO */
+#define UARTFCR_DMS     (1 << 3)        /* 0: disable DMA mode */
+#define UARTFCR_UUE     (1 << 4)        /* 0: disable UART */
+#define UARTFCR_RTRG    (3 << 6)        /* Receive FIFO Data Trigger */
+#define UARTFCR_RTRG_1  (0 << 6)
+#define UARTFCR_RTRG_4  (1 << 6)
+#define UARTFCR_RTRG_8  (2 << 6)
+#define UARTFCR_RTRG_15 (3 << 6)
+
+/*
+ * Define macros for UARTLCR
+ * UART Line Control Register
+ */
+#define UARTLCR_WLEN    (3 << 0)        /* word length */
+#define UARTLCR_WLEN_5  (0 << 0)
+#define UARTLCR_WLEN_6  (1 << 0)
+#define UARTLCR_WLEN_7  (2 << 0)
+#define UARTLCR_WLEN_8  (3 << 0)
+#define UARTLCR_STOP    (1 << 2)        /* 0: 1 stop bit when word length is 5,6,7,8
+                                           1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
+#define UARTLCR_STOP1   (0 << 2)
+#define UARTLCR_STOP2   (1 << 2)
+#define UARTLCR_PE      (1 << 3)        /* 0: parity disable */
+#define UARTLCR_PROE    (1 << 4)        /* 0: even parity  1: odd parity */
+#define UARTLCR_SPAR    (1 << 5)        /* 0: sticky parity disable */
+#define UARTLCR_SBRK    (1 << 6)        /* write 0 normal, write 1 send break */
+#define UARTLCR_DLAB    (1 << 7)        /* 0: access UARTRDR/TDR/IER  1: access UARTDLLR/DLHR */
+
+/*
+ * Define macros for UARTLSR
+ * UART Line Status Register
+ */
+#define UARTLSR_DR      (1 << 0)        /* 0: receive FIFO is empty  1: receive data is ready */
+#define UARTLSR_ORER    (1 << 1)        /* 0: no overrun error */
+#define UARTLSR_PER     (1 << 2)        /* 0: no parity error */
+#define UARTLSR_FER     (1 << 3)        /* 0; no framing error */
+#define UARTLSR_BRK     (1 << 4)        /* 0: no break detected  1: receive a break signal */
+#define UARTLSR_TDRQ    (1 << 5)        /* 1: transmit FIFO half "empty" */
+#define UARTLSR_TEMT    (1 << 6)        /* 1: transmit FIFO and shift registers empty */
+#define UARTLSR_RFER    (1 << 7)        /* 0: no receive error  1: receive error in FIFO mode */
+
+/*
+ * Define macros for UARTMCR
+ * UART Modem Control Register
+ */
+#define UARTMCR_RTS     (1 << 1)        /* 0: RTS_ output high, 1: RTS_ output low */
+#define UARTMCR_LOOP    (1 << 4)        /* 0: normal  1: loopback mode */
+#define UARTMCR_FCM     (1 << 6)        /* 0: software  1: hardware */
+#define UARTMCR_MCE     (1 << 7)        /* 0: modem function is disable */
+
+/*
+ * Define macros for UARTMSR
+ * UART Modem Status Register
+ */
+#define UARTMSR_CCTS    (1 << 0)        /* 1: a change on CTS_ pin */
+#define UARTMSR_CTS     (1 << 4)        /* 0: CTS_ pin is high */
+
+/*
+ * Define macros for SIRCR
+ * Slow IrDA Control Register
+ */
+#define SIRCR_TSIRE     (1 << 0)  /* 0: transmitter is in UART mode  1: SIR mode */
+#define SIRCR_RSIRE     (1 << 1)  /* 0: receiver is in UART mode  1: SIR mode */
+#define SIRCR_TPWS      (1 << 2)  /* 0: transmit 0 pulse width is 3/16 of bit length
+                                           1: 0 pulse width is 1.6us for 115.2Kbps */
+#define SIRCR_TDPL      (1 << 3)  /* 0: encoder generates a positive pulse for 0 */
+#define SIRCR_RDPL      (1 << 4)  /* 0: decoder interprets positive pulse as 0 */
+
+#ifndef __MIPS_ASSEMBLER
+
+/***************************************************************************
+ * UART
+ ***************************************************************************/
+#define __jtag_as_uart3()                       \
+do {                                            \
+        REG_GPIO_PXSELC(0) = 0x40000000;        \
+        REG_GPIO_PXSELS(0) = 0x80000000;        \
+} while(0)
+
+#define __uart_enable(n) \
+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) |= UARTFCR_UUE | UARTFCR_FE )
+#define __uart_disable(n) \
+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE )
+
+#define __uart_enable_transmit_irq(n) \
+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE )
+#define __uart_disable_transmit_irq(n) \
+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE )
+
+#define __uart_enable_receive_irq(n) \
+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
+#define __uart_disable_receive_irq(n) \
+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
+
+#define __uart_enable_loopback(n) \
+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP )
+#define __uart_disable_loopback(n) \
+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP )
+
+#define __uart_set_8n1(n) \
+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 )
+
+#define __uart_set_baud(n, devclk, baud)                                                \
+  do {                                                                                  \
+        REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB;                       \
+        REG8(UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff;        \
+        REG8(UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \
+        REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB;                      \
+  } while (0)
+
+#define __uart_parity_error(n) \
+  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 )
+
+#define __uart_clear_errors(n) \
+  ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )
+
+#define __uart_transmit_fifo_empty(n) \
+  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 )
+
+#define __uart_transmit_end(n) \
+  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 )
+
+#define __uart_transmit_char(n, ch) \
+  REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch)
+
+#define __uart_receive_fifo_full(n) \
+  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 )
+
+#define __uart_receive_ready(n) \
+  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 )
+
+#define __uart_receive_char(n) \
+  REG8(UART_BASE + UART_OFF*(n) + OFF_RDR)
+
+#define __uart_disable_irda() \
+  ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
+#define __uart_enable_irda() \
+  /* Tx high pulse as 0, Rx low pulse as 0 */ \
+  ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
+
+#endif /* __MIPS_ASSEMBLER */
+
+/*
+ * Watchdog timer module(WDT) address definition
+ */
+#define WDT_BASE        0xb0002000
+
+/*
+ * WDT registers offset address definition
+ */
+#define WDT_WDR_OFFSET          (0x00)  /* rw, 16, 0x???? */
+#define WDT_WCER_OFFSET         (0x04)  /* rw,  8, 0x00 */
+#define WDT_WCNT_OFFSET         (0x08)  /* rw, 16, 0x???? */
+#define WDT_WCSR_OFFSET         (0x0c)  /* rw, 16, 0x0000 */
+
+/*
+ * WDT registers address definition
+ */
+#define WDT_WDR         (WDT_BASE + WDT_WDR_OFFSET)
+#define WDT_WCER        (WDT_BASE + WDT_WCER_OFFSET)
+#define WDT_WCNT        (WDT_BASE + WDT_WCNT_OFFSET)
+#define WDT_WCSR        (WDT_BASE + WDT_WCSR_OFFSET)
+
+/*
+ * WDT registers common define
+ */
+
+/* Watchdog counter enable register(WCER) */
+#define WCER_TCEN       BIT0
+
+/* Watchdog control register(WCSR) */
+#define WCSR_PRESCALE_LSB       3
+#define WCSR_PRESCALE_MASK      BITS_H2L(5, WCSR_PRESCALE_LSB)
+#define WCSR_PRESCALE1          (0x0 << WCSR_PRESCALE_LSB)
+#define WCSR_PRESCALE4          (0x1 << WCSR_PRESCALE_LSB)
+#define WCSR_PRESCALE16         (0x2 << WCSR_PRESCALE_LSB)
+#define WCSR_PRESCALE64         (0x3 << WCSR_PRESCALE_LSB)
+#define WCSR_PRESCALE256        (0x4 << WCSR_PRESCALE_LSB)
+#define WCSR_PRESCALE1024       (0x5 << WCSR_PRESCALE_LSB)
+
+#define WCSR_CLKIN_LSB          0
+#define WCSR_CLKIN_MASK         BITS_H2L(2, WCSR_CLKIN_LSB)
+#define WCSR_CLKIN_PCK          (0x1 << WCSR_CLKIN_LSB)
+#define WCSR_CLKIN_RTC          (0x2 << WCSR_CLKIN_LSB)
+#define WCSR_CLKIN_EXT          (0x4 << WCSR_CLKIN_LSB)
+
+#ifndef __MIPS_ASSEMBLER
+
+#define REG_WDT_WDR     REG16(WDT_WDR)
+#define REG_WDT_WCER    REG8(WDT_WCER)
+#define REG_WDT_WCNT    REG16(WDT_WCNT)
+#define REG_WDT_WCSR    REG16(WDT_WCSR)
+
+#endif /* __MIPS_ASSEMBLER */
+
+/*
+ * Operating system timer module(OST) address definition
+ */
+#define OST_BASE        0xb0002000
+
+/*
+ * OST registers offset address definition
+ */
+#define OST_OSTDR_OFFSET        (0xe0)  /* rw, 32, 0x???????? */
+#define OST_OSTCNT_OFFSET       (0xe4)  /* rw, 32, 0x???????? */
+#define OST_OSTCNTL_OFFSET      (0xe4)  /* rw, 32, 0x???????? */
+#define OST_OSTCNTH_OFFSET      (0xe8)  /* rw, 32, 0x???????? */
+#define OST_OSTCSR_OFFSET       (0xec)  /* rw, 16, 0x0000 */
+#define OST_OSTCNTHBUF_OFFSET   (0xfc)  /*  r, 32, 0x???????? */
+
+/*
+ * OST registers address definition
+ */
+#define OST_OSTDR       (OST_BASE + OST_OSTDR_OFFSET)
+#define OST_OSTCNT      (OST_BASE + OST_OSTCNT_OFFSET)
+#define OST_OSTCNTL     (OST_BASE + OST_OSTCNTL_OFFSET)
+#define OST_OSTCNTH     (OST_BASE + OST_OSTCNTH_OFFSET)
+#define OST_OSTCSR      (OST_BASE + OST_OSTCSR_OFFSET)
+#define OST_OSTCNTHBUF  (OST_BASE + OST_OSTCNTHBUF_OFFSET)
+
+/*
+ * OST registers common define
+ */
+
+/* Operating system control register(OSTCSR) */
+#define OSTCSR_CNT_MD           BIT15
+#define OSTCSR_SD               BIT9
+#define OSTCSR_EXT_EN           BIT2
+#define OSTCSR_RTC_EN           BIT1
+#define OSTCSR_PCK_EN           BIT0
+
+#define OSTCSR_PRESCALE_LSB     3
+#define OSTCSR_PRESCALE_MASK    BITS_H2L(5, OSTCSR_PRESCALE_LSB)
+#define OSTCSR_PRESCALE1        (0x0 << OSTCSR_PRESCALE_LSB)
+#define OSTCSR_PRESCALE4        (0x1 << OSTCSR_PRESCALE_LSB)
+#define OSTCSR_PRESCALE16       (0x2 << OSTCSR_PRESCALE_LSB)
+#define OSTCSR_PRESCALE64       (0x3 << OSTCSR_PRESCALE_LSB)
+#define OSTCSR_PRESCALE256      (0x4 << OSTCSR_PRESCALE_LSB)
+#define OSTCSR_PRESCALE1024     (0x5 << OSTCSR_PRESCALE_LSB)
+
+#ifndef __MIPS_ASSEMBLER
+
+#define REG_OST_OSTDR           REG32(OST_OSTDR)
+#define REG_OST_OSTCNT          REG32(OST_OSTCNT)
+#define REG_OST_OSTCNTL         REG32(OST_OSTCNTL)
+#define REG_OST_OSTCNTH         REG32(OST_OSTCNTH)
+#define REG_OST_OSTCSR          REG16(OST_OSTCSR)
+#define REG_OST_OSTCNTHBUF      REG32(OST_OSTCNTHBUF)
+
+#endif /* __MIPS_ASSEMBLER */
+
+#define AOSD_BASE        0xB3070000
+
+/*************************************************************************
+ * OSD (On Screen Display)
+ *************************************************************************/
+#define AOSD_ADDR0             (AOSD_BASE + 0x00)
+#define AOSD_ADDR1             (AOSD_BASE + 0x04)
+#define AOSD_ADDR2             (AOSD_BASE + 0x08)
+#define AOSD_ADDR3             (AOSD_BASE + 0x0C)
+#define AOSD_WADDR             (AOSD_BASE + 0x10)
+#define AOSD_ADDRLEN           (AOSD_BASE + 0x14)
+#define AOSD_ALPHA_VALUE       (AOSD_BASE + 0x18)
+#define AOSD_CTRL              (AOSD_BASE + 0x1C)
+#define AOSD_INT               (AOSD_BASE + 0x20)
+
+#define REG_AOSD_ADDR0         REG32(AOSD_ADDR0)
+#define REG_AOSD_ADDR1         REG32(AOSD_ADDR1)
+#define REG_AOSD_ADDR2         REG32(AOSD_ADDR2)
+#define REG_AOSD_ADDR3         REG32(AOSD_ADDR3)
+#define REG_AOSD_WADDR         REG32(AOSD_WADDR)
+#define REG_AOSD_ADDRLEN       REG32(AOSD_ADDRLEN)
+#define REG_AOSD_ALPHA_VALUE   REG32(AOSD_ALPHA_VALUE)
+#define REG_AOSD_CTRL          REG32(AOSD_CTRL)
+#define REG_AOSD_INT           REG32(AOSD_INT)
+
+#define AOSD_CTRL_FRMLV_MASK        (0x3 << 18)
+#define AOSD_CTRL_FRMLV_2        (0x1 << 18)
+#define AOSD_CTRL_FRMLV_3        (0x2 << 18)
+#define AOSD_CTRL_FRMLV_4        (0x3 << 18)
+
+#define AOSD_CTRL_FRM_END        (1 << 17)
+#define AOSD_CTRL_ALPHA_START    (1 << 16)
+#define AOSD_CTRL_INT_MAKS            (1 << 15)
+#define AOSD_CTRL_CHANNEL_LEVEL_BIT    7
+#define AOSD_CTRL_CHANNEL_LEVEL_MASK   (0xff <<  AOSD_CTRL_CHANNEL_LEVEL_BIT)
+#define AOSD_CTRL_ALPHA_MODE_BIT       3
+#define AOSD_CTRL_ALPHA_MODE_MASK      (0xf << AOSD_CTRL_ALPHA_MODE_BIT)
+#define AOSD_CTRL_ALPHA_PIXEL_MODE     0
+#define AOSD_CTRL_ALPHA_FRAME_MODE     1
+
+#define AOSD_CTRL_FORMAT_MODE_BIT     1
+#define AOSD_CTRL_FORMAT_MODE_MASK     (0x3 << 1)
+#define AOSD_CTRL_RGB565_FORMAT_MODE   (0 << AOSD_CTRL_FORMAT_MODE_BIT)
+#define AOSD_CTRL_RGB555_FORMAT_MODE   (1 << AOSD_CTRL_FORMAT_MODE_BIT)
+#define AOSD_CTRL_RGB8888_FORMAT_MODE  (2 << AOSD_CTRL_FORMAT_MODE_BIT)
+
+#define AOSD_ALPHA_ENABLE        (1 << 0)
+
+#define AOSD_INT_COMPRESS_END   (1 << 1)
+#define AOSD_INT_AOSD_END        (1 << 0)
+
+#define __osd_enable_alpha()    (REG_AOSD_CTRL |= AOSD_ALPHA_ENABLE)
+#define __osd_alpha_start()     (REG_AOSD_CTRL |= AOSD_CTRL_ALPHA_START) 
+
+/*************************************************************************
+ * COMPRESS
+ *************************************************************************/
+#define COMPRESS_SCR_ADDR      (AOSD_BASE + 0x00)
+#define COMPRESS_DES_ADDR      (AOSD_BASE + 0x10)
+#define COMPRESS_DST_OFFSET       (AOSD_BASE + 0x34)
+#define COMPRESS_FRAME_SIZE       (AOSD_BASE + 0x38)
+#define COMPRESS_CTRL       (AOSD_BASE + 0x3C)
+#define COMPRESS_RATIO      (AOSD_BASE + 0x40)
+#define COMPRESS_SRC_OFFSET     (AOSD_BASE + 0x44)
+ 
+#define REG_COMPRESS_SCR_ADDR      REG32(COMPRESS_SCR_ADDR)
+#define REG_COMPRESS_DES_ADDR      REG32(COMPRESS_DES_ADDR)
+#define REG_COMPRESS_DST_OFFSET       REG32(COMPRESS_DST_OFFSET)
+#define REG_COMPRESS_FRAME_SIZE       REG32(COMPRESS_FRAME_SIZE)
+#define REG_COMPRESS_CTRL       REG32(COMPRESS_CTRL)
+#define REG_COMPRESS_RATIO      REG32(COMPRESS_RATIO)
+#define REG_COMPRESS_SRC_OFFSET     REG32(COMPRESS_SRC_OFFSET)
+
+#define COMPRESS_CTRL_WITHOUT_ALPHA     (1 << 4)
+#define COMPRESS_CTRL_WITH_ALPHA     (0 << 4)
+#define COMPRESS_CTRL_COMP_START   (1 << 3)
+#define COMPRESS_CTRL_COMP_END     (1 << 2)
+#define COMPRESS_CTRL_INT_MASK     (1 << 1)
+#define COMPRESS_CTRL_COMP_ENABLE  (1 << 0)
+
+#define COMPRESS_RATIO_FRM_BYPASS   (1 << 31)
+#define COMPRESS_BYPASS_ROW         (1 << 12)
+#define COMPRESS_ROW_QUARTER        (1 << 0)
+
+#define COMPRESS_CTRL_ALIGNED_MODE_BIT  (31)
+#define COMPRESS_CTRL_ALIGNED_16_WORD   (0 << COMPRESS_CTRL_ALIGNED_MODE_BIT)
+#define COMPRESS_CTRL_ALIGNED_64_WORD   (1 << COMPRESS_CTRL_ALIGNED_MODE_BIT)
+
+#define __compress_enable()       (REG_COMPRESS_CTRL |= COMPRESS_INT_AOSD_END)      
+#define __compress_start()        (REG_COMPRESS_CTRL |= COMPRESS_CTRL_COMP_START)      
+#define __compress_with_alpha()   (REG_COMPRESS_CTRL |= COMPRESS_CTRL_ALPHA_EN)      
+
+/* Rockbox defines */
+
+/* Timer frequency */
+#define TIMER_FREQ (CFG_EXTAL) /* For full precision! */
+
+/* Serial */
+#define CFG_UART_BASE UART1_BASE /* Base of the UART channel */
+#define CFG_BAUDRATE  57600
+
+#endif /* __JZ4760B_H__ */
diff --git a/firmware/powermgmt.c b/firmware/powermgmt.c
index 4cfcbbd56d..60565b1573 100644
--- a/firmware/powermgmt.c
+++ b/firmware/powermgmt.c
@@ -129,7 +129,7 @@ static int battery_type = 0;
 /* Power history: power_history[0] is the newest sample */
 unsigned short power_history[POWER_HISTORY_LEN] = {0};
 
-#if CONFIG_CPU == JZ4732 /* FIXME! */ || (CONFIG_PLATFORM & PLATFORM_HOSTED)
+#if (CONFIG_CPU == JZ4732) || (CONFIG_CPU == JZ4760B) || (CONFIG_PLATFORM & PLATFORM_HOSTED)
 static char power_stack[DEFAULT_STACK_SIZE + POWERMGMT_DEBUG_STACK];
 #else
 static char power_stack[DEFAULT_STACK_SIZE/2 + POWERMGMT_DEBUG_STACK];
diff --git a/firmware/sound.c b/firmware/sound.c
index a19cc15c41..eb66f34c5d 100644
--- a/firmware/sound.c
+++ b/firmware/sound.c
@@ -324,6 +324,16 @@ void sound_set_filter_roll_off(int value)
 }
 #endif
 
+#if defined(AUDIOHW_HAVE_FUNCTIONAL_MODE)
+void sound_set_functional_mode(int value)
+{
+    if (!audio_is_initialized)
+        return;
+
+    audiohw_set_functional_mode(value);
+}
+#endif
+
 #if defined(AUDIOHW_HAVE_EQ)
 int sound_enum_hw_eq_band_setting(unsigned int band,
                                   unsigned int band_setting)
diff --git a/firmware/target/hosted/sdl/sim-ui-defines.h b/firmware/target/hosted/sdl/sim-ui-defines.h
index 1ac124c881..b237842711 100644
--- a/firmware/target/hosted/sdl/sim-ui-defines.h
+++ b/firmware/target/hosted/sdl/sim-ui-defines.h
@@ -508,6 +508,7 @@
 #define UI_LCD_POSX                 46
 #define UI_LCD_POSY                 40
 
+<<<<<<< HEAD
 #elif defined(SONY_NWZA860)
 #define UI_TITLE                    "Sony NWZ-A860 Series"
 #define UI_WIDTH                    390 /* width of GUI window */
@@ -521,6 +522,12 @@
 #define UI_HEIGHT                   380
 #define UI_LCD_POSX                 29
 #define UI_LCD_POSY                 25
+#elif defined(XDUOO_X3)
+#define UI_TITLE                    "xDuoo X3"
+#define UI_WIDTH                    192 /* width of GUI window */
+#define UI_HEIGHT                   457 /* height of GUI window */
+#define UI_LCD_POSX                 34
+#define UI_LCD_POSY                 73
 #elif defined(SIMULATOR)
 #error no UI defines
 #endif
diff --git a/firmware/target/mips/ingenic_jz47xx/app.lds b/firmware/target/mips/ingenic_jz47xx/app.lds
index a8ac6ff0bf..85c332b182 100644
--- a/firmware/target/mips/ingenic_jz47xx/app.lds
+++ b/firmware/target/mips/ingenic_jz47xx/app.lds
@@ -5,8 +5,10 @@ OUTPUT_ARCH(MIPS)
 ENTRY(_start)
 STARTUP(target/mips/ingenic_jz47xx/crt0.o)
 
-#define DRAMORIG      0x80004000
-#define DRAMSIZE      (MEMORYSIZE * 0x100000)
+#define STUBOFFSET    0x4000
+
+#define DRAMORIG      (0x80000000 + STUBOFFSET)
+#define DRAMSIZE      (MEMORYSIZE * 0x100000 - STUBOFFSET)
 #define IRAMORIG      0x80000000
 #define IRAMSIZE      16K
 
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c
index ac4092f043..0ce0ed1e19 100644
--- a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c
@@ -20,7 +20,7 @@
  ****************************************************************************/
 
 #include "config.h"
-#include "jz4740.h"
+#include "cpu.h"
 #include "nand.h"
 #include "nand_id.h"
 #include "system.h"
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4760.c b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4760.c
new file mode 100644
index 0000000000..b3cc589528
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4760.c
@@ -0,0 +1,692 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "cpu.h"
+#include "nand.h"
+#include "nand_id.h"
+#include "system.h"
+#include "panic.h"
+#include "kernel.h"
+#include "storage.h"
+#include "string.h"
+/*#define LOGF_ENABLE*/
+#include "logf.h"
+
+//#define USE_DMA
+//#define USE_ECC
+
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_CMD_READ0          0
+#define NAND_CMD_READ1          1
+#define NAND_CMD_RNDOUT         5
+#define NAND_CMD_PAGEPROG       0x10
+#define NAND_CMD_READOOB        0x50
+#define NAND_CMD_ERASE1         0x60
+#define NAND_CMD_STATUS         0x70
+#define NAND_CMD_STATUS_MULTI   0x71
+#define NAND_CMD_SEQIN          0x80
+#define NAND_CMD_RNDIN          0x85
+#define NAND_CMD_READID         0x90
+#define NAND_CMD_ERASE2         0xd0
+#define NAND_CMD_RESET          0xff
+
+/* Extended commands for large page devices */
+#define NAND_CMD_READSTART      0x30
+#define NAND_CMD_RNDOUTSTART    0xE0
+#define NAND_CMD_CACHEDPROG     0x15
+
+/* Status bits */
+#define NAND_STATUS_FAIL        0x01
+#define NAND_STATUS_FAIL_N1     0x02
+#define NAND_STATUS_TRUE_READY  0x20
+#define NAND_STATUS_READY       0x40
+#define NAND_STATUS_WP          0x80
+
+/*
+ * NAND parameter struct
+ */
+struct nand_param {
+        unsigned int bus_width;         /* data bus width: 8-bit/16-bit         */
+        unsigned int row_cycle;         /* row address cycles: 2/3              */
+        unsigned int page_size;         /* page size in bytes: 512/2048/4096    */
+        unsigned int oob_size;          /* oob size in bytes: 16/64/128         */
+        unsigned int page_per_block;    /* pages per block: 32/64/128           */
+        unsigned int bad_block_pos;     /* bad block pos in oob: 0/5            */
+};
+
+/*
+ * jz4760_nand.c
+ *
+ * NAND read routine for JZ4760
+ *
+ * Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
+ *
+ */
+
+#define CFG_NAND_BASE      0xBA000000
+#define NAND_ADDR_OFFSET   0x00800000
+#define NAND_CMD_OFFSET    0x00400000
+
+#define CFG_NAND_SMCR1     0x0d444400
+
+#define NAND_DATAPORT      CFG_NAND_BASE
+#define NAND_ADDRPORT      (CFG_NAND_BASE | NAND_ADDR_OFFSET)
+#define NAND_COMMPORT      (CFG_NAND_BASE | NAND_CMD_OFFSET)
+
+#define ECC_BLOCK          512
+#define ECC_POS            24
+#define PAR_SIZE           13
+
+#define __nand_cmd(n)      (REG8(NAND_COMMPORT) = (n))
+#define __nand_addr(n)     (REG8(NAND_ADDRPORT) = (n))
+#define __nand_data8()     (REG8(NAND_DATAPORT))
+#define __nand_data16()    (REG16(NAND_DATAPORT))
+
+#define __nand_select()    (REG_NEMC_NFCSR |= NEMC_NFCSR_NFE1 | NEMC_NFCSR_NFCE1)
+#define __nand_deselect()  (REG_NEMC_NFCSR &= ~(NEMC_NFCSR_NFE1 | NEMC_NFCSR_NFCE1))
+
+/*--------------------------------------------------------------*/
+
+static struct nand_info* chip_info = NULL;
+static struct nand_info* bank;
+static unsigned long nand_size;
+static struct nand_param internal_param;
+static struct mutex nand_mtx;
+#ifdef USE_DMA
+static struct mutex nand_dma_mtx;
+static struct semaphore nand_dma_complete;
+#endif
+static unsigned char temp_page[2048]; /* Max page size */
+
+static inline void jz_nand_wait_ready(void)
+{
+    unsigned int timeout = 1000;
+    while ((REG_GPIO_PXPIN(0) & 0x00100000) && timeout--);
+    while (!(REG_GPIO_PXPIN(0) & 0x00100000));
+}
+
+#ifndef USE_DMA
+static inline void jz_nand_read_buf16(void *buf, int count)
+{
+    register int i;
+    register unsigned short *p = (unsigned short *)buf;
+
+    for (i = 0; i < count; i += 2)
+        *p++ = __nand_data16();
+}
+
+static inline void jz_nand_read_buf8(void *buf, int count)
+{
+    register int i;
+    register unsigned char *p = (unsigned char *)buf;
+
+    for (i = 0; i < count; i++)
+        *p++ = __nand_data8();
+}
+#else
+static void jz_nand_write_dma(void *source, unsigned int len, int bw)
+{
+    mutex_lock(&nand_dma_mtx);
+    
+    if(((unsigned int)source < 0xa0000000) && len)
+         dma_cache_wback_inv((unsigned long)source, len);
+    
+    dma_enable();
+
+    REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES;
+    REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)source);       
+    REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT);       
+    REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 16;                        
+    REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO;                
+    REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_16BYTE |
+                                       (bw == 8 ? DMAC_DCMD_DWDH_8 : DMAC_DCMD_DWDH_16));
+    
+    REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */
+#if 1
+    while( REG_DMAC_DTCR(DMA_NAND_CHANNEL) )
+        yield();
+#else
+    REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE;  /* Enable DMA interrupt */
+    semaphore_wait(&nand_dma_complete, TIMEOUT_BLOCK);
+#endif
+
+    REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */
+    
+    dma_disable();
+    
+    mutex_unlock(&nand_dma_mtx);
+}
+
+static void jz_nand_read_dma(void *target, unsigned int len, int bw)
+{
+    mutex_lock(&nand_dma_mtx);
+    
+    if(((unsigned int)target < 0xa0000000) && len)
+        dma_cache_wback_inv((unsigned long)target, len);
+
+    dma_enable();
+    
+    REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES ;
+    REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT);       
+    REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)target);       
+    REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 4;                        
+    REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO;                
+    REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT |
+                                       (bw == 8 ? DMAC_DCMD_SWDH_8 : DMAC_DCMD_SWDH_16));
+    REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */
+#if 1
+    while( REG_DMAC_DTCR(DMA_NAND_CHANNEL) )
+        yield();
+#else
+    REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE;  /* Enable DMA interrupt */
+    semaphore_wait(&nand_dma_complete, TIMEOUT_BLOCK);
+#endif
+
+    //REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */
+    
+    dma_disable();
+    
+    mutex_unlock(&nand_dma_mtx);
+}
+
+void DMA_CALLBACK(DMA_NAND_CHANNEL)(void)
+{
+    if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_HLT)
+        REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_HLT;
+
+    if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_AR)
+        REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_AR;
+
+    if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_CT)
+        REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_CT;
+
+    if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_TT)
+        REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_TT;
+    
+    semaphore_release(&nand_dma_complete);
+}
+#endif /* USE_DMA */
+
+static inline void jz_nand_read_buf(void *buf, int count, int bw)
+{
+#ifdef USE_DMA
+    if (bw == 8)
+        jz_nand_read_dma(buf, count, 8);
+    else
+        jz_nand_read_dma(buf, count, 16);
+#else
+    if (bw == 8)
+        jz_nand_read_buf8(buf, count);
+    else
+        jz_nand_read_buf16(buf, count);
+#endif
+}
+
+#ifdef USE_ECC
+/*
+ * Correct 1~9-bit errors in 512-bytes data 
+ */
+static void jz_rs_correct(unsigned char *dat, int idx, int mask)
+{
+    int i, j;
+    unsigned short d, d1, dm;
+
+    i = (idx * 9) >> 3;
+    j = (idx * 9) & 0x7;
+
+    i = (j == 0) ? (i - 1) : i;
+    j = (j == 0) ? 7 : (j - 1);
+
+    if (i > 512)
+        return;
+
+    if (i == 512)
+        d = dat[i - 1];
+    else
+        d = (dat[i] << 8) | dat[i - 1];
+
+    d1 = (d >> j) & 0x1ff;
+    d1 ^= mask;
+
+    dm = ~(0x1ff << j);
+    d = (d & dm) | (d1 << j);
+
+    dat[i - 1] = d & 0xff;
+    if (i < 512)
+        dat[i] = (d >> 8) & 0xff;
+}
+#endif
+
+/*
+ * Read oob
+ */
+static int jz_nand_read_oob(unsigned long page_addr, unsigned char *buf, int size)
+{
+    struct nand_param *nandp = &internal_param;
+    int page_size, row_cycle, bus_width;
+    int col_addr;
+
+    page_size = nandp->page_size;
+    row_cycle = nandp->row_cycle;
+    bus_width = nandp->bus_width;
+
+    if (page_size >= 2048)
+        col_addr = page_size;
+    else
+        col_addr = 0;
+
+    if (page_size >= 2048)
+        /* Send READ0 command */
+        __nand_cmd(NAND_CMD_READ0);
+    else
+        /* Send READOOB command */
+        __nand_cmd(NAND_CMD_READOOB);
+
+    /* Send column address */
+    __nand_addr(col_addr & 0xff);
+    if (page_size >= 2048)
+        __nand_addr((col_addr >> 8) & 0xff);
+
+    /* Send page address */
+    __nand_addr(page_addr & 0xff);
+    __nand_addr((page_addr >> 8) & 0xff);
+    if (row_cycle == 3)
+        __nand_addr((page_addr >> 16) & 0xff);
+
+    /* Send READSTART command for 2048 ps NAND */
+    if (page_size >= 2048)
+        __nand_cmd(NAND_CMD_READSTART);
+
+    /* Wait for device ready */
+    jz_nand_wait_ready();
+
+    /* Read oob data */
+    jz_nand_read_buf(buf, size, bus_width);
+
+    return 0;
+}
+
+
+/*
+ * nand_read_page()
+ *
+ * Input:
+ *
+ *    block - block number: 0, 1, 2, ...
+ *    page - page number within a block: 0, 1, 2, ...
+ *    dst - pointer to target buffer
+ */
+static int jz_nand_read_page(unsigned long page_addr, unsigned char *dst)
+{
+    struct nand_param *nandp = &internal_param;
+    int page_size, oob_size, page_per_block;
+    int row_cycle, bus_width, ecc_count;
+    int i;
+#ifdef USE_ECC
+    int j;
+#endif
+    unsigned char *data_buf;
+    unsigned char oob_buf[nandp->oob_size];
+    
+    page_size = nandp->page_size;
+    oob_size = nandp->oob_size;
+    page_per_block = nandp->page_per_block;
+    row_cycle = nandp->row_cycle;
+    bus_width = nandp->bus_width;
+
+    /*
+     * Read oob data
+     */
+    jz_nand_read_oob(page_addr, oob_buf, oob_size);
+
+    /*
+     * Read page data
+     */
+
+    /* Send READ0 command */
+    __nand_cmd(NAND_CMD_READ0);
+
+    /* Send column address */
+    __nand_addr(0);
+    if (page_size >= 2048)
+        __nand_addr(0);
+
+    /* Send page address */
+    __nand_addr(page_addr & 0xff);
+    __nand_addr((page_addr >> 8) & 0xff);
+    if (row_cycle >= 3)
+        __nand_addr((page_addr >> 16) & 0xff);
+
+    /* Send READSTART command for 2048 ps NAND */
+    if (page_size >= 2048)
+        __nand_cmd(NAND_CMD_READSTART);
+
+    /* Wait for device ready */
+    jz_nand_wait_ready();
+
+    /* Read page data */
+    data_buf = dst;
+
+    ecc_count = page_size / ECC_BLOCK;
+
+    for (i = 0; i < ecc_count; i++)
+    {
+#ifdef USE_ECC
+        volatile unsigned char *paraddr = (volatile unsigned char *)EMC_NFPAR0;
+        unsigned int stat;
+
+        /* Enable RS decoding */
+        REG_EMC_NFINTS = 0x0;
+        __ecc_decoding_4bit();
+#endif
+
+        /* Read data */
+        jz_nand_read_buf((void *)data_buf, ECC_BLOCK, bus_width);
+
+#ifdef USE_ECC
+        /* Set PAR values */
+        for (j = 0; j < PAR_SIZE; j++)
+            *paraddr++ = oob_buf[ECC_POS + i*PAR_SIZE + j];
+
+        /* Set PRDY */
+        REG_EMC_NFECR |= EMC_NFECR_PRDY;
+
+        /* Wait for completion */
+        __ecc_decode_sync();
+
+        /* Disable decoding */
+        __ecc_disable();
+
+        /* Check result of decoding */
+        stat = REG_EMC_NFINTS;
+        if (stat & EMC_NFINTS_ERR)
+        {
+            /* Error occurred */
+            if (stat & EMC_NFINTS_UNCOR)
+            {
+                /* Uncorrectable error occurred */
+                logf("Uncorrectable ECC error at NAND page address 0x%lx", page_addr);
+                return -1;
+            }
+            else
+            {
+                unsigned int errcnt, index, mask;
+
+                errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
+                switch (errcnt)
+                {
+                case 4:
+                    index = (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
+                    mask = (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
+                    jz_rs_correct(data_buf, index, mask);
+                case 3:
+                    index = (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
+                    mask = (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
+                    jz_rs_correct(data_buf, index, mask);
+                case 2:
+                    index = (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
+                    mask = (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
+                    jz_rs_correct(data_buf, index, mask);
+                case 1:
+                    index = (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
+                    mask = (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
+                    jz_rs_correct(data_buf, index, mask);
+                    break;
+                default:
+                    break;
+                }
+            }
+        }
+#endif
+
+        data_buf += ECC_BLOCK;
+    }
+
+    return 0;
+}
+
+static int jz_nand_init(void)
+{
+    unsigned char cData[5];
+
+    __gpio_as_nand_16bit(1);
+
+    REG_NEMC_SMCR1 = CFG_NAND_SMCR1 | 0x40;
+    
+    __nand_select();
+       
+    __nand_cmd(NAND_CMD_READID);
+    __nand_addr(NAND_CMD_READ0);
+    cData[0] = __nand_data8();
+    cData[1] = __nand_data8();
+    cData[2] = __nand_data8();
+    cData[3] = __nand_data8();
+    cData[4] = __nand_data8();
+        
+    __nand_deselect();
+        
+    logf("NAND chip %d: 0x%x 0x%x 0x%x 0x%x 0x%x", i+1, cData[0], cData[1],
+                                                  cData[2], cData[3], cData[4]);
+        
+    bank = nand_identify(cData);
+        
+    if(bank == NULL)
+    {
+        panicf("Unknown NAND flash chip: 0x%x 0x%x 0x%x 0x%x 0x%x", cData[0],
+                                      cData[1], cData[2], cData[3], cData[4]);
+        return -1; /* panicf() doesn't return though */
+    }
+
+    chip_info = bank;
+    
+    internal_param.bus_width = 16;
+    internal_param.row_cycle = chip_info->row_cycles;
+    internal_param.page_size = chip_info->page_size;
+    internal_param.oob_size = chip_info->spare_size;
+    internal_param.page_per_block = chip_info->pages_per_block;
+    internal_param.bad_block_pos = 0;
+    
+    nand_size = ((chip_info->page_size * chip_info->blocks_per_bank * chip_info->pages_per_block) - 0x200000) / 512;
+     
+    return 0;
+}
+
+int nand_init(void)
+{
+    int res = 0;
+    static bool inited = false;
+    
+    if(!inited)
+    {
+        res = jz_nand_init();
+        mutex_init(&nand_mtx);
+#ifdef USE_DMA
+        mutex_init(&nand_dma_mtx);
+        semaphore_init(&nand_dma_complete, 1, 0);
+        system_enable_irq(DMA_IRQ(DMA_NAND_CHANNEL));
+#endif
+        
+        inited = true;
+    }
+
+    return res;
+}
+
+static inline int read_sector(unsigned long start, unsigned int count,
+                               void* buf, unsigned int chip_size)
+{
+    register int ret;
+    
+    if(UNLIKELY(start % chip_size == 0 && count == chip_size))
+        ret = jz_nand_read_page(start / chip_size, buf);
+    else
+    {
+        ret = jz_nand_read_page(start / chip_size, temp_page);
+        memcpy(buf, temp_page + (start % chip_size), count);
+    }
+    
+    return ret;
+}
+
+static inline int write_sector(unsigned long start, unsigned int count,
+                               const void* buf, unsigned int chip_size)
+{
+    int ret = 0;
+
+    (void)start;
+    (void)count;
+    (void)buf;
+    (void)chip_size;
+
+    /* TODO */
+    
+    return ret;
+}
+
+int nand_read_sectors(IF_MV(int drive,) unsigned long start, int count, void* buf)
+{
+#ifdef HAVE_MULTIVOLUME
+    (void)drive;
+#endif
+    int ret = 0;
+    unsigned int _count, chip_size = chip_info->page_size;
+    unsigned long _start;
+    
+    logf("start");
+    mutex_lock(&nand_mtx);
+      
+    _start = start << 9;
+    _start += 0x200000; /* skip BL */
+    _count = count << 9;
+    
+    __nand_select();
+    ret = read_sector(_start, _count, buf, chip_size);
+    __nand_deselect();
+
+    mutex_unlock(&nand_mtx);
+    
+    logf("nand_read_sectors(%ld, %d, 0x%x): %d", start, count, (int)buf, ret);
+
+    return ret;
+}
+
+int nand_write_sectors(IF_MV(int drive,) unsigned long start, int count, const void* buf)
+{
+#ifdef HAVE_MULTIVOLUME
+    (void)drive;
+#endif
+    int ret = 0;
+    unsigned int _count, chip_size = chip_info->page_size;
+    unsigned long _start;
+    
+    logf("start");
+    mutex_lock(&nand_mtx);
+      
+    _start = start << 9;
+    _start += chip_info->page_size * chip_info->pages_per_block; /* skip BL */
+    _count = count << 9;
+    
+    __nand_select();
+    ret = write_sector(_start, _count, buf, chip_size);
+    __nand_deselect();
+
+    mutex_unlock(&nand_mtx);
+    
+    logf("nand_write_sectors(%ld, %d, 0x%x): %d", start, count, (int)buf, ret);
+
+    return ret;
+}
+
+#ifdef HAVE_STORAGE_FLUSH
+int nand_flush(void)
+{
+    return 0;
+}
+#endif
+
+void nand_spindown(int seconds)
+{
+    /* null */
+    (void)seconds;
+}
+
+void nand_sleep(void)
+{
+    /* null */
+}
+
+void nand_spin(void)
+{
+    /* null */
+}
+
+void nand_enable(bool on)
+{
+    /* null - flash controller is enabled/disabled as needed. */
+    (void)on;
+}
+
+/* TODO */
+long nand_last_disk_activity(void)
+{
+    return 0;
+}
+
+int nand_spinup_time(void)
+{
+    return 0;
+}
+
+void nand_sleepnow(void)
+{
+}
+
+#ifdef STORAGE_GET_INFO
+void nand_get_info(IF_MV(int drive,) struct storage_info *info)
+{
+#ifdef HAVE_MULTIVOLUME
+    (void)drive;
+#endif
+    
+    /* firmware version */
+    info->revision="0.00";
+
+    info->vendor="Rockbox";
+    info->product="NAND Storage";
+
+    /* blocks count */
+    info->num_sectors = nand_size;
+    info->sector_size = 512;
+}
+#endif
+
+#ifdef CONFIG_STORAGE_MULTI
+int nand_num_drives(int first_drive)
+{
+    /* We don't care which logical drive number(s) we have been assigned */
+    (void)first_drive;
+    
+    return 1;
+}
+#endif
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c
index 9565551df6..9215d7d08a 100644
--- a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c
@@ -21,7 +21,7 @@
 
 #include "config.h"
 #include "gcc_extensions.h"
-#include "jz4740.h"
+#include "cpu.h"
 #include "ata-sd-target.h"
 #include "led.h"
 #include "sdmmc.h"
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c
new file mode 100644
index 0000000000..c34f74a202
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c
@@ -0,0 +1,1487 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "gcc_extensions.h"
+#include "cpu.h"
+#include "ata-sd-target.h"
+#include "dma-target.h"
+#include "led.h"
+#include "sdmmc.h"
+#include "logf.h"
+#include "storage.h"
+#include "string.h"
+
+static long               last_disk_activity = -1;
+static tCardInfo          card[NUM_DRIVES];
+
+static struct mutex       sd_mtx;
+static struct semaphore   sd_wakeup;
+
+static int                use_4bit[NUM_DRIVES];
+static int                num_6[NUM_DRIVES];
+static int                sd2_0[NUM_DRIVES];
+
+#define SD_DMA_ENABLE 1
+
+//#define DEBUG(x...)         logf(x)
+#define DEBUG(x, ...)
+
+/* volumes */
+#define SD_SLOT_1  0       /* SD card 1 */
+#define SD_SLOT_2  1       /* SD card 2 */
+
+#define MSC_CHN(n) (2-n)
+
+#define SD_IRQ_MASK(n)                \
+do {                                  \
+          REG_MSC_IMASK(n) = 0xffff;  \
+          REG_MSC_IREG(n) = 0xffff;   \
+} while (0)
+
+/* Error codes */
+enum sd_result_t
+{
+    SD_NO_RESPONSE        = -1,
+    SD_NO_ERROR           = 0,
+    SD_ERROR_OUT_OF_RANGE,
+    SD_ERROR_ADDRESS,
+    SD_ERROR_BLOCK_LEN,
+    SD_ERROR_ERASE_SEQ,
+    SD_ERROR_ERASE_PARAM,
+    SD_ERROR_WP_VIOLATION,
+    SD_ERROR_CARD_IS_LOCKED,
+    SD_ERROR_LOCK_UNLOCK_FAILED,
+    SD_ERROR_COM_CRC,
+    SD_ERROR_ILLEGAL_COMMAND,
+    SD_ERROR_CARD_ECC_FAILED,
+    SD_ERROR_CC,
+    SD_ERROR_GENERAL,
+    SD_ERROR_UNDERRUN,
+    SD_ERROR_OVERRUN,
+    SD_ERROR_CID_CSD_OVERWRITE,
+    SD_ERROR_STATE_MISMATCH,
+    SD_ERROR_HEADER_MISMATCH,
+    SD_ERROR_TIMEOUT,
+    SD_ERROR_CRC,
+    SD_ERROR_DRIVER_FAILURE,
+};
+
+/* Standard MMC/SD clock speeds */
+#define MMC_CLOCK_SLOW    400000      /* 400 kHz for initial setup */
+#define SD_CLOCK_FAST   24000000      /* 24 MHz for SD Cards */
+#define SD_CLOCK_HIGH   48000000      /* 48 MHz for SD Cards */
+
+/* Extra commands for state control */
+/* Use negative numbers to disambiguate */
+#define SD_CIM_RESET            -1
+
+/* Proprietary commands, illegal/reserved according to SD Specification 2.00 */
+    /* class 1 */
+#define SD_READ_DAT_UNTIL_STOP  11   /* adtc [31:0]  dadr       R1  */
+
+    /* class 3 */
+#define SD_WRITE_DAT_UNTIL_STOP 20   /* adtc [31:0]  data addr  R1  */
+
+    /* class 4 */
+#define SD_PROGRAM_CID          26   /* adtc                    R1  */
+#define SD_PROGRAM_CSD          27   /* adtc                    R1  */
+
+    /* class 9 */
+#define SD_GO_IRQ_STATE         40   /* bcr                     R5  */
+
+/* Don't change the order of these; they are used in dispatch tables */
+enum sd_rsp_t
+{
+    RESPONSE_NONE    = 0,
+    RESPONSE_R1      = 1,
+    RESPONSE_R1B     = 2,
+    RESPONSE_R2_CID  = 3,
+    RESPONSE_R2_CSD  = 4,
+    RESPONSE_R3      = 5,
+    RESPONSE_R4      = 6,
+    RESPONSE_R5      = 7,
+    RESPONSE_R6      = 8,
+    RESPONSE_R7      = 9,
+};
+
+/*
+  MMC status in R1
+  Type
+    e : error bit
+    s : status bit
+    r : detected and set for the actual command response
+    x : detected and set during command execution. the host must poll
+        the card by sending status command in order to read these bits.
+  Clear condition
+    a : according to the card state
+    b : always related to the previous command. Reception of
+        a valid command will clear it (with a delay of one command)
+    c : clear by read
+ */
+
+#define R1_OUT_OF_RANGE        (1 << 31)    /* er, c */
+#define R1_ADDRESS_ERROR       (1 << 30)    /* erx, c */
+#define R1_BLOCK_LEN_ERROR     (1 << 29)    /* er, c */
+#define R1_ERASE_SEQ_ERROR     (1 << 28)    /* er, c */
+#define R1_ERASE_PARAM         (1 << 27)    /* ex, c */
+#define R1_WP_VIOLATION        (1 << 26)    /* erx, c */
+#define R1_CARD_IS_LOCKED      (1 << 25)    /* sx, a */
+#define R1_LOCK_UNLOCK_FAILED  (1 << 24)    /* erx, c */
+#define R1_COM_CRC_ERROR       (1 << 23)    /* er, b */
+#define R1_ILLEGAL_COMMAND     (1 << 22)    /* er, b */
+#define R1_CARD_ECC_FAILED     (1 << 21)    /* ex, c */
+#define R1_CC_ERROR            (1 << 20)    /* erx, c */
+#define R1_ERROR               (1 << 19)    /* erx, c */
+#define R1_UNDERRUN            (1 << 18)    /* ex, c */
+#define R1_OVERRUN             (1 << 17)    /* ex, c */
+#define R1_CID_CSD_OVERWRITE   (1 << 16)    /* erx, c, CID/CSD overwrite */
+#define R1_WP_ERASE_SKIP       (1 << 15)    /* sx, c */
+#define R1_CARD_ECC_DISABLED   (1 << 14)    /* sx, a */
+#define R1_ERASE_RESET         (1 << 13)    /* sr, c */
+#define R1_STATUS(x)           (x & 0xFFFFE000)
+#define R1_CURRENT_STATE(x)    ((x & 0x00001E00) >> 9)    /* sx, b (4 bits) */
+#define R1_READY_FOR_DATA      (1 << 8)     /* sx, a */
+#define R1_APP_CMD             (1 << 7)     /* sr, c */
+
+/* These are unpacked versions of the actual responses */
+struct sd_response_r1
+{
+    unsigned char  cmd;
+    unsigned int   status;
+};
+
+struct sd_response_r3
+{  
+    unsigned int ocr;
+};
+
+#define SD_CARD_BUSY    0x80000000    /* Card Power up status bit */
+
+struct sd_request
+{
+    int               index;      /* Slot index - used for CS lines */
+    int               cmd;        /* Command to send */
+    unsigned int      arg;        /* Argument to send */
+    enum sd_rsp_t    rtype;      /* Response type expected */
+
+    /* Data transfer (these may be modified at the low level) */
+    unsigned short    nob;        /* Number of blocks to transfer*/
+    unsigned short    block_len;  /* Block length */
+    unsigned char     *buffer;    /* Data buffer */
+    unsigned int      cnt;        /* Data length, for PIO */
+
+    /* Results */
+    unsigned char     response[18]; /* Buffer to store response - CRC is optional */
+    enum sd_result_t result;
+};
+
+#define SD_OCR_ARG             0x00ff8000  /* Argument of OCR */
+
+/***********************************************************************
+ *  SD Events
+ */
+#define SD_EVENT_NONE            0x00    /* No events */
+#define SD_EVENT_RX_DATA_DONE    0x01    /* Rx data done */
+#define SD_EVENT_TX_DATA_DONE    0x02    /* Tx data done */
+#define SD_EVENT_PROG_DONE       0x04    /* Programming is done */
+
+/**************************************************************************
+ * Utility functions
+ **************************************************************************/
+
+#define PARSE_U32(_buf,_index) \
+    (((unsigned int)_buf[_index]) << 24) | (((unsigned int)_buf[_index+1]) << 16) | \
+        (((unsigned int)_buf[_index+2]) << 8) | ((unsigned int)_buf[_index+3]);
+
+#define PARSE_U16(_buf,_index) \
+    (((unsigned short)_buf[_index]) << 8) | ((unsigned short)_buf[_index+1]);
+
+static int sd_unpack_r1(struct sd_request *request, struct sd_response_r1 *r1)
+{
+    unsigned char *buf = request->response;
+
+    if (request->result)
+        return request->result;
+
+    r1->cmd    = buf[0];
+    r1->status = PARSE_U32(buf,1);
+
+    DEBUG("sd_unpack_r1: cmd=%d status=%08x", r1->cmd, r1->status);
+
+    if (R1_STATUS(r1->status)) {
+        if (r1->status & R1_OUT_OF_RANGE)       return SD_ERROR_OUT_OF_RANGE;
+        if (r1->status & R1_ADDRESS_ERROR)      return SD_ERROR_ADDRESS;
+        if (r1->status & R1_BLOCK_LEN_ERROR)    return SD_ERROR_BLOCK_LEN;
+        if (r1->status & R1_ERASE_SEQ_ERROR)    return SD_ERROR_ERASE_SEQ;
+        if (r1->status & R1_ERASE_PARAM)        return SD_ERROR_ERASE_PARAM;
+        if (r1->status & R1_WP_VIOLATION)       return SD_ERROR_WP_VIOLATION;
+        //if (r1->status & R1_CARD_IS_LOCKED)     return SD_ERROR_CARD_IS_LOCKED;
+        if (r1->status & R1_LOCK_UNLOCK_FAILED) return SD_ERROR_LOCK_UNLOCK_FAILED;
+        if (r1->status & R1_COM_CRC_ERROR)      return SD_ERROR_COM_CRC;
+        if (r1->status & R1_ILLEGAL_COMMAND)    return SD_ERROR_ILLEGAL_COMMAND;
+        if (r1->status & R1_CARD_ECC_FAILED)    return SD_ERROR_CARD_ECC_FAILED;
+        if (r1->status & R1_CC_ERROR)           return SD_ERROR_CC;
+        if (r1->status & R1_ERROR)              return SD_ERROR_GENERAL;
+        if (r1->status & R1_UNDERRUN)           return SD_ERROR_UNDERRUN;
+        if (r1->status & R1_OVERRUN)            return SD_ERROR_OVERRUN;
+        if (r1->status & R1_CID_CSD_OVERWRITE)  return SD_ERROR_CID_CSD_OVERWRITE;
+    }
+
+    if (buf[0] != request->cmd)
+        return SD_ERROR_HEADER_MISMATCH;
+
+    /* This should be last - it's the least dangerous error */
+
+    return 0;
+}
+
+static int sd_unpack_r6(struct sd_request *request, struct sd_response_r1 *r1, unsigned long *rca)
+{
+    unsigned char *buf = request->response;
+
+    if (request->result)
+        return request->result;
+
+    *rca = PARSE_U16(buf,1);  /* Save RCA returned by the SD Card */
+
+    *(buf+1) = 0;
+    *(buf+2) = 0;
+
+    return sd_unpack_r1(request, r1);
+}
+
+static int sd_unpack_r3(struct sd_request *request, struct sd_response_r3 *r3)
+{
+    unsigned char *buf = request->response;
+
+    if (request->result) return request->result;
+
+    r3->ocr = PARSE_U32(buf,1);
+    DEBUG("sd_unpack_r3: ocr=%08x", r3->ocr);
+
+    if (buf[0] != 0x3f)
+        return SD_ERROR_HEADER_MISMATCH;
+
+    return 0;
+}
+
+/* Stop the MMC clock and wait while it happens */
+static inline int jz_sd_stop_clock(const int drive)
+{
+    register int timeout = 1000;
+
+    //DEBUG("stop MMC clock");
+    REG_MSC_STRPCL(MSC_CHN(drive)) = MSC_STRPCL_CLOCK_CONTROL_STOP;
+
+    while (timeout && (REG_MSC_STAT(MSC_CHN(drive)) & MSC_STAT_CLK_EN))
+    {
+        timeout--;
+        if (timeout == 0)
+        {
+            DEBUG("Timeout on stop clock waiting");
+            return SD_ERROR_TIMEOUT;
+        }
+        udelay(1);
+    }
+    //DEBUG("clock off time is %d microsec", timeout);
+    return SD_NO_ERROR;
+}
+
+/* Start the MMC clock and operation */
+static inline int jz_sd_start_clock(const int drive)
+{
+    REG_MSC_STRPCL(MSC_CHN(drive)) = MSC_STRPCL_CLOCK_CONTROL_START | MSC_STRPCL_START_OP;
+    return SD_NO_ERROR;
+}
+
+static int jz_sd_check_status(const int drive, struct sd_request *request)
+{
+    (void)request;
+    unsigned int status = REG_MSC_STAT(MSC_CHN(drive));
+
+    /* Checking for response or data timeout */
+    if (status & (MSC_STAT_TIME_OUT_RES | MSC_STAT_TIME_OUT_READ))
+    {
+        DEBUG("SD timeout, MSC_STAT 0x%x CMD %d", status,
+               request->cmd);
+        return SD_ERROR_TIMEOUT;
+    }
+
+    /* Checking for CRC error */
+    if (status &
+        (MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR |
+         MSC_STAT_CRC_RES_ERR))
+    {
+        DEBUG("SD CRC error, MSC_STAT 0x%x", status);
+        return SD_ERROR_CRC;
+    
+    }
+    
+    
+    /* Checking for FIFO empty */
+    /*if(status & MSC_STAT_DATA_FIFO_EMPTY && request->rtype != RESPONSE_NONE)
+    {
+        DEBUG("SD FIFO empty, MSC_STAT 0x%x", status);
+        return SD_ERROR_UNDERRUN;
+    }*/
+
+    return SD_NO_ERROR;
+}
+
+/* Obtain response to the command and store it to response buffer */
+static void jz_sd_get_response(const int drive, struct sd_request *request)
+{
+    int i;
+    unsigned char *buf;
+    unsigned int data;
+
+    DEBUG("fetch response for request %d, cmd %d", request->rtype,
+          request->cmd);
+    buf = request->response;
+    request->result = SD_NO_ERROR;
+
+    switch (request->rtype)
+    {
+        case RESPONSE_R1:
+        case RESPONSE_R1B:
+        case RESPONSE_R7:
+        case RESPONSE_R6:
+        case RESPONSE_R3:
+        case RESPONSE_R4:
+        case RESPONSE_R5:
+        {
+            data = REG_MSC_RES(MSC_CHN(drive));
+            buf[0] = (data >> 8) & 0xff;
+            buf[1] = data & 0xff;
+            data = REG_MSC_RES(MSC_CHN(drive));
+            buf[2] = (data >> 8) & 0xff;
+            buf[3] = data & 0xff;
+            data = REG_MSC_RES(MSC_CHN(drive));
+            buf[4] = data & 0xff;
+
+            DEBUG("request %d, response [%02x %02x %02x %02x %02x]",
+                  request->rtype, buf[0], buf[1], buf[2],
+                  buf[3], buf[4]);
+            break;
+        }
+        case RESPONSE_R2_CID:
+        case RESPONSE_R2_CSD:
+        {
+            for (i = 0; i < 16; i += 2)
+            {
+                data = REG_MSC_RES(MSC_CHN(drive));
+                buf[i] = (data >> 8) & 0xff;
+                buf[i + 1] = data & 0xff;
+            }
+            DEBUG("request %d, response []", request->rtype);
+            break;
+        }
+        case RESPONSE_NONE:
+            DEBUG("No response");
+            break;
+
+        default:
+            DEBUG("unhandled response type for request %d",
+                  request->rtype);
+            break;
+    }
+}
+
+static int jz_sd_receive_data(const int drive, struct sd_request *req)
+{
+    unsigned int nob = req->nob;
+    unsigned int wblocklen = (unsigned int) (req->block_len + 3) >> 2;    /* length in word */
+    unsigned char *buf = req->buffer;
+    unsigned int *wbuf = (unsigned int *) buf;
+    unsigned int waligned = (((unsigned int) buf & 0x3) == 0);    /* word aligned ? */
+    unsigned int stat, timeout, data, cnt;
+
+    for (; nob >= 1; nob--)
+    {
+        timeout = 0x3FFFFFF;
+
+        while (timeout)
+        {
+            timeout--;
+            stat = REG_MSC_STAT(MSC_CHN(drive));
+
+            if (stat & MSC_STAT_TIME_OUT_READ)
+                return SD_ERROR_TIMEOUT;
+            else if (stat & MSC_STAT_CRC_READ_ERROR)
+                return SD_ERROR_CRC;
+            else if (!(stat & MSC_STAT_DATA_FIFO_EMPTY)
+                 || (stat & MSC_STAT_DATA_FIFO_AFULL))
+                /* Ready to read data */
+                break;
+
+            udelay(1);
+        }
+
+        if (!timeout)
+            return SD_ERROR_TIMEOUT;
+
+        /* Read data from RXFIFO. It could be FULL or PARTIAL FULL */
+        DEBUG("Receive Data = %d", wblocklen);
+        cnt = wblocklen;
+        while (cnt)
+        {
+            data = REG_MSC_RXFIFO(MSC_CHN(drive));
+            if (waligned)
+                *wbuf++ = data;
+            else
+            {
+                *buf++ = (unsigned char) (data >> 0);
+                *buf++ = (unsigned char) (data >> 8);
+                *buf++ = (unsigned char) (data >> 16);
+                *buf++ = (unsigned char) (data >> 24);
+            }
+            cnt--;
+            while (cnt
+                   && (REG_MSC_STAT(MSC_CHN(drive)) &
+                   MSC_STAT_DATA_FIFO_EMPTY));
+        }
+    }
+
+    return SD_NO_ERROR;
+}
+
+static int jz_sd_transmit_data(const int drive, struct sd_request *req)
+{
+    unsigned int nob = req->nob;
+    unsigned int wblocklen = (unsigned int) (req->block_len + 3) >> 2;    /* length in word */
+    unsigned char *buf = req->buffer;
+    unsigned int *wbuf = (unsigned int *) buf;
+    unsigned int waligned = (((unsigned int) buf & 0x3) == 0);    /* word aligned ? */
+    unsigned int stat, timeout, data, cnt;
+
+    for (; nob >= 1; nob--)
+    {
+        timeout = 0x3FFFFFF;
+
+        while (timeout)
+        {
+            timeout--;
+            stat = REG_MSC_STAT(MSC_CHN(drive));
+
+            if (stat &
+                (MSC_STAT_CRC_WRITE_ERROR |
+                 MSC_STAT_CRC_WRITE_ERROR_NOSTS))
+                return SD_ERROR_CRC;
+            else if (!(stat & MSC_STAT_DATA_FIFO_FULL))
+                /* Ready to write data */
+                break;
+
+            udelay(1);
+        }
+
+        if (!timeout)
+            return SD_ERROR_TIMEOUT;
+
+        /* Write data to TXFIFO */
+        cnt = wblocklen;
+        while (cnt)
+        {
+            while (REG_MSC_STAT(MSC_CHN(drive)) & MSC_STAT_DATA_FIFO_FULL);
+
+            if (waligned)
+                REG_MSC_TXFIFO(MSC_CHN(drive)) = *wbuf++;
+            else
+            {
+                data = *buf++;
+                data |= *buf++ << 8;
+                data |= *buf++ << 16;
+                data |= *buf++ << 24;
+                REG_MSC_TXFIFO(MSC_CHN(drive)) = data;
+            }
+
+            cnt--;
+        }
+    }
+
+    return SD_NO_ERROR;
+}
+
+#if SD_DMA_ENABLE
+static void jz_sd_receive_data_dma(const int drive, struct sd_request *req)
+{
+    unsigned int waligned = (((unsigned int)req->buffer & 0x3) == 0);    /* word aligned ? */
+    unsigned int size = req->block_len * req->nob;
+
+    if (!waligned)
+    {
+        jz_sd_receive_data(drive, req);
+        return;
+    }
+
+    /* flush dcache */
+    dma_cache_wback_inv((unsigned long) req->buffer, size);
+
+    /* setup dma channel */
+    REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = 0;
+    REG_DMAC_DSAR(DMA_SD_RX_CHANNEL) = PHYSADDR(MSC_RXFIFO(MSC_CHN(drive))); /* DMA source addr */
+    REG_DMAC_DTAR(DMA_SD_RX_CHANNEL) = PHYSADDR((unsigned long)req->buffer); /* DMA dest addr */
+    REG_DMAC_DTCR(DMA_SD_RX_CHANNEL) = (size + 3) >> 2;                      /* DMA transfer count */
+    REG_DMAC_DRSR(DMA_SD_RX_CHANNEL) = (drive == SD_SLOT_1) ? DMAC_DRSR_RS_MSC2IN : DMAC_DRSR_RS_MSC1IN;    /* DMA request type */
+
+    REG_DMAC_DCMD(DMA_SD_RX_CHANNEL) =
+        DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
+        DMAC_DCMD_DS_32BIT;
+    REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
+
+    /* wait for dma completion */
+    while (REG_DMAC_DTCR(DMA_SD_RX_CHANNEL));
+
+    /* clear status and disable channel */
+    REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = 0;
+}
+
+static void jz_sd_transmit_data_dma(const int drive, struct sd_request *req)
+{
+    unsigned int waligned = (((unsigned int)req->buffer & 0x3) == 0);    /* word aligned ? */
+    unsigned int size = req->block_len * req->nob;
+
+    if (!waligned)
+    {
+        jz_sd_transmit_data(drive, req);
+        return;
+    }
+
+    /* flush dcache */
+    dma_cache_wback_inv((unsigned long) req->buffer, size);
+
+    /* setup dma channel */
+    REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = 0;
+    REG_DMAC_DSAR(DMA_SD_TX_CHANNEL) = PHYSADDR((unsigned long) req->buffer); /* DMA source addr */
+    REG_DMAC_DTAR(DMA_SD_TX_CHANNEL) = PHYSADDR(MSC_TXFIFO(MSC_CHN(drive)));  /* DMA dest addr */
+    REG_DMAC_DTCR(DMA_SD_TX_CHANNEL) = (size + 3) >> 2;                       /* DMA transfer count */
+    REG_DMAC_DRSR(DMA_SD_TX_CHANNEL) = (drive == SD_SLOT_1) ? DMAC_DRSR_RS_MSC2OUT : DMAC_DRSR_RS_MSC1OUT;    /* DMA request type */
+
+    REG_DMAC_DCMD(DMA_SD_TX_CHANNEL) =
+        DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
+        DMAC_DCMD_DS_32BIT;
+    REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
+
+    /* wait for dma completion */
+    while (REG_DMAC_DTCR(DMA_SD_TX_CHANNEL));
+
+    /* clear status and disable channel */
+    REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = 0;
+}
+
+void DMA_CALLBACK(DMA_SD_RX_CHANNEL)(void)
+{
+    if (REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) & DMAC_DCCSR_AR)
+    {
+        logf("SD RX DMA address error");
+        REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) &= ~DMAC_DCCSR_AR;
+    }
+
+    if (REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) & DMAC_DCCSR_HLT)
+    {
+        logf("SD RX DMA halt");
+        REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) &= ~DMAC_DCCSR_HLT;
+    }
+
+    if (REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) & DMAC_DCCSR_TT)
+    {
+        REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) &= ~DMAC_DCCSR_TT;
+        //sd_rx_dma_callback();
+    }
+}
+
+void DMA_CALLBACK(DMA_SD_TX_CHANNEL)(void)
+{
+    if (REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) & DMAC_DCCSR_AR)
+    {
+        logf("SD TX DMA address error: %x, %x, %x", var1, var2, var3);
+        REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) &= ~DMAC_DCCSR_AR;
+    }
+
+    if (REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) & DMAC_DCCSR_HLT)
+    {
+        logf("SD TX DMA halt");
+        REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) &= ~DMAC_DCCSR_HLT;
+    }
+
+    if (REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) & DMAC_DCCSR_TT)
+    {
+        REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) &= ~DMAC_DCCSR_TT;
+        //sd_tx_dma_callback();
+    }
+}
+#endif                /* SD_DMA_ENABLE */
+
+static inline unsigned int jz_sd_calc_clkrt(const int drive, unsigned int rate)
+{
+    unsigned int clkrt;
+    unsigned int clk_src = sd2_0[drive] ? SD_CLOCK_HIGH : SD_CLOCK_FAST;
+
+    clkrt = 0;
+    while (rate < clk_src)
+    {
+        clkrt++;
+        clk_src >>= 1;
+    }
+    return clkrt;
+}
+
+static inline void cpm_select_msc_clk(unsigned int rate)
+{
+    unsigned int div = __cpm_get_pllout2() / rate;
+
+    REG_CPM_MSCCDR = div - 1;
+}
+
+/* Set the MMC clock frequency */
+static void jz_sd_set_clock(const int drive, unsigned int rate)
+{
+    int clkrt;
+
+    jz_sd_stop_clock(drive);
+
+    /* select clock source from CPM */
+    cpm_select_msc_clk(rate);
+
+    __cpm_enable_pll_change();
+    clkrt = jz_sd_calc_clkrt(drive, rate);
+    REG_MSC_CLKRT(MSC_CHN(drive)) = clkrt;
+
+    DEBUG("set clock to %u Hz clkrt=%d", rate, clkrt);
+}
+
+/********************************************************************************************************************
+** Name:      int jz_sd_exec_cmd()
+** Function:  send command to the card, and get a response
+** Input:     struct sd_request *req: SD request
+** Output:    0:  right        >0:  error code
+********************************************************************************************************************/
+static int jz_sd_exec_cmd(const int drive, struct sd_request *request)
+{
+    unsigned int cmdat = 0, events = 0;
+    int retval, timeout = 0x3fffff;
+
+    /* Indicate we have no result yet */
+    request->result = SD_NO_RESPONSE;
+
+    if (request->cmd == SD_CIM_RESET) {
+        /* On reset, 1-bit bus width */
+        use_4bit[drive] = 0;
+
+        /* Reset MMC/SD controller */
+        __msc_reset(MSC_CHN(drive));
+
+        /* On reset, drop SD clock down */
+        jz_sd_set_clock(drive, MMC_CLOCK_SLOW);
+
+        /* On reset, stop SD clock */
+        jz_sd_stop_clock(drive);
+    }
+    if (request->cmd == SD_SET_BUS_WIDTH)
+    {
+        if (request->arg == 0x2)
+        {
+            DEBUG("Use 4-bit bus width");
+            use_4bit[drive] = 1;
+        }
+        else
+        {
+            DEBUG("Use 1-bit bus width");
+            use_4bit[drive] = 0;
+        }
+    }
+
+    /* stop clock */
+    jz_sd_stop_clock(drive);
+
+    /* mask all interrupts */
+    //REG_MSC_IMASK(MSC_CHN(drive)) = 0xffff;
+    /* clear status */
+    REG_MSC_IREG(MSC_CHN(drive)) = 0xffff;
+    /*open interrupt */
+    REG_MSC_IMASK(MSC_CHN(drive)) = (~7);
+    /* use 4-bit bus width when possible */
+    if (use_4bit[drive])
+        cmdat |= MSC_CMDAT_BUS_WIDTH_4BIT;
+
+    /* Set command type and events */
+    switch (request->cmd)
+    {
+        /* SD core extra command */
+        case SD_CIM_RESET:
+            cmdat |= MSC_CMDAT_INIT; /* Initialization sequence sent prior to command */
+            break;
+            /* bc - broadcast - no response */
+        case SD_GO_IDLE_STATE:
+        case SD_SET_DSR:
+            break;
+
+            /* bcr - broadcast with response */
+        case SD_APP_OP_COND:
+        case SD_ALL_SEND_CID:
+        case SD_GO_IRQ_STATE:
+            break;
+
+            /* adtc - addressed with data transfer */
+        case SD_READ_DAT_UNTIL_STOP:
+        case SD_READ_SINGLE_BLOCK:
+        case SD_READ_MULTIPLE_BLOCK:
+        case SD_SEND_SCR:
+#if SD_DMA_ENABLE
+            cmdat |=
+                MSC_CMDAT_DATA_EN | MSC_CMDAT_READ | MSC_CMDAT_DMA_EN;
+#else
+            cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ;
+#endif
+            events = SD_EVENT_RX_DATA_DONE;
+            break;
+
+        case 6:
+            if (num_6[drive] < 2)
+            {
+#if SD_DMA_ENABLE
+                cmdat |=
+                    MSC_CMDAT_DATA_EN | MSC_CMDAT_READ |
+                    MSC_CMDAT_DMA_EN;
+#else
+                cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ;
+#endif
+                events = SD_EVENT_RX_DATA_DONE;
+            }
+            break;
+
+        case SD_WRITE_DAT_UNTIL_STOP:
+        case SD_WRITE_BLOCK:
+        case SD_WRITE_MULTIPLE_BLOCK:
+        case SD_PROGRAM_CID:
+        case SD_PROGRAM_CSD:
+        case SD_LOCK_UNLOCK:
+#if SD_DMA_ENABLE
+            cmdat |=
+                MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE | MSC_CMDAT_DMA_EN;
+#else
+            cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE;
+#endif
+            events = SD_EVENT_TX_DATA_DONE | SD_EVENT_PROG_DONE;
+            break;
+
+        case SD_STOP_TRANSMISSION:
+            events = SD_EVENT_PROG_DONE;
+            break;
+
+        /* ac - no data transfer */
+        default:
+            break;
+    }
+
+    /* Set response type */
+    switch (request->rtype)
+    {
+        case RESPONSE_NONE:
+            break;
+        case RESPONSE_R1B:
+            cmdat |= MSC_CMDAT_BUSY;
+            /* FALLTHRU */
+        case RESPONSE_R1:
+        case RESPONSE_R7:
+            cmdat |= MSC_CMDAT_RESPONSE_R1;
+            break;
+        case RESPONSE_R2_CID:
+        case RESPONSE_R2_CSD:
+            cmdat |= MSC_CMDAT_RESPONSE_R2;
+            break;
+        case RESPONSE_R3:
+            cmdat |= MSC_CMDAT_RESPONSE_R3;
+            break;
+        case RESPONSE_R4:
+            cmdat |= MSC_CMDAT_RESPONSE_R4;
+            break;
+        case RESPONSE_R5:
+            cmdat |= MSC_CMDAT_RESPONSE_R5;
+            break;
+        case RESPONSE_R6:
+            cmdat |= MSC_CMDAT_RESPONSE_R6;
+            break;
+        default:
+            break;
+    }
+
+    /* Set command index */
+    if (request->cmd == SD_CIM_RESET)
+        REG_MSC_CMD(MSC_CHN(drive)) = SD_GO_IDLE_STATE;
+    else
+        REG_MSC_CMD(MSC_CHN(drive)) = request->cmd;
+
+    /* Set argument */
+    REG_MSC_ARG(MSC_CHN(drive)) = request->arg;
+
+    /* Set block length and nob */
+    if (request->cmd == SD_SEND_SCR)
+    {    /* get SCR from DataFIFO */
+        REG_MSC_BLKLEN(MSC_CHN(drive)) = 8;
+        REG_MSC_NOB(MSC_CHN(drive)) = 1;
+    }
+    else
+    {
+        REG_MSC_BLKLEN(MSC_CHN(drive)) = request->block_len;
+        REG_MSC_NOB(MSC_CHN(drive)) = request->nob;
+    }
+
+    /* Set command */
+    REG_MSC_CMDAT(MSC_CHN(drive)) = cmdat;
+
+    DEBUG("Send cmd %d cmdat: %x arg: %x resp %d", request->cmd,
+          cmdat, request->arg, request->rtype);
+
+    /* Start SD clock and send command to card */
+    jz_sd_start_clock(drive);
+
+    /* Wait for command completion */
+    //__intc_unmask_irq(IRQ_MSC);
+    //semaphore_wait(&sd_wakeup, 100);
+    while (timeout-- && !(REG_MSC_STAT(MSC_CHN(drive)) & MSC_STAT_END_CMD_RES));
+
+
+    if (timeout == 0)
+        return SD_ERROR_TIMEOUT;
+
+    REG_MSC_IREG(MSC_CHN(drive)) = MSC_IREG_END_CMD_RES;    /* clear flag */
+
+    /* Check for status */
+    retval = jz_sd_check_status(drive, request);
+    if (retval)
+        return retval;
+
+    /* Complete command with no response */
+    if (request->rtype == RESPONSE_NONE)
+        return SD_NO_ERROR;
+
+    /* Get response */
+    jz_sd_get_response(drive, request);
+
+    /* Start data operation */
+    if (events & (SD_EVENT_RX_DATA_DONE | SD_EVENT_TX_DATA_DONE))
+    {
+        if (events & SD_EVENT_RX_DATA_DONE)
+        {
+            if (request->cmd == SD_SEND_SCR)
+            {
+                /* SD card returns SCR register as data. 
+                   SD core expect it in the response buffer, 
+                   after normal response. */
+                request->buffer =
+                    (unsigned char *) ((unsigned int) request->response + 5);
+            }
+#if SD_DMA_ENABLE
+            jz_sd_receive_data_dma(drive, request);
+#else
+            jz_sd_receive_data(drive, request);
+#endif
+        }
+
+        if (events & SD_EVENT_TX_DATA_DONE)
+        {
+#if SD_DMA_ENABLE
+            jz_sd_transmit_data_dma(drive, request);
+#else
+            jz_sd_transmit_data(drive, request);
+#endif
+        }
+        //__intc_unmask_irq(IRQ_MSC);
+        //semaphore_wait(&sd_wakeup, 100);
+        /* Wait for Data Done */
+        while (!(REG_MSC_IREG(MSC_CHN(drive)) & MSC_IREG_DATA_TRAN_DONE));
+        REG_MSC_IREG(MSC_CHN(drive)) = MSC_IREG_DATA_TRAN_DONE;    /* clear status */
+    }
+
+    /* Wait for Prog Done event */
+    if (events & SD_EVENT_PROG_DONE)
+    {
+        //__intc_unmask_irq(IRQ_MSC);
+        //semaphore_wait(&sd_wakeup, 100);
+        while (!(REG_MSC_IREG(MSC_CHN(drive)) & MSC_IREG_PRG_DONE));
+        REG_MSC_IREG(MSC_CHN(drive)) = MSC_IREG_PRG_DONE;    /* clear status */
+    }
+
+    /* Command completed */
+
+    return SD_NO_ERROR;    /* return successfully */
+}
+
+/*******************************************************************************************************************
+** Name:      int sd_chkcard()
+** Function:  check whether card is insert entirely
+** Input:     NULL
+** Output:    1: insert entirely    0: not insert entirely
+********************************************************************************************************************/
+static int jz_sd_chkcard(const int drive)
+{
+    return (__gpio_get_pin((drive == SD_SLOT_1) ? PIN_SD1_CD : PIN_SD2_CD) == 0 ? 1 : 0);
+}
+
+/* MSC interrupt handler */
+void MSC(void)
+{
+    //semaphore_release(&sd_wakeup);
+    logf("MSC interrupt");
+}
+
+#ifdef HAVE_HOTSWAP
+static void sd_gpio_setup_irq(const int drive, bool inserted)
+{
+    int pin = (drive == SD_SLOT_1) ? PIN_SD1_CD : PIN_SD2_CD;
+    int irq = (drive == SD_SLOT_1) ? IRQ_SD1_CD : IRQ_SD2_CD;
+    if(inserted)
+        __gpio_as_irq_rise_edge(pin);
+    else
+        __gpio_as_irq_fall_edge(pin);
+    system_enable_irq(irq);
+}
+#endif
+
+/*******************************************************************************************************************
+** Name:      void sd_hardware_init()
+** Function:  initialize the hardware condiction that access sd card
+** Input:     NULL
+** Output:    NULL
+********************************************************************************************************************/
+static void jz_sd_hardware_init(const int drive)
+{
+    if (drive == SD_SLOT_1)
+        __cpm_start_msc2();   /* enable mmc2 clock */
+    else
+        __cpm_start_msc1();   /* enable mmc1 clock */
+#ifdef HAVE_HOTSWAP
+    sd_gpio_setup_irq(drive, jz_sd_chkcard(drive));
+#endif
+    __msc_reset(MSC_CHN(drive));  /* reset mmc/sd controller */
+    SD_IRQ_MASK(MSC_CHN(drive));  /* mask all IRQs */
+    jz_sd_stop_clock(drive); /* stop SD clock */
+}
+
+static int sd_send_cmd(const int drive, struct sd_request *request, int cmd, unsigned int arg,
+                         unsigned short nob, unsigned short block_len,
+                         enum sd_rsp_t rtype, unsigned char* buffer)
+{
+    request->cmd = cmd;
+    request->arg = arg;
+    request->rtype = rtype;
+    request->nob = nob;
+    request->block_len = block_len;
+    request->buffer = buffer;
+    request->cnt = nob * block_len;
+
+    return jz_sd_exec_cmd(drive, request);
+}
+
+static void sd_simple_cmd(const int drive, struct sd_request *request, int cmd, unsigned int arg,
+                           enum sd_rsp_t rtype)
+{
+    sd_send_cmd(drive, request, cmd, arg, 0, 0, rtype, NULL);
+}
+
+#define SD_INIT_DOING   0
+#define SD_INIT_PASSED  1
+#define SD_INIT_FAILED  2
+static int sd_init_card_state(const int drive, struct sd_request *request)
+{
+    struct sd_response_r1 r1;
+    struct sd_response_r3 r3;
+    int retval, i, ocr = 0x40300000, limit_41 = 0;
+
+    switch (request->cmd)
+    {
+        case SD_GO_IDLE_STATE: /* No response to parse */
+            sd_simple_cmd(drive, request, SD_SEND_IF_COND, 0x1AA, RESPONSE_R1);
+            break;
+
+        case SD_SEND_IF_COND:
+            retval = sd_unpack_r1(request, &r1);
+            sd_simple_cmd(drive, request, SD_APP_CMD,  0, RESPONSE_R1);
+            break;
+
+        case SD_APP_CMD:
+            retval = sd_unpack_r1(request, &r1);
+            if (retval & (limit_41 < 100))
+            {
+                DEBUG("sd_init_card_state: unable to SD_APP_CMD error=%d", 
+                      retval);
+                limit_41++;
+                sd_simple_cmd(drive, request, SD_APP_OP_COND, ocr, RESPONSE_R3);
+            }
+            else if (limit_41 < 100)
+            {
+                limit_41++;
+                sd_simple_cmd(drive, request, SD_APP_OP_COND, ocr, RESPONSE_R3);
+            }
+            else
+                /* reset the card to idle*/
+                sd_simple_cmd(drive, request, SD_GO_IDLE_STATE, 0, RESPONSE_NONE);
+            break;
+
+        case SD_APP_OP_COND:
+            retval = sd_unpack_r3(request, &r3);
+            if (retval)
+                break;
+
+            DEBUG("sd_init_card_state: read ocr value = 0x%08x", r3.ocr);
+            card[drive].ocr = r3.ocr;
+
+            if(!(r3.ocr & SD_CARD_BUSY || ocr == 0))
+            {
+                sleep(HZ / 100);
+                sd_simple_cmd(drive, request, SD_APP_CMD, 0, RESPONSE_R1);
+            }
+            else
+            {
+                /* Set the data bus width to 4 bits */
+                use_4bit[drive] = 1;
+                sd_simple_cmd(drive, request, SD_ALL_SEND_CID, 0, RESPONSE_R2_CID);
+            }
+            break;
+
+        case SD_ALL_SEND_CID:
+            for(i=0; i<4; i++)
+                card[drive].cid[i] = ((request->response[1+i*4]<<24) | (request->response[2+i*4]<<16) | 
+                               (request->response[3+i*4]<< 8) | request->response[4+i*4]);
+
+            logf("CID: %08lx%08lx%08lx%08lx", card[drive].cid[0], card[drive].cid[1], card[drive].cid[2], card[drive].cid[3]);
+            sd_simple_cmd(drive, request, SD_SEND_RELATIVE_ADDR, 0, RESPONSE_R6);
+            break;
+        case SD_SEND_RELATIVE_ADDR:
+            retval = sd_unpack_r6(request, &r1, &card[drive].rca);
+            card[drive].rca = card[drive].rca << 16; 
+            DEBUG("sd_init_card_state: Get RCA from SD: 0x%04lx Status: %x", card[drive].rca, r1.status);
+            if (retval)
+            {
+                DEBUG("sd_init_card_state: unable to SET_RELATIVE_ADDR error=%d", 
+                      retval);
+                return SD_INIT_FAILED;
+            }
+
+            sd_simple_cmd(drive, request, SD_SEND_CSD, card[drive].rca, RESPONSE_R2_CSD);
+            break;
+
+        case SD_SEND_CSD:
+            for(i=0; i<4; i++)
+                card[drive].csd[i] = ((request->response[1+i*4]<<24) | (request->response[2+i*4]<<16) | 
+                               (request->response[3+i*4]<< 8) | request->response[4+i*4]);
+
+            sd_parse_csd(&card[drive]);
+            sd2_0[drive] = (card_extract_bits(card[drive].csd, 127, 2) == 1);
+
+            logf("CSD: %08lx%08lx%08lx%08lx", card[drive].csd[0], card[drive].csd[1], card[drive].csd[2], card[drive].csd[3]);
+            DEBUG("SD card is ready");
+            jz_sd_set_clock(drive, SD_CLOCK_FAST);
+            return SD_INIT_PASSED;
+
+        default:
+            DEBUG("sd_init_card_state: error!  Illegal last cmd %d", request->cmd);
+            return SD_INIT_FAILED;
+    }
+
+    return SD_INIT_DOING;
+}
+
+static int sd_switch(const int drive, struct sd_request *request, int mode, int group,
+              unsigned char value, unsigned char * resp)
+{
+    unsigned int arg;
+
+    mode = !!mode;
+    value &= 0xF;
+    arg = (mode << 31 | 0x00FFFFFF);
+    arg &= ~(0xF << (group * 4));
+    arg |= value << (group * 4);
+    sd_send_cmd(drive, request, 6, arg, 1, 64, RESPONSE_R1, resp);
+
+    return 0;
+}
+
+/*
+ * Fetches and decodes switch information
+ */
+static int sd_read_switch(const int drive, struct sd_request *request)
+{
+    unsigned int status[64 / 4];
+
+    memset((unsigned char *)status, 0, 64);
+    sd_switch(drive, request, 0, 0, 1, (unsigned char*) status);
+
+    if (((unsigned char *)status)[13] & 0x02)
+        return 0;
+    else 
+        return 1;
+}
+
+/*
+ * Test if the card supports high-speed mode and, if so, switch to it.
+ */
+static int sd_switch_hs(const int drive, struct sd_request *request)
+{
+    unsigned int status[64 / 4];
+
+    sd_switch(drive, request, 1, 0, 1, (unsigned char*) status);
+    return 0;
+}
+
+static int sd_select_card(const int drive)
+{
+    struct sd_request request;
+    struct sd_response_r1 r1;
+    int retval;
+
+    sd_simple_cmd(drive, &request, SD_SELECT_CARD, card[drive].rca,
+               RESPONSE_R1B);
+    retval = sd_unpack_r1(&request, &r1);
+    if (retval)
+        return retval;
+
+    if (sd2_0[drive])
+    {
+        retval = sd_read_switch(drive, &request);
+        if (!retval)
+        {
+            sd_switch_hs(drive, &request);
+            jz_sd_set_clock(drive, SD_CLOCK_HIGH);
+        }
+    }
+    num_6[drive] = 3;
+    sd_simple_cmd(drive, &request, SD_APP_CMD, card[drive].rca,
+               RESPONSE_R1);
+    retval = sd_unpack_r1(&request, &r1);
+    if (retval)
+        return retval;
+    sd_simple_cmd(drive, &request, SD_SET_BUS_WIDTH, 2, RESPONSE_R1);
+    retval = sd_unpack_r1(&request, &r1);
+    if (retval)
+        return retval;
+
+    card[drive].initialized = 1;
+
+    return 0;
+}
+
+static int sd_init_device(const int drive)
+{
+    int retval = 0;
+    struct sd_request init_req;
+    register int timeout = 1000;
+
+    mutex_lock(&sd_mtx);
+
+    /* Initialise card data as blank */
+    memset(&card[drive], 0, sizeof(tCardInfo));
+
+    sd2_0[drive] = 0;
+    num_6[drive] = 0;
+    use_4bit[drive] = 0;
+
+    /* reset mmc/sd controller */
+    jz_sd_hardware_init(drive);
+
+    sd_simple_cmd(drive, &init_req, SD_CIM_RESET,     0,     RESPONSE_NONE);
+    sd_simple_cmd(drive, &init_req, SD_GO_IDLE_STATE, 0,     RESPONSE_NONE);
+
+    sleep(HZ/2); /* Give the card/controller some rest */
+
+    while(timeout-- && ((retval = sd_init_card_state(drive, &init_req)) == SD_INIT_DOING));
+    retval = (retval == SD_INIT_PASSED ? sd_select_card(drive) : -1);
+
+    if (drive == SD_SLOT_1)
+        __cpm_stop_msc2(); /* disable SD1 clock */
+    else
+        __cpm_stop_msc1(); /* disable SD2 clock */
+
+    mutex_unlock(&sd_mtx);
+
+    return retval;
+}
+
+int sd_init(void)
+{
+    static bool inited = false;
+
+    sd_init_gpio();     /* init GPIO */
+
+#if SD_DMA_ENABLE
+    __dmac_channel_enable_clk(DMA_SD_RX_CHANNEL);
+    __dmac_channel_enable_clk(DMA_SD_TX_CHANNEL);
+#endif
+
+    if(!inited)
+    {
+        semaphore_init(&sd_wakeup, 1, 0);
+        mutex_init(&sd_mtx);
+        inited = true;
+    }
+
+    for (int drive = 0; drive < NUM_DRIVES; drive++)
+        sd_init_device(drive);
+
+    return 0;
+}
+
+static inline bool card_detect_target(const int drive)
+{
+    return (jz_sd_chkcard(drive) == 1);
+}
+
+tCardInfo* card_get_info_target(const int drive)
+{
+    return &card[drive];
+}
+
+static inline void sd_start_transfer(const int drive)
+{
+    mutex_lock(&sd_mtx);
+    if (drive == SD_SLOT_1)
+        __cpm_start_msc2();
+    else
+        __cpm_start_msc1();
+    led(true);
+}
+
+static inline void sd_stop_transfer(const int drive)
+{
+    led(false);
+    if (drive == SD_SLOT_1)
+        __cpm_stop_msc2();
+    else
+        __cpm_stop_msc1();
+    mutex_unlock(&sd_mtx);
+}
+
+int sd_read_sectors(const int drive, unsigned long start, int count, void* buf)
+{
+    sd_start_transfer(drive);
+
+    struct sd_request request;
+    struct sd_response_r1 r1;
+    int retval = -1;
+
+    if (!card_detect_target(drive) || count == 0 || start > card[drive].numblocks)
+        goto err;
+
+    if(card[drive].initialized == 0 && !sd_init_device(drive))
+        goto err;
+
+    sd_simple_cmd(drive, &request, SD_SEND_STATUS, card[drive].rca, RESPONSE_R1);
+    retval = sd_unpack_r1(&request, &r1);
+    if (retval && (retval != SD_ERROR_STATE_MISMATCH))
+        goto err;
+
+    sd_simple_cmd(drive, &request, SD_SET_BLOCKLEN, SD_BLOCK_SIZE, RESPONSE_R1);
+    if ((retval = sd_unpack_r1(&request, &r1)))
+        goto err;
+
+    if (sd2_0[drive])
+    {
+        sd_send_cmd(drive, &request, SD_READ_MULTIPLE_BLOCK, start,
+                     count, SD_BLOCK_SIZE, RESPONSE_R1, buf);
+        if ((retval = sd_unpack_r1(&request, &r1)))
+            goto err;
+    }
+    else
+    {
+        sd_send_cmd(drive, &request, SD_READ_MULTIPLE_BLOCK,
+                     start * SD_BLOCK_SIZE, count,
+                     SD_BLOCK_SIZE, RESPONSE_R1, buf);
+        if ((retval = sd_unpack_r1(&request, &r1)))
+            goto err;
+    }
+
+    last_disk_activity = current_tick;
+
+    sd_simple_cmd(drive, &request, SD_STOP_TRANSMISSION, 0, RESPONSE_R1B);
+    if ((retval = sd_unpack_r1(&request, &r1)))
+        goto err;
+
+err:
+    sd_stop_transfer(drive);
+
+    return retval;
+}
+
+int sd_write_sectors(const int drive, unsigned long start, int count, const void* buf)
+{
+    sd_start_transfer(drive);
+
+    struct sd_request request;
+    struct sd_response_r1 r1;
+    int retval = -1;
+
+    if (!card_detect_target(drive) || count == 0 || start > card[drive].numblocks)
+        goto err;
+
+    if(card[drive].initialized == 0 && !sd_init_device(drive))
+        goto err;
+
+    sd_simple_cmd(drive, &request, SD_SEND_STATUS, card[drive].rca, RESPONSE_R1);
+    retval = sd_unpack_r1(&request, &r1);
+    if (retval && (retval != SD_ERROR_STATE_MISMATCH))
+        goto err;
+
+    sd_simple_cmd(drive, &request, SD_SET_BLOCKLEN, SD_BLOCK_SIZE, RESPONSE_R1);
+    if ((retval = sd_unpack_r1(&request, &r1)))
+        goto err;
+
+    if (sd2_0[drive])
+    {
+        sd_send_cmd(drive, &request, SD_WRITE_MULTIPLE_BLOCK, start,
+                 count, SD_BLOCK_SIZE, RESPONSE_R1,
+                 (void*)buf);
+        if ((retval = sd_unpack_r1(&request, &r1)))
+            goto err;
+    }
+    else
+    {
+        sd_send_cmd(drive, &request, SD_WRITE_MULTIPLE_BLOCK,
+                 start * SD_BLOCK_SIZE, count,
+                 SD_BLOCK_SIZE, RESPONSE_R1, (void*)buf);
+        if ((retval = sd_unpack_r1(&request, &r1)))
+            goto err;
+    }
+
+    last_disk_activity = current_tick;
+
+    sd_simple_cmd(drive, &request, SD_STOP_TRANSMISSION, 0, RESPONSE_R1B);
+    if ((retval = sd_unpack_r1(&request, &r1)))
+        goto err;
+
+err:
+    sd_stop_transfer(drive);
+
+    return retval;
+}
+
+long sd_last_disk_activity(void)
+{
+    return last_disk_activity;
+}
+
+int sd_spinup_time(void)
+{
+    return 0;
+}
+
+void sd_enable(bool on)
+{
+    (void)on;
+}
+
+bool sd_disk_is_active(void)
+{
+    return false;
+}
+
+int sd_soft_reset(void)
+{
+    return 0;
+}
+
+#ifdef HAVE_HOTSWAP
+bool sd_removable(const int drive)
+{
+    (void)drive;
+    return true;
+}
+
+static int sd1_oneshot_callback(struct timeout *tmo)
+{
+    int state = card_detect_target(SD_SLOT_1);
+
+    /* This is called only if the state was stable for 300ms - check state
+     * and post appropriate event. */
+    queue_broadcast(state ? SYS_HOTSWAP_INSERTED : SYS_HOTSWAP_EXTRACTED,
+                    0);
+
+    sd_gpio_setup_irq(SD_SLOT_1, state);
+
+    return 0;
+    (void)tmo;
+}
+
+static int sd2_oneshot_callback(struct timeout *tmo)
+{
+    int state = card_detect_target(SD_SLOT_2);
+
+    /* This is called only if the state was stable for 300ms - check state
+     * and post appropriate event. */
+    queue_broadcast(state ? SYS_HOTSWAP_INSERTED : SYS_HOTSWAP_EXTRACTED,
+                    1);
+
+    sd_gpio_setup_irq(SD_SLOT_2, state);
+
+    return 0;
+    (void)tmo;
+}
+
+/* called on insertion/removal interrupt */
+void GPIO_SD1_CD(void)
+{
+    static struct timeout sd1_oneshot;
+    timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
+}
+
+void GPIO_SD2_CD(void)
+{
+    static struct timeout sd2_oneshot;
+    timeout_register(&sd2_oneshot, sd2_oneshot_callback, (3*HZ/10), 0);
+}
+#endif
+
+bool sd_present(const int drive)
+{
+    return card_detect_target(drive);
+}
+
+#ifdef CONFIG_STORAGE_MULTI
+int sd_num_drives(int first_drive)
+{
+    return NUM_DRIVES;
+}
+#endif /* CONFIG_STORAGE_MULTI */
+
+int sd_event(long id, intptr_t data)
+{
+    int rc = 0;
+
+    switch (id)
+    {
+#ifdef HAVE_HOTSWAP
+    case SYS_HOTSWAP_INSERTED:
+    case SYS_HOTSWAP_EXTRACTED:
+        /* Force card init for new card, re-init for re-inserted one or
+         * clear if the last attempt to init failed with an error. */
+        mutex_lock(&sd_mtx); /* lock-out card activity */
+        card[data].initialized = 0;
+        mutex_unlock(&sd_mtx);
+        break;
+#endif /* HAVE_HOTSWAP */
+    default:
+        rc = storage_event_default_handler(id, data, last_disk_activity,
+                                           STORAGE_SD);
+        break;
+    }
+
+    return rc;
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/backlight-target.h b/firmware/target/mips/ingenic_jz47xx/backlight-target.h
index 0dc7ce387a..1b61d13e4c 100644
--- a/firmware/target/mips/ingenic_jz47xx/backlight-target.h
+++ b/firmware/target/mips/ingenic_jz47xx/backlight-target.h
@@ -26,6 +26,8 @@
 bool backlight_hw_init(void);
 void backlight_hw_on(void);
 void backlight_hw_off(void);
+#ifdef HAVE_BACKLIGHT_BRIGHTNESS
 void backlight_hw_brightness(int brightness);
+#endif /* HAVE_BACKLIGHT_BRIGHTNESS */
 
 #endif /* BACKLIGHT_TARGET_H */
diff --git a/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c b/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c
new file mode 100644
index 0000000000..f25dc70eb4
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c
@@ -0,0 +1,293 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "audio.h"
+#include "sound.h"
+#include "cpu.h"
+#include "system.h"
+#include "pcm_sw_volume.h"
+#include "cs4398.h"
+#include "kernel.h"
+
+#define PIN_CS_RST      (32*1+10)
+#define PIN_CODEC_PWRON (32*1+13)
+#define PIN_AP_MUTE     (32*1+14)
+#define PIN_JD_CON      (32*1+16)
+
+static void pop_ctrl(const int val)
+{
+    if(val)
+        __gpio_clear_pin(PIN_JD_CON);
+    else
+        __gpio_set_pin(PIN_JD_CON);
+}
+
+static void amp_enable(const int val)
+{
+    if(val)
+        __gpio_set_pin(PIN_CODEC_PWRON);
+    else
+        __gpio_clear_pin(PIN_CODEC_PWRON);
+}
+
+static void dac_enable(const int val)
+{
+    if(val)
+        __gpio_set_pin(PIN_CS_RST);
+    else
+        __gpio_clear_pin(PIN_CS_RST);
+}
+
+static void ap_mute(bool mute)
+{
+    if(mute)
+        __gpio_clear_pin(PIN_AP_MUTE);
+    else
+        __gpio_set_pin(PIN_AP_MUTE);
+}
+
+static void audiohw_mute(bool mute)
+{
+    if(mute)
+        cs4398_write_reg(CS4398_REG_MUTE, cs4398_read_reg(CS4398_REG_MUTE) | CS4398_MUTE_A | CS4398_MUTE_B);
+    else
+        cs4398_write_reg(CS4398_REG_MUTE, cs4398_read_reg(CS4398_REG_MUTE) & ~(CS4398_MUTE_A | CS4398_MUTE_B));
+}
+
+void audiohw_preinit(void)
+{
+    cs4398_write_reg(CS4398_REG_MISC, CS4398_CPEN | CS4398_PDN);
+    cs4398_write_reg(CS4398_REG_MODECTL, CS4398_FM_SINGLE | CS4398_DEM_NONE | CS4398_DIF_LJUST);
+    cs4398_write_reg(CS4398_REG_VOLMIX, CS4398_ATAPI_A_L | CS4398_ATAPI_B_R);
+    cs4398_write_reg(CS4398_REG_MUTE, CS4398_MUTEP_LOW);
+    cs4398_write_reg(CS4398_REG_VOL_A, 0xff);
+    cs4398_write_reg(CS4398_REG_VOL_B, 0xff);
+    cs4398_write_reg(CS4398_REG_RAMPFILT, CS4398_ZERO_CROSS | CS4398_SOFT_RAMP);
+    cs4398_write_reg(CS4398_REG_MISC, CS4398_CPEN);
+}
+
+void audiohw_init(void)
+{
+    __gpio_as_func1(3*32+12); // BCK
+    __gpio_as_func0(3*32+13); // LRCK
+    __gpio_as_func2(4*32+5);  // MCLK
+    __gpio_as_func0(4*32+7);  // DO
+
+    pop_ctrl(0);
+    ap_mute(true);
+    amp_enable(0);
+    dac_enable(0);
+
+    __gpio_as_output(PIN_JD_CON);
+    __gpio_as_output(PIN_AP_MUTE);
+    __gpio_as_output(PIN_CODEC_PWRON);
+    __gpio_as_output(PIN_CS_RST);
+
+    mdelay(100);
+    amp_enable(1);
+
+    /* set AIC clk PLL1 */
+    __cpm_select_i2sclk_pll();
+    __cpm_select_i2sclk_pll1();
+
+    __cpm_enable_pll_change();
+    __cpm_set_i2sdiv(43-1);
+
+    __cpm_start_aic();
+
+    /* Init AIC */
+    __i2s_enable_sclk();
+    __i2s_external_codec();
+    __i2s_select_msbjustified();
+    __i2s_as_master();
+    __i2s_enable_transmit_dma();
+    __i2s_set_transmit_trigger(24);
+    __i2s_set_oss_sample_size(16);
+    __i2s_enable();
+
+    /* Init DAC */
+    dac_enable(1);
+    udelay(1);
+    audiohw_preinit();
+}
+
+static int vol_tenthdb2hw(const int tdb)
+{
+    if (tdb < CS4398_VOLUME_MIN) {
+        return 0xff;
+    } else if (tdb > CS4398_VOLUME_MAX) {
+        return 0x00;
+    } else {
+        return (-tdb/5);
+    }
+}
+
+void audiohw_set_volume(int vol_l, int vol_r)
+{
+    cs4398_write_reg(CS4398_REG_VOL_A, vol_tenthdb2hw(vol_l));
+    cs4398_write_reg(CS4398_REG_VOL_B, vol_tenthdb2hw(vol_r));
+}
+
+void audiohw_set_lineout_volume(int vol_l, int vol_r)
+{
+#if 0 /* unused */
+    cs4398_write_reg(CS4398_REG_VOL_A, vol_tenthdb2hw(vol_l));
+    cs4398_write_reg(CS4398_REG_VOL_B, vol_tenthdb2hw(vol_r));
+#else
+    (void)vol_l;
+    (void)vol_r;
+#endif
+}
+
+void audiohw_set_filter_roll_off(int value)
+{
+    /* 0 = fast (sharp);
+       1 = slow */
+    if (value == 0) {
+        cs4398_write_reg(CS4398_REG_RAMPFILT, cs4398_read_reg(CS4398_REG_RAMPFILT) & ~CS4398_FILT_SEL);
+    } else {
+        cs4398_write_reg(CS4398_REG_RAMPFILT, cs4398_read_reg(CS4398_REG_RAMPFILT) | CS4398_FILT_SEL);
+    }
+}
+
+void pll1_init(unsigned int freq);
+void audiohw_set_frequency(int fsel)
+{
+    unsigned int  pll1_speed;
+    unsigned char mclk_div, bclk_div, func_mode;
+
+    switch(fsel)
+    {
+        case HW_FREQ_8:
+            pll1_speed = 426000000;
+            mclk_div = 52;
+            bclk_div = 16;
+            func_mode = 0;
+            break;
+        case HW_FREQ_11:
+            pll1_speed = 508000000;
+            mclk_div = 45;
+            bclk_div = 16;
+            func_mode = 0;
+            break;
+        case HW_FREQ_12:
+            pll1_speed = 516000000;
+            mclk_div = 42;
+            bclk_div = 16;
+            func_mode = 0;
+            break;
+        case HW_FREQ_16:
+            pll1_speed = 426000000;
+            mclk_div = 52;
+            bclk_div = 8;
+            func_mode = 0;
+            break;
+        case HW_FREQ_22:
+            pll1_speed = 508000000;
+            mclk_div = 45;
+            bclk_div = 8;
+            func_mode = 0;
+            break;
+        case HW_FREQ_24:
+            pll1_speed = 516000000;
+            mclk_div = 42;
+            bclk_div = 8;
+            func_mode = 0;
+            break;
+        case HW_FREQ_32:
+            pll1_speed = 426000000;
+            mclk_div = 52;
+            bclk_div = 4;
+            func_mode = 0;
+            break;
+        case HW_FREQ_44:
+            pll1_speed = 508000000;
+            mclk_div = 45;
+            bclk_div = 4;
+            func_mode = 0;
+            break;
+        case HW_FREQ_48:
+            pll1_speed = 516000000;
+            mclk_div = 42;
+            bclk_div = 4;
+            func_mode = 0;
+            break;
+        case HW_FREQ_64:
+            pll1_speed = 426000000;
+            mclk_div = 52;
+            bclk_div = 2;
+            func_mode = 1;
+            break;
+        case HW_FREQ_88:
+            pll1_speed = 508000000;
+            mclk_div = 45;
+            bclk_div = 2;
+            func_mode = 1;
+            break;
+        case HW_FREQ_96:
+            pll1_speed = 516000000;
+            mclk_div = 42;
+            bclk_div = 2;
+            func_mode = 1;
+            break;
+        default:
+            return;
+    }
+
+    __i2s_stop_bitclk();
+
+    /* 0 = Single-Speed Mode (<50KHz);
+       1 = Double-Speed Mode (50-100KHz);
+       2 = Quad-Speed Mode;  (100-200KHz) */
+    cs4398_write_reg(CS4398_REG_MODECTL, (cs4398_read_reg(CS4398_REG_MODECTL) & ~CS4398_FM_MASK) | func_mode);
+    if (func_mode == 2)
+        cs4398_write_reg(CS4398_REG_MISC, cs4398_read_reg(CS4398_REG_MISC) | CS4398_MCLKDIV2);
+    else
+        cs4398_write_reg(CS4398_REG_MISC, cs4398_read_reg(CS4398_REG_MISC) & ~CS4398_MCLKDIV2);
+
+    pll1_init(pll1_speed);
+    __cpm_enable_pll_change();
+    __cpm_set_i2sdiv(mclk_div-1);
+    __i2s_set_i2sdiv(bclk_div-1);
+    __i2s_start_bitclk();
+}
+
+void audiohw_postinit(void)
+{
+    sleep(HZ);
+    audiohw_mute(false);
+    ap_mute(false);
+    pop_ctrl(1);
+}
+
+void audiohw_close(void)
+{
+    pop_ctrl(0);
+    sleep(HZ/10);
+    ap_mute(true);
+    audiohw_mute(true);
+    amp_enable(0);
+    dac_enable(0);
+    __i2s_disable();
+    __cpm_stop_aic();
+    sleep(HZ);
+    pop_ctrl(1);
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/crt0.S b/firmware/target/mips/ingenic_jz47xx/crt0.S
index 0ae365022a..49de3e6a01 100644
--- a/firmware/target/mips/ingenic_jz47xx/crt0.S
+++ b/firmware/target/mips/ingenic_jz47xx/crt0.S
@@ -50,6 +50,7 @@
     .set    noat
 
 #ifdef BOOTLOADER
+#ifndef XDUOO_X3
     /* These will get filled in by scramble */
     .word 0 /* Empty    */
     .word 0 /* Filesize */
@@ -65,6 +66,7 @@ _relocate_loop:
     bne    t1, t2, _relocate_loop
     sw     t3, -4(t1)
 #endif
+#endif
 
 _start:
     la      ra, _start
diff --git a/firmware/target/mips/ingenic_jz47xx/debug-jz4760.c b/firmware/target/mips/ingenic_jz47xx/debug-jz4760.c
new file mode 100644
index 0000000000..88fc351946
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/debug-jz4760.c
@@ -0,0 +1,146 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "system.h"
+#include "cpu.h"
+#include <stdarg.h>
+#include <stdio.h>
+#include "lcd.h"
+#include "kernel.h"
+#include "font.h"
+#include "button.h"
+#include "timefuncs.h"
+
+#define CFG_UART_BASE           UART1_BASE      /* Base of the UART channel */
+
+void serial_putc (const char c)
+{
+        volatile u8 *uart_lsr = (volatile u8 *)(CFG_UART_BASE + OFF_LSR);
+        volatile u8 *uart_tdr = (volatile u8 *)(CFG_UART_BASE + OFF_TDR);
+
+        if (c == '\n') serial_putc ('\r');
+
+        /* Wait for fifo to shift out some bytes */
+        while ( !((*uart_lsr & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60) );
+
+        *uart_tdr = (u8)c;
+}
+
+void serial_puts (const char *s)
+{
+        while (*s) {
+                serial_putc (*s++);
+        }
+}
+
+void serial_putsf(const char *format, ...)
+{
+    static char printfbuf[256];
+    int len;
+    unsigned char *ptr;
+    va_list ap;
+    va_start(ap, format);
+
+    ptr = printfbuf;
+    len = vsnprintf(ptr, sizeof(printfbuf), format, ap);
+    va_end(ap);
+
+    serial_puts(ptr);
+    serial_putc('\n');
+}
+
+void serial_put_hex(unsigned int  d)
+{
+        char c[12];
+        int i;
+        for(i = 0; i < 8;i++)
+        {
+                c[i] = (d >> ((7 - i) * 4)) & 0xf;
+                if(c[i] < 10)
+                        c[i] += 0x30;
+                else
+                        c[i] += (0x41 - 10);
+        }
+        c[8] = '\n';
+        c[9] = 0;
+        serial_puts(c);
+
+}
+
+void serial_put_dec(unsigned int  d)
+{
+        char c[16];
+        int i;
+        int j = 0;
+        int x = d;
+
+        while (x /= 10)
+                j++;
+
+        for (i = j; i >= 0; i--) {
+                c[i] = d % 10;
+                c[i] += 0x30;
+                d /= 10;
+        }
+        c[j + 1] = '\n';
+        c[j + 2] = 0;
+        serial_puts(c);
+}
+
+void serial_dump_data(unsigned char* data, int len)
+{
+        int i;
+        for(i=0; i<len; i++)
+        {
+                unsigned char a = ((*data)>>4) & 0xf;
+                if(a < 10)
+                        a += 0x30;
+                else
+                        a += (0x41 - 10);
+                serial_putc( a );
+                
+                a = (*data) & 0xf;
+                if(a < 10)
+                        a += 0x30;
+                else
+                        a += (0x41 - 10);
+                serial_putc( a );
+
+                serial_putc( ' ' );
+                
+                data++;
+        }
+        
+        serial_putc( '\n' );
+}
+
+bool dbg_ports(void)
+{
+    serial_puts("dbg_ports\n");
+    return false;
+}
+
+bool dbg_hw_info(void)
+{
+    serial_puts("dbg_hw_info\n");
+    return false;
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/dma-target.h b/firmware/target/mips/ingenic_jz47xx/dma-target.h
new file mode 100644
index 0000000000..792d8fe87c
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/dma-target.h
@@ -0,0 +1,31 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef __DMA_TARGET_H_
+#define __DMA_TARGET_H_
+
+#include "system.h"
+#include <string.h>
+
+void memset_dma(void *target, int c, size_t len, unsigned int bits);
+void memcpy_dma(void *target, const void *source, size_t len, unsigned int bits);
+
+#endif /* __DMA_TARGET_H_ */
diff --git a/firmware/target/mips/ingenic_jz47xx/dma_acc-jz4760.c b/firmware/target/mips/ingenic_jz47xx/dma_acc-jz4760.c
new file mode 100644
index 0000000000..4cdea2ad08
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/dma_acc-jz4760.c
@@ -0,0 +1,102 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "dma-target.h"
+
+#define MDMA_CHANNEL 0
+
+void memset_dma(void *target, int c, size_t len, unsigned int bits)
+{
+    unsigned int d;
+    unsigned char *dp;
+
+    if(((unsigned int)target < 0xa0000000) && len)
+         dma_cache_wback_inv((unsigned long)target, len);
+
+    dp = (unsigned char *)((unsigned int)(&d) | 0xa0000000);
+    *(dp + 0) = c;
+    *(dp + 1) = c;
+    *(dp + 2) = c;
+    *(dp + 3) = c;
+
+    REG_MDMAC_DCCSR(MDMA_CHANNEL) = 0;
+    REG_MDMAC_DSAR(MDMA_CHANNEL) = PHYSADDR((unsigned long)dp);
+    REG_MDMAC_DTAR(MDMA_CHANNEL) = PHYSADDR((unsigned long)target);
+    REG_MDMAC_DRSR(MDMA_CHANNEL) = DMAC_DRSR_RS_AUTO;
+    switch (bits)
+    {
+        case 8:
+            REG_MDMAC_DTCR(MDMA_CHANNEL) = len;
+            REG_MDMAC_DCMD(MDMA_CHANNEL) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_8 | DMAC_DCMD_DS_8BIT;
+            break;
+        case 16:
+            REG_MDMAC_DTCR(MDMA_CHANNEL) = len / 2;
+            REG_MDMAC_DCMD(MDMA_CHANNEL) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT;
+            break;
+        case 32:
+            REG_MDMAC_DTCR(MDMA_CHANNEL) = len / 4;
+            REG_MDMAC_DCMD(MDMA_CHANNEL) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT;
+            break;
+        default:
+            return;
+    }
+    REG_MDMAC_DCCSR(MDMA_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
+
+    while (REG_MDMAC_DTCR(MDMA_CHANNEL));
+
+    REG_MDMAC_DCCSR(MDMA_CHANNEL) = 0;
+}
+
+void memcpy_dma(void *target, const void *source, size_t len, unsigned int bits)
+{
+    if(((unsigned int)source < 0xa0000000) && len)
+        dma_cache_wback_inv((unsigned long)source, len);
+    
+    if(((unsigned int)target < 0xa0000000) && len)
+        dma_cache_wback_inv((unsigned long)target, len);
+    
+    REG_MDMAC_DCCSR(MDMA_CHANNEL) = 0;
+    REG_MDMAC_DSAR(MDMA_CHANNEL) = PHYSADDR((unsigned long)source);
+    REG_MDMAC_DTAR(MDMA_CHANNEL) = PHYSADDR((unsigned long)target); 
+    REG_MDMAC_DRSR(MDMA_CHANNEL) = DMAC_DRSR_RS_AUTO;
+    switch (bits)
+    {
+        case 8:
+            REG_MDMAC_DTCR(MDMA_CHANNEL) = len;
+            REG_MDMAC_DCMD(MDMA_CHANNEL) = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_8 | DMAC_DCMD_DS_8BIT;
+            break;
+        case 16:
+            REG_MDMAC_DTCR(MDMA_CHANNEL) = len / 2;
+            REG_MDMAC_DCMD(MDMA_CHANNEL) = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT;
+            break;
+        case 32:
+            REG_MDMAC_DTCR(MDMA_CHANNEL) = len / 4;
+            REG_MDMAC_DCMD(MDMA_CHANNEL) = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT;
+            break;
+        default:
+            return;
+    }
+    REG_MDMAC_DCCSR(MDMA_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
+
+    while (REG_MDMAC_DTCR(MDMA_CHANNEL));
+
+    REG_MDMAC_DCCSR(MDMA_CHANNEL) = 0;
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/i2c-jz4760.c b/firmware/target/mips/ingenic_jz47xx/i2c-jz4760.c
new file mode 100644
index 0000000000..e35fe7a091
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/i2c-jz4760.c
@@ -0,0 +1,355 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+#include "system.h"
+#include "cpu.h"
+#include "logf.h"
+#include "i2c.h"
+
+#define I2C_CHN   1
+#define I2C_CLK   100000
+
+#define I2C_READ  1
+#define I2C_WRITE 0
+
+#define I2C_M_RD  1
+#define I2C_M_WR  2
+
+#define TIMEOUT   100000
+
+static char i2c_rwflags;
+static int i2c_ctrl_rest = 0;
+static unsigned char *msg_buf;
+static int cmd_cnt;
+static volatile int cmd_flag;
+static int r_cnt;
+static unsigned char i2c_subaddr = 0;
+
+/*
+ * I2C bus protocol basic routines
+ */
+
+/* Interrupt handler */
+void I2C1(void)
+{
+    int timeout = TIMEOUT;
+
+    if (__i2c_abrt_7b_addr_nack(I2C_CHN)) {
+        int ret;
+        cmd_flag = -1;
+        __i2c_clear_interrupts(ret,I2C_CHN);
+        REG_I2C_INTM(I2C_CHN) = 0x0;
+        return;
+    }
+
+    /* first byte,when length > 1 */
+    if (cmd_flag == 0 && cmd_cnt > 1) {
+        cmd_flag = 1;
+        if (i2c_rwflags == I2C_M_RD) {
+            REG_I2C_DC(I2C_CHN) = I2C_READ << 8;
+        } else {
+            REG_I2C_DC(I2C_CHN) = (I2C_WRITE << 8) | *msg_buf++;
+        }
+        cmd_cnt--;
+    }
+
+    if (i2c_rwflags == I2C_M_RD) {
+        if (REG_I2C_STA(I2C_CHN) & I2C_STA_RFNE) {
+            *msg_buf++ = REG_I2C_DC(I2C_CHN) & 0xff;
+            r_cnt--;
+        }
+
+        REG_I2C_DC(I2C_CHN) = I2C_READ << 8;
+    } else {
+        REG_I2C_DC(I2C_CHN) = (I2C_WRITE << 8) | *msg_buf++;
+    }
+
+    cmd_cnt--;
+        
+    if (!(cmd_cnt)) {
+        REG_I2C_INTM(I2C_CHN) = 0x0;
+        cmd_flag = 2;
+        if (i2c_rwflags == I2C_M_RD){
+            while (r_cnt > 2) {
+                if ((REG_I2C_STA(I2C_CHN) & I2C_STA_RFNE) && timeout) {
+                    *msg_buf++ = REG_I2C_DC(I2C_CHN) & 0xff;
+                    r_cnt--;
+                }
+                if (!(timeout--)) {
+                    cmd_flag = -1;
+                    return;
+                }
+            }
+        }
+    }
+
+    return;
+}
+
+static int i2c_set_clk(int i2c_clk)
+{
+    int dev_clk = __cpm_get_pclk();
+    int count = 0;
+
+    if (i2c_clk < 0 || i2c_clk > 400000)
+        goto Set_clk_err;
+
+    count = dev_clk/i2c_clk - 23;
+    if (count < 0)
+        goto Set_clk_err;
+
+    if (i2c_clk <= 100000) {
+        REG_I2C_CTRL(I2C_CHN) = 0x43 | i2c_ctrl_rest;      /* standard speed mode*/
+        if (count%2 == 0) {
+            REG_I2C_SHCNT(I2C_CHN) = count/2 + 6 - 5;
+            REG_I2C_SLCNT(I2C_CHN) = count/2 + 8 + 5;
+        } else {
+            REG_I2C_SHCNT(I2C_CHN) = count/2 + 6 -5;
+            REG_I2C_SLCNT(I2C_CHN) = count/2 + 8 +5 + 1;
+        }
+    } else {
+        REG_I2C_CTRL(I2C_CHN) = 0x45 | i2c_ctrl_rest;       /* high speed mode*/
+        if (count%2 == 0) {
+            REG_I2C_FHCNT(I2C_CHN) = count/2 + 6;
+            REG_I2C_FLCNT(I2C_CHN) = count/2 + 8;
+        } else {
+            REG_I2C_FHCNT(I2C_CHN) = count/2 + 6;
+            REG_I2C_FLCNT(I2C_CHN) = count/2 + 8 + 1;
+        }
+    }
+    return 0;
+
+Set_clk_err:
+
+    logf("i2c set sclk faild,i2c_clk=%d,dev_clk=%d.\n",i2c_clk,dev_clk);
+    return -1;
+}
+
+static int i2c_disable(void)
+{
+    int timeout = TIMEOUT;
+
+    __i2c_disable(I2C_CHN);
+    while(__i2c_is_enable(I2C_CHN) && (timeout > 0)) {
+        udelay(1);
+        timeout--;
+    }
+    if(timeout)
+        return 0;
+    else
+        return 1;
+}
+
+static int i2c_enable(void)
+{
+    int timeout = TIMEOUT;
+
+    __i2c_enable(I2C_CHN);
+    while(__i2c_is_disable(I2C_CHN) && (timeout > 0)) {
+        udelay(1);
+        timeout--;
+    }
+    if(timeout)
+        return 0;
+    else
+        return 1;
+}
+
+static void i2c_init_as_master(unsigned char address)
+{
+    if(i2c_disable())
+        logf("i2c not disable\n");
+
+    i2c_set_clk(I2C_CLK);
+
+    REG_I2C_TAR(I2C_CHN) = address;  /* slave id needed write only once */
+    REG_I2C_INTM(I2C_CHN) = 0x0; /* unmask all interrupts */
+    REG_I2C_TXTL(I2C_CHN) = 0x1;
+
+    if(i2c_enable())
+        logf("i2c not enable\n");
+}
+
+int xfer_read_subaddr(unsigned char subaddr, unsigned char device, unsigned char *buf, int length)
+{
+    int timeout,r_i = 0;
+
+    cmd_cnt = length;
+    r_cnt = length;
+    msg_buf = buf;
+    i2c_rwflags = I2C_M_RD;
+    i2c_ctrl_rest = I2C_CTRL_REST;
+    i2c_init_as_master(device);
+        
+    REG_I2C_DC(I2C_CHN) = (I2C_WRITE << 8) | subaddr;
+        
+    cmd_flag = 0;
+    REG_I2C_INTM(I2C_CHN) = 0x10;
+    timeout = TIMEOUT;
+    while (cmd_flag != 2 && --timeout) {
+        if (cmd_flag == -1) {
+            r_i = 1;
+            goto R_dev_err;
+        }
+        udelay(10);
+    }
+    if (!timeout) {
+        r_i = 4;
+        goto R_timeout;
+    }
+
+    while (r_cnt) {
+        while (!(REG_I2C_STA(I2C_CHN) & I2C_STA_RFNE)) {
+            if ((cmd_flag == -1) ||
+                (REG_I2C_INTST(I2C_CHN) & I2C_INTST_TXABT) ||
+                REG_I2C_TXABRT(I2C_CHN)) {
+                int ret;
+                r_i = 2;
+                __i2c_clear_interrupts(ret,I2C_CHN);
+                goto R_dev_err;
+            }
+        }
+        *msg_buf++ = REG_I2C_DC(I2C_CHN) & 0xff;
+        r_cnt--;
+    }
+
+    timeout = TIMEOUT;
+    while ((REG_I2C_STA(I2C_CHN) & I2C_STA_MSTACT) && --timeout)
+        udelay(10);
+    if (!timeout){
+        r_i = 3;
+        goto R_timeout;
+    }
+
+    return 0;
+
+R_dev_err:
+R_timeout:
+
+    i2c_init_as_master(device);
+    if (r_i == 1) {
+        logf("Read i2c device 0x%2x failed in r_i = %d :device no ack.\n",device,r_i);
+    } else if (r_i == 2) {
+        logf("Read i2c device 0x%2x failed in r_i = %d :i2c abort.\n",device,r_i);
+    } else if (r_i == 3) {
+        logf("Read i2c device 0x%2x failed in r_i = %d :waite master inactive timeout.\n",device,r_i);
+    } else if (r_i == 4) {
+        logf("Read i2c device 0x%2x failed in r_i = %d.\n",device,r_i);
+    } else {
+        logf("Read i2c device 0x%2x failed in r_i = %d.\n",device,r_i);
+    }
+    return -1;
+}
+
+int xfer_write_subaddr(unsigned char subaddr, unsigned char device, const unsigned char *buf, int length)
+{
+    int timeout,w_i = 0;
+
+    cmd_cnt = length;
+    r_cnt = length;
+    msg_buf = (unsigned char *)buf;
+    i2c_rwflags = I2C_M_WR;
+    i2c_ctrl_rest = I2C_CTRL_REST;
+    i2c_init_as_master(device);
+        
+    REG_I2C_DC(I2C_CHN) = (I2C_WRITE << 8) | subaddr;
+
+    cmd_flag = 0;
+    REG_I2C_INTM(I2C_CHN) = 0x10;
+
+    timeout = TIMEOUT;
+    while ((cmd_flag != 2) && (--timeout)) 
+    {
+        if (cmd_flag == -1){
+            w_i = 1;
+            goto W_dev_err;
+        }
+        udelay(10);
+    }
+
+    timeout = TIMEOUT;
+    while((!(REG_I2C_STA(I2C_CHN) & I2C_STA_TFE)) && --timeout){
+        udelay(10);
+    }
+    if (!timeout){
+        w_i = 2;
+        goto W_timeout;
+    }
+
+    timeout = TIMEOUT;
+    while (__i2c_master_active(I2C_CHN) && --timeout);
+    if (!timeout){
+        w_i = 3;
+        goto W_timeout;
+    }
+
+    if ((length == 1)&&
+        ((cmd_flag == -1) ||
+        (REG_I2C_INTST(I2C_CHN) & I2C_INTST_TXABT) ||
+        REG_I2C_TXABRT(I2C_CHN))) {
+        int ret;
+        w_i = 5;
+        __i2c_clear_interrupts(ret,I2C_CHN);
+        goto W_dev_err;
+    }
+
+    return 0;
+
+W_dev_err:
+W_timeout:
+
+    i2c_init_as_master(device);
+    if (w_i == 1) {
+        logf("Write i2c device 0x%2x failed in w_i=%d:device no ack. I2C_CHN:[%d]sxyzhang\n",device,w_i,I2C_CHN);
+    } else if (w_i == 2) {
+        logf("Write i2c device 0x%2x failed in w_i=%d:waite TF buff empty timeout.\n",device,w_i);
+    } else if (w_i == 3) {
+        logf("Write i2c device 0x%2x failed in w_i=%d:waite master inactive timeout.\n",device,w_i);
+    } else if (w_i == 5) {
+        logf("Write i2c device 0x%2x failed in w_i=%d:device no ack or abort.I2C_CHN:[%d]sxyzhang \n",device,w_i,I2C_CHN);
+    } else  {
+        logf("Write i2c device 0x%2x failed in w_i=%d.\n",device,w_i);
+    }
+
+    return -1;
+}
+
+int i2c_read(int device, unsigned char* buf, int count)
+{
+    return xfer_read_subaddr(i2c_subaddr, device, &buf[0], count);
+}
+
+int i2c_write(int device, const unsigned char* buf, int count)
+{
+    if (count < 2)
+    {
+        i2c_subaddr = buf[0];
+        return 0;
+    }
+    return xfer_write_subaddr(buf[0], device, &buf[1], count-1);
+}
+
+void i2c_init(void)
+{
+    __gpio_as_i2c(I2C_CHN);
+    __cpm_start_i2c1();
+    system_enable_irq(IRQ_I2C1);
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/kernel-jz4760.c b/firmware/target/mips/ingenic_jz47xx/kernel-jz4760.c
new file mode 100644
index 0000000000..ab0f152669
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/kernel-jz4760.c
@@ -0,0 +1,53 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "system.h"
+#include "kernel.h"
+#include "cpu.h"
+
+void tick_start(unsigned int interval_in_ms)
+{
+    unsigned int latch;
+
+    /* 12Mhz / 4 = 3Mhz */
+    latch = interval_in_ms*1000 * 3;
+
+    REG_OST_OSTCSR = OSTCSR_PRESCALE4 | OSTCSR_EXT_EN;
+    REG_OST_OSTDR = latch;
+    REG_OST_OSTCNTL = 0;
+    REG_OST_OSTCNTH = 0;
+
+    system_enable_irq(IRQ_TCU0);
+
+    REG_TCU_TMCR = TMCR_OSTMASK; /* unmask match irq */
+    REG_TCU_TSCR = TSCR_OST;  /* enable timer clock */
+    REG_TCU_TESR = TESR_OST;  /* start counting up */
+}
+
+/* Interrupt handler */
+void TCU0(void)
+{
+    REG_TCU_TFCR = TFCR_OSTFLAG; /* ACK timer */
+    
+    /* Run through the list of tick tasks */
+    call_tick_tasks();
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/lcd-jz4760.c b/firmware/target/mips/ingenic_jz47xx/lcd-jz4760.c
new file mode 100644
index 0000000000..03fb937d0a
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/lcd-jz4760.c
@@ -0,0 +1,28 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include <sys/types.h> /* off_t */
+
+#include "config.h"
+#include "cpu.h"
+#include "lcd.h"
+#include "lcd-target.h"
+#include "system.h"
+#include "kernel.h"
diff --git a/firmware/target/mips/ingenic_jz47xx/pcm-jz4760.c b/firmware/target/mips/ingenic_jz47xx/pcm-jz4760.c
new file mode 100644
index 0000000000..39df037f76
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/pcm-jz4760.c
@@ -0,0 +1,240 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "system.h"
+#include "kernel.h"
+#include "logf.h"
+#include "audio.h"
+#include "sound.h"
+#include "pcm.h"
+#include "pcm-internal.h"
+#include "cpu.h"
+
+
+/****************************************************************************
+ ** Playback DMA transfer
+ **/
+
+void pcm_play_dma_postinit(void)
+{
+    audiohw_postinit();
+
+    /* Flush FIFO */
+    __aic_flush_tfifo();
+}
+
+void pcm_play_dma_init(void)
+{
+    system_enable_irq(DMA_IRQ(DMA_AIC_TX_CHANNEL));
+
+    /* Initialize default register values. */
+    audiohw_init();
+}
+
+void pcm_dma_apply_settings(void)
+{
+    audiohw_set_frequency(pcm_fsel);
+}
+
+static const void* playback_address;
+static inline void set_dma(const void *addr, size_t size)
+{
+    int burst_size;
+    logf("%x %d %x", (unsigned int)addr, size, REG_AIC_SR);
+
+    dma_cache_wback_inv((unsigned long)addr, size);
+    
+    if(size % 16)
+    {
+        if(size % 4)
+        {
+            size /= 2;
+            burst_size = DMAC_DCMD_DS_16BIT;
+        }
+        else
+        {
+            size /= 4;
+            burst_size = DMAC_DCMD_DS_32BIT;
+        }
+    }
+    else
+    {
+        size /= 16;
+        burst_size = DMAC_DCMD_DS_16BYTE;
+    }
+
+    REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = 0;
+    REG_DMAC_DSAR(DMA_AIC_TX_CHANNEL)  = PHYSADDR((unsigned long)addr);
+    REG_DMAC_DTAR(DMA_AIC_TX_CHANNEL)  = PHYSADDR((unsigned long)AIC_DR);
+    REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL)  = size;
+    REG_DMAC_DRSR(DMA_AIC_TX_CHANNEL)  = DMAC_DRSR_RS_AICOUT;
+    REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL)  = (DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | burst_size | DMAC_DCMD_DWDH_16 | DMAC_DCMD_TIE);
+    REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
+
+    playback_address = addr;
+}
+
+static inline void play_dma_callback(void)
+{
+    const void *start;
+    size_t size;
+
+    if (pcm_play_dma_complete_callback(PCM_DMAST_OK, &start, &size))
+    {
+        set_dma(start, size);
+        REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) |= DMAC_DCCSR_EN;
+        pcm_play_dma_status_callback(PCM_DMAST_STARTED);
+    }
+}
+
+void DMA_CALLBACK(DMA_AIC_TX_CHANNEL)(void) __attribute__ ((section(".icode")));
+void DMA_CALLBACK(DMA_AIC_TX_CHANNEL)(void)
+{
+    if (REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) & DMAC_DCCSR_AR)
+    {
+        logf("PCM DMA address error");
+        REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) &= ~DMAC_DCCSR_AR;
+    }
+
+    if (REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) & DMAC_DCCSR_HLT)
+    {
+        logf("PCM DMA halt");
+        REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) &= ~DMAC_DCCSR_HLT;
+    }
+
+    if (REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) & DMAC_DCCSR_TT)
+    {
+        REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) &= ~DMAC_DCCSR_TT;
+        play_dma_callback();
+    }
+}
+
+void pcm_play_dma_start(const void *addr, size_t size)
+{
+    __dmac_channel_enable_clk(DMA_AIC_TX_CHANNEL);
+
+    set_dma(addr, size);
+
+    __aic_enable_replay();
+
+    __dmac_channel_enable_irq(DMA_AIC_TX_CHANNEL);
+}
+
+void pcm_play_dma_stop(void)
+{
+    int flags = disable_irq_save();
+
+    REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = (REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) | DMAC_DCCSR_HLT) & ~DMAC_DCCSR_EN;
+
+    __dmac_channel_disable_clk(DMA_AIC_TX_CHANNEL);
+
+    __aic_disable_replay();
+
+    restore_irq(flags);
+}
+
+static unsigned int play_lock = 0;
+void pcm_play_lock(void)
+{
+    int flags = disable_irq_save();
+
+    if (++play_lock == 1)
+        __dmac_channel_disable_irq(DMA_AIC_TX_CHANNEL);
+
+    restore_irq(flags);
+}
+
+void pcm_play_unlock(void)
+{
+    int flags = disable_irq_save();
+
+    if (--play_lock == 0)
+        __dmac_channel_enable_irq(DMA_AIC_TX_CHANNEL);
+
+    restore_irq(flags);
+}
+
+void pcm_play_dma_pause(bool pause)
+{
+    int flags = disable_irq_save();
+
+    if(pause)
+        REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) &= ~DMAC_DCCSR_EN;
+    else
+        REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) |= DMAC_DCCSR_EN;
+
+    restore_irq(flags);
+}
+
+static int get_dma_count(void)
+{
+    int count = REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL);
+    switch(REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) & DMAC_DCMD_DS_MASK)
+    {
+        case DMAC_DCMD_DS_16BIT:
+            count *= 2;
+            break;
+        case DMAC_DCMD_DS_32BIT:
+            count *= 4;
+            break;
+        case DMAC_DCMD_DS_16BYTE:
+            count *= 16;
+            break;
+    }
+
+    return count;
+}
+
+size_t pcm_get_bytes_waiting(void)
+{
+    int bytes, flags = disable_irq_save();
+
+    if(REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) & DMAC_DCCSR_EN)
+        bytes = get_dma_count() & ~3;
+    else
+        bytes = 0;
+
+    restore_irq(flags);
+
+    return bytes;
+}
+
+const void * pcm_play_dma_get_peak_buffer(int *count)
+{
+    int flags = disable_irq_save();
+
+    const void* addr;
+    if(REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) & DMAC_DCCSR_EN)
+    {
+        int bytes = get_dma_count();
+        *count = bytes >> 2;
+        addr = (const void*)((int)(playback_address + bytes + 2) & ~3);
+    }
+    else
+    {
+        *count = 0;
+        addr = NULL;
+    }
+
+    restore_irq(flags);
+
+    return addr;
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
new file mode 100644
index 0000000000..8472a7378f
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
@@ -0,0 +1,710 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+ 
+#include "config.h"
+#include "cpu.h"
+#include "mips.h"
+#include "mmu-mips.h"
+#include "panic.h"
+#include "system.h"
+#include "kernel.h"
+#include "power.h"
+
+static int irq;
+static void UIRQ(void)
+{
+    panicf("Unhandled interrupt occurred: %d", irq);
+}
+
+#define intr(name) extern __attribute__((weak,alias("UIRQ"))) void name (void)
+
+intr(I2C1);intr(I2C0);intr(UART3);intr(UART2);intr(UART1);intr(UART0);intr(GPU);
+intr(SSI1);intr(SSI0);intr(TSSI);intr(KBC);intr(SADC);intr(ETH);intr(UHC);
+intr(OTG);intr(TCU2);intr(TCU1);intr(TCU0);intr(GPS);intr(IPU);intr(CIM);
+intr(LCD);intr(RTC);intr(OWI);intr(AIC);intr(MSC2);intr(MSC1);intr(MSC0);
+intr(SCC);intr(BCH);intr(PCM);intr(HARB0);intr(HARB2);intr(AOSD);intr(CPM);
+
+intr(DMA0);intr(DMA1);intr(DMA2);intr(DMA3);intr(DMA4);intr(DMA5);
+intr(DMA6);intr(DMA7);intr(DMA8);intr(DMA9);intr(DMA10);intr(DMA11);
+intr(MDMA0);intr(MDMA1);intr(MDMA2);
+intr(BDMA0);intr(BDMA1);intr(BDMA2);
+
+intr(GPIO0);intr(GPIO1);intr(GPIO2);intr(GPIO3);intr(GPIO4);intr(GPIO5);
+intr(GPIO6);intr(GPIO7);intr(GPIO8);intr(GPIO9);intr(GPIO10);intr(GPIO11);
+intr(GPIO12);intr(GPIO13);intr(GPIO14);intr(GPIO15);intr(GPIO16);intr(GPIO17);
+intr(GPIO18);intr(GPIO19);intr(GPIO20);intr(GPIO21);intr(GPIO22);intr(GPIO23);
+intr(GPIO24);intr(GPIO25);intr(GPIO26);intr(GPIO27);intr(GPIO28);intr(GPIO29);
+intr(GPIO30);intr(GPIO31);intr(GPIO32);intr(GPIO33);intr(GPIO34);intr(GPIO35);
+intr(GPIO36);intr(GPIO37);intr(GPIO38);intr(GPIO39);intr(GPIO40);intr(GPIO41);
+intr(GPIO42);intr(GPIO43);intr(GPIO44);intr(GPIO45);intr(GPIO46);intr(GPIO47);
+intr(GPIO48);intr(GPIO49);intr(GPIO50);intr(GPIO51);intr(GPIO52);intr(GPIO53);
+intr(GPIO54);intr(GPIO55);intr(GPIO56);intr(GPIO57);intr(GPIO58);intr(GPIO59);
+intr(GPIO60);intr(GPIO61);intr(GPIO62);intr(GPIO63);intr(GPIO64);intr(GPIO65);
+intr(GPIO66);intr(GPIO67);intr(GPIO68);intr(GPIO69);intr(GPIO70);intr(GPIO71);
+intr(GPIO72);intr(GPIO73);intr(GPIO74);intr(GPIO75);intr(GPIO76);intr(GPIO77);
+intr(GPIO78);intr(GPIO79);intr(GPIO80);intr(GPIO81);intr(GPIO82);intr(GPIO83);
+intr(GPIO84);intr(GPIO85);intr(GPIO86);intr(GPIO87);intr(GPIO88);intr(GPIO89);
+intr(GPIO90);intr(GPIO91);intr(GPIO92);intr(GPIO93);intr(GPIO94);intr(GPIO95);
+intr(GPIO96);intr(GPIO97);intr(GPIO98);intr(GPIO99);intr(GPIO100);intr(GPIO101);
+intr(GPIO102);intr(GPIO103);intr(GPIO104);intr(GPIO105);intr(GPIO106);
+intr(GPIO107);intr(GPIO108);intr(GPIO109);intr(GPIO110);intr(GPIO111);
+intr(GPIO112);intr(GPIO113);intr(GPIO114);intr(GPIO115);intr(GPIO116);
+intr(GPIO117);intr(GPIO118);intr(GPIO119);intr(GPIO120);intr(GPIO121);
+intr(GPIO122);intr(GPIO123);intr(GPIO124);intr(GPIO125);intr(GPIO126);
+intr(GPIO127);intr(GPIO128);intr(GPIO129);intr(GPIO130);intr(GPIO131);
+intr(GPIO132);intr(GPIO133);intr(GPIO134);intr(GPIO135);intr(GPIO136);
+intr(GPIO137);intr(GPIO138);intr(GPIO139);intr(GPIO140);intr(GPIO141);
+intr(GPIO142);intr(GPIO143);intr(GPIO144);intr(GPIO145);intr(GPIO146);
+intr(GPIO147);intr(GPIO148);intr(GPIO149);intr(GPIO150);intr(GPIO151);
+intr(GPIO152);intr(GPIO153);intr(GPIO154);intr(GPIO155);intr(GPIO156);
+intr(GPIO157);intr(GPIO158);intr(GPIO159);intr(GPIO160);intr(GPIO161);
+intr(GPIO162);intr(GPIO163);intr(GPIO164);intr(GPIO165);intr(GPIO166);
+intr(GPIO167);intr(GPIO168);intr(GPIO169);intr(GPIO170);intr(GPIO171);
+intr(GPIO172);intr(GPIO173);intr(GPIO174);intr(GPIO175);intr(GPIO176);
+intr(GPIO177);intr(GPIO178);intr(GPIO179);intr(GPIO180);intr(GPIO181);
+intr(GPIO182);intr(GPIO183);intr(GPIO184);intr(GPIO185);intr(GPIO186);
+intr(GPIO187);intr(GPIO188);intr(GPIO189);intr(GPIO190);intr(GPIO191);
+
+static void (* const irqvector[])(void) =
+{
+    I2C1,I2C0,UART3,UART2,UART1,UART0,GPU,SSI1,
+    SSI0,TSSI,UIRQ,KBC,UIRQ,UIRQ,UIRQ,UIRQ,
+    UIRQ,UIRQ,SADC,ETH,UHC,OTG,UIRQ,UIRQ,
+    UIRQ,TCU2,TCU1,TCU0,GPS,IPU,CIM,LCD,
+
+    RTC,OWI,AIC,MSC2,MSC1,MSC0,SCC,BCH, // 32
+    PCM,HARB0,HARB2,AOSD,CPM,UIRQ,
+
+    DMA0,DMA1,DMA2,DMA3,DMA4,DMA5,DMA6,DMA7, // 46
+    DMA8,DMA9,DMA10,DMA11,MDMA0,MDMA1,MDMA2,BDMA0,
+    BDMA1,BDMA2,
+
+    GPIO0,GPIO1,GPIO2,GPIO3,GPIO4,GPIO5,GPIO6,GPIO7, // 64
+    GPIO8,GPIO9,GPIO10,GPIO11,GPIO12,GPIO13,GPIO14,GPIO15,
+    GPIO16,GPIO17,GPIO18,GPIO19,GPIO20,GPIO21,GPIO22,GPIO23,
+    GPIO24,GPIO25,GPIO26,GPIO27,GPIO28,GPIO29,GPIO30,GPIO31,
+    GPIO32,GPIO33,GPIO34,GPIO35,GPIO36,GPIO37,GPIO38,GPIO39,
+    GPIO40,GPIO41,GPIO42,GPIO43,GPIO44,GPIO45,GPIO46,GPIO47,
+    GPIO48,GPIO49,GPIO50,GPIO51,GPIO52,GPIO53,GPIO54,GPIO55,
+    GPIO56,GPIO57,GPIO58,GPIO59,GPIO60,GPIO61,GPIO62,GPIO63,
+    GPIO64,GPIO65,GPIO66,GPIO67,GPIO68,GPIO69,GPIO70,GPIO71,
+    GPIO72,GPIO73,GPIO74,GPIO75,GPIO76,GPIO77,GPIO78,GPIO79,
+    GPIO80,GPIO81,GPIO82,GPIO83,GPIO84,GPIO85,GPIO86,GPIO87,
+    GPIO88,GPIO89,GPIO90,GPIO91,GPIO92,GPIO93,GPIO94,GPIO95,
+    GPIO96,GPIO97,GPIO98,GPIO99,GPIO100,GPIO101,GPIO102,GPIO103,
+    GPIO104,GPIO105,GPIO106,GPIO107,GPIO108,GPIO109,GPIO110,GPIO111,
+    GPIO112,GPIO113,GPIO114,GPIO115,GPIO116,GPIO117,GPIO118,GPIO119,
+    GPIO120,GPIO121,GPIO122,GPIO123,GPIO124,GPIO125,GPIO126,GPIO127,
+    GPIO128,GPIO129,GPIO130,GPIO131,GPIO132,GPIO133,GPIO134,GPIO135,
+    GPIO136,GPIO137,GPIO138,GPIO139,GPIO140,GPIO141,GPIO142,GPIO143,
+    GPIO144,GPIO145,GPIO146,GPIO147,GPIO148,GPIO149,GPIO150,GPIO151,
+    GPIO152,GPIO153,GPIO154,GPIO155,GPIO156,GPIO157,GPIO158,GPIO159,
+    GPIO160,GPIO161,GPIO162,GPIO163,GPIO164,GPIO165,GPIO166,GPIO167,
+    GPIO168,GPIO169,GPIO170,GPIO171,GPIO172,GPIO173,GPIO174,GPIO175,
+    GPIO176,GPIO177,GPIO178,GPIO179,GPIO180,GPIO181,GPIO182,GPIO183,
+    GPIO184,GPIO185,GPIO186,GPIO187,GPIO188,GPIO189,GPIO190,GPIO191
+};
+
+static unsigned int dma_irq_mask = 0;
+static unsigned char mdma_irq_mask = 0;
+static unsigned char bdma_irq_mask = 0;
+static unsigned int gpio_irq_mask[6] = {0};
+
+void system_enable_irq(unsigned int irq)
+{
+    register unsigned int t;
+    if ((irq >= IRQ_GPIO_0) && (irq <= IRQ_GPIO_0 + NUM_GPIO))
+    {
+        __gpio_unmask_irq(irq - IRQ_GPIO_0);
+        t = (irq - IRQ_GPIO_0) >> 5;
+        gpio_irq_mask[t] |= (1 << ((irq - IRQ_GPIO_0) & 0x1f));
+        __intc_unmask_irq(IRQ_GPIO0 - t);
+    }
+    else if ((irq >= IRQ_DMA_0) && (irq <= IRQ_DMA_0 + NUM_DMA))
+    {
+        __dmac_channel_enable_irq(irq - IRQ_DMA_0);
+        t = (irq - IRQ_DMA_0) / HALF_DMA_NUM;
+        dma_irq_mask |= (1 << (irq - IRQ_DMA_0));
+        __intc_unmask_irq(IRQ_DMAC0 - t);
+    }
+    else if ((irq >= IRQ_MDMA_0) && (irq <= IRQ_MDMA_0 + NUM_MDMA))
+    {
+        __mdmac_channel_enable_irq(irq - IRQ_MDMA_0);
+        mdma_irq_mask |= (1 << (irq - IRQ_MDMA_0));
+        __intc_unmask_irq(IRQ_MDMA);
+    }
+    else if ((irq >= IRQ_BDMA_0) && (irq <= IRQ_BDMA_0 + NUM_BDMA))
+    {
+        __bdmac_channel_enable_irq(irq - IRQ_BDMA_0);
+        bdma_irq_mask |= (1 << (irq - IRQ_BDMA_0));
+        __intc_unmask_irq(IRQ_BDMA);
+    }
+    else if (irq < IRQ_INTC_MAX)
+        __intc_unmask_irq(irq);
+}
+
+static void dis_irq(unsigned int irq)
+{
+    register unsigned int t;
+    if ((irq >= IRQ_GPIO_0) && (irq <= IRQ_GPIO_0 + NUM_GPIO))
+    {
+        __gpio_mask_irq(irq - IRQ_GPIO_0);
+        t = (irq - IRQ_GPIO_0) >> 5;
+        gpio_irq_mask[t] &= ~(1 << ((irq - IRQ_GPIO_0) & 0x1f));
+        if (!gpio_irq_mask[t])
+            __intc_mask_irq(IRQ_GPIO0 - t);
+    }
+    else if ((irq >= IRQ_DMA_0) && (irq < IRQ_DMA_0 + NUM_DMA))
+    {
+        __dmac_channel_disable_irq(irq - IRQ_DMA_0);
+        dma_irq_mask &= ~(1 << (irq - IRQ_DMA_0));
+        if (!(dma_irq_mask & 0x003F))
+            __intc_mask_irq(IRQ_DMAC0);
+        if (!(dma_irq_mask & 0x0FC0))
+            __intc_mask_irq(IRQ_DMAC1);
+    }
+    else if ((irq >= IRQ_MDMA_0) && (irq < IRQ_MDMA_0 + NUM_MDMA))
+    {
+        __mdmac_channel_disable_irq(irq - IRQ_MDMA_0);
+        mdma_irq_mask &= ~(1 << (irq - IRQ_MDMA_0));
+        if (!mdma_irq_mask)
+            __intc_mask_irq(IRQ_MDMA);
+    }
+    else if ((irq >= IRQ_BDMA_0) && (irq < IRQ_BDMA_0 + NUM_BDMA))
+    {
+        __bdmac_channel_disable_irq(irq - IRQ_BDMA_0);
+        bdma_irq_mask &= ~(1 << (irq - IRQ_BDMA_0));
+        if (!bdma_irq_mask)
+            __intc_mask_irq(IRQ_BDMA);
+    }
+    else if (irq < IRQ_INTC_MAX)
+        __intc_mask_irq(irq);
+}
+
+static void ack_irq(unsigned int irq)
+{
+    if ((irq >= IRQ_GPIO_0) && (irq <= IRQ_GPIO_0 + NUM_GPIO))
+    {
+        __gpio_ack_irq(irq - IRQ_GPIO_0);
+    }
+}
+
+static int get_irq_number(void)
+{
+    static unsigned long ipl0, ipl1;
+    register int irq0, irq1;
+
+    ipl0 |= REG_INTC_ICPR(0);
+    ipl1 |= REG_INTC_ICPR(1);
+
+    if (!(ipl0 || ipl1))
+        return -1;
+
+    __asm__ __volatile__("negu  $8, %0        \n"
+                         "and   $8, %0, $8    \n"
+                         "clz   %0, %1        \n"
+                         "li    $8, 31        \n"
+                         "subu  %0, $8, %0    \n"
+                         : "=r" (irq0)
+                         : "r" (ipl0)
+                         : "t0"
+                        );
+
+    __asm__ __volatile__("negu  $8, %0        \n"
+                         "and   $8, %0, $8    \n"
+                         "clz   %0, %1        \n"
+                         "li    $8, 31        \n"
+                         "subu  %0, $8, %0    \n"
+                         : "=r" (irq1)
+                         : "r" (ipl1)
+                         : "t0"
+                        );
+
+    if (UNLIKELY(irq0 < 0) && UNLIKELY(irq1 < 0))
+        return -1;
+
+    if (!(ipl0 & 3)) {
+        if (ipl0) {
+            irq = irq0;
+            ipl0 &= ~(1<<irq0);
+        } else {
+            irq = irq1 + 32;
+            ipl1 &= ~(1<<irq1);
+        }
+    } else  {
+        if (ipl0 & 2) {
+            irq = 1;
+            ipl0 &= ~(1<<irq);
+        } else {
+            irq = 0;
+            ipl0 &= ~(1<<irq);
+        }
+    }
+
+    switch (irq)
+    {
+        case IRQ_GPIO0:
+        case IRQ_GPIO1:
+        case IRQ_GPIO2:
+        case IRQ_GPIO3:
+        case IRQ_GPIO4:
+        case IRQ_GPIO5:
+            irq = __gpio_get_irq() + IRQ_GPIO_0;
+            break;
+        case IRQ_DMAC0:
+        case IRQ_DMAC1:
+            irq = __dmac_get_irq() + IRQ_DMA_0;
+            break;
+        case IRQ_MDMA:
+            irq = __mdmac_get_irq() + IRQ_MDMA_0;
+            break;
+        case IRQ_BDMA:
+            irq = __bdmac_get_irq() + IRQ_BDMA_0;
+            break;
+    }
+
+    return irq;
+}
+
+void intr_handler(void)
+{
+    register int irq = get_irq_number();
+    if(UNLIKELY(irq < 0))
+        return;
+    
+    ack_irq(irq);
+    if(LIKELY(irq >= 0))
+        irqvector[irq]();
+}
+
+#define EXC(x,y) case (x): return (y);
+static char* parse_exception(unsigned int cause)
+{
+    switch(cause & M_CauseExcCode)
+    {
+        EXC(EXC_INT, "Interrupt");
+        EXC(EXC_MOD, "TLB Modified");
+        EXC(EXC_TLBL, "TLB Exception (Load or Ifetch)");
+        EXC(EXC_ADEL, "Address Error (Load or Ifetch)");
+        EXC(EXC_ADES, "Address Error (Store)");
+        EXC(EXC_TLBS, "TLB Exception (Store)");
+        EXC(EXC_IBE, "Instruction Bus Error");
+        EXC(EXC_DBE, "Data Bus Error");
+        EXC(EXC_SYS, "Syscall");
+        EXC(EXC_BP, "Breakpoint");
+        EXC(EXC_RI, "Reserved Instruction");
+        EXC(EXC_CPU, "Coprocessor Unusable");
+        EXC(EXC_OV, "Overflow");
+        EXC(EXC_TR, "Trap Instruction");
+        EXC(EXC_FPE, "Floating Point Exception");
+        EXC(EXC_C2E, "COP2 Exception");
+        EXC(EXC_MDMX, "MDMX Exception");
+        EXC(EXC_WATCH, "Watch Exception");
+        EXC(EXC_MCHECK, "Machine Check Exception");
+        EXC(EXC_CacheErr, "Cache error caused re-entry to Debug Mode");
+        default:
+            return NULL;
+    }
+}
+
+void exception_handler(void* stack_ptr, unsigned int cause, unsigned int epc)
+{
+    panicf("Exception occurred: %s [0x%08x] at 0x%08x (stack at 0x%08x)", parse_exception(cause), read_c0_badvaddr(), epc, (unsigned int)stack_ptr);
+}
+
+void tlb_refill_handler(void)
+{
+    panicf("TLB refill handler at 0x%08lx! [0x%x]", read_c0_epc(), read_c0_badvaddr());
+}
+
+void udelay(unsigned int usec)
+{
+    unsigned int i = usec * (__cpm_get_cclk() / 2000000);
+    __asm__ __volatile__ (
+                          ".set noreorder    \n"
+                          "1:                \n"
+                          "bne  %0, $0, 1b   \n"
+                          "addi %0, %0, -1   \n"
+                          ".set reorder      \n"
+                          : "=r" (i)
+                          : "0" (i)
+                          );
+}
+
+void mdelay(unsigned int msec)
+{
+    unsigned int i;
+    for(i=0; i<msec; i++)
+        udelay(1000);
+}
+
+#define MHZ (1000 * 1000)
+static inline unsigned int pll_calc_m_n_od(unsigned int speed, unsigned int xtal)
+{
+        const int pll_m_max = 0x7f, pll_m_min = 4;
+        const int pll_n_max = 0x0f, pll_n_min = 2;
+
+        int od[] = {1, 2, 4, 8};
+
+        unsigned int plcr_m_n_od = 0;
+        unsigned int distance;
+        unsigned int tmp, raw;
+
+        int i, j, k;
+        int m, n;
+
+        distance = 0xFFFFFFFF;
+
+        for (i = 0; i < (int)sizeof (od) / (int)sizeof(int); i++) {
+                /* Limit: 500MHZ <= CLK_OUT * OD <= 1500MHZ */
+                if ((speed * od[i]) < 500 * MHZ || (speed * od[i]) > 1500 * MHZ)
+                        continue;
+                for (k = pll_n_min; k <= pll_n_max; k++) {
+                        n = k;
+                        
+                        /* Limit: 1MHZ <= XIN/N <= 50MHZ */
+                        if ((xtal / n) < (1 * MHZ))
+                                break;
+                        if ((xtal / n) > (15 * MHZ))
+                                continue;
+
+                        for (j = pll_m_min; j <= pll_m_max; j++) {
+                                m = j*2;
+
+                                raw = xtal * m / n;
+                                tmp = raw / od[i];
+
+                                tmp = (tmp > speed) ? (tmp - speed) : (speed - tmp);
+
+                                if (tmp < distance) {
+                                        distance = tmp;
+                                        
+                                        plcr_m_n_od = (j << CPPCR0_PLLM_LSB) 
+                                                | (k << CPPCR0_PLLN_LSB)
+                                                | (i << CPPCR0_PLLOD_LSB);
+
+                                        if (!distance) {        /* Match. */
+                                                return plcr_m_n_od;
+                                        }
+                                }
+                        }
+                }
+        }
+        return plcr_m_n_od;
+}
+
+/* PLL output clock = EXTAL * NF / (NR * NO)
+ *
+ * NF = FD + 2, NR = RD + 2
+ * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
+ */
+static void pll0_init(unsigned int freq)
+{
+    register unsigned int cfcr, plcr1;
+    int n2FR[9] = {
+        0, 0, 1, 2, 3, 0, 4, 0, 5
+    };
+
+    /** divisors,
+     *  for jz4760b,I:H:H2:P:M:S.
+     *  DIV should be one of [1, 2, 3, 4, 6, 8]
+     */
+    int div[6] = {1, 4, 4, 4, 4, 4};
+    int usbdiv;
+
+    /* set ahb **/
+    REG32(HARB0_BASE) = 0x00300000;
+    REG32(0xb3070048) = 0x00000000;
+    REG32(HARB2_BASE) = 0x00FFFFFF;
+        
+    cfcr = CPCCR_PCS |
+        (n2FR[div[0]] << CPCCR_CDIV_LSB) |
+        (n2FR[div[1]] << CPCCR_HDIV_LSB) |
+        (n2FR[div[2]] << CPCCR_H2DIV_LSB) |
+        (n2FR[div[3]] << CPCCR_PDIV_LSB) |
+        (n2FR[div[4]] << CPCCR_MDIV_LSB) |
+        (n2FR[div[5]] << CPCCR_SDIV_LSB);
+
+    // write REG_DDRC_CTRL 8 times to clear ddr fifo
+    REG_DDRC_CTRL = 0;
+    REG_DDRC_CTRL = 0;
+    REG_DDRC_CTRL = 0;
+    REG_DDRC_CTRL = 0;
+    REG_DDRC_CTRL = 0;
+    REG_DDRC_CTRL = 0;
+    REG_DDRC_CTRL = 0;
+    REG_DDRC_CTRL = 0;
+
+    if (CFG_EXTAL > 16000000)
+        cfcr |= CPCCR_ECS;
+    else
+        cfcr &= ~CPCCR_ECS;
+
+    cfcr &= ~CPCCR_MEM; /* mddr */
+    cfcr |= CPCCR_CE;
+
+    plcr1 = pll_calc_m_n_od(freq, CFG_EXTAL);
+    plcr1 |= (0x20 << CPPCR0_PLLST_LSB)  /* PLL stable time */
+             | CPPCR0_PLLEN;             /* enable PLL */
+        
+    /*
+     * Init USB Host clock, pllout2 must be n*48MHz
+     * For JZ4760b UHC - River.
+     */
+    usbdiv = (cfcr & CPCCR_PCS) ? CPU_FREQ : (CPU_FREQ / 2);
+    REG_CPM_UHCCDR = usbdiv / 48000000 - 1;
+
+    /* init PLL */
+    REG_CPM_CPCCR = cfcr;
+    REG_CPM_CPPCR0 = plcr1;
+
+    __cpm_enable_pll_change();
+
+    /*wait for pll output stable ...*/
+    while (!(REG_CPM_CPPCR0 & CPPCR0_PLLS));
+
+    REG_CPM_CPPCR0 &= ~CPPCR0_LOCK;
+}
+
+void pll1_init(unsigned int freq)
+{
+    register unsigned int plcr2;
+
+    /* set CPM_CPCCR_MEM only for ddr1 or ddr2 */
+    plcr2 = pll_calc_m_n_od(freq, CFG_EXTAL)
+            | CPPCR1_PLL1EN;            /* enable PLL1 */
+
+    /* init PLL_1 , source clock is extal clock */
+    REG_CPM_CPPCR1 = plcr2;
+
+    __cpm_enable_pll_change();
+
+    /*wait for pll_1 output stable ...*/
+    while (!(REG_CPM_CPPCR1 & CPPCR1_PLL1S));
+
+    REG_CPM_CPPCR1 &= ~CPPCR1_LOCK;
+}
+
+static void serial_setbrg(void)
+{
+    volatile u8 *uart_lcr = (volatile u8 *)(CFG_UART_BASE + OFF_LCR);
+    volatile u8 *uart_dlhr = (volatile u8 *)(CFG_UART_BASE + OFF_DLHR);
+    volatile u8 *uart_dllr = (volatile u8 *)(CFG_UART_BASE + OFF_DLLR);
+    volatile u8 *uart_umr = (volatile u8 *)(CFG_UART_BASE + OFF_UMR);
+    volatile u8 *uart_uacr = (volatile u8 *)(CFG_UART_BASE + OFF_UACR);
+    u16 baud_div, tmp;
+
+    *uart_umr = 16;
+    *uart_uacr = 0;
+    baud_div = 13; /* 57600 */
+
+    tmp = *uart_lcr;
+    tmp |= UARTLCR_DLAB;
+    *uart_lcr = tmp;
+
+    *uart_dlhr = (baud_div >> 8) & 0xff;
+    *uart_dllr = baud_div & 0xff;
+
+    tmp &= ~UARTLCR_DLAB;
+    *uart_lcr = tmp;
+}
+
+int serial_preinit(void)
+{
+    volatile u8 *uart_fcr = (volatile u8 *)(CFG_UART_BASE + OFF_FCR);
+    volatile u8 *uart_lcr = (volatile u8 *)(CFG_UART_BASE + OFF_LCR);
+    volatile u8 *uart_ier = (volatile u8 *)(CFG_UART_BASE + OFF_IER);
+    volatile u8 *uart_sircr = (volatile u8 *)(CFG_UART_BASE + OFF_SIRCR);
+
+    __gpio_as_uart1();
+    __cpm_start_uart1();
+
+    /* Disable port interrupts while changing hardware */
+    *uart_ier = 0;
+
+    /* Disable UART unit function */
+    *uart_fcr = ~UARTFCR_UUE;
+
+    /* Set both receiver and transmitter in UART mode (not SIR) */
+    *uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE);
+
+    /* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
+    *uart_lcr = UARTLCR_WLEN_8 | UARTLCR_STOP1;
+        
+    /* Set baud rate */
+    serial_setbrg();
+        
+    /* Enable UART unit, enable and clear FIFO */
+    *uart_fcr = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
+
+    return 0;
+}
+
+void usb_preinit(void)
+{
+    /* Clear ECS bit of CPCCR, 0:clock source is EXCLK, 1:clock source is EXCLK/2 */
+    REG_CPM_CPCCR &= ~CPCCR_ECS;
+
+    /* Clear all bits of USBCDR, 0:OTG clock source is pin EXCLK, PLL0 output, divider = 1:12MHZ */
+    REG_CPM_USBCDR = 0;
+
+    /* Set CE bit of CPCCR, it means frequence is changed immediately */
+    REG_CPM_CPCCR |= CPCCR_CE;
+
+    udelay(3);
+
+    /* Clear OTG bit of CLKGR0, 0:device can be accessed */
+    REG_CPM_CLKGR0 &= ~CLKGR0_OTG;
+
+    /* fil */
+    REG_CPM_USBVBFIL = 0x80;
+
+    /* rdt */
+    REG_CPM_USBRDT = (600 * (CPU_FREQ / 1000000)) / 1000;
+
+    /* rdt - filload_en */
+    REG_CPM_USBRDT |= (1 << 25);
+
+    /* TXRISETUNE & TXVREFTUNE. */
+    REG_CPM_USBPCR &= ~0x3f;
+    REG_CPM_USBPCR |= 0x35;
+
+    /* enable tx pre-emphasis */
+    REG_CPM_USBPCR |= 0x40;
+
+    /* most DC leave of tx */
+    REG_CPM_USBPCR |= 0xf;
+
+    /* Device Mode. */
+    REG_CPM_USBPCR &= ~(1 << 31);
+    REG_CPM_USBPCR |= USBPCR_VBUSVLDEXT;
+
+    /* phy reset */
+    REG_CPM_USBPCR |= USBPCR_POR;
+    udelay(30);
+    REG_CPM_USBPCR &= ~USBPCR_POR;
+    udelay(300);
+
+    /* Enable the USB PHY */
+    REG_CPM_OPCR |= OPCR_OTGPHY_ENABLE;
+
+    /* Wait PHY Clock Stable. */
+    udelay(300);
+}
+
+void dma_preinit(void)
+{
+    __cpm_start_mdma();
+    __cpm_start_dmac();
+
+    REG_MDMAC_DMACKES = 0x1;
+
+    REG_DMAC_DMACR(DMA_AIC_TX_CHANNEL) = DMAC_DMACR_DMAE | DMAC_DMACR_FAIC;
+    REG_DMAC_DMACR(DMA_SD_RX_CHANNEL) = DMAC_DMACR_DMAE | DMAC_DMACR_FMSC;
+    REG_DMAC_DMACR(DMA_SD_TX_CHANNEL) = DMAC_DMACR_DMAE | DMAC_DMACR_FMSC;
+}
+
+/* Gets called *before* main */
+void ICODE_ATTR system_main(void)
+{
+    int i;
+       
+    __dcache_writeback_all();
+    __icache_invalidate_all();
+    
+    write_c0_status(1 << 28 | 1 << 10 ); /* Enable CP | Mask interrupt 2 */
+
+    /* Disable all interrupts */
+    for(i=0; i<IRQ_INTC_MAX; i++)
+        dis_irq(i);
+
+    mmu_init();
+
+    pll0_init(CPU_FREQ);
+    pll1_init(CPU_FREQ);
+
+    serial_preinit();
+    usb_preinit();
+    dma_preinit();
+
+    /* Enable interrupts at core level */
+    enable_interrupt();
+}
+
+void system_reboot(void)
+{
+    REG_WDT_WCSR = WCSR_PRESCALE4 | WCSR_CLKIN_EXT;
+    REG_WDT_WCNT = 0;
+    REG_WDT_WDR = JZ_EXTAL/1000; /* reset after 4ms */
+    REG_TCU_TSCR = TSCR_WDT;     /* enable wdt clock */
+    REG_WDT_WCER = WCER_TCEN;    /* wdt start */
+    while (1);
+}
+
+void system_exception_wait(void)
+{
+    /* check for power button without including any .h file */
+    while(1)
+    {
+        if( (~REG_GPIO_PXPIN(0)) & (1 << 30) )
+            return;
+        asm volatile("nop");
+    }
+}
+
+void power_off(void)
+{
+    REG_CPM_RSR = 0x0;
+        
+    /* Set minimum wakeup_n pin low-level assertion time for wakeup: 100ms */
+    rtc_write_reg(RTC_HWFCR, HWFCR_WAIT_TIME(1000));
+
+    /* Set reset pin low-level assertion time after wakeup: must  > 60ms */
+    rtc_write_reg(RTC_HRCR, HRCR_WAIT_TIME(60));
+
+    /* clear wakeup status register */
+    rtc_write_reg(RTC_HWRSR, 0x0);
+
+    /* set wake up valid level as low */
+    rtc_write_reg(RTC_HWCR,0x8);
+
+    /* Put CPU to hibernate mode */
+    rtc_write_reg(RTC_HCR, HCR_PD);
+
+    while (1);
+}
+
+void system_init(void)
+{
+}
+
+int system_memory_guard(int newmode)
+{
+    (void)newmode;
+    return 0;
+}
+
+#ifdef HAVE_ADJUSTABLE_CPU_FREQ
+void set_cpu_frequency(long frequency)
+{
+    serial_putsf("set_cpu_frequency: %d\n", frequency);
+}
+#endif
diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h
index 1c2e7d7173..9720d3a80c 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-target.h
+++ b/firmware/target/mips/ingenic_jz47xx/system-target.h
@@ -25,7 +25,7 @@
 #include <inttypes.h>
 
 #include "config.h"
-#include "jz4740.h"
+#include "cpu.h"
 #include "mipsregs.h"
 
 #define CACHE_SIZE       16*1024
@@ -35,6 +35,8 @@
 /* no optimized byteswap functions implemented for mips, yet */
 #define NEED_GENERIC_BYTESWAPS
 
+#define STORAGE_WANTS_ALIGN
+
 /* This one returns the old status */
 static inline int set_interrupt_status(int status, int mask)
 {
@@ -86,10 +88,18 @@ void mdelay(unsigned int msec);
 void dma_enable(void);
 void dma_disable(void);
 
+#if CONFIG_CPU == JZ4732
 #define DMA_AIC_TX_CHANNEL 0
 #define DMA_NAND_CHANNEL   1
 #define DMA_USB_CHANNEL    2
 #define DMA_LCD_CHANNEL    3
+#elif CONFIG_CPU == JZ4760B
+#define DMA_AIC_TX_CHANNEL 0
+#define DMA_NAND_CHANNEL   1
+#define DMA_USB_CHANNEL    2
+#define DMA_SD_RX_CHANNEL  3
+#define DMA_SD_TX_CHANNEL  4
+#endif
 
 #define XDMA_CALLBACK(n) DMA ## n
 #define DMA_CALLBACK(n)  XDMA_CALLBACK(n)
@@ -103,7 +113,7 @@ void dma_disable(void);
  */
 static inline void core_sleep(void)
 {
-#if CONFIG_CPU == JZ4732
+#if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B
     __cpm_idle_mode();
 #endif
     asm volatile(".set   mips32r2           \n"
diff --git a/firmware/target/mips/ingenic_jz47xx/timer-jz4760.c b/firmware/target/mips/ingenic_jz47xx/timer-jz4760.c
new file mode 100644
index 0000000000..0f16825b34
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/timer-jz4760.c
@@ -0,0 +1,101 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+ 
+#include "config.h"
+#include "cpu.h"
+#include "system.h"
+#include "timer.h"
+
+/* Interrupt handler */
+void TCU1(void)
+{
+    __tcu_clear_full_match_flag(5);
+
+    if (pfn_timer != NULL)
+        pfn_timer();
+}
+
+bool timer_set(long cycles, bool start)
+{
+    unsigned int divider = cycles, prescaler_bit = 0, prescaler = 1, old_irq;
+
+    if(cycles < 1)
+        return false;
+
+    if(start && pfn_unregister != NULL)
+    {
+        pfn_unregister();
+        pfn_unregister = NULL;
+    }
+
+    /* Increase prescale values starting from 0 to make the cycle count fit */
+    while(divider > 65535 && prescaler <= 1024)
+    {
+        prescaler <<= 2; /* 1, 4, 16, 64, 256, 1024 */
+        prescaler_bit++;
+        divider = cycles / prescaler;
+    }
+
+    old_irq = disable_irq_save();
+
+    __tcu_stop_counter(5);
+    if(start)
+    {
+        __tcu_disable_pwm_output(5);
+
+        __tcu_mask_half_match_irq(5); 
+        __tcu_unmask_full_match_irq(5);
+
+        /* EXTAL clock = CFG_EXTAL (12Mhz in most targets) */
+        __tcu_select_extalclk(5);
+    }
+
+    REG_TCU_TCSR(5) = (REG_TCU_TCSR(5) & ~TCSR_PRESCALE_MASK) | (prescaler_bit << TCSR_PRESCALE_LSB);
+    REG_TCU_TCNT(5) = 0;
+    REG_TCU_TDHR(5) = 0;
+    REG_TCU_TDFR(5) = divider;
+
+    __tcu_clear_full_match_flag(5);
+
+    if(start)
+    {
+        system_enable_irq(IRQ_TCU1);
+        __tcu_start_counter(5);
+    }
+
+    restore_irq(old_irq);
+
+    return true;
+}
+
+bool timer_start(void)
+{
+    __tcu_start_counter(5);
+
+    return true;
+}
+
+void timer_stop(void)
+{
+    unsigned int old_irq = disable_irq_save();
+    __tcu_stop_counter(5);
+    restore_irq(old_irq);
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/usb-jz4760.c b/firmware/target/mips/ingenic_jz47xx/usb-jz4760.c
new file mode 100644
index 0000000000..bc2158fb6f
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/usb-jz4760.c
@@ -0,0 +1,870 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+/*#define LOGF_ENABLE*/
+#include "logf.h"
+#include "system.h"
+#include "usb_ch9.h"
+#include "usb_drv.h"
+#include "usb_core.h"
+#include "cpu.h"
+#include "thread.h"
+
+#define PIN_USB_DET      (32*4+19)
+#define IRQ_USB_DET      GPIO_IRQ(PIN_USB_DET)
+#define GPIO_USB_DET     GPIO147
+
+#define PIN_USB_DRVVBUS  (32*4+10)
+#define PIN_USB_OTG_ID   (32*3+7)
+
+#define EP_BUF_LEFT(ep)  ((ep)->length - (ep)->sent)
+#define EP_PTR(ep)       ((void*)((unsigned int)(ep)->buf + (ep)->sent))
+#define EP_NUMBER(ep)    (((int)(ep) - (int)&endpoints[0])/sizeof(struct usb_endpoint))
+#define EP_NUMBER2(ep)   (EP_NUMBER((ep))/2)
+#define TOTAL_EP()       (sizeof(endpoints)/sizeof(struct usb_endpoint))
+#define EP_IS_IN(ep)     (EP_NUMBER((ep))%2)
+
+enum ep_type
+{
+    ep_control,
+    ep_bulk,
+    ep_interrupt,
+    ep_isochronous
+};
+
+struct usb_endpoint
+{
+    void *buf;
+    size_t length;
+    union
+    {
+        size_t sent;
+        size_t received;
+    };
+    bool busy;
+
+    const enum ep_type type;
+    const bool use_dma;
+
+    const long fifo_addr;
+    unsigned short fifo_size;
+
+    bool wait;
+    struct semaphore complete;
+};
+
+#define EP_INIT(_type, _fifo_addr, _fifo_size, _buf, _use_dma) \
+    { .type = (_type), .fifo_addr = (_fifo_addr), .fifo_size = (_fifo_size), \
+      .buf = (_buf), .use_dma = (_use_dma), .length = 0, .busy = false, .wait = false }
+
+static unsigned char ep0_rx_buf[64];
+static struct usb_endpoint endpoints[] =
+{
+    EP_INIT(ep_control,   USB_FIFO_EP(0),  64, NULL,        false),
+    EP_INIT(ep_control,   USB_FIFO_EP(0),  64, &ep0_rx_buf, false),
+    EP_INIT(ep_bulk,      USB_FIFO_EP(1), 512, NULL,        false),
+    EP_INIT(ep_bulk,      USB_FIFO_EP(1), 512, NULL,        false),
+    EP_INIT(ep_interrupt, USB_FIFO_EP(2),  64, NULL,        false),
+    EP_INIT(ep_interrupt, USB_FIFO_EP(2),  64, NULL,        false),
+};
+
+static inline void select_endpoint(int ep)
+{
+    REG_USB_INDEX = ep;
+}
+
+static void readFIFO(struct usb_endpoint *ep, unsigned int size)
+{
+    logf("%s(EP%d, %d)", __func__, EP_NUMBER2(ep), size);
+
+    register unsigned char *ptr = (unsigned char*)EP_PTR(ep);
+    register unsigned int *ptr32 = (unsigned int*)ptr;
+    register unsigned int s = size >> 2;
+    register unsigned int x;
+
+    if(size > 0)
+    {
+        if( ((unsigned int)ptr & 3) == 0 )
+        {
+            while(s--)
+                *ptr32++ = REG32(ep->fifo_addr);
+
+            ptr = (unsigned char*)ptr32;
+        }
+        else
+        {
+            while(s--)
+            {
+                x = REG32(ep->fifo_addr);
+                *ptr++ = x & 0xFF; x >>= 8;
+                *ptr++ = x & 0xFF; x >>= 8;
+                *ptr++ = x & 0xFF; x >>= 8;
+                *ptr++ = x;
+            }
+        }
+
+        s = size & 3;
+        while(s--)
+            *ptr++ = REG8(ep->fifo_addr);
+    }
+}
+
+static void writeFIFO(struct usb_endpoint *ep, size_t size)
+{
+    logf("%s(EP%d, %d)", __func__, EP_NUMBER2(ep), size);
+
+    register unsigned int *d32 = (unsigned int *)EP_PTR(ep);
+    register size_t s = size >> 2;
+
+    if(size > 0)
+    {
+        while (s--)
+            REG32(ep->fifo_addr) = *d32++;
+
+        if( (s = size & 3) )
+        {
+            register unsigned char *d8 = (unsigned char *)d32;
+            while (s--)
+                REG8(ep->fifo_addr) = *d8++;
+        }
+    }
+}
+
+static void flushFIFO(struct usb_endpoint *ep)
+{
+    logf("%s(%d)", __func__, EP_NUMBER(ep));
+
+    switch (ep->type)
+    {
+        case ep_control:
+        break;
+
+        case ep_bulk:
+        case ep_interrupt:
+        case ep_isochronous:
+            if(EP_IS_IN(ep))
+                REG_USB_INCSR |= (USB_INCSR_FF | USB_INCSR_CDT);
+            else
+                REG_USB_OUTCSR |= (USB_OUTCSR_FF | USB_OUTCSR_CDT);
+        break;
+    }
+}
+
+static inline void ep_transfer_completed(struct usb_endpoint* ep)
+{
+    ep->sent   = 0;
+    ep->length = 0;
+    ep->buf    = NULL;
+    ep->busy   = false;
+    if(ep->wait)
+        semaphore_release(&ep->complete);
+}
+
+static void EP0_send(void)
+{
+    struct usb_endpoint* ep = &endpoints[0];
+    unsigned int length;
+    unsigned char csr0;
+
+    select_endpoint(0);
+    csr0 = REG_USB_CSR0;
+
+    if(ep->sent == 0)
+        length = MIN(ep->length, ep->fifo_size);
+    else
+        length = MIN(EP_BUF_LEFT(ep), ep->fifo_size);
+
+    writeFIFO(ep, length);
+    ep->sent += length;
+
+    if(ep->sent >= ep->length)
+    {
+        REG_USB_CSR0 = (csr0 | USB_CSR0_INPKTRDY | USB_CSR0_DATAEND); /* Set data end! */
+        usb_core_transfer_complete(0, USB_DIR_IN, 0, ep->sent);
+        ep_transfer_completed(ep);
+    }
+    else
+        REG_USB_CSR0 = (csr0 | USB_CSR0_INPKTRDY);
+}
+
+static void EP0_handler(void)
+{
+    logf("%s()", __func__);
+
+    unsigned char csr0;
+    struct usb_endpoint *ep_send = &endpoints[0];
+    struct usb_endpoint *ep_recv = &endpoints[1];
+
+    /* Read CSR0 */
+    select_endpoint(0);
+    csr0 = REG_USB_CSR0;
+
+    /* Check for SentStall:
+        This bit is set when a STALL handshake is transmitted. The CPU should clear this bit.
+     */
+    if(csr0 & USB_CSR0_SENTSTALL)
+    {
+        REG_USB_CSR0 = csr0 & ~USB_CSR0_SENTSTALL;
+        return;
+    }
+
+    /* Check for SetupEnd:
+        This bit will be set when a control transaction ends before the DataEnd bit has been set.
+        An interrupt will be generated and the FIFO flushed at this time.
+        The bit is cleared by the CPU writing a 1 to the ServicedSetupEnd bit.
+     */
+    if(csr0 & USB_CSR0_SETUPEND)
+    {
+        REG_USB_CSR0 = csr0 | USB_CSR0_SVDSETUPEND;
+        return;
+    }
+
+    /* Call relevant routines for endpoint 0 state */
+    if(ep_send->busy)
+        EP0_send();
+    else if(csr0 & USB_CSR0_OUTPKTRDY)   /* There is a packet in the fifo */
+    {
+        readFIFO(ep_recv, REG_USB_COUNT0);
+        REG_USB_CSR0 = csr0 | USB_CSR0_SVDOUTPKTRDY; /* clear OUTPKTRDY bit */
+        usb_core_control_request((struct usb_ctrlrequest*)ep_recv->buf);
+    }
+}
+
+static void EPIN_handler(unsigned int endpoint)
+{
+    struct usb_endpoint* ep = &endpoints[endpoint*2];
+    unsigned int length, csr;
+
+    select_endpoint(endpoint);
+    csr = REG_USB_INCSR;
+    logf("%s(%d): 0x%x", __func__, endpoint, csr);
+
+    if(!ep->busy)
+    {
+        logf("Entered EPIN handler without work!");
+        return;
+    }
+
+    if(csr & USB_INCSR_SENTSTALL)
+    {
+        REG_USB_INCSR = csr & ~USB_INCSR_SENTSTALL;
+        return;
+    }
+
+    if(ep->use_dma)
+        return;
+
+    if(csr & USB_INCSR_FFNOTEMPT)
+    {
+        logf("FIFO is not empty! 0x%x", csr);
+        return;
+    }
+
+    logf("EP%d: %d -> %d", endpoint, ep->sent, ep->length);
+    
+    if(ep->sent == 0)
+        length = MIN(ep->length, ep->fifo_size);
+    else
+        length = MIN(EP_BUF_LEFT(ep), ep->fifo_size);
+
+    writeFIFO(ep, length);
+    REG_USB_INCSR = csr | USB_INCSR_INPKTRDY;
+    ep->sent += length;
+
+    if(ep->sent >= ep->length)
+    {
+        usb_core_transfer_complete(endpoint, USB_DIR_IN, 0, ep->sent);
+        ep_transfer_completed(ep);
+        logf("sent complete");
+    }
+}
+
+static void EPOUT_handler(unsigned int endpoint)
+{
+    struct usb_endpoint* ep = &endpoints[endpoint*2+1];
+    unsigned int size, csr;
+
+    if(!ep->busy)
+    {
+        logf("Entered EPOUT handler without work!");
+        return;
+    }
+
+    select_endpoint(endpoint);
+    while((csr = REG_USB_OUTCSR) & (USB_OUTCSR_SENTSTALL|USB_OUTCSR_OUTPKTRDY))
+    {
+        logf("%s(%d): 0x%x", __func__, endpoint, csr);
+        if(csr & USB_OUTCSR_SENTSTALL)
+        {
+            logf("stall sent, flushing fifo..");
+            flushFIFO(ep);
+            REG_USB_OUTCSR = csr & ~USB_OUTCSR_SENTSTALL;
+            return;
+        }
+
+        if(ep->use_dma)
+            return;
+
+        if(csr & USB_OUTCSR_OUTPKTRDY) /* There is a packet in the fifo */
+        {
+            size = REG_USB_OUTCOUNT;
+
+            readFIFO(ep, size);
+            ep->received += size;
+
+            /*if(csr & USB_OUTCSR_FFFULL)
+                csr &= ~USB_OUTCSR_FFFULL;*/
+
+            REG_USB_OUTCSR = csr & ~USB_OUTCSR_OUTPKTRDY;
+
+            logf("received: %d max length: %d", ep->received, ep->length);
+
+            if(size < ep->fifo_size || ep->received >= ep->length)
+            {
+                usb_core_transfer_complete(endpoint, USB_DIR_OUT, 0, ep->received);
+                ep_transfer_completed(ep);
+                logf("receive transfer_complete");
+            }
+        }
+    }
+}
+
+static void EPDMA_handler(int number)
+{
+    int endpoint = -1;
+    unsigned int size = 0;
+
+    if(number == USB_INTR_DMA_BULKIN)
+        endpoint = (REG_USB_CNTL(0) >> 4) & 0xF;
+    else if(number == USB_INTR_DMA_BULKOUT)
+        endpoint = (REG_USB_CNTL(1) >> 4) & 0xF;
+
+    struct usb_endpoint* ep = &endpoints[endpoint];
+    logf("DMA_BULK%d %d", number, endpoint);
+
+    if(number == USB_INTR_DMA_BULKIN)
+        size = (unsigned int)ep->buf - REG_USB_ADDR(0);
+    else if(number == USB_INTR_DMA_BULKOUT)
+        size = (unsigned int)ep->buf - REG_USB_ADDR(1);
+
+    if(number == USB_INTR_DMA_BULKOUT)
+    {
+        /* Disable DMA */
+        REG_USB_CNTL(1) = 0;
+
+        __dcache_invalidate_all();
+
+        select_endpoint(endpoint);
+        /* Read out last packet manually */
+        unsigned int lpack_size = REG_USB_OUTCOUNT;
+        if(lpack_size > 0)
+        {
+            ep->buf += ep->length - lpack_size;
+            readFIFO(ep, lpack_size);
+            REG_USB_OUTCSR &= ~USB_OUTCSR_OUTPKTRDY;
+        }
+    }
+    else if(number == USB_INTR_DMA_BULKIN && size % ep->fifo_size)
+    {
+        /* If the last packet is less than MAXP, set INPKTRDY manually */
+        REG_USB_INCSR |= USB_INCSR_INPKTRDY;
+    }
+
+    usb_core_transfer_complete(endpoint, EP_IS_IN(ep) ? USB_DIR_IN : USB_DIR_OUT,
+                               0, ep->length);
+    ep_transfer_completed(ep);
+}
+
+static void setup_endpoint(struct usb_endpoint *ep)
+{
+    int csr, csrh;
+
+    select_endpoint(EP_NUMBER2(ep));
+
+    ep->busy = false;
+    ep->wait = false;
+    ep->sent = 0;
+    ep->length = 0;
+
+    if(ep->type == ep_bulk)
+    {
+        if(REG_USB_POWER & USB_POWER_HSMODE)
+            ep->fifo_size = 512;
+        else
+            ep->fifo_size = 64;
+    }
+
+    if(EP_IS_IN(ep))
+    {
+        csr = (USB_INCSR_FF | USB_INCSR_CDT);
+        csrh = USB_INCSRH_MODE;
+
+        if(ep->use_dma)
+            csrh |= (USB_INCSRH_DMAREQENAB | USB_INCSRH_AUTOSET | USB_INCSRH_DMAREQMODE);
+
+        if(ep->type == ep_interrupt)
+            csrh |= USB_INCSRH_FRCDATATOG;
+
+        REG_USB_INMAXP   = ep->fifo_size;
+        REG_USB_INCSR    = csr;
+        REG_USB_INCSRH   = csrh;
+        REG_USB_INTRINE |= USB_INTR_EP(EP_NUMBER2(ep));
+    }
+    else
+    {
+        csr = (USB_OUTCSR_FF | USB_OUTCSR_CDT);
+        csrh = 0;
+
+        if(ep->type == ep_interrupt)
+            csrh |= USB_OUTCSRH_DNYT;
+
+        if(ep->use_dma)
+            csrh |= (USB_OUTCSRH_DMAREQENAB | USB_OUTCSRH_AUTOCLR | USB_OUTCSRH_DMAREQMODE);
+
+        REG_USB_OUTMAXP   = ep->fifo_size;
+        REG_USB_OUTCSR    = csr;
+        REG_USB_OUTCSRH   = csrh;
+        REG_USB_INTROUTE |= USB_INTR_EP(EP_NUMBER2(ep));
+    }
+}
+
+static void udc_reset(void)
+{
+    /* From the datasheet:
+
+       When a reset condition is detected on the USB, the controller performs the following actions:
+           * Sets FAddr to 0.
+           * Sets Index to 0.
+           * Flushes all endpoint FIFOs.
+           * Clears all control/status registers.
+           * Enables all endpoint interrupts.
+           * Generates a Reset interrupt.
+    */
+
+    logf("%s()", __func__);
+
+    unsigned int i;
+
+    REG_USB_FADDR = 0;
+    REG_USB_INDEX = 0;
+
+    /* Disable interrupts */
+    REG_USB_INTRINE  = 0;
+    REG_USB_INTROUTE = 0;
+    REG_USB_INTRUSBE = 0;
+
+    /* Disable DMA */
+    REG_USB_CNTL(0) = 0;
+    REG_USB_CNTL(1) = 0;
+
+    /* High speed, softconnect */
+    REG_USB_POWER = (USB_POWER_SOFTCONN | USB_POWER_HSENAB);
+
+    /* Reset EP0 */
+    select_endpoint(0);
+    REG_USB_CSR0 = (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_SVDSETUPEND | USB_CSR0_FLUSHFIFO);
+
+    /* Reset other endpoints */
+    for(i=2; i<TOTAL_EP(); i++)
+        setup_endpoint(&endpoints[i]);
+
+    /* Enable interrupts */
+    REG_USB_INTRINE  |= USB_INTR_EP(0);
+    REG_USB_INTRUSBE |= USB_INTR_RESET;
+
+    usb_core_bus_reset();
+}
+
+/* Interrupt handler */
+void OTG(void)
+{
+    /* Read interrupt registers */
+    unsigned char    intrUSB = REG_USB_INTRUSB & 0x07; /* Mask SOF */
+    unsigned short   intrIn  = REG_USB_INTRIN;
+    unsigned short   intrOut = REG_USB_INTROUT;
+    unsigned char    intrDMA = REG_USB_INTR;
+
+    logf("%x %x %x %x", intrUSB, intrIn, intrOut, intrDMA);
+
+    /* EPIN & EPOUT are all handled in DMA */
+    if(intrIn & USB_INTR_EP(0))
+        EP0_handler();
+    if(intrIn & USB_INTR_EP(1))
+        EPIN_handler(1);
+    if(intrIn & USB_INTR_EP(2))
+        EPIN_handler(2);
+    if(intrOut & USB_INTR_EP(1))
+        EPOUT_handler(1);
+    if(intrOut & USB_INTR_EP(2))
+        EPOUT_handler(2);
+    if(intrUSB & USB_INTR_RESET)
+        udc_reset();
+    if(intrUSB & USB_INTR_SUSPEND)
+        logf("USB suspend");
+    if(intrUSB & USB_INTR_RESUME)
+        logf("USB resume");
+    if(intrDMA & USB_INTR_DMA_BULKIN)
+        EPDMA_handler(USB_INTR_DMA_BULKIN);
+    if(intrDMA & USB_INTR_DMA_BULKOUT)
+        EPDMA_handler(USB_INTR_DMA_BULKOUT);
+}
+
+bool usb_drv_stalled(int endpoint, bool in)
+{
+    endpoint &= 0x7F;
+
+    logf("%s(%d, %s)", __func__, endpoint, in?"IN":"OUT");
+
+    select_endpoint(endpoint);
+
+    if(endpoint == EP_CONTROL)
+        return (REG_USB_CSR0 & USB_CSR0_SENDSTALL) != 0;
+    else
+    {
+        if(in)
+            return (REG_USB_INCSR & USB_INCSR_SENDSTALL) != 0;
+        else
+            return (REG_USB_OUTCSR & USB_OUTCSR_SENDSTALL) != 0;
+    }
+}
+
+void usb_drv_stall(int endpoint, bool stall, bool in)
+{
+    endpoint &= 0x7F;
+
+    logf("%s(%d,%s,%s)", __func__, endpoint, stall?"Y":"N", in?"IN":"OUT");
+
+    select_endpoint(endpoint);
+
+    if(endpoint == EP_CONTROL)
+    {
+        if(stall)
+            REG_USB_CSR0 |= USB_CSR0_SENDSTALL;
+        else
+            REG_USB_CSR0 &= ~USB_CSR0_SENDSTALL;
+    }
+    else
+    {
+        if(in)
+        {
+            if(stall)
+                REG_USB_INCSR |= USB_INCSR_SENDSTALL;
+            else
+                REG_USB_INCSR = (REG_USB_INCSR & ~USB_INCSR_SENDSTALL) | USB_INCSR_CDT;
+        }
+        else
+        {
+            if(stall)
+                REG_USB_OUTCSR |= USB_OUTCSR_SENDSTALL;
+            else
+                REG_USB_OUTCSR = (REG_USB_OUTCSR & ~USB_OUTCSR_SENDSTALL) | USB_OUTCSR_CDT;
+        }
+    }
+}
+
+int usb_detect(void)
+{
+    return (__gpio_get_pin(PIN_USB_DET) == 1)
+        ? USB_INSERTED : USB_EXTRACTED;
+}
+
+void usb_init_device(void)
+{
+    __gpio_clear_pin(PIN_USB_DRVVBUS);
+    __gpio_as_output(PIN_USB_DRVVBUS);
+
+    __gpio_as_input(PIN_USB_OTG_ID);
+    __gpio_as_input(PIN_USB_DET);
+
+    __gpio_disable_pull(PIN_USB_OTG_ID);
+    __gpio_disable_pull(PIN_USB_DET);
+
+#ifdef USB_STATUS_BY_EVENT
+    __gpio_as_irq_rise_edge(PIN_USB_DET);
+    system_enable_irq(IRQ_USB_DET);
+#endif
+
+    system_enable_irq(IRQ_OTG);
+
+    for(unsigned i=0; i<TOTAL_EP(); i++)
+        semaphore_init(&endpoints[i].complete, 1, 0);
+}
+
+#ifdef USB_STATUS_BY_EVENT
+static int usb_oneshot_callback(struct timeout *tmo)
+{
+    (void)tmo;
+    int state = usb_detect();
+
+    /* This is called only if the state was stable for HZ/16 - check state
+     * and post appropriate event. */
+    usb_status_event(state);
+
+    if(state == USB_EXTRACTED)
+        __gpio_as_irq_rise_edge(PIN_USB_DET);
+    else
+        __gpio_as_irq_fall_edge(PIN_USB_DET);
+
+    return 0;
+}
+
+void GPIO_USB_DET(void)
+{
+    static struct timeout usb_oneshot;
+    timeout_register(&usb_oneshot, usb_oneshot_callback, (HZ/16), 0);
+}
+#endif
+
+void usb_enable(bool on)
+{
+    if(on)
+        usb_core_init();
+    else
+        usb_core_exit();
+}
+
+void usb_attach(void)
+{
+    usb_enable(true);
+}
+
+void usb_drv_init(void)
+{
+    logf("%s()", __func__);
+
+    /* Dis- and reconnect from USB */
+    REG_USB_POWER &= ~USB_POWER_SOFTCONN;
+    mdelay(20);
+    REG_USB_POWER |= USB_POWER_SOFTCONN;
+    mdelay(20);
+
+    udc_reset();
+}
+
+void usb_drv_exit(void)
+{
+    logf("%s()", __func__);
+
+    REG_USB_FADDR = 0;
+    REG_USB_INDEX = 0;
+
+    /* Disable interrupts */
+    REG_USB_INTRINE  = 0;
+    REG_USB_INTROUTE = 0;
+    REG_USB_INTRUSBE = 0;
+
+    /* Disable DMA */
+    REG_USB_CNTL(0) = 0;
+    REG_USB_CNTL(1) = 0;
+
+    /* Disconnect from USB */
+    REG_USB_POWER &= ~USB_POWER_SOFTCONN;
+}
+
+void usb_drv_set_address(int address)
+{
+    logf("%s(%d)", __func__, address);
+
+    REG_USB_FADDR = address;
+}
+
+static void usb_drv_send_internal(struct usb_endpoint* ep, void* ptr, int length, bool blocking)
+{
+    if(ep->type == ep_control && ptr == NULL && length == 0)
+        return; /* ACK request, handled in the ISR */
+
+    int flags = disable_irq_save();
+
+    ep->buf = ptr;
+    ep->sent = 0;
+    ep->length = length;
+    ep->busy = true;
+    if(blocking)
+        ep->wait = true;
+
+    if(ep->type == ep_control)
+    {
+        EP0_send();
+    }
+    else
+    {
+        if(ep->use_dma)
+        {
+            //dma_cache_wback_inv((unsigned long)ptr, length);
+            __dcache_writeback_all();
+            REG_USB_ADDR(0) = PHYSADDR((unsigned long)ptr);
+            REG_USB_COUNT(0) = length;
+            REG_USB_CNTL(0) = (USB_CNTL_INTR_EN | USB_CNTL_MODE_1 |
+                                 USB_CNTL_DIR_IN  | USB_CNTL_ENA |
+                                 USB_CNTL_EP(EP_NUMBER2(ep)) | USB_CNTL_BURST_16);
+        }
+        else
+            EPIN_handler(EP_NUMBER2(ep));
+    }
+
+    restore_irq(flags);
+
+    if(blocking)
+    {
+        semaphore_wait(&ep->complete, TIMEOUT_BLOCK);
+        ep->wait = false;
+    }
+}
+
+int usb_drv_send_nonblocking(int endpoint, void* ptr, int length)
+{
+    logf("%s(%d, 0x%x, %d)", __func__, endpoint, (int)ptr, length);
+
+    usb_drv_send_internal(&endpoints[(endpoint & 0x7F)*2], ptr, length, false);
+
+    return 0;
+}
+
+int usb_drv_send(int endpoint, void* ptr, int length)
+{
+    logf("%s(%d, 0x%x, %d)", __func__, endpoint, (int)ptr, length);
+
+    usb_drv_send_internal(&endpoints[(endpoint & 0x7F)*2], ptr, length, true);
+
+    return 0;
+}
+
+int usb_drv_recv(int endpoint, void* ptr, int length)
+{
+    int flags;
+    struct usb_endpoint *ep;
+    endpoint &= 0x7F;
+
+    logf("%s(%d, 0x%x, %d)", __func__, endpoint, (int)ptr, length);
+
+    if(endpoint == EP_CONTROL)
+        return 0; /* all EP0 OUT transactions are handled within the ISR */
+    else
+    {
+        flags = disable_irq_save();
+        ep = &endpoints[endpoint*2+1];
+
+        ep->buf = ptr;
+        ep->received = 0;
+        ep->length = length;
+        ep->busy = true;
+        if(ep->use_dma)
+        {
+            //dma_cache_wback_inv((unsigned long)ptr, length);
+            __dcache_writeback_all();
+            REG_USB_ADDR(1) = PHYSADDR((unsigned long)ptr);
+            REG_USB_COUNT(1) = length;
+            REG_USB_CNTL(1) = (USB_CNTL_INTR_EN | USB_CNTL_MODE_1 |
+                                 USB_CNTL_ENA | USB_CNTL_EP(endpoint) |
+                                 USB_CNTL_BURST_16);
+        }
+        else
+            EPOUT_handler(endpoint);
+
+        restore_irq(flags);
+        return 0;
+    }
+}
+
+void usb_drv_set_test_mode(int mode)
+{
+    logf("%s(%d)", __func__, mode);
+
+    switch(mode)
+    {
+        case 0:
+            REG_USB_TESTMODE &= ~USB_TEST_ALL;
+            break;
+        case 1:
+            REG_USB_TESTMODE |= USB_TEST_J;
+            break;
+        case 2:
+            REG_USB_TESTMODE |= USB_TEST_K;
+            break;
+        case 3:
+            REG_USB_TESTMODE |= USB_TEST_SE0NAK;
+            break;
+        case 4:
+            REG_USB_TESTMODE |= USB_TEST_PACKET;
+            break;
+    }
+}
+
+int usb_drv_port_speed(void)
+{
+    return (REG_USB_POWER & USB_POWER_HSMODE) ? 1 : 0;
+}
+
+void usb_drv_cancel_all_transfers(void)
+{
+    logf("%s()", __func__);
+
+    unsigned int i, flags;
+    flags = disable_irq_save();
+
+    for(i=0; i<TOTAL_EP(); i++)
+    {
+        if(i != 1) /* ep0 out needs special handling */
+            endpoints[i].buf = NULL;
+
+        endpoints[i].sent = 0;
+        endpoints[i].length = 0;
+
+        select_endpoint(i/2);
+        flushFIFO(&endpoints[i]);
+    }
+    restore_irq(flags);
+}
+
+
+void usb_drv_release_endpoint(int ep)
+{
+    (void)ep;
+    logf("%s(%d, %s)", __func__, (ep & 0x7F), (ep >> 7) ? "IN" : "OUT");
+}
+
+int usb_drv_request_endpoint(int type, int dir)
+{
+    logf("%s(%d, %s)", __func__, type, (dir == USB_DIR_IN) ? "IN" : "OUT");
+
+    dir  &= USB_ENDPOINT_DIR_MASK;
+    type &= USB_ENDPOINT_XFERTYPE_MASK;
+
+    /* There are only 3+2 endpoints, so hardcode this ... */
+    switch(type)
+    {
+        case USB_ENDPOINT_XFER_BULK:
+            if(dir == USB_DIR_IN)
+                return (1 | USB_DIR_IN);
+            else
+                return (1 | USB_DIR_OUT);
+
+        case USB_ENDPOINT_XFER_INT:
+            if(dir == USB_DIR_IN)
+                return (2 | USB_DIR_IN);
+            else
+                return (2 | USB_DIR_OUT);
+
+        default:
+            return -1;
+    }
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/xdebug.h b/firmware/target/mips/ingenic_jz47xx/xdebug.h
new file mode 100644
index 0000000000..2f348e266b
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/xdebug.h
@@ -0,0 +1,31 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef __XDEBUG_H_
+#define __XDEBUG_H_
+
+void serial_puts(const char *s);
+void serial_putsf(const char *format, ...);
+void serial_put_hex(unsigned int d);
+void serial_put_dec(unsigned int d);
+void serial_dump_data(unsigned char* data, int len);
+
+#endif /* __XDEBUG_H_ */
diff --git a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/adc-target.h b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/adc-target.h
new file mode 100644
index 0000000000..c47406ca21
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/adc-target.h
@@ -0,0 +1,28 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef _ADC_TARGET_H_
+#define _ADC_TARGET_H_
+
+#define NUM_ADC_CHANNELS 4
+
+#define ADC_BUTTONS 0
+
+#endif /* _ADC_TARGET_H_ */
diff --git a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/ata-sd-target.h b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/ata-sd-target.h
new file mode 100644
index 0000000000..bb2cced15b
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/ata-sd-target.h
@@ -0,0 +1,48 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef ATA_SD_TARGET_H
+#define ATA_SD_TARGET_H
+
+#include "cpu.h"
+#include "system.h"
+
+#define PIN_SD1_CD    (32*0+29)  /* Pin to check card insertion */
+#define IRQ_SD1_CD    GPIO_IRQ(PIN_SD1_CD)
+#define GPIO_SD1_CD   GPIO29
+
+#define PIN_SD2_CD    (32*0+28)  /* Pin to check card insertion */
+#define IRQ_SD2_CD    GPIO_IRQ(PIN_SD2_CD)
+#define GPIO_SD2_CD   GPIO28
+
+static inline void sd_init_gpio(void)
+{
+    __gpio_as_msc1_pd_4bit();
+    __gpio_as_msc2_pb_4bit();
+
+    __gpio_as_input(PIN_SD1_CD);
+    __gpio_as_input(PIN_SD2_CD);
+
+    __gpio_disable_pull(PIN_SD1_CD);
+    __gpio_disable_pull(PIN_SD2_CD);
+}
+
+#endif
diff --git a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/backlight-xduoo_x3.c b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/backlight-xduoo_x3.c
new file mode 100644
index 0000000000..3f00b0b67d
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/backlight-xduoo_x3.c
@@ -0,0 +1,50 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+ 
+#include "config.h"
+#include "cpu.h"
+#include "backlight-target.h"
+#include "lcd.h"
+
+bool backlight_hw_init(void)
+{
+    return true;
+}
+
+void backlight_hw_on(void)
+{
+    lcd_enable(true);
+}
+
+void backlight_hw_off(void)
+{
+    lcd_enable(false);
+}
+
+void backlight_hw_brightness(int brightness)
+{
+    lcd_set_contrast(brightness*16-1);
+}
+
+void lcd_sleep(void)
+{
+    backlight_hw_off();
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/button-target.h b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/button-target.h
new file mode 100644
index 0000000000..2dd94b14bc
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/button-target.h
@@ -0,0 +1,46 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef BUTTON_TARGET_H
+#define BUTTON_TARGET_H
+
+#define HAS_BUTTON_HOLD
+
+/* Main unit's buttons */
+#define BUTTON_POWER      0x00000001
+#define BUTTON_HOME       0x00000002
+#define BUTTON_OPTION     0x00000004
+#define BUTTON_PREV       0x00000008
+#define BUTTON_NEXT       0x00000010
+#define BUTTON_PLAY       0x00000020
+#define BUTTON_VOL_UP     0x00000040
+#define BUTTON_VOL_DOWN   0x00000080
+
+#define BUTTON_LEFT  0
+#define BUTTON_RIGHT 0
+
+#define BUTTON_MAIN  (BUTTON_POWER | BUTTON_HOME | BUTTON_OPTION | BUTTON_PREV | \
+                      BUTTON_NEXT | BUTTON_PLAY | BUTTON_VOL_UP | BUTTON_VOL_DOWN)
+
+/* Software power-off */
+#define POWEROFF_BUTTON BUTTON_POWER
+#define POWEROFF_COUNT  10
+
+#endif /* BUTTON_TARGET_H */
diff --git a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c
new file mode 100644
index 0000000000..89251b727d
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c
@@ -0,0 +1,420 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+
+#include "lcd.h"
+#include "system.h"
+#include "cpu.h"
+#include "string.h"
+
+/* LCD pins */
+#define PIN_BL_EN   (32*4+0)
+
+#define PIN_LCD_D0  (32*2+2)
+#define PIN_LCD_D1  (32*2+3)
+#define PIN_LCD_D2  (32*2+4)
+#define PIN_LCD_D3  (32*2+5)
+#define PIN_LCD_D4  (32*2+6)
+#define PIN_LCD_D5  (32*2+7)
+#define PIN_LCD_D6  (32*2+12)
+#define PIN_LCD_D7  (32*2+13)
+
+#define PIN_LCD_RD  (32*2+8)
+#define PIN_LCD_DC  (32*2+9)
+#define PIN_LCD_CS  (32*2+14)
+#define PIN_LCD_RES (32*2+18)
+#define PIN_LCD_WR  (32*2+19)
+
+/* LCD setup codes */
+#define LCD_SET_LOWER_COLUMN_ADDRESS              ((char)0x00)
+#define LCD_SET_HIGHER_COLUMN_ADDRESS             ((char)0x10)
+#define LCD_SET_DISPLAY_START_LINE                ((char)0x40)
+#define LCD_SET_CONTRAST_CONTROL_REGISTER         ((char)0x81)
+#define LCD_SET_CHARGE_PUMP                       ((char)0x8D)
+#define LCD_SET_SEGMENT_REMAP                     ((char)0xA0)
+#define LCD_SET_SEGMENT_REMAP_INV                 ((char)0xA1)
+#define LCD_SET_ENTIRE_DISPLAY_OFF                ((char)0xA4)
+#define LCD_SET_ENTIRE_DISPLAY_ON                 ((char)0xA5)
+#define LCD_SET_NORMAL_DISPLAY                    ((char)0xA6)
+#define LCD_SET_REVERSE_DISPLAY                   ((char)0xA7)
+#define LCD_SET_MULTIPLEX_RATIO                   ((char)0xA8)
+#define LCD_SET_DC_DC                             ((char)0xAD)
+#define LCD_SET_DISPLAY_OFF                       ((char)0xAE)
+#define LCD_SET_DISPLAY_ON                        ((char)0xAF)
+#define LCD_SET_PAGE_ADDRESS                      ((char)0xB0)
+#define LCD_SET_COM_OUTPUT_SCAN_DIRECTION         ((char)0xC0)
+#define LCD_SET_COM_OUTPUT_SCAN_DIRECTION_INV     ((char)0xC8)
+#define LCD_SET_DISPLAY_OFFSET                    ((char)0xD3)
+#define LCD_SET_DISPLAY_CLOCK_AND_OSC_FREQ        ((char)0xD5)
+#define LCD_SET_VCOM_HW_CONFIGURATION             ((char)0xDA)
+#define LCD_SET_VCOM_DESELECT_LEVEL               ((char)0xDB)
+#define LCD_SET_PRECHARGE_PERIOD                  ((char)0xD9)
+#define LCD_NOP                                   ((char)0xE3)
+
+/* LCD command codes */
+#define LCD_CNTL_CONTRAST       0x81    /* Contrast */
+#define LCD_CNTL_OUTSCAN        0xc8    /* Output scan direction */
+#define LCD_CNTL_SEGREMAP       0xa1    /* Segment remap */
+#define LCD_CNTL_DISPON         0xaf    /* Display on */
+
+#define LCD_CNTL_PAGE           0xb0    /* Page address */
+#define LCD_CNTL_HIGHCOL        0x10    /* Upper column address */
+#define LCD_CNTL_LOWCOL         0x00    /* Lower column address */
+
+#define LCD_COL_OFFSET 2 /* column offset */
+
+static inline void bitdelay(void)
+{
+    unsigned int i = 15;
+    __asm__ __volatile__ (
+                          ".set noreorder    \n"
+                          "1:                \n"
+                          "bne  %0, $0, 1b   \n"
+                          "addi %0, %0, -1   \n"
+                          ".set reorder      \n"
+                          : "=r" (i)
+                          : "0" (i)
+                          );
+}
+
+void lcd_hw_init(void)
+{
+    REG_GPIO_PXFUNC(2) = 0x000C73FC; /* D0-D7 RD DC CS RES WR */
+    REG_GPIO_PXSELC(2) = 0x000C73FC;
+    REG_GPIO_PXDIRS(2) = 0x000C73FC;
+    REG_GPIO_PXDATS(2) = 0x000C73FC;
+    __gpio_clear_pin(PIN_BL_EN);
+    __gpio_as_output(PIN_BL_EN);
+    __gpio_clear_pin(PIN_LCD_RES);
+    udelay(1);
+    __gpio_set_pin(PIN_LCD_RES);
+    __gpio_clear_pin(PIN_LCD_CS);
+}
+
+void lcd_write_command(int byte)
+{
+    __gpio_clear_pin(PIN_LCD_DC);
+    REG_GPIO_PXDATC(2) = 0x000030FC;
+    REG_GPIO_PXDATS(2) = ((byte & 0xC0) << 6) | ((byte & 0x3F) << 2);
+    __gpio_clear_pin(PIN_LCD_WR);
+    bitdelay();
+    __gpio_set_pin(PIN_LCD_WR);
+    bitdelay();
+}
+
+void lcd_write_data(const fb_data* p_bytes, int count)
+{
+    __gpio_set_pin(PIN_LCD_DC);
+    while (count--)
+    {
+        REG_GPIO_PXDATC(2) = 0x000030FC;
+        REG_GPIO_PXDATS(2) = ((*p_bytes & 0xC0) << 6) | ((*p_bytes & 0x3F) << 2);
+        p_bytes++;
+        __gpio_clear_pin(PIN_LCD_WR);
+        bitdelay();
+        __gpio_set_pin(PIN_LCD_WR);
+        bitdelay();
+    }
+}
+
+void lcd_enable_power(bool onoff)
+{
+    if (onoff)
+        __gpio_set_pin(PIN_BL_EN);
+    else
+        __gpio_clear_pin(PIN_BL_EN);
+}
+
+/** globals **/
+
+static bool display_on = false; /* used by lcd_enable */
+
+/*** hardware configuration ***/
+
+void lcd_set_contrast(int val)
+{
+    lcd_write_command(LCD_CNTL_CONTRAST);
+    lcd_write_command(val);
+}
+
+void lcd_set_invert_display(bool yesno)
+{
+    if (yesno)
+        lcd_write_command(LCD_SET_REVERSE_DISPLAY);
+    else
+        lcd_write_command(LCD_SET_NORMAL_DISPLAY);
+}
+
+/* turn the display upside down (call lcd_update() afterwards) */
+void lcd_set_flip(bool yesno)
+{
+    if (yesno)
+    {
+        lcd_write_command(LCD_SET_SEGMENT_REMAP);
+        lcd_write_command(LCD_SET_COM_OUTPUT_SCAN_DIRECTION);
+    }
+    else
+    {
+        lcd_write_command(LCD_SET_SEGMENT_REMAP_INV);
+        lcd_write_command(LCD_SET_COM_OUTPUT_SCAN_DIRECTION_INV);
+    }
+}
+
+#ifdef HAVE_LCD_ENABLE
+void lcd_enable(bool enable)
+{
+    if(display_on == enable)
+        return;
+
+    if( (display_on = enable) ) /* simple '=' is not a typo ! */
+    {
+        lcd_enable_power(enable);
+        lcd_write_command(LCD_SET_DISPLAY_ON);
+        send_event(LCD_EVENT_ACTIVATION, NULL);
+    }
+    else
+    {
+        lcd_write_command(LCD_SET_DISPLAY_OFF);
+        lcd_enable_power(enable);
+    }
+}
+
+bool lcd_active(void)
+{
+    return display_on;
+}
+#endif
+
+/* LCD init, largely based on what OF does */
+void lcd_init_device(void)
+{
+    int i;
+
+    lcd_hw_init();
+
+    /* Set display off */
+    lcd_write_command(LCD_SET_DISPLAY_OFF);
+
+    /* Set display clock and oscillator frequency */
+    lcd_write_command(LCD_SET_DISPLAY_CLOCK_AND_OSC_FREQ);
+    lcd_write_command(0x80);
+
+    /* Set multiplex ratio*/
+    lcd_write_command(LCD_SET_MULTIPLEX_RATIO);
+    lcd_write_command(0x3F);
+
+    /* Set display offset */
+    lcd_write_command(LCD_SET_DISPLAY_OFFSET);
+    lcd_write_command(0x00);
+
+    /* Set starting line as 0 */
+    lcd_write_command(LCD_SET_DISPLAY_START_LINE);
+
+    /* Set charge pump */
+    lcd_write_command(LCD_SET_CHARGE_PUMP);
+    lcd_write_command(0x14); /* VCC Generated by Internal DC/DC Circuit */
+
+    /* Column 131 is remapped to SEG0 */
+    lcd_write_command(LCD_SET_SEGMENT_REMAP_INV);
+
+    /* Invert COM scan direction (N-1 to 0) */
+    lcd_write_command(LCD_SET_COM_OUTPUT_SCAN_DIRECTION_INV);
+
+    /* Set COM hardware configuration */
+    lcd_write_command(LCD_SET_VCOM_HW_CONFIGURATION);
+    lcd_write_command(0x12);
+
+    /* Set contrast control */
+    lcd_write_command(LCD_SET_CONTRAST_CONTROL_REGISTER);
+    lcd_write_command(0xCF); /* VCC Generated by Internal DC/DC Circuit */
+
+    /* Set pre-charge period */
+    lcd_write_command(LCD_SET_PRECHARGE_PERIOD);
+    lcd_write_command(0xF1); /* VCC Generated by Internal DC/DC Circuit */
+
+    /* Set VCOM deselect level */
+    lcd_write_command(LCD_SET_VCOM_DESELECT_LEVEL);
+    lcd_write_command(0x40);
+
+    /* Set normal display mode (not every pixel ON) */
+    lcd_write_command(LCD_SET_ENTIRE_DISPLAY_OFF);
+
+    /* Set normal display mode (not inverted) */
+    lcd_write_command(LCD_SET_NORMAL_DISPLAY);
+
+    fb_data p_bytes[LCD_WIDTH + 2 * LCD_COL_OFFSET];
+    memset(p_bytes, 0, sizeof(p_bytes)); /* fills with 0 : pixel off */
+    for(i = 0; i < 8; i++)
+    {
+        lcd_write_command (LCD_SET_PAGE_ADDRESS | (i /*& 0xf*/));
+        lcd_write_data(p_bytes, LCD_WIDTH + 2 * LCD_COL_OFFSET);
+    }
+
+    lcd_enable(true);
+
+    lcd_update();
+}
+
+/*** Update functions ***/
+
+/* Performance function that works with an external buffer
+   note that by and bheight are in 8-pixel units! */
+void lcd_blit_mono(const unsigned char *data, int x, int by, int width,
+                   int bheight, int stride)
+{
+    if(!display_on)
+        return;
+
+    /* Copy display bitmap to hardware */
+    while (bheight--)
+    {
+        lcd_write_command (LCD_CNTL_PAGE | (by++ & 0xf));
+        lcd_write_command (LCD_CNTL_HIGHCOL | (((x+LCD_COL_OFFSET)>>4) & 0xf));
+        lcd_write_command (LCD_CNTL_LOWCOL | ((x+LCD_COL_OFFSET) & 0xf));
+
+        lcd_write_data(data, width);
+        data += stride;
+    }
+}
+
+
+#ifndef BOOTLOADER
+/* Helper function for lcd_grey_phase_blit(). */
+void lcd_grey_data(unsigned char *values, unsigned char *phases, int count) ICODE_ATTR;
+void lcd_grey_data(unsigned char *values, unsigned char *phases, int count)
+{
+    unsigned char a, b, c, d;
+
+    __gpio_set_pin(PIN_LCD_DC);
+    while(count--)
+    {
+        c = 0;
+        d = 8;
+        while(d--)
+        {
+            a = *phases;
+            b = *values++;
+            b += a & ~0x80;
+            *phases++ = b;
+            c <<= 1;
+            c |= a >> 7;
+        }
+        REG_GPIO_PXDATC(2) = 0x000030FC;
+        REG_GPIO_PXDATS(2) = ((c & 0xC0) << 6) | ((c & 0x3F) << 2);
+        __gpio_clear_pin(PIN_LCD_WR);
+        bitdelay();
+        __gpio_set_pin(PIN_LCD_WR);
+        bitdelay();
+    }
+}
+
+/* Performance function that works with an external buffer
+   note that by and bheight are in 8-pixel units! */
+void lcd_blit_grey_phase(unsigned char *values, unsigned char *phases,
+                         int x, int by, int width, int bheight, int stride)
+{
+    if(!display_on)
+        return;
+
+    stride <<= 3; /* 8 pixels per block */
+    /* Copy display bitmap to hardware */
+    while (bheight--)
+    {
+        lcd_write_command (LCD_CNTL_PAGE | (by++ & 0xf));
+        lcd_write_command (LCD_CNTL_HIGHCOL | (((x+LCD_COL_OFFSET)>>4) & 0xf));
+        lcd_write_command (LCD_CNTL_LOWCOL | ((x+LCD_COL_OFFSET) & 0xf));
+
+        lcd_grey_data(values, phases, width);
+
+        values += stride;
+        phases += stride;
+    }
+}
+#endif
+
+/* Update the display.
+   This must be called after all other LCD functions that change the display. */
+void lcd_update(void) ICODE_ATTR;
+void lcd_update(void)
+{
+    int y;
+
+    if(!display_on)
+        return;
+
+    /* Copy display bitmap to hardware */
+    for (y = 0; y < LCD_FBHEIGHT; y++)
+    {
+        lcd_write_command (LCD_CNTL_PAGE | (y & 0xf));
+        lcd_write_command (LCD_CNTL_HIGHCOL | ((LCD_COL_OFFSET >> 4) & 0xf));
+        lcd_write_command (LCD_CNTL_LOWCOL | (LCD_COL_OFFSET & 0xf));
+
+        lcd_write_data (FBADDR(0, y), LCD_WIDTH);
+    }
+}
+
+/* Update a fraction of the display. */
+void lcd_update_rect(int, int, int, int) ICODE_ATTR;
+void lcd_update_rect(int x, int y, int width, int height)
+{
+    int ymax;
+
+    if(!display_on)
+        return;
+
+    /* The Y coordinates have to work on even 8 pixel rows */
+    if (x < 0)
+    {
+        width += x;
+        x = 0;
+    }
+
+    if (x + width > LCD_WIDTH)
+        width = LCD_WIDTH - x;
+
+    if (width <= 0)
+        return; /* nothing left to do, 0 is harmful to lcd_write_data() */
+
+    if (y < 0)
+    {
+        height += y;
+        y = 0;
+    }
+
+    if (y + height > LCD_HEIGHT)
+        height = LCD_HEIGHT - y;
+
+    if (height <= 0)
+        return; /* nothing left to do */
+
+    ymax = (y + height-1) >> 3;
+    y >>= 3;
+
+    /* Copy specified rectange bitmap to hardware */
+    for (; y <= ymax; y++)
+    {
+        lcd_write_command (LCD_CNTL_PAGE | (y & 0xf));
+        lcd_write_command (LCD_CNTL_HIGHCOL | (((x+LCD_COL_OFFSET) >> 4) & 0xf));
+        lcd_write_command (LCD_CNTL_LOWCOL | ((x+LCD_COL_OFFSET) & 0xf));
+
+        lcd_write_data (FBADDR(x,y), width);
+    }
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/power-xduoo_x3.c b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/power-xduoo_x3.c
new file mode 100644
index 0000000000..9ae602ba56
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/power-xduoo_x3.c
@@ -0,0 +1,46 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "power.h"
+#include "cpu.h"
+
+#define CHARGE_STAT_GPIO (32*1+6) /* STAT port */
+
+/* Detect which power sources are present. */
+unsigned int power_input_status(void)
+{
+    if(!__gpio_get_pin(CHARGE_STAT_GPIO))
+        return POWER_INPUT_USB_CHARGER;
+
+    return POWER_INPUT_NONE;
+}
+
+void power_init(void)
+{
+    __gpio_as_input(CHARGE_STAT_GPIO);
+    __gpio_disable_pull(CHARGE_STAT_GPIO);
+}
+
+bool charging_state(void)
+{
+    return (power_input_status() == POWER_INPUT_USB_CHARGER);
+}
diff --git a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/sadc-xduoo_x3.c b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/sadc-xduoo_x3.c
new file mode 100644
index 0000000000..d4a3548305
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/sadc-xduoo_x3.c
@@ -0,0 +1,214 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+ 
+#include "config.h"
+#include "system.h"
+#include "cpu.h"
+#include "button.h"
+#include "button-target.h"
+#include "powermgmt.h"
+#include "kernel.h"
+#include "backlight.h"
+#include "logf.h"
+#include "adc.h"
+
+#define PIN_BTN_POWER (32*0+30)
+#define PIN_BTN_HOLD  (32*1+15)
+
+#define PIN_KEY_INT   (32*4+13)
+#define KEY_INT_IRQ   GPIO141
+
+#define PIN_CHARGE_CON (32*1+7)
+
+#define PIN_PH_DECT   (32*1+11)
+#define IRQ_PH_DECT   GPIO_IRQ(PIN_PH_DECT)
+#define GPIO_PH_DECT  GPIO43
+
+#define PIN_LO_DECT   (32*1+12)
+#define IRQ_LO_DECT   GPIO_IRQ(PIN_LO_DECT)
+#define GPIO_LO_DECT  GPIO44
+
+static volatile unsigned short bat_val,key_val;
+
+bool headphones_inserted(void)
+{
+    return (__gpio_get_pin(PIN_PH_DECT) != 0);
+}
+
+void button_init_device(void)
+{
+    key_val = 0xfff;
+
+    __gpio_as_input(PIN_BTN_POWER);
+    __gpio_as_input(PIN_BTN_HOLD);
+
+    __gpio_disable_pull(PIN_BTN_POWER);
+    __gpio_disable_pull(PIN_BTN_HOLD);
+    
+    __gpio_as_irq_fall_edge(PIN_KEY_INT);
+    system_enable_irq(GPIO_IRQ(PIN_KEY_INT));
+
+    __gpio_set_pin(PIN_CHARGE_CON); /* 0.7 A */
+    __gpio_as_output(PIN_CHARGE_CON);
+
+    __gpio_as_input(PIN_LO_DECT);
+    __gpio_as_input(PIN_PH_DECT);
+
+    __gpio_disable_pull(PIN_LO_DECT);
+    __gpio_disable_pull(PIN_PH_DECT);
+}
+
+bool button_hold(void)
+{
+   return (__gpio_get_pin(PIN_BTN_HOLD) ? true : false);
+}
+
+int button_read_device(void)
+{
+    static bool hold_button = false;
+    bool hold_button_old;
+    
+    hold_button_old = hold_button;
+    hold_button = (__gpio_get_pin(PIN_BTN_HOLD) ? true : false);
+
+    int btn = BUTTON_NONE;
+    bool gpio_btn = (__gpio_get_pin(PIN_BTN_POWER) ? false : true);
+
+    REG_SADC_ADCFG = ADCFG_VBAT_SEL + ADCFG_CMD_AUX(1);
+    REG_SADC_ADENA = ADENA_VBATEN + ADENA_AUXEN;
+
+#ifndef BOOTLOADER
+    if (hold_button != hold_button_old) {
+        backlight_hold_changed(hold_button);
+    }
+    if (hold_button) {
+        return BUTTON_NONE;
+    }
+#endif
+
+    if (gpio_btn)
+        btn |= BUTTON_POWER;
+
+    if (key_val < 261)
+        btn |= BUTTON_VOL_UP;
+    else
+    if (key_val < 653)
+        btn |= BUTTON_VOL_DOWN;
+    else
+    if (key_val < 1101)
+        btn |= BUTTON_PREV;
+    else
+    if (key_val < 1498)
+        btn |= BUTTON_NEXT;
+    else
+    if (key_val < 1839)
+        btn |= BUTTON_PLAY;
+    else
+    if (key_val < 2213)
+        btn |= BUTTON_OPTION;
+    else
+    if (key_val < 2600)
+        btn |= BUTTON_HOME;
+       
+    return btn;
+}
+
+/* called on button press interrupt */
+void KEY_INT_IRQ(void)
+{
+}
+
+const unsigned short battery_level_dangerous[BATTERY_TYPES_COUNT] =
+{
+    /* 5% */
+    3634
+};
+
+const unsigned short battery_level_shutoff[BATTERY_TYPES_COUNT] =
+{
+    /* 0% */
+    3300
+};
+
+
+/* voltages (millivolt) of 0%, 10%, ... 100% when charging disabled */
+const unsigned short percent_to_volt_discharge[BATTERY_TYPES_COUNT][11] =
+{
+    { 3300, 3652, 3704, 3730, 3753, 3786, 3836, 3906, 3973, 4061, 4160 }
+};
+
+#if CONFIG_CHARGING
+/* voltages (millivolt) of 0%, 10%, ... 100% when charging enabled */
+const unsigned short percent_to_volt_charge[11] =
+    { 3300, 3652, 3704, 3730, 3753, 3786, 3836, 3906, 3973, 4061, 4160 };
+#endif /* CONFIG_CHARGING */
+
+/* VBAT = (BDATA/1024) * 2.5V */
+#define BATTERY_SCALE_FACTOR 2460
+
+/* Returns battery voltage from ADC [millivolts] */
+int _battery_voltage(void)
+{
+    return (bat_val*BATTERY_SCALE_FACTOR)>>10;
+}
+
+void adc_init(void)
+{
+    bat_val = 0xfff;
+
+    __cpm_start_sadc();
+    mdelay(10);
+    REG_SADC_ADENA = 0; /* Power Up */
+    mdelay(70);
+    REG_SADC_ADSTATE = 0;
+    REG_SADC_ADCTRL = ADCTRL_MASK_ALL - ADCTRL_ARDYM - ADCTRL_VRDYM;
+    REG_SADC_ADCFG = ADCFG_VBAT_SEL + ADCFG_CMD_AUX(1);
+    REG_SADC_ADCLK = (4 << 16) | (1 << 8) | 59; /* 200KHz */
+    system_enable_irq(IRQ_SADC);
+}
+
+void adc_close(void)
+{
+    REG_SADC_ADENA = ADENA_POWER; /* Power Down */
+    __intc_mask_irq(IRQ_SADC);
+    mdelay(20);
+    __cpm_stop_sadc();
+}
+
+/* Interrupt handler */
+void SADC(void)
+{
+    unsigned char state;
+    unsigned char sadcstate;
+
+    sadcstate = REG_SADC_ADSTATE;
+    state = REG_SADC_ADSTATE & (~REG_SADC_ADCTRL);
+    REG_SADC_ADSTATE &= sadcstate;
+    
+    if(state & ADCTRL_ARDYM)
+    {
+        key_val = REG_SADC_ADADAT;
+    }
+    if(state & ADCTRL_VRDYM)
+    {
+        bat_val = REG_SADC_ADVDAT;
+    }
+}
diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c
index 9dcec43321..b519bf9331 100644
--- a/firmware/target/mips/mmu-mips.c
+++ b/firmware/target/mips/mmu-mips.c
@@ -127,86 +127,76 @@ void mmu_init(void)
 
 #define SYNC_WB() __asm__ __volatile__ ("sync")
 
-#define __CACHE_OP(op, addr)                 \
-    __asm__ __volatile__(                    \
-    "    .set    noreorder        \n"        \
-    "    .set    mips32\n\t       \n"        \
-    "    cache   %0, %1           \n"        \
-    "    .set    mips0            \n"        \
-    "    .set    reorder          \n"        \
-    :                                        \
-    : "i" (op), "m" (*(unsigned char *)(addr)))
-
-void __flush_dcache_line(unsigned long addr)
+#define cache_op(base,op)                       \
+        __asm__ __volatile__("                  \
+                .set noreorder;                 \
+                .set mips3;                     \
+                cache %1, (%0);                 \
+                .set mips0;                     \
+                .set reorder"                   \
+                :                               \
+                : "r" (base),                   \
+                  "i" (op));
+
+void __icache_invalidate_all(void)
 {
-    __CACHE_OP(DCHitWBInv, addr);
+    unsigned long start;
+    unsigned long end;
+
+    start = A_K0BASE;
+    end = start + CACHE_SIZE;
+    while(start < end)
+    {
+        cache_op(start,ICIndexInv);
+        start += CACHE_LINE_SIZE;
+    }
     SYNC_WB();
 }
 
-void __icache_invalidate_all(void)
+void __dcache_invalidate_all(void)
 {
-    unsigned int i;
-
-    asm volatile (".set   noreorder  \n"
-                  ".set   mips32     \n"
-                  "mtc0   $0, $28    \n" /* TagLo */
-                  "mtc0   $0, $29    \n" /* TagHi */
-                  ".set   mips0      \n"
-                  ".set   reorder    \n"
-                  );
-    for(i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHE_LINE_SIZE)
-        __CACHE_OP(ICIndexStTag, i);
-
-    /* invalidate btb */
-    asm volatile (
-        ".set mips32        \n"
-        "mfc0 %0, $16, 7    \n"
-        "nop                \n"
-        "ori  %0, 2         \n"
-        "mtc0 %0, $16, 7    \n"
-        ".set mips0         \n"
-        :
-        : "r" (i));
+    unsigned long start;
+    unsigned long end;
+
+    start = A_K0BASE;
+    end = start + CACHE_SIZE;
+    while (start < end)
+    {
+        cache_op(start,DCIndexWBInv);
+        start += CACHE_LINE_SIZE;
+    }
+    SYNC_WB();
 }
 
-void __dcache_invalidate_all(void)
+void __idcache_invalidate_all(void)
 {
-    unsigned int i;
-
-    asm volatile (".set   noreorder  \n"
-                  ".set   mips32     \n"
-                  "mtc0   $0, $28    \n"
-                  "mtc0   $0, $29    \n"
-                  ".set   mips0      \n"
-                  ".set   reorder    \n"
-                  );
-    for (i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHE_LINE_SIZE)
-        __CACHE_OP(DCIndexStTag, i);
+    __dcache_invalidate_all();
+    __icache_invalidate_all();
 }
 
-void __dcache_writeback_all(void) __attribute__ ((section(".icode")));
 void __dcache_writeback_all(void)
 {
-    unsigned int i;
-    for(i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHE_LINE_SIZE)
-        __CACHE_OP(DCIndexWBInv, i);
-    
-    SYNC_WB();
+    __dcache_invalidate_all();
 }
 
 void dma_cache_wback_inv(unsigned long addr, unsigned long size)
 {
     unsigned long end, a;
 
-    if (size >= CACHE_SIZE)
+    if (size >= CACHE_SIZE*2) {
         __dcache_writeback_all();
-    else
-    {
+    }
+    else {
         unsigned long dc_lsize = CACHE_LINE_SIZE;
-        
+
         a = addr & ~(dc_lsize - 1);
         end = (addr + size - 1) & ~(dc_lsize - 1);
-        for(; a < end; a += dc_lsize)
-            __flush_dcache_line(a);
+        while (1) {
+            cache_op(a,DCHitWBInv);
+            if (a == end)
+                break;
+            a += dc_lsize;
+        }
     }
+    SYNC_WB();
 }
diff --git a/firmware/target/mips/mmu-mips.h b/firmware/target/mips/mmu-mips.h
index 47aea807cc..7e1e36d3f4 100644
--- a/firmware/target/mips/mmu-mips.h
+++ b/firmware/target/mips/mmu-mips.h
@@ -31,14 +31,16 @@ void mmu_init(void);
 #define HAVE_CPUCACHE_INVALIDATE
 //#define HAVE_CPUCACHE_FLUSH
 
-void __dcache_writeback_all(void);
-void __dcache_invalidate_all(void);
+void __idcache_invalidate_all(void);
 void __icache_invalidate_all(void);
-void __flush_dcache_line(unsigned long addr);
+void __dcache_invalidate_all(void);
+void __dcache_writeback_all(void);
+
 void dma_cache_wback_inv(unsigned long addr, unsigned long size);
 
-#define commit_discard_idcache  __icache_invalidate_all
-#define commit_discard_dcache   __dcache_invalidate_all
-#define commit_dcache           __dcache_writeback_all
+#define commit_discard_idcache   __idcache_invalidate_all
+#define commit_discard_icache    __icache_invalidate_all
+#define commit_discard_dcache    __dcache_invalidate_all
+#define commit_dcache            __dcache_writeback_all
 
 #endif /* __MMU_MIPS_INCLUDE_H */
diff --git a/firmware/usb.c b/firmware/usb.c
index 562734c84a..375bb6d768 100644
--- a/firmware/usb.c
+++ b/firmware/usb.c
@@ -49,7 +49,8 @@
      (defined(HAVE_USBSTACK) && (defined(CREATIVE_ZVx))) || \
      (defined(HAVE_USBSTACK) && (defined(OLYMPUS_MROBE_500))) || \
      defined(CPU_TCC77X) || defined(CPU_TCC780X) || \
-     (CONFIG_USBOTG == USBOTG_JZ4740)
+     (CONFIG_USBOTG == USBOTG_JZ4740) || \
+     (CONFIG_USBOTG == USBOTG_JZ4760)
 /* TODO: condition should be reset to be only the original
    (defined(HAVE_USBSTACK) && defined(HAVE_BOOTLOADER_USB_MODE)) */
 #define USB_FULL_INIT
diff --git a/tools/builds.pm b/tools/builds.pm
index 1dfe937426..e002bfca7b 100644
--- a/tools/builds.pm
+++ b/tools/builds.pm
@@ -418,6 +418,10 @@ $releasenotes="/wiki/ReleaseNotes314";
         name => 'Agptek Rocker',
         status => 2
     }
+    'xduoox3' => {
+        name => 'xDuoo X3',
+        status => 2,
+    },
 );
 
 sub manualname {
diff --git a/tools/configure b/tools/configure
index 76a62a6364..330c6640fe 100755
--- a/tools/configure
+++ b/tools/configure
@@ -1535,6 +1535,8 @@ cat <<EOF
  232) DX50                240) Rocker            227) NW-A20 series
  233) DX90                                       228) NWZ-A860 series
                                                  229) NWZ-S750 series
+ ==xDuoo==
+ 241) X3
 EOF
 
   buildfor=`input`;
@@ -4215,6 +4217,28 @@ fi
     mipsellinuxcc
     ;;
 
+    241|xduoox3)
+    target_id=106
+    modelname="xduoox3"
+    target="XDUOO_X3"
+    memory=64
+    mipselcc
+    tool="$rootdir/tools/scramble -add=xdx3"
+    bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
+    bmp2rb_native="$bmp2rb_mono"
+    output="rockbox.x3"
+    appextra="recorder:gui:radio"
+    plugins="yes"
+    swcodec="yes"
+    toolset=$genericbitmaptools
+    boottool="cp"
+    bootoutput="bootloader-x3.bin"
+    # architecture, manufacturer and model for the target-tree build
+    t_cpu="mips"
+    t_manufacturer="ingenic_jz47xx"
+    t_model="xduoo_x3"
+    ;;
+
    *)
     echo "Please select a supported target platform!"
     exit 7
diff --git a/tools/release/sims.pl b/tools/release/sims.pl
index d5cef51c67..190516907e 100755
--- a/tools/release/sims.pl
+++ b/tools/release/sims.pl
@@ -225,3 +225,4 @@ runone("sonynwze370");
 runone("creativezenxfi");
 runone("creativezen");
 runone("creativezenmozaic");
+runone("xduoox3");
diff --git a/tools/rockboxdev.sh b/tools/rockboxdev.sh
index 856ab2003d..fac56e1102 100755
--- a/tools/rockboxdev.sh
+++ b/tools/rockboxdev.sh
@@ -700,7 +700,7 @@ if [ -z "$RBDEV_TARGET" ]; then
     echo "s   - sh       (Archos models)"
     echo "m   - m68k     (iriver h1x0/h3x0, iaudio m3/m5/x5 and mpio hd200)"
     echo "a   - arm      (ipods, iriver H10, Sansa, D2, Gigabeat, etc)"
-    echo "i   - mips     (Jz4740 and ATJ-based players)"
+    echo "i   - mips     (Jz47xx and ATJ-based players)"
     echo "r   - arm-app  (Samsung ypr0)"
     echo "x   - arm-linux  (Generic Linux ARM: Samsung ypr0, Linux-based Sony NWZ)"
     echo "y   - mips-linux  (Generic Linux MIPS: AGPTek Rocker)"
diff --git a/tools/scramble.c b/tools/scramble.c
index 14be30de69..7aa468ebaa 100644
--- a/tools/scramble.c
+++ b/tools/scramble.c
@@ -130,7 +130,7 @@ void usage(void)
            "\t                   747p, x777, nn2g, m244, cli+, fuz2, hd20, hd30,\n"
            "\t                   ip6g, rk27, clzp, zxf2, zxf3, fuz+, e370, e360,\n"
            "\t                   zxfi, zmoz, zen, zenv, ypz5, zxfs, e450, e460,\n"
-           "\t                   e470,e580,a10,a20,a860,s750,e350)\n");
+           "\t                   e470, e580, a10, a20, a860, s750, e350, xdx3)\n");
     printf("\nNo option results in Archos standard player/recorder format.\n");
 
     exit(1);
@@ -383,6 +383,8 @@ int main (int argc, char** argv)
             modelnum = 90;
         else if (!strcmp(&argv[1][5], "zxfs")) /* Creative ZEN X-Fi Style */
             modelnum = 94;
+        else if (!strcmp(&argv[1][5], "xdx3")) /* xDuoo X3 */
+            modelnum = 96;
         else if (!strcmp(&argv[1][5], "e450")) /* Sony NWZ-E450 series */
             modelnum = 100;
         else if (!strcmp(&argv[1][5], "e460")) /* Sony NWZ-E460 series */
diff --git a/uisimulator/bitmaps/UI-xduoox3.bmp b/uisimulator/bitmaps/UI-xduoox3.bmp
new file mode 100644
index 0000000000..8546d22032
--- /dev/null
+++ b/uisimulator/bitmaps/UI-xduoox3.bmp
diff --git a/uisimulator/buttonmap/SOURCES b/uisimulator/buttonmap/SOURCES
index 901b4ebd2f..d46066d478 100644
--- a/uisimulator/buttonmap/SOURCES
+++ b/uisimulator/buttonmap/SOURCES
@@ -85,5 +85,7 @@ creative-zen.c
 sony-nwza860.c
 #elif CONFIG_KEYPAD == AGPTEK_ROCKER_PAD
 agptek-rocker.c
+#elif CONFIG_KEYPAD == XDUOO_X3_PAD
+xduoo-x3.c
 #endif
 #endif /* SIMULATOR */
diff --git a/uisimulator/buttonmap/xduoo-x3.c b/uisimulator/buttonmap/xduoo-x3.c
new file mode 100644
index 0000000000..e0b5a476c3
--- /dev/null
+++ b/uisimulator/buttonmap/xduoo-x3.c
@@ -0,0 +1,82 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2016 by Roman Stolyarov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+
+#include <SDL.h>
+#include "button.h"
+#include "buttonmap.h"
+
+int key_to_button(int keyboard_button)
+{
+    int new_btn = BUTTON_NONE;
+    switch (keyboard_button)
+    {
+        case SDLK_KP4:
+        case SDLK_UP:
+            new_btn = BUTTON_PREV;
+            break;
+        case SDLK_KP1:
+        case SDLK_DOWN:
+            new_btn = BUTTON_NEXT;
+            break;
+        case SDLK_KP3:
+        case SDLK_KP_ENTER:
+        case SDLK_SPACE:
+        case SDLK_RETURN:
+            new_btn = BUTTON_PLAY;
+            break;
+        case SDLK_KP5:
+        case SDLK_END:
+        case SDLK_BACKSPACE:
+            new_btn = BUTTON_OPTION;
+            break;
+        case SDLK_KP7:
+        case SDLK_ESCAPE:
+            new_btn = BUTTON_POWER;
+            break;
+        case SDLK_KP9:
+        case SDLK_HOME:
+            new_btn = BUTTON_HOME;
+            break;
+        case SDLK_KP_MINUS:
+        case SDLK_PAGEUP:
+            new_btn = BUTTON_VOL_UP;
+            break;
+        case SDLK_KP_PLUS:
+        case SDLK_PAGEDOWN:
+            new_btn = BUTTON_VOL_DOWN;
+            break;
+    }
+    return new_btn;
+}
+
+struct button_map bm[] = {
+    { SDLK_KP4,     68, 342, 17, "Prev" },
+    { SDLK_KP1,     72, 404, 17, "Next" },
+    { SDLK_KP3,    142, 374, 28, "Play" },
+    { SDLK_KP5,    106, 288, 17, "Option" },
+    { SDLK_KP7,     38, 244, 17, "Power" },
+    { SDLK_KP9,    155, 244, 17, "Home" },
+    { SDLK_KP_MINUS, 192,  74, 17, "Vol Up" },
+    { SDLK_KP_PLUS,  192, 132, 17, "Vol Dn" },
+    { SDLK_h,        0,  66, 17, "Hold" },
+    { 0, 0, 0, 0, "None" }
+};