summaryrefslogtreecommitdiff
path: root/firmware/export/jz4760b.h
diff options
context:
space:
mode:
Diffstat (limited to 'firmware/export/jz4760b.h')
-rw-r--r--firmware/export/jz4760b.h9643
1 files changed, 9643 insertions, 0 deletions
diff --git a/firmware/export/jz4760b.h b/firmware/export/jz4760b.h
new file mode 100644
index 0000000000..c523cc64c9
--- /dev/null
+++ b/firmware/export/jz4760b.h
@@ -0,0 +1,9643 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2016 by Roman Stolyarov
11 * Copyright (C) 2008 Ingenic Semiconductor Inc.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
17 *
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
20 *
21 ****************************************************************************/
22
23/*
24 * jz4760b.h
25 *
26 * JZ4760B common definition.
27 *
28 * Copyright (C) 2008 Ingenic Semiconductor Inc.
29 *
30 * Author: <cwjia@ingenic.cn>
31 *
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License version 2 as
34 * published by the Free Software Foundation.
35 */
36
37#ifndef __JZ4760B_H__
38#define __JZ4760B_H__
39
40#if defined(__ASSEMBLY__) || defined(__LANGUAGE_ASSEMBLY)
41 #ifndef __MIPS_ASSEMBLER
42 #define __MIPS_ASSEMBLER
43 #endif
44 #define REG8(addr) (addr)
45 #define REG16(addr) (addr)
46 #define REG32(addr) (addr)
47#else
48 typedef unsigned char u8;
49 typedef unsigned short u16;
50 typedef unsigned int u32;
51
52 #define REG8(addr) *((volatile unsigned char *)(addr))
53 #define REG16(addr) *((volatile unsigned short *)(addr))
54 #define REG32(addr) *((volatile unsigned int *)(addr))
55
56 #define INREG8(x) ((unsigned char)(*(volatile unsigned char *)(x)))
57 #define OUTREG8(x, y) *(volatile unsigned char *)(x) = (y)
58 #define SETREG8(x, y) OUTREG8(x, INREG8(x)|(y))
59 #define CLRREG8(x, y) OUTREG8(x, INREG8(x)&~(y))
60 #define CMSREG8(x, y, m) OUTREG8(x, (INREG8(x)&~(m))|(y))
61
62 #define INREG16(x) ((unsigned short)(*(volatile unsigned short *)(x)))
63 #define OUTREG16(x, y) *(volatile unsigned short *)(x) = (y)
64 #define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y))
65 #define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y))
66 #define CMSREG16(x, y, m) OUTREG16(x, (INREG16(x)&~(m))|(y))
67
68 #define INREG32(x) ((unsigned int)(*(volatile unsigned int *)(x)))
69 #define OUTREG32(x, y) *(volatile unsigned int *)(x) = (y)
70 #define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y))
71 #define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y))
72 #define CMSREG32(x, y, m) OUTREG32(x, (INREG32(x)&~(m))|(y))
73#endif
74
75/*
76 * Define the bit field macro to avoid the bit mistake
77 */
78#define BIT0 (1 << 0)
79#define BIT1 (1 << 1)
80#define BIT2 (1 << 2)
81#define BIT3 (1 << 3)
82#define BIT4 (1 << 4)
83#define BIT5 (1 << 5)
84#define BIT6 (1 << 6)
85#define BIT7 (1 << 7)
86#define BIT8 (1 << 8)
87#define BIT9 (1 << 9)
88#define BIT10 (1 << 10)
89#define BIT11 (1 << 11)
90#define BIT12 (1 << 12)
91#define BIT13 (1 << 13)
92#define BIT14 (1 << 14)
93#define BIT15 (1 << 15)
94#define BIT16 (1 << 16)
95#define BIT17 (1 << 17)
96#define BIT18 (1 << 18)
97#define BIT19 (1 << 19)
98#define BIT20 (1 << 20)
99#define BIT21 (1 << 21)
100#define BIT22 (1 << 22)
101#define BIT23 (1 << 23)
102#define BIT24 (1 << 24)
103#define BIT25 (1 << 25)
104#define BIT26 (1 << 26)
105#define BIT27 (1 << 27)
106#define BIT28 (1 << 28)
107#define BIT29 (1 << 29)
108#define BIT30 (1 << 30)
109#define BIT31 (1 << 31)
110
111/* Generate the bit field mask from msb to lsb */
112#define BITS_H2L(msb, lsb) ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))
113
114/* Get the bit field value from the data which is read from the register */
115#define get_bf_value(data, lsb, mask) (((data) & (mask)) >> (lsb))
116
117/*
118 * Define the module base addresses
119 */
120/* AHB0 BUS Devices Base */
121#define HARB0_BASE 0xB3000000
122/* AHB1 BUS Devices Base */
123#define HARB1_BASE 0xB3200000
124#define DMAGP0_BASE 0xB3210000
125#define DMAGP1_BASE 0xB3220000
126#define DMAGP2_BASE 0xB3230000
127#define DEBLK_BASE 0xB3270000
128#define IDCT_BASE 0xB3280000
129#define CABAC_BASE 0xB3290000
130#define TCSM0_BASE 0xB32B0000
131#define TCSM1_BASE 0xB32C0000
132#define SRAM_BASE 0xB32D0000
133/* AHB2 BUS Devices Base */
134#define HARB2_BASE 0xB3400000
135#define UHC_BASE 0xB3430000
136#define GPS_BASE 0xB3480000
137#define ETHC_BASE 0xB34B0000
138/* APB BUS Devices Base */
139#define PS2_BASE 0xB0060000
140
141/*
142 * General purpose I/O port module(GPIO) address definition
143 */
144#define GPIO_BASE 0xb0010000
145
146/* GPIO group offset */
147#define GPIO_GOS 0x100
148
149/* Each group address */
150#define GPIO_BASEA (GPIO_BASE + (0) * GPIO_GOS)
151#define GPIO_BASEB (GPIO_BASE + (1) * GPIO_GOS)
152#define GPIO_BASEC (GPIO_BASE + (2) * GPIO_GOS)
153#define GPIO_BASED (GPIO_BASE + (3) * GPIO_GOS)
154#define GPIO_BASEE (GPIO_BASE + (4) * GPIO_GOS)
155#define GPIO_BASEF (GPIO_BASE + (5) * GPIO_GOS)
156
157/*
158 * GPIO registers offset address definition
159 */
160#define GPIO_PXPIN_OFFSET (0x00) /* r, 32, 0x00000000 */
161#define GPIO_PXDAT_OFFSET (0x10) /* r, 32, 0x00000000 */
162#define GPIO_PXDATS_OFFSET (0x14) /* w, 32, 0x???????? */
163#define GPIO_PXDATC_OFFSET (0x18) /* w, 32, 0x???????? */
164#define GPIO_PXIM_OFFSET (0x20) /* r, 32, 0xffffffff */
165#define GPIO_PXIMS_OFFSET (0x24) /* w, 32, 0x???????? */
166#define GPIO_PXIMC_OFFSET (0x28) /* w, 32, 0x???????? */
167#define GPIO_PXPE_OFFSET (0x30) /* r, 32, 0x00000000 */
168#define GPIO_PXPES_OFFSET (0x34) /* w, 32, 0x???????? */
169#define GPIO_PXPEC_OFFSET (0x38) /* w, 32, 0x???????? */
170#define GPIO_PXFUN_OFFSET (0x40) /* r, 32, 0x00000000 */
171#define GPIO_PXFUNS_OFFSET (0x44) /* w, 32, 0x???????? */
172#define GPIO_PXFUNC_OFFSET (0x48) /* w, 32, 0x???????? */
173#define GPIO_PXSEL_OFFSET (0x50) /* r, 32, 0x00000000 */
174#define GPIO_PXSELS_OFFSET (0x54) /* w, 32, 0x???????? */
175#define GPIO_PXSELC_OFFSET (0x58) /* w, 32, 0x???????? */
176#define GPIO_PXDIR_OFFSET (0x60) /* r, 32, 0x00000000 */
177#define GPIO_PXDIRS_OFFSET (0x64) /* w, 32, 0x???????? */
178#define GPIO_PXDIRC_OFFSET (0x68) /* w, 32, 0x???????? */
179#define GPIO_PXTRG_OFFSET (0x70) /* r, 32, 0x00000000 */
180#define GPIO_PXTRGS_OFFSET (0x74) /* w, 32, 0x???????? */
181#define GPIO_PXTRGC_OFFSET (0x78) /* w, 32, 0x???????? */
182#define GPIO_PXFLG_OFFSET (0x80) /* r, 32, 0x00000000 */
183#define GPIO_PXFLGC_OFFSET (GPIO_PXDATS_OFFSET) /* w, 32, 0x???????? */
184#define GPIO_PXDS0_OFFSET (0xC0) /* r, 32, 0x00000000 */
185#define GPIO_PXDS0S_OFFSET (0xC4) /* w, 32, 0x00000000 */
186#define GPIO_PXDS0C_OFFSET (0xC8) /* w, 32, 0x00000000 */
187#define GPIO_PXDS1_OFFSET (0xD0) /* r, 32, 0x00000000 */
188#define GPIO_PXDS1S_OFFSET (0xD4) /* w, 32, 0x00000000 */
189#define GPIO_PXDS1C_OFFSET (0xD8) /* w, 32, 0x00000000 */
190#define GPIO_PXDS2_OFFSET (0xE0) /* r, 32, 0x00000000 */
191#define GPIO_PXDS2S_OFFSET (0xE4) /* w, 32, 0x00000000 */
192#define GPIO_PXDS2C_OFFSET (0xE8) /* w, 32, 0x00000000 */
193#define GPIO_PXSL_OFFSET (0xF0) /* r, 32, 0x00000000 */
194#define GPIO_PXSLS_OFFSET (0xF4) /* w, 32, 0x00000000 */
195#define GPIO_PXSLC_OFFSET (0xF8) /* w, 32, 0x00000000 */
196
197/*
198 * GPIO registers address definition
199 */
200#define GPIO_PXPIN(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPIN_OFFSET)
201#define GPIO_PXDAT(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDAT_OFFSET)
202#define GPIO_PXDATS(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDATS_OFFSET)
203#define GPIO_PXDATC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDATC_OFFSET)
204#define GPIO_PXIM(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXIM_OFFSET)
205#define GPIO_PXIMS(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXIMS_OFFSET)
206#define GPIO_PXIMC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXIMC_OFFSET)
207#define GPIO_PXPE(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPE_OFFSET)
208#define GPIO_PXPES(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPES_OFFSET)
209#define GPIO_PXPEC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPEC_OFFSET)
210#define GPIO_PXFUN(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFUN_OFFSET)
211#define GPIO_PXFUNS(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFUNS_OFFSET)
212#define GPIO_PXFUNC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFUNC_OFFSET)
213#define GPIO_PXSEL(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSEL_OFFSET)
214#define GPIO_PXSELS(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSELS_OFFSET)
215#define GPIO_PXSELC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSELC_OFFSET)
216#define GPIO_PXDIR(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDIR_OFFSET)
217#define GPIO_PXDIRS(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDIRS_OFFSET)
218#define GPIO_PXDIRC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDIRC_OFFSET)
219#define GPIO_PXTRG(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXTRG_OFFSET)
220#define GPIO_PXTRGS(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXTRGS_OFFSET)
221#define GPIO_PXTRGC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXTRGC_OFFSET)
222#define GPIO_PXFLG(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFLG_OFFSET)
223#define GPIO_PXFLGC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFLGC_OFFSET)
224#define GPIO_PXDS0(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS0_OFFSET)
225#define GPIO_PXDS0S(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS0S_OFFSET)
226#define GPIO_PXDS0C(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS0C_OFFSET)
227#define GPIO_PXDS1(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS1_OFFSET)
228#define GPIO_PXDS1S(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS1S_OFFSET)
229#define GPIO_PXDS1C(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS1C_OFFSET)
230#define GPIO_PXDS2(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS2_OFFSET)
231#define GPIO_PXDS2S(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS2S_OFFSET)
232#define GPIO_PXDS2C(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS2C_OFFSET)
233#define GPIO_PXSL(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSL_OFFSET)
234#define GPIO_PXSLS(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSLS_OFFSET)
235#define GPIO_PXSLC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSLC_OFFSET)
236
237/* */
238#define GPIO_PORT_NUM 6
239#define MAX_GPIO_NUM 192
240#define GPIO_WAKEUP (30)
241
242#ifndef __MIPS_ASSEMBLER
243
244//n = 0,1,2,3,4,5 (PORTA, PORTB, PORTC, PORTD, PORTE, PORTF)
245#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN(n))
246#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT(n))
247#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS(n))
248#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC(n))
249#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM(n))
250#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS(n))
251#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC(n))
252#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE(n))
253#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES(n))
254#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC(n))
255#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN(n))
256#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS(n))
257#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC(n))
258#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL(n))
259#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS(n))
260#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC(n))
261#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR(n))
262#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS(n))
263#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC(n))
264#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG(n))
265#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS(n))
266#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC(n))
267#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG(n))
268#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC(n))
269#define REG_GPIO_PXDS0(n) REG32(GPIO_PXDS0(n))
270#define REG_GPIO_PXDS0S(n) REG32(GPIO_PXDS0S(n))
271#define REG_GPIO_PXDS0C(n) REG32(GPIO_PXDS0C(n))
272#define REG_GPIO_PXDS1(n) REG32(GPIO_PXDS1(n))
273#define REG_GPIO_PXDS1S(n) REG32(GPIO_PXDS1S(n))
274#define REG_GPIO_PXDS1C(n) REG32(GPIO_PXDS1C(n))
275#define REG_GPIO_PXDS2(n) REG32(GPIO_PXDS2(n))
276#define REG_GPIO_PXDS2S(n) REG32(GPIO_PXDS2S(n))
277#define REG_GPIO_PXDS2C(n) REG32(GPIO_PXDS2C(n))
278#define REG_GPIO_PXSL(n) REG32(GPIO_PXSL(n))
279#define REG_GPIO_PXSLS(n) REG32(GPIO_PXSLS(n))
280#define REG_GPIO_PXSLC(n) REG32(GPIO_PXSLC(n))
281
282/*----------------------------------------------------------------
283 * p is the port number (0,1,2,3,4,5)
284 * o is the pin offset (0-31) inside the port
285 * n is the absolute number of a pin (0-127), regardless of the port
286 */
287
288//----------------------------------------------------------------
289// Function Pins Mode
290
291#define __gpio_as_func0(n) \
292do { \
293 unsigned int p, o; \
294 p = (n) / 32; \
295 o = (n) % 32; \
296 REG_GPIO_PXFUNS(p) = (1 << o); \
297 REG_GPIO_PXTRGC(p) = (1 << o); \
298 REG_GPIO_PXSELC(p) = (1 << o); \
299} while (0)
300
301#define __gpio_as_func1(n) \
302do { \
303 unsigned int p, o; \
304 p = (n) / 32; \
305 o = (n) % 32; \
306 REG_GPIO_PXFUNS(p) = (1 << o); \
307 REG_GPIO_PXTRGC(p) = (1 << o); \
308 REG_GPIO_PXSELS(p) = (1 << o); \
309} while (0)
310
311#define __gpio_as_func2(n) \
312do { \
313 unsigned int p, o; \
314 p = (n) / 32; \
315 o = (n) % 32; \
316 REG_GPIO_PXFUNS(p) = (1 << o); \
317 REG_GPIO_PXTRGS(p) = (1 << o); \
318 REG_GPIO_PXSELC(p) = (1 << o); \
319} while (0)
320
321#define __gpio_as_func3(n) \
322do { \
323 unsigned int p, o; \
324 p = (n) / 32; \
325 o = (n) % 32; \
326 REG_GPIO_PXFUNS(p) = (1 << o); \
327 REG_GPIO_PXTRGS(p) = (1 << o); \
328 REG_GPIO_PXSELS(p) = (1 << o); \
329} while (0)
330
331/*
332 * UART0_TxD, UART0_RxD
333 */
334#define __gpio_as_uart0() \
335do { \
336 unsigned int bits = BIT3 | BIT0; \
337 REG_GPIO_PXFUNS(5) = bits; \
338 REG_GPIO_PXTRGC(5) = bits; \
339 REG_GPIO_PXSELC(5) = bits; \
340 REG_GPIO_PXPES(5) = bits; \
341} while (0)
342
343/*
344 * UART0_TxD, UART0_RxD, UART0_CTS, UART0_RTS
345 */
346#define __gpio_as_uart0_ctsrts() \
347do { \
348 unsigned int bits = BITS_H2L(3, 0); \
349 REG_GPIO_PXFUNS(5) = bits; \
350 REG_GPIO_PXTRGC(5) = bits; \
351 REG_GPIO_PXSELC(5) = bits; \
352 REG_GPIO_PXPES(5) = bits; \
353} while (0)
354
355/*
356 * UART1_TxD, UART1_RxD
357 */
358#define __gpio_as_uart1() \
359do { \
360 unsigned int bits = BIT28 | BIT26; \
361 REG_GPIO_PXFUNS(3) = bits; \
362 REG_GPIO_PXTRGC(3) = bits; \
363 REG_GPIO_PXSELC(3) = bits; \
364 REG_GPIO_PXPES(3) = bits; \
365} while (0)
366
367/*
368 * UART1_TxD, UART1_RxD, UART1_CTS, UART1_RTS
369 */
370#define __gpio_as_uart1_ctsrts() \
371do { \
372 unsigned int bits = BITS_H2L(29, 26); \
373 REG_GPIO_PXFUNS(3) = bits; \
374 REG_GPIO_PXTRGC(3) = bits; \
375 REG_GPIO_PXSELC(3) = bits; \
376 REG_GPIO_PXPES(3) = bits; \
377} while (0)
378
379/*
380 * UART2_TxD, UART2_RxD
381 */
382#define __gpio_as_uart2() \
383do { \
384 unsigned int bits = BIT30 | BIT28; \
385 REG_GPIO_PXFUNS(2) = bits; \
386 REG_GPIO_PXTRGC(2) = bits; \
387 REG_GPIO_PXSELC(2) = bits; \
388 REG_GPIO_PXPES(2) = bits; \
389} while (0)
390
391/*
392 * UART2_TxD, UART2_RxD, UART2_CTS, UART2_RTS
393 */
394#define __gpio_as_uart2_ctsrts() \
395do { \
396 unsigned int bits = BITS_H2L(31, 28); \
397 REG_GPIO_PXFUNS(2) = bits; \
398 REG_GPIO_PXTRGC(2) = bits; \
399 REG_GPIO_PXSELC(2) = bits; \
400 REG_GPIO_PXPES(2) = bits; \
401} while (0)
402
403/* WARNING: the folloing macro do NOT check */
404/*
405 * UART3_TxD, UART3_RxD
406 */
407#define __gpio_as_uart3() \
408do { \
409 unsigned int bits = BIT12; \
410 REG_GPIO_PXFUNS(3) = bits; \
411 REG_GPIO_PXTRGC(3) = bits; \
412 REG_GPIO_PXSELS(3) = bits; \
413 REG_GPIO_PXPES(3) = bits; \
414 bits = BIT5; \
415 REG_GPIO_PXFUNS(4) = bits; \
416 REG_GPIO_PXTRGC(4) = bits; \
417 REG_GPIO_PXSELS(4) = bits; \
418 REG_GPIO_PXPES(4) = bits; \
419} while (0)
420/*
421 * UART3_TxD, UART3_RxD, UART3_CTS, UART3_RTS
422 */
423#define __gpio_as_uart3_ctsrts() \
424do { \
425 REG_GPIO_PXFUNS(3) = (1 << 12); \
426 REG_GPIO_PXTRGC(3) = (1 << 12); \
427 REG_GPIO_PXSELC(3) = (1 << 12); \
428 REG_GPIO_PXPES(3) = (1 << 12); \
429 REG_GPIO_PXFUNS(4) = 0x00000320; \
430 REG_GPIO_PXTRGC(4) = 0x00000320; \
431 REG_GPIO_PXSELS(4) = 0x00000020; \
432 REG_GPIO_PXSELC(4) = 0x00000300; \
433 REG_GPIO_PXPES(4) = 0x00000320; \
434} while (0)
435
436/*
437 * SD0 ~ SD7, CS1#, CLE, ALE, FRE#, FWE#, FRB#
438 * @n: chip select number(1 ~ 6)
439 */
440#define __gpio_as_nand_8bit(n) \
441do { \
442 \
443 REG_GPIO_PXFUNS(0) = 0x000c00ff; /* SD0 ~ SD7, FRE#, FWE# */ \
444 REG_GPIO_PXSELC(0) = 0x000c00ff; \
445 REG_GPIO_PXTRGC(0) = 0x000c00ff; \
446 REG_GPIO_PXPES(0) = 0x000c00ff; \
447 REG_GPIO_PXFUNS(1) = 0x00000003; /* CLE(SA0_CL), ALE(SA1_AL) */ \
448 REG_GPIO_PXSELC(1) = 0x00000003; \
449 REG_GPIO_PXTRGC(1) = 0x00000003; \
450 REG_GPIO_PXPES(1) = 0x00000003; \
451 \
452 REG_GPIO_PXFUNS(0) = 0x00200000 << ((n)-1); /* CSn */ \
453 REG_GPIO_PXSELC(0) = 0x00200000 << ((n)-1); \
454 REG_GPIO_PXTRGC(0) = 0x00200000 << ((n)-1); \
455 REG_GPIO_PXPES(0) = 0x00200000 << ((n)-1); \
456 \
457 REG_GPIO_PXFUNC(0) = 0x00100000; /* FRB#(input) */ \
458 REG_GPIO_PXSELC(0) = 0x00100000; \
459 REG_GPIO_PXDIRC(0) = 0x00100000; \
460 REG_GPIO_PXPES(0) = 0x00100000; \
461} while (0)
462
463#define __gpio_as_nand_16bit(n) \
464do { \
465 \
466 REG_GPIO_PXFUNS(0) = 0x000cffff; /* SD0 ~ SD15, CS1#, FRE#, FWE# */ \
467 REG_GPIO_PXSELC(0) = 0x000cffff; \
468 REG_GPIO_PXTRGC(0) = 0x000cffff; \
469 REG_GPIO_PXPES(0) = 0x000cffff; \
470 REG_GPIO_PXFUNS(1) = 0x00000003; /* CLE(SA2), ALE(SA3) */ \
471 REG_GPIO_PXSELC(1) = 0x00000003; \
472 REG_GPIO_PXTRGC(1) = 0x00000003; \
473 REG_GPIO_PXPES(1) = 0x00000003; \
474 \
475 REG_GPIO_PXFUNS(0) = 0x00200000 << ((n)-1); /* CSn */ \
476 REG_GPIO_PXSELC(0) = 0x00200000 << ((n)-1); \
477 REG_GPIO_PXTRGC(0) = 0x00200000 << ((n)-1); \
478 REG_GPIO_PXPES(0) = 0x00200000 << ((n)-1); \
479 \
480 REG_GPIO_PXFUNC(0) = 0x00100000; /* FRB#(input) */ \
481 REG_GPIO_PXSELC(0) = 0x00100000; \
482 REG_GPIO_PXDIRC(0) = 0x00100000; \
483 REG_GPIO_PXPES(0) = 0x00100000; \
484} while (0)
485
486/*
487 * SLCD
488 */
489#define __gpio_as_slcd_16bit() \
490do { \
491 REG_GPIO_PXFUNS(2) = 0x03cff0fc; \
492 REG_GPIO_PXTRGC(2) = 0x03cff0fc; \
493 REG_GPIO_PXSELC(2) = 0x03cff0fc; \
494 REG_GPIO_PXPES(2) = 0x03cff0fc; \
495} while (0)
496
497/*
498 * LCD_R3~LCD_R7, LCD_G2~LCD_G7, LCD_B3~LCD_B7,
499 * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
500 */
501#define __gpio_as_lcd_16bit() \
502do { \
503 REG_GPIO_PXFUNS(2) = 0x0f8ff3f8; \
504 REG_GPIO_PXTRGC(2) = 0x0f8ff3f8; \
505 REG_GPIO_PXSELC(2) = 0x0f8ff3f8; \
506 REG_GPIO_PXPES(2) = 0x0f8ff3f8; \
507} while (0)
508
509/*
510 * LCD_R2~LCD_R7, LCD_G2~LCD_G7, LCD_B2~LCD_B7,
511 * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
512 */
513#define __gpio_as_lcd_18bit() \
514do { \
515 REG_GPIO_PXFUNS(2) = 0x0fcff3fc; \
516 REG_GPIO_PXTRGC(2) = 0x0fcff3fc; \
517 REG_GPIO_PXSELC(2) = 0x0fcff3fc; \
518 REG_GPIO_PXPES(2) = 0x0fcff3fc; \
519} while (0)
520
521/*
522 * LCD_R0~LCD_R7, LCD_G0~LCD_G7, LCD_B0~LCD_B7,
523 * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
524 */
525#define __gpio_as_lcd_24bit() \
526do { \
527 REG_GPIO_PXFUNS(2) = 0x0fffffff; \
528 REG_GPIO_PXTRGC(2) = 0x0fffffff; \
529 REG_GPIO_PXSELC(2) = 0x0fffffff; \
530 REG_GPIO_PXPES(2) = 0x0fffffff; \
531} while (0)
532
533/*
534 * LCD_R0~LCD_R7, LCD_G0~LCD_G7, LCD_B0~LCD_B7,
535 * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
536 */
537#define __gpio_clear_lcd_24bit() \
538do { \
539 REG_GPIO_PXFUNC(2) = 0x0fffffff; \
540 REG_GPIO_PXTRGC(2) = 0x0fffffff; \
541 REG_GPIO_PXSELC(2) = 0x0fffffff; \
542 REG_GPIO_PXDIRS(2) = 0x0fffffff; \
543 REG_GPIO_PXDATC(2) = 0x0fffffff; \
544 REG_GPIO_PXPES(2) = 0x0fffffff; \
545} while (0)
546
547/* Set data pin driver strength v: 0~7 */
548#define __gpio_set_lcd_data_driving_strength(v) \
549do { \
550 unsigned int d; \
551 d = v & 0x1; \
552 if(d) REG_GPIO_PXDS0S(2) = 0x0ff3fcff; \
553 else REG_GPIO_PXDS0C(2) = 0x0ff3fcff; \
554 d = v & 0x2; \
555 if(d) REG_GPIO_PXDS1S(2) = 0x0ff3fcff; \
556 else REG_GPIO_PXDS1C(2) = 0x0ff3fcff; \
557 d = v & 0x4; \
558 if(d) REG_GPIO_PXDS2S(2) = 0x0ff3fcff; \
559 else REG_GPIO_PXDS2C(2) = 0x0ff3fcff; \
560} while(0)
561/* Set HSYNC VSYNC DE driver strength v: 0~7 */
562#define __gpio_set_lcd_sync_driving_strength(v) \
563do { \
564 unsigned int d; \
565 d = v & 0x1; \
566 if(d) REG_GPIO_PXDS0S(2) = 0x000c0200; \
567 else REG_GPIO_PXDS0C(2) = 0x000c0200; \
568 d = v & 0x2; \
569 if(d) REG_GPIO_PXDS1S(2) = 0x000c0200; \
570 else REG_GPIO_PXDS1C(2) = 0x000c0200; \
571 d = v & 0x4; \
572 if(d) REG_GPIO_PXDS2S(2) = 0x000c0200; \
573 else REG_GPIO_PXDS2C(2) = 0x000c0200; \
574} while(0)
575/* Set PCLK driver strength v: 0~7 */
576#define __gpio_set_lcd_clk_driving_strength(v) \
577do { \
578 unsigned int d; \
579 d = v & 0x1; \
580 if(d) REG_GPIO_PXDS0S(2) = (1 << 8); \
581 else REG_GPIO_PXDS0C(2) = (1 << 8); \
582 d = v & 0x2; \
583 if(d) REG_GPIO_PXDS1S(2) = (1 << 8); \
584 else REG_GPIO_PXDS1C(2) = (1 << 8); \
585 d = v & 0x4; \
586 if(d) REG_GPIO_PXDS2S(2) = (1 << 8); \
587 else REG_GPIO_PXDS2C(2) = (1 << 8); \
588} while(0)
589
590/* Set fast slew rate */
591#define __gpio_set_lcd_data_fslew(n) \
592do { \
593 unsigned int p, o; \
594 p = (n) / 32; \
595 o = (n) % 32; \
596 REG_GPIO_PXSLS(p) = 0x0ff3fcff; \
597} while(0)
598
599/* Set slow slew rate */
600#define __gpio_set_lcd_data_sslew(n) \
601do { \
602 unsigned int p, o; \
603 p = (n) / 32; \
604 o = (n) % 32; \
605 REG_GPIO_PXSLC(p) = 0x0ff3fcff; \
606} while(0)
607
608/* Set fast slew rate */
609#define __gpio_set_lcd_sync_fslew(n) \
610do { \
611 unsigned int p, o; \
612 p = (n) / 32; \
613 o = (n) % 32; \
614 REG_GPIO_PXSLS(p) = 0x000c0200; \
615} while(0)
616
617/* Set slow slew rate */
618#define __gpio_set_lcd_sync_sslew(n) \
619do { \
620 unsigned int p, o; \
621 p = (n) / 32; \
622 o = (n) % 32; \
623 REG_GPIO_PXSLC(p) = 0x000c0200; \
624} while(0)
625
626/* Set fast slew rate */
627#define __gpio_set_lcd_pclk_fslew(n) \
628do { \
629 unsigned int p, o; \
630 p = (n) / 32; \
631 o = (n) % 32; \
632 REG_GPIO_PXSLS(p) = (1 << 8); \
633} while(0)
634
635/* Set slow slew rate */
636#define __gpio_set_lcd_pclk_sslew(n) \
637do { \
638 unsigned int p, o; \
639 p = (n) / 32; \
640 o = (n) % 32; \
641 REG_GPIO_PXSLC(p) = (1 << 8); \
642} while(0)
643
644/*
645 * LCD_CLS, LCD_SPL, LCD_PS, LCD_REV
646 */
647#define __gpio_as_lcd_special() \
648do { \
649 REG_GPIO_PXFUNS(2) = 0x0fffffff; \
650 REG_GPIO_PXTRGC(2) = 0x0fffffff; \
651 REG_GPIO_PXSELC(2) = 0x0feffbfc; \
652 REG_GPIO_PXSELS(2) = 0x00100403; \
653 REG_GPIO_PXPES(2) = 0x0fffffff; \
654} while (0)
655
656#define __gpio_as_epd() \
657do { \
658 REG_GPIO_PXFUNS(1) = 0x00011e00; \
659 REG_GPIO_PXTRGS(1) = 0x00011e00; \
660 REG_GPIO_PXSELS(1) = 0x00011e00; \
661 REG_GPIO_PXPES(1) = 0x00011e00; \
662} while (0)
663/*
664 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
665 */
666#define __gpio_as_cim() \
667do { \
668 REG_GPIO_PXFUNS(1) = 0x0003ffc0; \
669 REG_GPIO_PXTRGC(1) = 0x0003ffc0; \
670 REG_GPIO_PXSELC(1) = 0x0003ffc0; \
671 REG_GPIO_PXPES(1) = 0x0003ffc0; \
672} while (0)
673
674/*
675 * SDATO, SDATI, BCLK, SYNC, SCLK_RSTN(gpio sepc) or
676 * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET(aic spec)
677 */
678#define __gpio_as_aic() \
679do { \
680 REG_GPIO_PXFUNS(3) = 0x00003000; \
681 REG_GPIO_PXTRGC(3) = 0x00003000; \
682 REG_GPIO_PXSELS(3) = 0x00001000; \
683 REG_GPIO_PXSELC(3) = 0x00002000; \
684 REG_GPIO_PXPES(3) = 0x00003000; \
685 REG_GPIO_PXFUNS(4) = 0x000000e0; \
686 REG_GPIO_PXTRGS(4) = 0x00000020; \
687 REG_GPIO_PXTRGC(4) = 0x000000c0; \
688 REG_GPIO_PXSELC(4) = 0x000000e0; \
689 REG_GPIO_PXPES(4) = 0x000000e0; \
690} while (0)
691
692#define __gpio_as_spdif() \
693do { \
694 REG_GPIO_PXFUNS(3) = 0x00003000; \
695 REG_GPIO_PXTRGC(3) = 0x00003000; \
696 REG_GPIO_PXSELS(3) = 0x00001000; \
697 REG_GPIO_PXSELC(3) = 0x00002000; \
698 REG_GPIO_PXPES(3) = 0x00003000; \
699 REG_GPIO_PXFUNS(4) = 0x000038e0; \
700 REG_GPIO_PXTRGC(4) = 0x000038c0; \
701 REG_GPIO_PXTRGS(4) = 0x00000020; \
702 REG_GPIO_PXSELC(4) = 0x000038e0; \
703 REG_GPIO_PXPES(4) = 0x000038e0; \
704} while (0)
705
706/*
707 * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D3
708 */
709#define __gpio_as_msc0_pa_4bit() \
710do { \
711 REG_GPIO_PXFUNS(0) = 0x00fc0000; \
712 REG_GPIO_PXTRGC(0) = 0x00fc0000; \
713 REG_GPIO_PXSELS(0) = 0x00ec0000; \
714 REG_GPIO_PXSELC(0) = 0x00100000; \
715 REG_GPIO_PXPES(0) = 0x00fc0000; \
716} while (0)
717
718/*
719 * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D7
720 */
721#define __gpio_as_msc0_pe_8bit() \
722do { \
723 REG_GPIO_PXFUNS(4) = 0x3ff00000; \
724 REG_GPIO_PXTRGC(4) = 0x3ff00000; \
725 REG_GPIO_PXSELC(4) = 0x3ff00000; \
726 REG_GPIO_PXPES(4) = 0x3ff00000; \
727 REG_GPIO_PXDS0S(4) = 0x3ff00000; \
728} while (0)
729/*
730 * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D3
731 */
732#define __gpio_as_msc0_pe_4bit() \
733do { \
734 REG_GPIO_PXFUNS(4) = 0x30f00000; \
735 REG_GPIO_PXTRGC(4) = 0x30f00000; \
736 REG_GPIO_PXSELC(4) = 0x30f00000; \
737 REG_GPIO_PXPES(4) = 0x30f00000; \
738 REG_GPIO_PXDS0S(4) = 0x30f00000; \
739} while (0)
740
741#define __gpio_as_msc0_boot() \
742do { \
743 REG_GPIO_PXFUNS(0) = 0x00ec0000; \
744 REG_GPIO_PXTRGC(0) = 0x00ec0000; \
745 REG_GPIO_PXSELS(0) = 0x00ec0000; \
746 REG_GPIO_PXPES(0) = 0x00ec0000; \
747 REG_GPIO_PXFUNS(0) = 0x00100000; \
748 REG_GPIO_PXTRGC(0) = 0x00100000; \
749 REG_GPIO_PXSELC(0) = 0x00100000; \
750 REG_GPIO_PXPES(0) = 0x00100000; \
751 \
752} while (0)
753
754/*
755 * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D7
756 */
757#define __gpio_as_msc1_pe_8bit() \
758do { \
759 REG_GPIO_PXFUNS(4) = 0x3ff00000; \
760 REG_GPIO_PXTRGC(4) = 0x3ff00000; \
761 REG_GPIO_PXSELS(4) = 0x3ff00000; \
762 REG_GPIO_PXPES(4) = 0x3ff00000; \
763 REG_GPIO_PXDS0S(4) = 0x3ff00000; \
764} while (0)
765/*
766 * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D3
767 */
768#define __gpio_as_msc1_pe_4bit() \
769do { \
770 REG_GPIO_PXFUNS(4) = 0x30f00000; \
771 REG_GPIO_PXTRGC(4) = 0x30f00000; \
772 REG_GPIO_PXSELS(4) = 0x30f00000; \
773 REG_GPIO_PXPES(4) = 0x30f00000; \
774 REG_GPIO_PXDS0S(4) = 0x30f00000; \
775} while (0)
776
777/*
778 * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D3
779 */
780#define __gpio_as_msc1_pd_4bit() \
781do { \
782 REG_GPIO_PXFUNS(3) = 0x03f00000; \
783 REG_GPIO_PXTRGC(3) = 0x03f00000; \
784 REG_GPIO_PXSELC(3) = 0x03f00000; \
785 REG_GPIO_PXPES(3) = 0x03f00000; \
786 REG_GPIO_PXDS0S(3) = 0x03f00000; \
787} while (0)
788
789/* Port B
790 * MSC2_CMD, MSC2_CLK, MSC2_D0 ~ MSC2_D3
791 */
792#define __gpio_as_msc2_pb_4bit() \
793do { \
794 REG_GPIO_PXFUNS(1) = 0xf0300000; \
795 REG_GPIO_PXTRGC(1) = 0xf0300000; \
796 REG_GPIO_PXSELC(1) = 0xf0300000; \
797 REG_GPIO_PXPES(1) = 0xf0300000; \
798 REG_GPIO_PXDS0S(1) = 0xf0300000; \
799} while (0)
800
801/*
802 * MSC2_CMD, MSC2_CLK, MSC2_D0 ~ MSC2_D7
803 */
804#define __gpio_as_msc2_pe_8bit() \
805do { \
806 REG_GPIO_PXFUNS(4) = 0x3ff00000; \
807 REG_GPIO_PXTRGS(4) = 0x3ff00000; \
808 REG_GPIO_PXSELC(4) = 0x3ff00000; \
809 REG_GPIO_PXPES(4) = 0x3ff00000; \
810 REG_GPIO_PXDS0S(4) = 0x3ff00000; \
811} while (0)
812/*
813 * MSC2_CMD, MSC2_CLK, MSC2_D0 ~ MSC2_D3
814 */
815#define __gpio_as_msc2_pe_4bit() \
816do { \
817 REG_GPIO_PXFUNS(4) = 0x30f00000; \
818 REG_GPIO_PXTRGS(4) = 0x30f00000; \
819 REG_GPIO_PXSELC(4) = 0x30f00000; \
820 REG_GPIO_PXPES(4) = 0x30f00000; \
821 REG_GPIO_PXDS0S(4)= 0x30f00000; \
822} while (0)
823#define __gpio_as_msc0_4bit __gpio_as_msc0_pe_4bit /* default as msc0 4bit */
824#define __gpio_as_msc1_4bit __gpio_as_msc1_pd_4bit /* msc1 only support 4bit */
825#define __gpio_as_msc __gpio_as_msc0_4bit /* default as msc0 4bit */
826#define __gpio_as_msc0 __gpio_as_msc0_4bit /* msc0 default as 4bit */
827#define __gpio_as_msc1 __gpio_as_msc1_4bit /* msc1 only support 4bit */
828#define __gpio_as_msc0_8bit __gpio_as_msc0_pe_8bit /* default as msc0 8bit */
829#define __gpio_as_msc1_8bit __gpio_as_msc1_pd_8bit /* msc1 only support 8bit */
830/*
831 * TSCLK, TSSTR, TSFRM, TSFAIL, TSDI0~7
832 */
833#define __gpio_as_tssi_1() \
834do { \
835 REG_GPIO_PXFUNS(1) = 0x0003ffc0; \
836 REG_GPIO_PXTRGC(1) = 0x0003ffc0; \
837 REG_GPIO_PXSELS(1) = 0x0003ffc0; \
838 REG_GPIO_PXPES(1) = 0x0003ffc0; \
839} while (0)
840
841/*
842 * TSCLK, TSSTR, TSFRM, TSFAIL, TSDI0~7
843 */
844#define __gpio_as_tssi_2() \
845do { \
846 REG_GPIO_PXFUNS(1) = 0xfff00000; \
847 REG_GPIO_PXTRGC(1) = 0x0fc00000; \
848 REG_GPIO_PXTRGS(1) = 0xf0300000; \
849 REG_GPIO_PXSELC(1) = 0xfff00000; \
850 REG_GPIO_PXPES(1) = 0xfff00000; \
851} while (0)
852
853/*
854 * SSI_CE0, SSI_CE1, SSI_GPC, SSI_CLK, SSI_DT, SSI_DR
855 */
856#define __gpio_as_ssi() \
857do { \
858 REG_GPIO_PXFUNS(0) = 0x002c0000; /* SSI0_CE0, SSI0_CLK, SSI0_DT */ \
859 REG_GPIO_PXTRGS(0) = 0x002c0000; \
860 REG_GPIO_PXSELC(0) = 0x002c0000; \
861 REG_GPIO_PXPES(0) = 0x002c0000; \
862 \
863 REG_GPIO_PXFUNS(0) = 0x00100000; /* SSI0_DR */ \
864 REG_GPIO_PXTRGC(0) = 0x00100000; \
865 REG_GPIO_PXSELS(0) = 0x00100000; \
866 REG_GPIO_PXPES(0) = 0x00100000; \
867} while (0)
868
869/*
870 * SSI_CE0, SSI_CE2, SSI_GPC, SSI_CLK, SSI_DT, SSI1_DR
871 */
872#define __gpio_as_ssi_1() \
873do { \
874 REG_GPIO_PXFUNS(5) = 0x0000fc00; \
875 REG_GPIO_PXTRGC(5) = 0x0000fc00; \
876 REG_GPIO_PXSELC(5) = 0x0000fc00; \
877 REG_GPIO_PXPES(5) = 0x0000fc00; \
878} while (0)
879
880/* Port B
881 * SSI2_CE0, SSI2_CE2, SSI2_GPC, SSI2_CLK, SSI2_DT, SSI12_DR
882 */
883#define __gpio_as_ssi2_1() \
884do { \
885 REG_GPIO_PXFUNS(5) = 0xf0300000; \
886 REG_GPIO_PXTRGC(5) = 0xf0300000; \
887 REG_GPIO_PXSELS(5) = 0xf0300000; \
888 REG_GPIO_PXPES(5) = 0xf0300000; \
889} while (0)
890
891#define __gpio_as_pcm0() \
892do { \
893 REG_GPIO_PXFUNS(3) = 0xf; \
894 REG_GPIO_PXTRGC(3) = 0xf; \
895 REG_GPIO_PXSELC(3) = 0xf; \
896 REG_GPIO_PXPES(3) = 0xf; \
897} while (0)
898
899#define __gpio_as_pcm1() \
900do { \
901 REG_GPIO_PXFUNS(3) = 0x1000; \
902 REG_GPIO_PXTRGS(3) = 0x1000; \
903 REG_GPIO_PXSELC(3) = 0x1000; \
904 REG_GPIO_PXPES(3) = 0x1000; \
905 REG_GPIO_PXFUNS(4) = 0x1000; \
906 REG_GPIO_PXTRGC(4) = 0x300; \
907 REG_GPIO_PXTRGS(4) = 0x20; \
908 REG_GPIO_PXSELS(4) = 0x320; \
909 REG_GPIO_PXPES(4) = 0x320; \
910} while (0)
911/*
912 * I2C_SCK, I2C_SDA
913 */
914#define __gpio_as_i2c(n) \
915do { \
916 REG_GPIO_PXFUNS(3+(n)) = 0xc0000000; \
917 REG_GPIO_PXTRGC(3+(n)) = 0xc0000000; \
918 REG_GPIO_PXSELC(3+(n)) = 0xc0000000; \
919 REG_GPIO_PXPES(3+(n)) = 0xc0000000; \
920} while (0)
921
922/*
923 * PWM0
924 */
925#define __gpio_as_pwm0() \
926do { \
927 REG_GPIO_PXFUNS(4) = 0x1; \
928 REG_GPIO_PXTRGC(4) = 0x1; \
929 REG_GPIO_PXSELC(4) = 0x1; \
930 REG_GPIO_PXPES(4) = 0x1; \
931} while (0)
932
933/*
934 * PWM1
935 */
936#define __gpio_as_pwm1() \
937do { \
938 REG_GPIO_PXFUNS(4) = 0x2; \
939 REG_GPIO_PXTRGC(4) = 0x2; \
940 REG_GPIO_PXSELC(4) = 0x2; \
941 REG_GPIO_PXPEC(4) = 0x2; \
942} while (0)
943
944/*
945 * PWM2
946 */
947#define __gpio_as_pwm2() \
948do { \
949 REG_GPIO_PXFUNS(4) = 0x4; \
950 REG_GPIO_PXTRGC(4) = 0x4; \
951 REG_GPIO_PXSELC(4) = 0x4; \
952 REG_GPIO_PXPES(4) = 0x4; \
953} while (0)
954
955/*
956 * PWM3
957 */
958#define __gpio_as_pwm3() \
959do { \
960 REG_GPIO_PXFUNS(4) = 0x8; \
961 REG_GPIO_PXTRGC(4) = 0x8; \
962 REG_GPIO_PXSELC(4) = 0x8; \
963 REG_GPIO_PXPES(4) = 0x8; \
964} while (0)
965
966/*
967 * PWM4
968 */
969#define __gpio_as_pwm4() \
970do { \
971 REG_GPIO_PXFUNS(4) = 0x10; \
972 REG_GPIO_PXTRGC(4) = 0x10; \
973 REG_GPIO_PXSELC(4) = 0x10; \
974 REG_GPIO_PXPES(4) = 0x10; \
975} while (0)
976
977/*
978 * PWM5
979 */
980#define __gpio_as_pwm5() \
981do { \
982 REG_GPIO_PXFUNS(4) = 0x20; \
983 REG_GPIO_PXTRGC(4) = 0x20; \
984 REG_GPIO_PXSELC(4) = 0x20; \
985 REG_GPIO_PXPES(4) = 0x20; \
986} while (0)
987
988/*
989 * n = 0 ~ 5
990 */
991#define __gpio_as_pwm(n) __gpio_as_pwm##n()
992
993/*
994 * OWI - PA29 function 1
995 */
996#define __gpio_as_owi() \
997do { \
998 REG_GPIO_PXFUNS(0) = 0x20000000; \
999 REG_GPIO_PXTRGC(0) = 0x20000000; \
1000 REG_GPIO_PXSELS(0) = 0x20000000; \
1001} while (0)
1002
1003/*
1004 * SCC - PD08 function 0
1005 * PD09 function 0
1006 */
1007#define __gpio_as_scc() \
1008do { \
1009 REG_GPIO_PXFUNS(3) = 0xc0000300; \
1010 REG_GPIO_PXTRGC(3) = 0xc0000300; \
1011 REG_GPIO_PXSELC(3) = 0xc0000300; \
1012} while (0)
1013
1014#define __gpio_as_otg_drvvbus() \
1015do { \
1016 REG_GPIO_PXDATC(4) = (1 << 10); \
1017 REG_GPIO_PXPEC(4) = (1 << 10); \
1018 REG_GPIO_PXSELC(4) = (1 << 10); \
1019 REG_GPIO_PXTRGC(4) = (1 << 10); \
1020 REG_GPIO_PXFUNS(4) = (1 << 10); \
1021} while (0)
1022
1023//-------------------------------------------
1024// GPIO or Interrupt Mode
1025
1026#define __gpio_get_port(p) (REG_GPIO_PXPIN(p))
1027
1028#define __gpio_port_as_output(p, o) \
1029do { \
1030 REG_GPIO_PXFUNC(p) = (1 << (o)); \
1031 REG_GPIO_PXSELC(p) = (1 << (o)); \
1032 REG_GPIO_PXDIRS(p) = (1 << (o)); \
1033 REG_GPIO_PXPES(p) = (1 << (o)); \
1034} while (0)
1035
1036#define __gpio_port_as_input(p, o) \
1037do { \
1038 REG_GPIO_PXFUNC(p) = (1 << (o)); \
1039 REG_GPIO_PXSELC(p) = (1 << (o)); \
1040 REG_GPIO_PXDIRC(p) = (1 << (o)); \
1041} while (0)
1042
1043#define __gpio_as_output(n) \
1044do { \
1045 unsigned int p, o; \
1046 p = (n) / 32; \
1047 o = (n) % 32; \
1048 __gpio_port_as_output(p, o); \
1049} while (0)
1050
1051#define __gpio_as_input(n) \
1052do { \
1053 unsigned int p, o; \
1054 p = (n) / 32; \
1055 o = (n) % 32; \
1056 __gpio_port_as_input(p, o); \
1057} while (0)
1058
1059#define __gpio_set_pin(n) \
1060do { \
1061 unsigned int p, o; \
1062 p = (n) / 32; \
1063 o = (n) % 32; \
1064 REG_GPIO_PXDATS(p) = (1 << o); \
1065} while (0)
1066
1067#define __gpio_clear_pin(n) \
1068do { \
1069 unsigned int p, o; \
1070 p = (n) / 32; \
1071 o = (n) % 32; \
1072 REG_GPIO_PXDATC(p) = (1 << o); \
1073} while (0)
1074
1075#define __gpio_get_pin(n) \
1076({ \
1077 unsigned int p, o, v; \
1078 p = (n) / 32; \
1079 o = (n) % 32; \
1080 if (__gpio_get_port(p) & (1 << o)) \
1081 v = 1; \
1082 else \
1083 v = 0; \
1084 v; \
1085})
1086
1087#define __gpio_as_irq_high_level(n) \
1088do { \
1089 unsigned int p, o; \
1090 p = (n) / 32; \
1091 o = (n) % 32; \
1092 REG_GPIO_PXIMS(p) = (1 << o); \
1093 REG_GPIO_PXTRGC(p) = (1 << o); \
1094 REG_GPIO_PXFUNC(p) = (1 << o); \
1095 REG_GPIO_PXSELS(p) = (1 << o); \
1096 REG_GPIO_PXDIRS(p) = (1 << o); \
1097 REG_GPIO_PXFLGC(p) = (1 << o); \
1098 REG_GPIO_PXIMC(p) = (1 << o); \
1099} while (0)
1100
1101#define __gpio_as_irq_low_level(n) \
1102do { \
1103 unsigned int p, o; \
1104 p = (n) / 32; \
1105 o = (n) % 32; \
1106 REG_GPIO_PXIMS(p) = (1 << o); \
1107 REG_GPIO_PXTRGC(p) = (1 << o); \
1108 REG_GPIO_PXFUNC(p) = (1 << o); \
1109 REG_GPIO_PXSELS(p) = (1 << o); \
1110 REG_GPIO_PXDIRC(p) = (1 << o); \
1111 REG_GPIO_PXFLGC(p) = (1 << o); \
1112 REG_GPIO_PXIMC(p) = (1 << o); \
1113} while (0)
1114
1115#define __gpio_as_irq_rise_edge(n) \
1116do { \
1117 unsigned int p, o; \
1118 p = (n) / 32; \
1119 o = (n) % 32; \
1120 REG_GPIO_PXIMS(p) = (1 << o); \
1121 REG_GPIO_PXTRGS(p) = (1 << o); \
1122 REG_GPIO_PXFUNC(p) = (1 << o); \
1123 REG_GPIO_PXSELS(p) = (1 << o); \
1124 REG_GPIO_PXDIRS(p) = (1 << o); \
1125 REG_GPIO_PXFLGC(p) = (1 << o); \
1126 REG_GPIO_PXIMC(p) = (1 << o); \
1127} while (0)
1128
1129#define __gpio_as_irq_fall_edge(n) \
1130do { \
1131 unsigned int p, o; \
1132 p = (n) / 32; \
1133 o = (n) % 32; \
1134 REG_GPIO_PXIMS(p) = (1 << o); \
1135 REG_GPIO_PXTRGS(p) = (1 << o); \
1136 REG_GPIO_PXFUNC(p) = (1 << o); \
1137 REG_GPIO_PXSELS(p) = (1 << o); \
1138 REG_GPIO_PXDIRC(p) = (1 << o); \
1139 REG_GPIO_PXFLGC(p) = (1 << o); \
1140 REG_GPIO_PXIMC(p) = (1 << o); \
1141} while (0)
1142
1143#define __gpio_mask_irq(n) \
1144do { \
1145 unsigned int p, o; \
1146 p = (n) / 32; \
1147 o = (n) % 32; \
1148 REG_GPIO_PXIMS(p) = (1 << o); \
1149} while (0)
1150
1151#define __gpio_unmask_irq(n) \
1152do { \
1153 unsigned int p, o; \
1154 p = (n) / 32; \
1155 o = (n) % 32; \
1156 REG_GPIO_PXIMC(p) = (1 << o); \
1157} while (0)
1158
1159#define __gpio_ack_irq(n) \
1160do { \
1161 unsigned int p, o; \
1162 p = (n) / 32; \
1163 o = (n) % 32; \
1164 REG_GPIO_PXFLGC(p) = (1 << o); \
1165} while (0)
1166
1167#define __gpio_get_irq() \
1168({ \
1169 unsigned int tmp, v = 0; \
1170 for (int p = 5; p >= 0; p--) { \
1171 tmp = REG_GPIO_PXFLG(p); \
1172 for (int i = 0; i < 32; i++) \
1173 if (tmp & (1 << i)) \
1174 v = (32*p + i); \
1175 } \
1176 v; \
1177})
1178
1179#define __gpio_group_irq(n) \
1180({ \
1181 register int tmp, i; \
1182 tmp = REG_GPIO_PXFLG(n) & (~REG_GPIO_PXIM(n)); \
1183 for (i=31;i>=0;i--) \
1184 if (tmp & (1 << i)) \
1185 break; \
1186 i; \
1187})
1188
1189#define __gpio_enable_pull(n) \
1190do { \
1191 unsigned int p, o; \
1192 p = (n) / 32; \
1193 o = (n) % 32; \
1194 REG_GPIO_PXPEC(p) = (1 << o); \
1195} while (0)
1196
1197#define __gpio_disable_pull(n) \
1198do { \
1199 unsigned int p, o; \
1200 p = (n) / 32; \
1201 o = (n) % 32; \
1202 REG_GPIO_PXPES(p) = (1 << o); \
1203} while (0)
1204
1205/* Set pin driver strength v: 0~7 */
1206#define __gpio_set_driving_strength(n, v) \
1207do { \
1208 unsigned int p, o, d; \
1209 p = (n) / 32; \
1210 o = (n) % 32; \
1211 d = v & 0x1; \
1212 if(d) REG_GPIO_PXDS0S(p) = (1 << o); \
1213 else REG_GPIO_PXDS0C(p) = (1 << o); \
1214 d = v & 0x2; \
1215 if(d) REG_GPIO_PXDS1S(p) = (1 << o); \
1216 else REG_GPIO_PXDS1C(p) = (1 << o); \
1217 d = v & 0x4; \
1218 if(d) REG_GPIO_PXDS2S(p) = (1 << o); \
1219 else REG_GPIO_PXDS2C(p) = (1 << o); \
1220} while(0)
1221
1222/* Set fast slew rate */
1223#define __gpio_set_fslew(n) \
1224do { \
1225 unsigned int p, o; \
1226 p = (n) / 32; \
1227 o = (n) % 32; \
1228 REG_GPIO_PXSLS(p) = (1 << o); \
1229} while(0)
1230
1231/* Set slow slew rate */
1232#define __gpio_set_sslew(n) \
1233do { \
1234 unsigned int p, o; \
1235 p = (n) / 32; \
1236 o = (n) % 32; \
1237 REG_GPIO_PXSLC(p) = (1 << o); \
1238} while(0)
1239
1240#endif /* __MIPS_ASSEMBLER */
1241
1242#define DMAC_BASE 0xB3420000
1243
1244/*************************************************************************
1245 * DMAC (DMA Controller)
1246 *************************************************************************/
1247
1248#define MAX_DMA_NUM 12 /* max 12 channels */
1249#define MAX_MDMA_NUM 3 /* max 3 channels */
1250#define MAX_BDMA_NUM 3 /* max 3 channels */
1251#define HALF_DMA_NUM 6 /* the number of one dma controller's channels */
1252
1253/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
1254
1255#define DMAC_DSAR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x00 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA source address */
1256#define DMAC_DTAR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x04 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA target address */
1257#define DMAC_DTCR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x08 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA transfer count */
1258#define DMAC_DRSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x0c + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA request source */
1259#define DMAC_DCCSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x10 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA control/status */
1260#define DMAC_DCMD(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x14 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA command */
1261#define DMAC_DDA(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x18 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA descriptor address */
1262#define DMAC_DSD(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0xc0 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x04)) /* DMA Stride Address */
1263
1264#define DMAC_DMACR(m) (DMAC_BASE + 0x0300 + 0x100 * (m)) /* DMA control register */
1265#define DMAC_DMAIPR(m) (DMAC_BASE + 0x0304 + 0x100 * (m)) /* DMA interrupt pending */
1266#define DMAC_DMADBR(m) (DMAC_BASE + 0x0308 + 0x100 * (m)) /* DMA doorbell */
1267#define DMAC_DMADBSR(m) (DMAC_BASE + 0x030C + 0x100 * (m)) /* DMA doorbell set */
1268#define DMAC_DMACKE(m) (DMAC_BASE + 0x0310 + 0x100 * (m))
1269#define DMAC_DMACKES(m) (DMAC_BASE + 0x0314 + 0x100 * (m))
1270#define DMAC_DMACKEC(m) (DMAC_BASE + 0x0318 + 0x100 * (m))
1271
1272#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
1273#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
1274#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
1275#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
1276#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
1277#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
1278#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
1279#define REG_DMAC_DSD(n) REG32(DMAC_DSD(n))
1280#define REG_DMAC_DMACR(m) REG32(DMAC_DMACR(m))
1281#define REG_DMAC_DMAIPR(m) REG32(DMAC_DMAIPR(m))
1282#define REG_DMAC_DMADBR(m) REG32(DMAC_DMADBR(m))
1283#define REG_DMAC_DMADBSR(m) REG32(DMAC_DMADBSR(m))
1284#define REG_DMAC_DMACKE(m) REG32(DMAC_DMACKE(m))
1285#define REG_DMAC_DMACKES(m) REG32(DMAC_DMACKES(m))
1286#define REG_DMAC_DMACKEC(m) REG32(DMAC_DMACKEC(m))
1287
1288// DMA request source register
1289#define DMAC_DRSR_RS_BIT 0
1290#define DMAC_DRSR_RS_MASK (0x3f << DMAC_DRSR_RS_BIT)
1291 #define DMAC_DRSR_RS_NAND (1 << DMAC_DRSR_RS_BIT)
1292 #define DMAC_DRSR_RS_BCH_ENC (2 << DMAC_DRSR_RS_BIT)
1293 #define DMAC_DRSR_RS_BCH_DEC (3 << DMAC_DRSR_RS_BIT)
1294 #define DMAC_DRSR_RS_AUTO (0x08 << DMAC_DRSR_RS_BIT)
1295 #define DMAC_DRSR_RS_TSSIIN (0x09 << DMAC_DRSR_RS_BIT)
1296 #define DMAC_DRSR_RS_EXT (0x0c << DMAC_DRSR_RS_BIT)
1297 #define DMAC_DRSR_RS_UART3OUT (0x0e << DMAC_DRSR_RS_BIT)
1298 #define DMAC_DRSR_RS_UART3IN (0x0f << DMAC_DRSR_RS_BIT)
1299 #define DMAC_DRSR_RS_UART2OUT (0x10 << DMAC_DRSR_RS_BIT)
1300 #define DMAC_DRSR_RS_UART2IN (0x11 << DMAC_DRSR_RS_BIT)
1301 #define DMAC_DRSR_RS_UART1OUT (0x12 << DMAC_DRSR_RS_BIT)
1302 #define DMAC_DRSR_RS_UART1IN (0x13 << DMAC_DRSR_RS_BIT)
1303 #define DMAC_DRSR_RS_UART0OUT (0x14 << DMAC_DRSR_RS_BIT)
1304 #define DMAC_DRSR_RS_UART0IN (0x15 << DMAC_DRSR_RS_BIT)
1305 #define DMAC_DRSR_RS_SSI0OUT (0x16 << DMAC_DRSR_RS_BIT)
1306 #define DMAC_DRSR_RS_SSI0IN (0x17 << DMAC_DRSR_RS_BIT)
1307 #define DMAC_DRSR_RS_AICOUT (0x18 << DMAC_DRSR_RS_BIT)
1308 #define DMAC_DRSR_RS_AICIN (0x19 << DMAC_DRSR_RS_BIT)
1309 #define DMAC_DRSR_RS_MSC0OUT (0x1a << DMAC_DRSR_RS_BIT)
1310 #define DMAC_DRSR_RS_MSC0IN (0x1b << DMAC_DRSR_RS_BIT)
1311 #define DMAC_DRSR_RS_TCU (0x1c << DMAC_DRSR_RS_BIT)
1312 #define DMAC_DRSR_RS_SADC (0x1d << DMAC_DRSR_RS_BIT)
1313 #define DMAC_DRSR_RS_MSC1OUT (0x1e << DMAC_DRSR_RS_BIT)
1314 #define DMAC_DRSR_RS_MSC1IN (0x1f << DMAC_DRSR_RS_BIT)
1315 #define DMAC_DRSR_RS_SSI1OUT (0x20 << DMAC_DRSR_RS_BIT)
1316 #define DMAC_DRSR_RS_SSI1IN (0x21 << DMAC_DRSR_RS_BIT)
1317 #define DMAC_DRSR_RS_PMOUT (0x22 << DMAC_DRSR_RS_BIT)
1318 #define DMAC_DRSR_RS_PMIN (0x23 << DMAC_DRSR_RS_BIT)
1319 #define DMAC_DRSR_RS_MSC2OUT (0x24 << DMAC_DRSR_RS_BIT)
1320 #define DMAC_DRSR_RS_MSC2IN (0x25 << DMAC_DRSR_RS_BIT)
1321
1322// DMA channel control/status register
1323#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
1324#define DMAC_DCCSR_DES8 (1 << 30) /* Descriptor 8 Word */
1325#define DMAC_DCCSR_DES4 (0 << 30) /* Descriptor 4 Word */
1326#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
1327#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
1328
1329#define DMAC_DCCSR_AR (1 << 4) /* address error */
1330#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
1331#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
1332#define DMAC_DCCSR_CT (1 << 1) /* count terminated */
1333#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
1334
1335// DMA channel command register
1336#define DMAC_DCMD_EACKS_LOW (1 << 31) /* External DACK Output Level Select, active low */
1337#define DMAC_DCMD_EACKS_HIGH (0 << 31) /* External DACK Output Level Select, active high */
1338#define DMAC_DCMD_EACKM_WRITE (1 << 30) /* External DACK Output Mode Select, output in write cycle */
1339#define DMAC_DCMD_EACKM_READ (0 << 30) /* External DACK Output Mode Select, output in read cycle */
1340#define DMAC_DCMD_ERDM_BIT 28 /* External DREQ Detection Mode Select */
1341#define DMAC_DCMD_ERDM_MASK (0x03 << DMAC_DCMD_ERDM_BIT)
1342 #define DMAC_DCMD_ERDM_LOW (0 << DMAC_DCMD_ERDM_BIT)
1343 #define DMAC_DCMD_ERDM_FALL (1 << DMAC_DCMD_ERDM_BIT)
1344 #define DMAC_DCMD_ERDM_HIGH (2 << DMAC_DCMD_ERDM_BIT)
1345 #define DMAC_DCMD_ERDM_RISE (3 << DMAC_DCMD_ERDM_BIT)
1346#define DMAC_DCMD_BLAST (1 << 25) /* BCH last */
1347#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
1348#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
1349#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
1350#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
1351 #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
1352 #define DMAC_DCMD_RDIL_2 (0x01 << DMAC_DCMD_RDIL_BIT)
1353 #define DMAC_DCMD_RDIL_4 (0x02 << DMAC_DCMD_RDIL_BIT)
1354 #define DMAC_DCMD_RDIL_8 (0x03 << DMAC_DCMD_RDIL_BIT)
1355 #define DMAC_DCMD_RDIL_12 (0x04 << DMAC_DCMD_RDIL_BIT)
1356 #define DMAC_DCMD_RDIL_16 (0x05 << DMAC_DCMD_RDIL_BIT)
1357 #define DMAC_DCMD_RDIL_20 (0x06 << DMAC_DCMD_RDIL_BIT)
1358 #define DMAC_DCMD_RDIL_24 (0x07 << DMAC_DCMD_RDIL_BIT)
1359 #define DMAC_DCMD_RDIL_28 (0x08 << DMAC_DCMD_RDIL_BIT)
1360 #define DMAC_DCMD_RDIL_32 (0x09 << DMAC_DCMD_RDIL_BIT)
1361 #define DMAC_DCMD_RDIL_48 (0x0a << DMAC_DCMD_RDIL_BIT)
1362 #define DMAC_DCMD_RDIL_60 (0x0b << DMAC_DCMD_RDIL_BIT)
1363 #define DMAC_DCMD_RDIL_64 (0x0c << DMAC_DCMD_RDIL_BIT)
1364 #define DMAC_DCMD_RDIL_124 (0x0d << DMAC_DCMD_RDIL_BIT)
1365 #define DMAC_DCMD_RDIL_128 (0x0e << DMAC_DCMD_RDIL_BIT)
1366 #define DMAC_DCMD_RDIL_200 (0x0f << DMAC_DCMD_RDIL_BIT)
1367#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
1368#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
1369 #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
1370 #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
1371 #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
1372#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
1373#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
1374 #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
1375 #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
1376 #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
1377#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
1378#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
1379 #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
1380 #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
1381 #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
1382 #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
1383 #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
1384 #define DMAC_DCMD_DS_64BYTE (5 << DMAC_DCMD_DS_BIT)
1385
1386#define DMAC_DCMD_STDE (1 << 2) /* Stride enable */
1387#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
1388#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
1389
1390// DMA descriptor address register
1391#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
1392#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
1393#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
1394#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
1395
1396// DMA stride address register
1397#define DMAC_DSD_TSD_BIT 16 /* target stride address */
1398#define DMAC_DSD_TSD_MASK (0xffff << DMAC_DSD_TSD_BIT)
1399#define DMAC_DSD_SSD_BIT 0 /* source stride address */
1400#define DMAC_DSD_SSD_MASK (0xffff << DMAC_DSD_SSD_BIT)
1401
1402// DMA control register
1403#define DMAC_DMACR_FMSC (1 << 31) /* MSC Fast DMA mode */
1404#define DMAC_DMACR_FSSI (1 << 30) /* SSI Fast DMA mode */
1405#define DMAC_DMACR_FTSSI (1 << 29) /* TSSI Fast DMA mode */
1406#define DMAC_DMACR_FUART (1 << 28) /* UART Fast DMA mode */
1407#define DMAC_DMACR_FAIC (1 << 27) /* AIC Fast DMA mode */
1408#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
1409#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
1410 #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
1411 #define DMAC_DMACR_PR_120345 (1 << DMAC_DMACR_PR_BIT)
1412 #define DMAC_DMACR_PR_230145 (2 << DMAC_DMACR_PR_BIT)
1413 #define DMAC_DMACR_PR_340125 (3 << DMAC_DMACR_PR_BIT)
1414#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
1415#define DMAC_DMACR_AR (1 << 2) /* address error flag */
1416#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
1417
1418// DMA doorbell register
1419#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
1420#define DMAC_DMADBR_DB4 (1 << 4) /* doorbell for channel 4 */
1421#define DMAC_DMADBR_DB3 (1 << 3) /* doorbell for channel 3 */
1422#define DMAC_DMADBR_DB2 (1 << 2) /* doorbell for channel 2 */
1423#define DMAC_DMADBR_DB1 (1 << 1) /* doorbell for channel 1 */
1424#define DMAC_DMADBR_DB0 (1 << 0) /* doorbell for channel 0 */
1425
1426// DMA doorbell set register
1427#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
1428#define DMAC_DMADBSR_DBS4 (1 << 4) /* enable doorbell for channel 4 */
1429#define DMAC_DMADBSR_DBS3 (1 << 3) /* enable doorbell for channel 3 */
1430#define DMAC_DMADBSR_DBS2 (1 << 2) /* enable doorbell for channel 2 */
1431#define DMAC_DMADBSR_DBS1 (1 << 1) /* enable doorbell for channel 1 */
1432#define DMAC_DMADBSR_DBS0 (1 << 0) /* enable doorbell for channel 0 */
1433
1434// DMA interrupt pending register
1435#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
1436#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
1437#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
1438#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
1439#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
1440#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
1441
1442#ifndef __MIPS_ASSEMBLER
1443
1444/***************************************************************************
1445 * DMAC
1446 ***************************************************************************/
1447
1448/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
1449
1450#define __dmac_enable_module(m) \
1451 ( REG_DMAC_DMACR(m) |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_012345 )
1452#define __dmac_disable_module(m) \
1453 ( REG_DMAC_DMACR(m) &= ~DMAC_DMACR_DMAE )
1454
1455/* p=0,1,2,3 */
1456#define __dmac_set_priority(m,p) \
1457do { \
1458 REG_DMAC_DMACR(m) &= ~DMAC_DMACR_PR_MASK; \
1459 REG_DMAC_DMACR(m) |= ((p) << DMAC_DMACR_PR_BIT); \
1460} while (0)
1461
1462#define __dmac_test_halt_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_HLT )
1463#define __dmac_test_addr_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_AR )
1464
1465#define __dmac_channel_enable_clk(n) \
1466 REG_DMAC_DMACKES((n)/HALF_DMA_NUM) = 1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM);
1467
1468#define __dmac_channel_disable_clk(n) \
1469 REG_DMAC_DMACKEC((n)/HALF_DMA_NUM) = 1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM);
1470
1471#define __dmac_enable_descriptor(n) \
1472 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
1473#define __dmac_disable_descriptor(n) \
1474 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
1475
1476#define __dmac_enable_channel(n) \
1477do { \
1478 REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN; \
1479} while (0)
1480#define __dmac_disable_channel(n) \
1481do { \
1482 REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN; \
1483} while (0)
1484#define __dmac_channel_enabled(n) \
1485 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )
1486
1487#define __dmac_channel_enable_irq(n) \
1488 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )
1489#define __dmac_channel_disable_irq(n) \
1490 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
1491
1492#define __dmac_channel_transmit_halt_detected(n) \
1493 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
1494#define __dmac_channel_transmit_end_detected(n) \
1495 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
1496#define __dmac_channel_address_error_detected(n) \
1497 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
1498
1499#define __dmac_channel_count_terminated_detected(n) \
1500 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )
1501#define __dmac_channel_descriptor_invalid_detected(n) \
1502 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )
1503
1504#define __dmac_channel_clear_transmit_halt(n) \
1505 do { \
1506 /* clear both channel halt error and globle halt error */ \
1507 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT; \
1508 REG_DMAC_DMACR(n/HALF_DMA_NUM) &= ~DMAC_DMACR_HLT; \
1509 } while (0)
1510#define __dmac_channel_clear_transmit_end(n) \
1511 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
1512#define __dmac_channel_clear_address_error(n) \
1513 do { \
1514 REG_DMAC_DDA(n) = 0; /* clear descriptor address register */ \
1515 REG_DMAC_DSAR(n) = 0; /* clear source address register */ \
1516 REG_DMAC_DTAR(n) = 0; /* clear target address register */ \
1517 /* clear both channel addr error and globle address error */ \
1518 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR; \
1519 REG_DMAC_DMACR(n/HALF_DMA_NUM) &= ~DMAC_DMACR_AR; \
1520 } while (0)
1521
1522#define __dmac_channel_clear_count_terminated(n) \
1523 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
1524#define __dmac_channel_clear_descriptor_invalid(n) \
1525 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
1526
1527#define __dmac_channel_set_transfer_unit_32bit(n) \
1528do { \
1529 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1530 REG_DMAC_DCMD((n)) |= MAC_DCMD_DS_32BIT; \
1531} while (0)
1532
1533#define __dmac_channel_set_transfer_unit_16bit(n) \
1534do { \
1535 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1536 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
1537} while (0)
1538
1539#define __dmac_channel_set_transfer_unit_8bit(n) \
1540do { \
1541 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1542 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
1543} while (0)
1544
1545#define __dmac_channel_set_transfer_unit_16byte(n) \
1546do { \
1547 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1548 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
1549} while (0)
1550
1551#define __dmac_channel_set_transfer_unit_32byte(n) \
1552do { \
1553 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1554 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
1555} while (0)
1556
1557/* w=8,16,32 */
1558#define __dmac_channel_set_dest_port_width(n,w) \
1559do { \
1560 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
1561 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
1562} while (0)
1563
1564/* w=8,16,32 */
1565#define __dmac_channel_set_src_port_width(n,w) \
1566do { \
1567 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
1568 REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
1569} while (0)
1570
1571/* v=0-15 */
1572#define __dmac_channel_set_rdil(n,v) \
1573do { \
1574 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
1575 REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \
1576} while (0)
1577
1578#define __dmac_channel_dest_addr_fixed(n) \
1579 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )
1580#define __dmac_channel_dest_addr_increment(n) \
1581 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )
1582
1583#define __dmac_channel_src_addr_fixed(n) \
1584 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )
1585#define __dmac_channel_src_addr_increment(n) \
1586 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )
1587
1588#define __dmac_channel_set_doorbell(n) \
1589 ( REG_DMAC_DMADBSR((n)/HALF_DMA_NUM) = (1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) )
1590
1591#define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR((n)/HALF_DMA_NUM) & (1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) )
1592#define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR((n)/HALF_DMA_NUM) &= ~(1 <<((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) )
1593
1594static __inline__ int __dmac_get_irq(void)
1595{
1596 int i;
1597 for (i = 0; i < MAX_DMA_NUM; i++)
1598 if (__dmac_channel_irq_detected(i))
1599 return i;
1600 return -1;
1601}
1602
1603#endif /* __MIPS_ASSEMBLER */
1604
1605/*
1606 * Interrupt controller module(INTC) address definition
1607 */
1608#define INTC_BASE 0xB0001000
1609
1610/*
1611 * INTC registers offset address definition
1612 */
1613#define INTC_ICSR_OFFSET (0x00) /* 32, r, 0x00000000 */
1614#define INTC_ICMR_OFFSET (0x04) /* 32, rw, 0xffffffff */
1615#define INTC_ICMSR_OFFSET (0x08) /* 32, w, 0x???????? */
1616#define INTC_ICMCR_OFFSET (0x0c) /* 32, w, 0x???????? */
1617#define INTC_ICPR_OFFSET (0x10) /* 32, r, 0x00000000 */
1618
1619/* INTC groups offset */
1620#define INTC_GOS 0x20
1621
1622/*
1623 * INTC registers address definition
1624 */
1625#define INTC_ICSR(n) (INTC_BASE + (n) * INTC_GOS + INTC_ICSR_OFFSET)
1626#define INTC_ICMR(n) (INTC_BASE + (n) * INTC_GOS + INTC_ICMR_OFFSET)
1627#define INTC_ICMSR(n) (INTC_BASE + (n) * INTC_GOS + INTC_ICMSR_OFFSET)
1628#define INTC_ICMCR(n) (INTC_BASE + (n) * INTC_GOS + INTC_ICMCR_OFFSET)
1629#define INTC_ICPR(n) (INTC_BASE + (n) * INTC_GOS + INTC_ICPR_OFFSET)
1630
1631/*
1632 * INTC registers common define
1633 */
1634
1635/* 1st-level interrupts */
1636#define IRQ_I2C1 0
1637#define IRQ_I2C0 1
1638#define IRQ_UART3 2
1639#define IRQ_UART2 3
1640#define IRQ_UART1 4
1641#define IRQ_UART0 5
1642#define IRQ_GPU 6
1643#define IRQ_SSI1 7
1644#define IRQ_SSI0 8
1645#define IRQ_TSSI 9
1646#define IRQ_BDMA 10
1647#define IRQ_KBC 11
1648#define IRQ_GPIO5 12
1649#define IRQ_GPIO4 13
1650#define IRQ_GPIO3 14
1651#define IRQ_GPIO2 15
1652#define IRQ_GPIO1 16
1653#define IRQ_GPIO0 17
1654#define IRQ_SADC 18
1655#define IRQ_ETH 19
1656#define IRQ_UHC 20
1657#define IRQ_OTG 21
1658#define IRQ_MDMA 22
1659#define IRQ_DMAC1 23
1660#define IRQ_DMAC0 24
1661#define IRQ_TCU2 25
1662#define IRQ_TCU1 26
1663#define IRQ_TCU0 27
1664#define IRQ_GPS 28
1665#define IRQ_IPU 29
1666#define IRQ_CIM 30
1667#define IRQ_LCD 31
1668
1669#define IRQ_RTC 32 /* 32 + 0 */
1670#define IRQ_OWI 33 /* 32 + 1 */
1671#define IRQ_AIC 34 /* 32 + 2 */
1672#define IRQ_MSC2 35 /* 32 + 3 */
1673#define IRQ_MSC1 36 /* 32 + 4 */
1674#define IRQ_MSC0 37 /* 32 + 5 */
1675#define IRQ_SCC 38 /* 32 + 6 */
1676#define IRQ_BCH 39 /* 32 + 7 */
1677#define IRQ_PCM 40 /* 32 + 8 */
1678#define IRQ_HARB0 41 /* 32 + 9 */
1679#define IRQ_HARB2 42 /* 32 + 10 */
1680#define IRQ_AOSD 43 /* 32 + 11 */
1681#define IRQ_CPM 44 /* 32 + 12 */
1682
1683#define IRQ_INTC_MAX 45
1684
1685/* 2nd-level interrupts */
1686#define IRQ_DMA_BASE (IRQ_INTC_MAX)
1687#define IRQ_DMA_MAX (IRQ_DMA_BASE + NUM_DMA)
1688
1689#define IRQ_MDMA_BASE (IRQ_DMA_MAX)
1690#define IRQ_MDMA_MAX (IRQ_MDMA_BASE + NUM_MDMA)
1691
1692#define IRQ_BDMA_BASE (IRQ_MDMA_MAX)
1693#define IRQ_BDMA_MAX (IRQ_BDMA_BASE + NUM_BDMA)
1694
1695/* To be cleanup begin */
1696#define IRQ_DMA_0 46
1697#define IRQ_DMA_1 (IRQ_DMA_0 + HALF_DMA_NUM) /* 46 + 6 = 52 */
1698#define IRQ_MDMA_0 (IRQ_DMA_0 + MAX_DMA_NUM) /* 46 + 12 = 58 */
1699#define IRQ_BDMA_0 (IRQ_DMA_0 + MAX_DMA_NUM + MAX_MDMA_NUM) /* 46 + 12 + 2 = 60 */
1700
1701#define IRQ_GPIO_0 64 /* 64 to (64+MAX_GPIO_NUM-1) for GPIO pin 0 to MAX_GPIO_NUM-1 */
1702
1703#define NUM_INTC 45
1704#define NUM_DMA MAX_DMA_NUM
1705#define NUM_MDMA MAX_MDMA_NUM
1706#define NUM_BDMA MAX_BDMA_NUM
1707#define NUM_GPIO MAX_GPIO_NUM
1708/* To be cleanup end */
1709
1710#ifndef __MIPS_ASSEMBLER
1711
1712#define REG_INTC_ICMR(n) REG32(INTC_ICMR(n))
1713#define REG_INTC_ICMSR(n) REG32(INTC_ICMSR(n))
1714#define REG_INTC_ICMCR(n) REG32(INTC_ICMCR(n))
1715#define REG_INTC_ICPR(n) REG32(INTC_ICPR(n))
1716
1717#define __intc_unmask_irq(n) (REG_INTC_ICMCR((n)/32) = (1 << ((n)%32)))
1718#define __intc_mask_irq(n) (REG_INTC_ICMSR((n)/32) = (1 << ((n)%32)))
1719
1720#endif /* __MIPS_ASSEMBLER */
1721
1722/*
1723 * AC97 and I2S controller module(AIC) address definition
1724 */
1725#define AIC_BASE 0xb0020000
1726
1727/*
1728 * AIC registers offset address definition
1729 */
1730#define AIC_FR_OFFSET (0x00)
1731#define AIC_CR_OFFSET (0x04)
1732#define AIC_ACCR1_OFFSET (0x08)
1733#define AIC_ACCR2_OFFSET (0x0c)
1734#define AIC_I2SCR_OFFSET (0x10)
1735#define AIC_SR_OFFSET (0x14)
1736#define AIC_ACSR_OFFSET (0x18)
1737#define AIC_I2SSR_OFFSET (0x1c)
1738#define AIC_ACCAR_OFFSET (0x20)
1739#define AIC_ACCDR_OFFSET (0x24)
1740#define AIC_ACSAR_OFFSET (0x28)
1741#define AIC_ACSDR_OFFSET (0x2c)
1742#define AIC_I2SDIV_OFFSET (0x30)
1743#define AIC_DR_OFFSET (0x34)
1744
1745#define SPDIF_ENA_OFFSET (0x80)
1746#define SPDIF_CTRL_OFFSET (0x84)
1747#define SPDIF_STATE_OFFSET (0x88)
1748#define SPDIF_CFG1_OFFSET (0x8c)
1749#define SPDIF_CFG2_OFFSET (0x90)
1750#define SPDIF_FIFO_OFFSET (0x94)
1751
1752#define ICDC_RGADW_OFFSET (0xa4)
1753#define ICDC_RGDATA_OFFSET (0xa8)
1754
1755/*
1756 * AIC registers address definition
1757 */
1758#define AIC_FR (AIC_BASE + AIC_FR_OFFSET)
1759#define AIC_CR (AIC_BASE + AIC_CR_OFFSET)
1760#define AIC_ACCR1 (AIC_BASE + AIC_ACCR1_OFFSET)
1761#define AIC_ACCR2 (AIC_BASE + AIC_ACCR2_OFFSET)
1762#define AIC_I2SCR (AIC_BASE + AIC_I2SCR_OFFSET)
1763#define AIC_SR (AIC_BASE + AIC_SR_OFFSET)
1764#define AIC_ACSR (AIC_BASE + AIC_ACSR_OFFSET)
1765#define AIC_I2SSR (AIC_BASE + AIC_I2SSR_OFFSET)
1766#define AIC_ACCAR (AIC_BASE + AIC_ACCAR_OFFSET)
1767#define AIC_ACCDR (AIC_BASE + AIC_ACCDR_OFFSET)
1768#define AIC_ACSAR (AIC_BASE + AIC_ACSAR_OFFSET)
1769#define AIC_ACSDR (AIC_BASE + AIC_ACSDR_OFFSET)
1770#define AIC_I2SDIV (AIC_BASE + AIC_I2SDIV_OFFSET)
1771#define AIC_DR (AIC_BASE + AIC_DR_OFFSET)
1772
1773#define SPDIF_ENA (AIC_BASE + SPDIF_ENA_OFFSET)
1774#define SPDIF_CTRL (AIC_BASE + SPDIF_CTRL_OFFSET)
1775#define SPDIF_STATE (AIC_BASE + SPDIF_STATE_OFFSET)
1776#define SPDIF_CFG1 (AIC_BASE + SPDIF_CFG1_OFFSET)
1777#define SPDIF_CFG2 (AIC_BASE + SPDIF_CFG2_OFFSET)
1778#define SPDIF_FIFO (AIC_BASE + SPDIF_FIFO_OFFSET)
1779
1780#define ICDC_RGADW (AIC_BASE + ICDC_RGADW_OFFSET)
1781#define ICDC_RGDATA (AIC_BASE + ICDC_RGDATA_OFFSET)
1782
1783/*
1784 * AIC registers common define
1785 */
1786
1787/* AIC controller configuration register(AICFR) */
1788#define AIC_FR_LSMP BIT6
1789#define AIC_FR_ICDC BIT5
1790#define AIC_FR_AUSEL BIT4
1791#define AIC_FR_RST BIT3
1792#define AIC_FR_BCKD BIT2
1793#define AIC_FR_SYNCD BIT1
1794#define AIC_FR_ENB BIT0
1795
1796#define AIC_FR_RFTH_LSB 24
1797#define AIC_FR_RFTH_MASK BITS_H2L(27, AIC_FR_RFTH_LSB)
1798
1799#define AIC_FR_TFTH_LSB 16
1800#define AIC_FR_TFTH_MASK BITS_H2L(20, AIC_FR_TFTH_LSB)
1801
1802/* AIC controller common control register(AICCR) */
1803#define AIC_CR_PACK16 BIT28
1804#define AIC_CR_RDMS BIT15
1805#define AIC_CR_TDMS BIT14
1806#define AIC_CR_M2S BIT11
1807#define AIC_CR_ENDSW BIT10
1808#define AIC_CR_AVSTSU BIT9
1809#define AIC_CR_TFLUSH BIT8
1810#define AIC_CR_RFLUSH BIT7
1811#define AIC_CR_EROR BIT6
1812#define AIC_CR_ETUR BIT5
1813#define AIC_CR_ERFS BIT4
1814#define AIC_CR_ETFS BIT3
1815#define AIC_CR_ENLBF BIT2
1816#define AIC_CR_ERPL BIT1
1817#define AIC_CR_EREC BIT0
1818
1819#define AIC_CR_CHANNEL_LSB 24
1820#define AIC_CR_CHANNEL_MASK BITS_H2L(26, AIC_CR_CHANNEL_LSB)
1821
1822#define AIC_CR_OSS_LSB 19
1823#define AIC_CR_OSS_MASK BITS_H2L(21, AIC_CR_OSS_LSB)
1824 #define AIC_CR_OSS(n) (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_OSS_LSB) /* n = 8, 16, 18, 20, 24 */
1825
1826#define AIC_CR_ISS_LSB 16
1827#define AIC_CR_ISS_MASK BITS_H2L(18, AIC_CR_ISS_LSB)
1828 #define AIC_CR_ISS(n) (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_ISS_LSB) /* n = 8, 16, 18, 20, 24 */
1829
1830/* AIC controller AC-link control register 1(ACCR1) */
1831#define AIC_ACCR1_RS_LSB 16
1832#define AIC_ACCR1_RS_MASK BITS_H2L(25, AIC_ACCR1_RS_LSB)
1833 #define AIC_ACCR1_RS_SLOT(n) ((1 << ((n) - 3)) << AIC_ACCR1_RS_LSB) /* n = 3 .. 12 */
1834
1835#define AIC_ACCR1_XS_LSB 0
1836#define AIC_ACCR1_XS_MASK BITS_H2L(9, AIC_ACCR1_XS_LSB)
1837 #define AIC_ACCR1_XS_SLOT(n) ((1 << ((n) - 3)) << AIC_ACCR1_XS_LSB) /* n = 3 .. 12 */
1838
1839/* AIC controller AC-link control register 2 (ACCR2) */
1840#define AIC_ACCR2_ERSTO BIT18
1841#define AIC_ACCR2_ESADR BIT17
1842#define AIC_ACCR2_ECADT BIT16
1843#define AIC_ACCR2_SO BIT3
1844#define AIC_ACCR2_SR BIT2
1845#define AIC_ACCR2_SS BIT1
1846#define AIC_ACCR2_SA BIT0
1847
1848/* AIC controller i2s/msb-justified control register (I2SCR) */
1849#define AIC_I2SCR_RFIRST BIT17
1850#define AIC_I2SCR_SWLH BIT16
1851#define AIC_I2SCR_STPBK BIT12
1852#define AIC_I2SCR_ESCLK BIT4
1853#define AIC_I2SCR_AMSL BIT0
1854
1855/* AIC controller FIFO status register (AICSR) */
1856#define AIC_SR_ROR BIT6
1857#define AIC_SR_TUR BIT5
1858#define AIC_SR_RFS BIT4
1859#define AIC_SR_TFS BIT3
1860
1861#define AIC_SR_RFL_LSB 24
1862#define AIC_SR_RFL_MASK BITS_H2L(29, AIC_SR_RFL_LSB)
1863
1864#define AIC_SR_TFL_LSB 8
1865#define AIC_SR_TFL_MASK BITS_H2L(13, AIC_SR_TFL_LSB)
1866
1867/* AIC controller AC-link status register (ACSR) */
1868#define AIC_ACSR_SLTERR BIT21
1869#define AIC_ACSR_CRDY BIT20
1870#define AIC_ACSR_CLPM BIT19
1871#define AIC_ACSR_RSTO BIT18
1872#define AIC_ACSR_SADR BIT17
1873#define AIC_ACSR_CADT BIT16
1874
1875/* AIC controller I2S/MSB-justified status register (I2SSR) */
1876#define AIC_I2SSR_CHBSY BIT5
1877#define AIC_I2SSR_TBSY BIT4
1878#define AIC_I2SSR_RBSY BIT3
1879#define AIC_I2SSR_BSY BIT2
1880
1881/* AIC controller AC97 codec command address register (ACCAR) */
1882#define AIC_ACCAR_CAR_LSB 0
1883#define AIC_ACCAR_CAR_MASK BITS_H2L(19, AIC_ACCAR_CAR_LSB)
1884
1885/* AIC controller AC97 codec command data register (ACCDR) */
1886#define AIC_ACCDR_CDR_LSB 0
1887#define AIC_ACCDR_CDR_MASK BITS_H2L(19, AIC_ACCDR_CDR_LSB)
1888
1889/* AC97 read and write macro based on ACCAR and ACCDR */
1890#define AC97_READ_CMD BIT19
1891#define AC97_WRITE_CMD (BIT19 & ~BIT19)
1892
1893#define AC97_INDEX_LSB 12
1894#define AC97_INDEX_MASK BITS_H2L(18, AC97_INDEX_LSB)
1895
1896#define AC97_DATA_LSB 4
1897#define AC97_DATA_MASK BITS_H2L(19, AC97_DATA_LSB)
1898
1899/* AIC controller AC97 codec status address register (ACSAR) */
1900#define AIC_ACSAR_SAR_LSB 0
1901#define AIC_ACSAR_SAR_MASK BITS_H2L(19, AIC_ACSAR_SAR_LSB)
1902
1903/* AIC controller AC97 codec status data register (ACSDR) */
1904#define AIC_ACSDR_SDR_LSB 0
1905#define AIC_ACSDR_SDR_MASK BITS_H2L(19, AIC_ACSDR_SDR_LSB)
1906
1907/* AIC controller I2S/MSB-justified clock divider register (I2SDIV) */
1908#define AIC_I2SDIV_DIV_LSB 0
1909#define AIC_I2SDIV_DIV_MASK BITS_H2L(3, AIC_I2SDIV_DIV_LSB)
1910
1911/* SPDIF enable register (SPDIF_ENA) */
1912#define SPDIF_ENA_SPEN BIT0
1913
1914/* SPDIF control register (SPDIF_CTRL) */
1915#define SPDIF_CTRL_DMAEN BIT15
1916#define SPDIF_CTRL_DTYPE BIT14
1917#define SPDIF_CTRL_SIGN BIT13
1918#define SPDIF_CTRL_INVALID BIT12
1919#define SPDIF_CTRL_RST BIT11
1920#define SPDIF_CTRL_SPDIFI2S BIT10
1921#define SPDIF_CTRL_MTRIG BIT1
1922#define SPDIF_CTRL_MFFUR BIT0
1923
1924/* SPDIF state register (SPDIF_STAT) */
1925#define SPDIF_STAT_BUSY BIT7
1926#define SPDIF_STAT_FTRIG BIT1
1927#define SPDIF_STAT_FUR BIT0
1928
1929#define SPDIF_STAT_FLVL_LSB 8
1930#define SPDIF_STAT_FLVL_MASK BITS_H2L(14, SPDIF_STAT_FLVL_LSB)
1931
1932/* SPDIF configure 1 register (SPDIF_CFG1) */
1933#define SPDIF_CFG1_INITLVL BIT17
1934#define SPDIF_CFG1_ZROVLD BIT16
1935
1936#define SPDIF_CFG1_TRIG_LSB 12
1937#define SPDIF_CFG1_TRIG_MASK BITS_H2L(13, SPDIF_CFG1_TRIG_LSB)
1938#define SPDIF_CFG1_TRIG(n) (((n) > 16 ? 3 : (n)/8) << SPDIF_CFG1_TRIG_LSB) /* n = 4, 8, 16, 32 */
1939
1940#define SPDIF_CFG1_SRCNUM_LSB 8
1941#define SPDIF_CFG1_SRCNUM_MASK BITS_H2L(11, SPDIF_CFG1_SRCNUM_LSB)
1942
1943#define SPDIF_CFG1_CH1NUM_LSB 4
1944#define SPDIF_CFG1_CH1NUM_MASK BITS_H2L(7, SPDIF_CFG1_CH1NUM_LSB)
1945
1946#define SPDIF_CFG1_CH2NUM_LSB 0
1947#define SPDIF_CFG1_CH2NUM_MASK BITS_H2L(3, SPDIF_CFG1_CH2NUM_LSB)
1948
1949/* SPDIF configure 2 register (SPDIF_CFG2) */
1950#define SPDIF_CFG2_MAXWL BIT18
1951#define SPDIF_CFG2_PRE BIT3
1952#define SPDIF_CFG2_COPYN BIT2
1953#define SPDIF_CFG2_AUDION BIT1
1954#define SPDIF_CFG2_CONPRO BIT0
1955
1956#define SPDIF_CFG2_FS_LSB 26
1957#define SPDIF_CFG2_FS_MASK BITS_H2L(29, SPDIF_CFG2_FS_LSB)
1958
1959#define SPDIF_CFG2_ORGFRQ_LSB 22
1960#define SPDIF_CFG2_ORGFRQ_MASK BITS_H2L(25, SPDIF_CFG2_ORGFRQ_LSB)
1961
1962#define SPDIF_CFG2_SAMWL_LSB 19
1963#define SPDIF_CFG2_SAMWL_MASK BITS_H2L(21, SPDIF_CFG2_SAMWL_LSB)
1964
1965#define SPDIF_CFG2_CLKACU_LSB 16
1966#define SPDIF_CFG2_CLKACU_MASK BITS_H2L(17, SPDIF_CFG2_CLKACU_LSB)
1967
1968#define SPDIF_CFG2_CATCODE_LSB 8
1969#define SPDIF_CFG2_CATCODE_MASK BITS_H2L(15, SPDIF_CFG2_CATCODE_LSB)
1970
1971#define SPDIF_CFG2_CHMD_LSB 6
1972#define SPDIF_CFG2_CHMD_MASK BITS_H2L(7, SPDIF_CFG2_CHMD_LSB)
1973
1974/* ICDC internal register access control register(RGADW) */
1975#define ICDC_RGADW_RGWR BIT16
1976
1977#define ICDC_RGADW_RGADDR_LSB 8
1978#define ICDC_RGADW_RGADDR_MASK BITS_H2L(14, ICDC_RGADW_RGADDR_LSB)
1979
1980#define ICDC_RGADW_RGDIN_LSB 0
1981#define ICDC_RGADW_RGDIN_MASK BITS_H2L(7, ICDC_RGADW_RGDIN_LSB)
1982
1983/* ICDC internal register data output register (RGDATA)*/
1984#define ICDC_RGDATA_IRQ BIT8
1985
1986#define ICDC_RGDATA_RGDOUT_LSB 0
1987#define ICDC_RGDATA_RGDOUT_MASK BITS_H2L(7, ICDC_RGDATA_RGDOUT_LSB)
1988
1989#ifndef __MIPS_ASSEMBLER
1990
1991#define REG_AIC_FR REG32(AIC_FR)
1992#define REG_AIC_CR REG32(AIC_CR)
1993#define REG_AIC_ACCR1 REG32(AIC_ACCR1)
1994#define REG_AIC_ACCR2 REG32(AIC_ACCR2)
1995#define REG_AIC_I2SCR REG32(AIC_I2SCR)
1996#define REG_AIC_SR REG32(AIC_SR)
1997#define REG_AIC_ACSR REG32(AIC_ACSR)
1998#define REG_AIC_I2SSR REG32(AIC_I2SSR)
1999#define REG_AIC_ACCAR REG32(AIC_ACCAR)
2000#define REG_AIC_ACCDR REG32(AIC_ACCDR)
2001#define REG_AIC_ACSAR REG32(AIC_ACSAR)
2002#define REG_AIC_ACSDR REG32(AIC_ACSDR)
2003#define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
2004#define REG_AIC_DR REG32(AIC_DR)
2005
2006#define REG_SPDIF_ENA REG32(SPDIF_ENA)
2007#define REG_SPDIF_CTRL REG32(SPDIF_CTRL)
2008#define REG_SPDIF_STATE REG32(SPDIF_STATE)
2009#define REG_SPDIF_CFG1 REG32(SPDIF_CFG1)
2010#define REG_SPDIF_CFG2 REG32(SPDIF_CFG2)
2011#define REG_SPDIF_FIFO REG32(SPDIF_FIFO)
2012
2013#define REG_ICDC_RGADW REG32(ICDC_RGADW)
2014#define REG_ICDC_RGDATA REG32(ICDC_RGDATA)
2015
2016#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB )
2017#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB )
2018
2019#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
2020#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL )
2021
2022#define __aic_play_zero() ( REG_AIC_FR &= ~AIC_FR_LSMP )
2023#define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP )
2024
2025#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
2026#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
2027#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST )
2028
2029#define __i2s_enable_sclk() ( REG_AIC_I2SCR |= AIC_I2SCR_ESCLK )
2030#define __i2s_disable_sclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_ESCLK )
2031
2032#define __aic_reset() \
2033do { \
2034 REG_AIC_FR |= AIC_FR_RST; \
2035} while(0)
2036
2037#define __aic_set_transmit_trigger(n) \
2038do { \
2039 REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \
2040 REG_AIC_FR |= ((n) << AIC_FR_TFTH_LSB); \
2041} while(0)
2042
2043#define __aic_set_receive_trigger(n) \
2044do { \
2045 REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \
2046 REG_AIC_FR |= ((n) << AIC_FR_RFTH_LSB); \
2047} while(0)
2048
2049#define __aic_enable_oldstyle()
2050#define __aic_enable_newstyle()
2051#define __aic_enable_pack16() ( REG_AIC_CR |= AIC_CR_PACK16 )
2052#define __aic_enable_unpack16() ( REG_AIC_CR &= ~AIC_CR_PACK16)
2053
2054/* n = AIC_CR_CHANNEL_MONO,AIC_CR_CHANNEL_STEREO ... */
2055#define __aic_out_channel_select(n) \
2056do { \
2057 REG_AIC_CR &= ~AIC_CR_CHANNEL_MASK; \
2058 REG_AIC_CR |= ((n) << AIC_CR_CHANNEL_LSB ); \
2059} while(0)
2060
2061#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC )
2062#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC )
2063#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL )
2064#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL )
2065#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
2066#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
2067
2068#define __aic_flush_tfifo() ( REG_AIC_CR |= AIC_CR_TFLUSH )
2069#define __aic_unflush_tfifo() ( REG_AIC_CR &= ~AIC_CR_TFLUSH )
2070#define __aic_flush_rfifo() ( REG_AIC_CR |= AIC_CR_RFLUSH )
2071#define __aic_unflush_rfifo() ( REG_AIC_CR &= ~AIC_CR_RFLUSH )
2072
2073#define __aic_enable_transmit_intr() \
2074 ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
2075#define __aic_disable_transmit_intr() \
2076 ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
2077#define __aic_enable_receive_intr() \
2078 ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
2079#define __aic_disable_receive_intr() \
2080 ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
2081
2082#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS )
2083#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
2084#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS )
2085#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS )
2086
2087#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S )
2088#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S )
2089#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW )
2090#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW )
2091#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU )
2092#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
2093
2094#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT(3)
2095#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT(4)
2096#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT(6)
2097#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT(7)
2098#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT(8)
2099#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT(9)
2100
2101#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT(3)
2102#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT(4)
2103#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT(6)
2104#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT(7)
2105#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT(8)
2106#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT(9)
2107
2108#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
2109#define __ac97_set_xs_mono() \
2110do { \
2111 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
2112 REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \
2113} while(0)
2114#define __ac97_set_xs_stereo() \
2115do { \
2116 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
2117 REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
2118} while(0)
2119
2120/* In fact, only stereo is support now. */
2121#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
2122#define __ac97_set_rs_mono() \
2123do { \
2124 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
2125 REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \
2126} while(0)
2127#define __ac97_set_rs_stereo() \
2128do { \
2129 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
2130 REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
2131} while(0)
2132
2133#define __ac97_warm_reset_codec() \
2134 do { \
2135 REG_AIC_ACCR2 |= AIC_ACCR2_SA; \
2136 REG_AIC_ACCR2 |= AIC_ACCR2_SS; \
2137 udelay(2); \
2138 REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \
2139 REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \
2140 } while (0)
2141
2142#define __ac97_cold_reset_codec() \
2143 do { \
2144 REG_AIC_ACCR2 |= AIC_ACCR2_SR; \
2145 udelay(2); \
2146 REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \
2147 } while (0)
2148
2149/* n=8,16,18,20 */
2150#define __ac97_set_iass(n) \
2151 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
2152#define __ac97_set_oass(n) \
2153 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
2154
2155/* This bit should only be set in 2 channels configuration */
2156#define __i2s_send_rfirst() ( REG_AIC_I2SCR |= AIC_I2SCR_RFIRST ) /* RL */
2157#define __i2s_send_lfirst() ( REG_AIC_I2SCR &= ~AIC_I2SCR_RFIRST ) /* LR */
2158
2159/* This bit should only be set in 2 channels configuration and 16bit-packed mode */
2160#define __i2s_switch_lr() ( REG_AIC_I2SCR |= AIC_I2SCR_SWLH )
2161#define __i2s_unswitch_lr() ( REG_AIC_I2SCR &= ~AIC_I2SCR_SWLH )
2162
2163#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
2164#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
2165
2166/* n=8,16,18,20,24 */
2167/*#define __i2s_set_sample_size(n) \
2168 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
2169
2170#define __i2s_out_channel_select(n) __aic_out_channel_select(n)
2171
2172#define __i2s_set_oss_sample_size(n) \
2173 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS(n))
2174#define __i2s_set_iss_sample_size(n) \
2175 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS(n))
2176
2177#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
2178#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
2179
2180#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS )
2181#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS )
2182#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
2183#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR )
2184
2185#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
2186
2187#define __aic_get_transmit_resident() \
2188 ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_LSB )
2189#define __aic_get_receive_count() \
2190 ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_LSB )
2191
2192#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT )
2193#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR )
2194#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO )
2195#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
2196#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY )
2197#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
2198#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
2199
2200#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
2201
2202#define __ac97_out_rcmd_addr(reg) \
2203do { \
2204 REG_AIC_ACCAR = AC97_READ_CMD | ((reg) << AC97_INDEX_LSB); \
2205} while (0)
2206
2207#define __ac97_out_wcmd_addr(reg) \
2208do { \
2209 REG_AIC_ACCAR = AC97_WRITE_CMD | ((reg) << AC97_INDEX_LSB); \
2210} while (0)
2211
2212#define __ac97_out_data(value) \
2213do { \
2214 REG_AIC_ACCDR = ((value) << AC97_DATA_LSB); \
2215} while (0)
2216
2217#define __ac97_in_data() \
2218 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> AC97_DATA_LSB )
2219
2220#define __ac97_in_status_addr() \
2221 ( (REG_AIC_ACSAR & AC97_INDEX_MASK) >> AC97_INDEX_LSB )
2222
2223#define __i2s_set_sample_rate(i2sclk, sync) \
2224 ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
2225
2226#define __i2s_set_i2sdiv(n) \
2227 ( REG_AIC_I2SDIV = (n) )
2228
2229#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) )
2230#define __aic_read_rfifo() ( REG_AIC_DR )
2231
2232#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC )
2233#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC )
2234
2235//
2236// Define next ops for AC97 compatible
2237//
2238
2239#define AC97_ACSR AIC_ACSR
2240
2241#define __ac97_enable() __aic_enable(); __aic_select_ac97()
2242#define __ac97_disable() __aic_disable()
2243#define __ac97_reset() __aic_reset()
2244
2245#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
2246#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n)
2247
2248#define __ac97_enable_record() __aic_enable_record()
2249#define __ac97_disable_record() __aic_disable_record()
2250#define __ac97_enable_replay() __aic_enable_replay()
2251#define __ac97_disable_replay() __aic_disable_replay()
2252#define __ac97_enable_loopback() __aic_enable_loopback()
2253#define __ac97_disable_loopback() __aic_disable_loopback()
2254
2255#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma()
2256#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma()
2257#define __ac97_enable_receive_dma() __aic_enable_receive_dma()
2258#define __ac97_disable_receive_dma() __aic_disable_receive_dma()
2259
2260#define __ac97_transmit_request() __aic_transmit_request()
2261#define __ac97_receive_request() __aic_receive_request()
2262#define __ac97_transmit_underrun() __aic_transmit_underrun()
2263#define __ac97_receive_overrun() __aic_receive_overrun()
2264
2265#define __ac97_clear_errors() __aic_clear_errors()
2266
2267#define __ac97_get_transmit_resident() __aic_get_transmit_resident()
2268#define __ac97_get_receive_count() __aic_get_receive_count()
2269
2270#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr()
2271#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr()
2272#define __ac97_enable_receive_intr() __aic_enable_receive_intr()
2273#define __ac97_disable_receive_intr() __aic_disable_receive_intr()
2274
2275#define __ac97_write_tfifo(v) __aic_write_tfifo(v)
2276#define __ac97_read_rfifo() __aic_read_rfifo()
2277
2278//
2279// Define next ops for I2S compatible
2280//
2281
2282#define I2S_ACSR AIC_I2SSR
2283
2284#define __i2s_enable() __aic_enable(); __aic_select_i2s()
2285#define __i2s_disable() __aic_disable()
2286#define __i2s_reset() __aic_reset()
2287
2288#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
2289#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n)
2290
2291#define __i2s_enable_record() __aic_enable_record()
2292#define __i2s_disable_record() __aic_disable_record()
2293#define __i2s_enable_replay() __aic_enable_replay()
2294#define __i2s_disable_replay() __aic_disable_replay()
2295#define __i2s_enable_loopback() __aic_enable_loopback()
2296#define __i2s_disable_loopback() __aic_disable_loopback()
2297
2298#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
2299#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma()
2300#define __i2s_enable_receive_dma() __aic_enable_receive_dma()
2301#define __i2s_disable_receive_dma() __aic_disable_receive_dma()
2302
2303#define __i2s_transmit_request() __aic_transmit_request()
2304#define __i2s_receive_request() __aic_receive_request()
2305#define __i2s_transmit_underrun() __aic_transmit_underrun()
2306#define __i2s_receive_overrun() __aic_receive_overrun()
2307
2308#define __i2s_clear_errors() __aic_clear_errors()
2309
2310#define __i2s_get_transmit_resident() __aic_get_transmit_resident()
2311#define __i2s_get_receive_count() __aic_get_receive_count()
2312
2313#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr()
2314#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr()
2315#define __i2s_enable_receive_intr() __aic_enable_receive_intr()
2316#define __i2s_disable_receive_intr() __aic_disable_receive_intr()
2317
2318#define __i2s_write_tfifo(v) __aic_write_tfifo(v)
2319#define __i2s_read_rfifo() __aic_read_rfifo()
2320
2321#define __i2s_enable_pack16() __aic_enable_pack16()
2322#define __i2s_enable_unpack16() __aic_enable_unpack16()
2323
2324#define __i2s_reset_codec() \
2325 do { \
2326 } while (0)
2327
2328/*************************************************************************
2329 * SPDIF INTERFACE in AIC Controller
2330 *************************************************************************/
2331
2332#define __spdif_enable() ( REG_SPDIF_ENA |= SPDIF_ENA_SPEN )
2333#define __spdif_disable() ( REG_SPDIF_ENA &= ~SPDIF_ENA_SPEN )
2334
2335#define __spdif_enable_transmit_dma() ( REG_SPDIF_CTRL |= SPDIF_CTRL_DMAEN )
2336#define __spdif_disable_transmit_dma() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DMAEN )
2337#define __spdif_enable_dtype() ( REG_SPDIF_CTRL |= SPDIF_CTRL_DTYPE )
2338#define __spdif_disable_dtype() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DTYPE )
2339#define __spdif_enable_sign() ( REG_SPDIF_CTRL |= SPDIF_CTRL_SIGN )
2340#define __spdif_disable_sign() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SIGN )
2341#define __spdif_enable_invalid() ( REG_SPDIF_CTRL |= SPDIF_CTRL_INVALID )
2342#define __spdif_disable_invalid() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_INVALID )
2343#define __spdif_enable_reset() ( REG_SPDIF_CTRL |= SPDIF_CTRL_RST )
2344#define __spdif_select_spdif() ( REG_SPDIF_CTRL |= SPDIF_CTRL_SPDIFI2S )
2345#define __spdif_select_i2s() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SPDIFI2S )
2346#define __spdif_enable_MTRIGmask() ( REG_SPDIF_CTRL |= SPDIF_CTRL_MTRIG )
2347#define __spdif_disable_MTRIGmask() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MTRIG )
2348#define __spdif_enable_MFFURmask() ( REG_SPDIF_CTRL |= SPDIF_CTRL_MFFUR )
2349#define __spdif_disable_MFFURmask() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MFFUR )
2350
2351#define __spdif_enable_initlvl_high() ( REG_SPDIF_CFG1 |= SPDIF_CFG1_INITLVL )
2352#define __spdif_enable_initlvl_low() ( REG_SPDIF_CFG1 &= ~SPDIF_CFG1_INITLVL )
2353#define __spdif_enable_zrovld_invald() ( REG_SPDIF_CFG1 |= SPDIF_CFG1_ZROVLD )
2354#define __spdif_enable_zrovld_vald() ( REG_SPDIF_CFG1 &= ~SPDIF_CFG1_ZROVLD )
2355
2356/* 0, 1, 2, 3 */
2357#define __spdif_set_transmit_trigger(n) \
2358do { \
2359 REG_SPDIF_CFG1 &= ~SPDIF_CFG1_TRIG_MASK; \
2360 REG_SPDIF_CFG1 |= SPDIF_CFG1_TRIG(n); \
2361} while(0)
2362
2363/* 1 ~ 15 */
2364#define __spdif_set_srcnum(n) \
2365do { \
2366 REG_SPDIF_CFG1 &= ~SPDIF_CFG1_SRCNUM_MASK; \
2367 REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_SRCNUM_LSB); \
2368} while(0)
2369
2370/* 1 ~ 15 */
2371#define __spdif_set_ch1num(n) \
2372do { \
2373 REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH1NUM_MASK; \
2374 REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH1NUM_LSB); \
2375} while(0)
2376
2377/* 1 ~ 15 */
2378#define __spdif_set_ch2num(n) \
2379do { \
2380 REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH2NUM_MASK; \
2381 REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH2NUM_LSB); \
2382} while(0)
2383
2384/* 0x0, 0x2, 0x3, 0xa, 0xe */
2385#define __spdif_set_fs(n) \
2386do { \
2387 REG_SPDIF_CFG2 &= ~SPDIF_CFG2_FS_MASK; \
2388 REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_FS_LSB); \
2389} while(0)
2390
2391/* 0xd, 0xc, 0x5, 0x1 */
2392#define __spdif_set_orgfrq(n) \
2393do { \
2394 REG_SPDIF_CFG2 &= ~SPDIF_CFG2_ORGFRQ_MASK; \
2395 REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_ORGFRQ_LSB); \
2396} while(0)
2397
2398/* 0x1, 0x6, 0x2, 0x4, 0x5 */
2399#define __spdif_set_samwl(n) \
2400do { \
2401 REG_SPDIF_CFG2 &= ~SPDIF_CFG2_SAMWL_MASK; \
2402 REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_SAMWL_LSB); \
2403} while(0)
2404
2405#define __spdif_enable_samwl_24() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_MAXWL )
2406#define __spdif_enable_samwl_20() ( REG_SPDIF_CFG1 &= ~SPDIF_CFG2_MAXWL )
2407
2408/* 0x1, 0x1, 0x2, 0x3 */
2409#define __spdif_set_clkacu(n) \
2410do { \
2411 REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CLKACU_MASK; \
2412 REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CLKACU_LSB); \
2413} while(0)
2414
2415/* see IEC60958-3 */
2416#define __spdif_set_catcode(n) \
2417do { \
2418 REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CATCODE_MASK; \
2419 REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CATCODE_LSB); \
2420} while(0)
2421
2422/* n = 0x0, */
2423#define __spdif_set_chmode(n) \
2424do { \
2425 REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CHMD_MASK; \
2426 REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CHMD_LSB); \
2427} while(0)
2428
2429#define __spdif_enable_pre() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_PRE )
2430#define __spdif_disable_pre() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_PRE )
2431#define __spdif_enable_copyn() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_COPYN )
2432#define __spdif_disable_copyn() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_COPYN )
2433/* audio sample word represents linear PCM samples */
2434#define __spdif_enable_audion() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_AUDION )
2435/* udio sample word used for other purpose */
2436#define __spdif_disable_audion() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_AUDION )
2437#define __spdif_enable_conpro() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CONPRO )
2438#define __spdif_disable_conpro() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_CONPRO )
2439
2440/***************************************************************************
2441 * ICDC
2442 ***************************************************************************/
2443#define __i2s_internal_codec() __aic_internal_codec()
2444#define __i2s_external_codec() __aic_external_codec()
2445
2446#define __icdc_clk_ready() ( REG_ICDC_CKCFG & ICDC_CKCFG_CKRDY )
2447#define __icdc_sel_adc() ( REG_ICDC_CKCFG |= ICDC_CKCFG_SELAD )
2448#define __icdc_sel_dac() ( REG_ICDC_CKCFG &= ~ICDC_CKCFG_SELAD )
2449
2450#define __icdc_set_rgwr() ( REG_ICDC_RGADW |= ICDC_RGADW_RGWR )
2451#define __icdc_clear_rgwr() ( REG_ICDC_RGADW &= ~ICDC_RGADW_RGWR )
2452#define __icdc_rgwr_ready() ( REG_ICDC_RGADW & ICDC_RGADW_RGWR )
2453
2454#define __icdc_set_addr(n) \
2455do { \
2456 REG_ICDC_RGADW &= ~ICDC_RGADW_RGADDR_MASK; \
2457 REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGADDR_LSB; \
2458} while(0)
2459
2460#define __icdc_set_cmd(n) \
2461do { \
2462 REG_ICDC_RGADW &= ~ICDC_RGADW_RGDIN_MASK; \
2463 REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGDIN_LSB; \
2464} while(0)
2465
2466#define __icdc_irq_pending() ( REG_ICDC_RGDATA & ICDC_RGDATA_IRQ )
2467#define __icdc_get_value() ( REG_ICDC_RGDATA & ICDC_RGDATA_RGDOUT_MASK )
2468
2469#endif /* __MIPS_ASSEMBLER */
2470
2471/*
2472 * Bose-Chaudhuri-Hocquenghem controller module(BCH) address definition
2473 */
2474#define BCH_BASE 0xb34d0000
2475
2476/*
2477 * BCH registers offset addresses definition
2478 */
2479#define BCH_BHCR_OFFSET (0x00) /* r, 32, 0x00000000 */
2480#define BCH_BHCSR_OFFSET (0x04) /* w, 32, 0x???????? */
2481#define BCH_BHCCR_OFFSET (0x08) /* w, 32, 0x???????? */
2482#define BCH_BHCNT_OFFSET (0x0c) /* rw, 32, 0x00000000 */
2483#define BCH_BHDR_OFFSET (0x10) /* w, 8, 0x???????? */
2484#define BCH_BHPAR0_OFFSET (0x14) /* rw, 32, 0x00000000 */
2485#define BCH_BHPAR1_OFFSET (0x18) /* rw, 32, 0x00000000 */
2486#define BCH_BHPAR2_OFFSET (0x1c) /* rw, 32, 0x00000000 */
2487#define BCH_BHPAR3_OFFSET (0x20) /* rw, 32, 0x00000000 */
2488#define BCH_BHPAR4_OFFSET (0x24) /* rw, 32, 0x00000000 */
2489#define BCH_BHPAR5_OFFSET (0x28) /* rw, 32, 0x00000000 */
2490#define BCH_BHPAR6_OFFSET (0x2c) /* rw, 32, 0x00000000 */
2491#define BCH_BHPAR7_OFFSET (0x30) /* rw, 32, 0x00000000 */
2492#define BCH_BHPAR8_OFFSET (0x34) /* rw, 32, 0x00000000 */
2493#define BCH_BHPAR9_OFFSET (0x38) /* rw, 32, 0x00000000 */
2494#define BCH_BHERR0_OFFSET (0x3c) /* r, 32, 0x00000000 */
2495#define BCH_BHERR1_OFFSET (0x40) /* r, 32, 0x00000000 */
2496#define BCH_BHERR2_OFFSET (0x44) /* r, 32, 0x00000000 */
2497#define BCH_BHERR3_OFFSET (0x48) /* r, 32, 0x00000000 */
2498#define BCH_BHERR4_OFFSET (0x4c) /* r, 32, 0x00000000 */
2499#define BCH_BHERR5_OFFSET (0x50) /* r, 32, 0x00000000 */
2500#define BCH_BHERR6_OFFSET (0x54) /* r, 32, 0x00000000 */
2501#define BCH_BHERR7_OFFSET (0x58) /* r, 32, 0x00000000 */
2502#define BCH_BHERR8_OFFSET (0x5c) /* r, 32, 0x00000000 */
2503#define BCH_BHERR9_OFFSET (0x60) /* r, 32, 0x00000000 */
2504#define BCH_BHERR10_OFFSET (0x64) /* r, 32, 0x00000000 */
2505#define BCH_BHERR11_OFFSET (0x68) /* r, 32, 0x00000000 */
2506#define BCH_BHINT_OFFSET (0x6c) /* r, 32, 0x00000000 */
2507#define BCH_BHINTE_OFFSET (0x70) /* rw, 32, 0x00000000 */
2508#define BCH_BHINTES_OFFSET (0x74) /* w, 32, 0x???????? */
2509#define BCH_BHINTEC_OFFSET (0x78) /* w, 32, 0x???????? */
2510
2511/*
2512 * BCH registers addresses definition
2513 */
2514#define BCH_BHCR (BCH_BASE + BCH_BHCR_OFFSET)
2515#define BCH_BHCSR (BCH_BASE + BCH_BHCSR_OFFSET)
2516#define BCH_BHCCR (BCH_BASE + BCH_BHCCR_OFFSET)
2517#define BCH_BHCNT (BCH_BASE + BCH_BHCNT_OFFSET)
2518#define BCH_BHDR (BCH_BASE + BCH_BHDR_OFFSET)
2519#define BCH_BHPAR0 (BCH_BASE + BCH_BHPAR0_OFFSET)
2520#define BCH_BHPAR1 (BCH_BASE + BCH_BHPAR1_OFFSET)
2521#define BCH_BHPAR2 (BCH_BASE + BCH_BHPAR2_OFFSET)
2522#define BCH_BHPAR3 (BCH_BASE + BCH_BHPAR3_OFFSET)
2523#define BCH_BHPAR4 (BCH_BASE + BCH_BHPAR4_OFFSET)
2524#define BCH_BHPAR5 (BCH_BASE + BCH_BHPAR5_OFFSET)
2525#define BCH_BHPAR6 (BCH_BASE + BCH_BHPAR6_OFFSET)
2526#define BCH_BHPAR7 (BCH_BASE + BCH_BHPAR7_OFFSET)
2527#define BCH_BHPAR8 (BCH_BASE + BCH_BHPAR8_OFFSET)
2528#define BCH_BHPAR9 (BCH_BASE + BCH_BHPAR9_OFFSET)
2529#define BCH_BHERR0 (BCH_BASE + BCH_BHERR0_OFFSET)
2530#define BCH_BHERR1 (BCH_BASE + BCH_BHERR1_OFFSET)
2531#define BCH_BHERR2 (BCH_BASE + BCH_BHERR2_OFFSET)
2532#define BCH_BHERR3 (BCH_BASE + BCH_BHERR3_OFFSET)
2533#define BCH_BHERR4 (BCH_BASE + BCH_BHERR4_OFFSET)
2534#define BCH_BHERR5 (BCH_BASE + BCH_BHERR5_OFFSET)
2535#define BCH_BHERR6 (BCH_BASE + BCH_BHERR6_OFFSET)
2536#define BCH_BHERR7 (BCH_BASE + BCH_BHERR7_OFFSET)
2537#define BCH_BHERR8 (BCH_BASE + BCH_BHERR8_OFFSET)
2538#define BCH_BHERR9 (BCH_BASE + BCH_BHERR9_OFFSET)
2539#define BCH_BHERR10 (BCH_BASE + BCH_BHERR10_OFFSET)
2540#define BCH_BHERR11 (BCH_BASE + BCH_BHERR11_OFFSET)
2541#define BCH_BHINT (BCH_BASE + BCH_BHINT_OFFSET)
2542#define BCH_BHINTES (BCH_BASE + BCH_BHINTES_OFFSET)
2543#define BCH_BHINTEC (BCH_BASE + BCH_BHINTEC_OFFSET)
2544#define BCH_BHINTE (BCH_BASE + BCH_BHINTE_OFFSET)
2545
2546/*
2547 * BCH registers common define
2548 */
2549
2550/* BCH control register (BHCR) */
2551#define BHCR_DMAE BIT7 /* BCH DMA enable */
2552#define BHCR_ENCE BIT2
2553#define BHCR_BRST BIT1 /* BCH reset */
2554#define BHCR_BCHE BIT0 /* BCH enable */
2555
2556#define BHCR_BSEL_LSB 3
2557#define BHCR_BSEL_MASK BITS_H2L(5, BHCR_BSEL_LSB)
2558 #define BHCR_BSEL(n) (((n)/4 - 1) << BHCR_BSEL_LSB) /* n = 4, 8, 12, 16, 20, 24 */
2559
2560/* BCH interrupt status register (BHINT) */
2561#define BHINT_ALL_F BIT4
2562#define BHINT_DECF BIT3
2563#define BHINT_ENCF BIT2
2564#define BHINT_UNCOR BIT1
2565#define BHINT_ERR BIT0
2566
2567#define BHINT_ERRC_LSB 27
2568#define BHINT_ERRC_MASK BITS_H2L(31, BHINT_ERRC_LSB)
2569
2570/* BCH ENC/DEC count register (BHCNT) */
2571#define BHCNT_DEC_LSB 16
2572#define BHCNT_DEC_MASK BITS_H2L(26, BHCNT_DEC_LSB)
2573
2574#define BHCNT_ENC_LSB 0
2575#define BHCNT_ENC_MASK BITS_H2L(10, BHCNT_ENC_LSB)
2576
2577/* BCH error report register (BCHERR)*/
2578#define BCH_ERR_INDEX_LSB 0
2579#define BCH_ERR_INDEX_MASK BITS_H2L(12, BCH_ERR_INDEX_LSB)
2580
2581/* BCH common macro define */
2582#define BCH_ENCODE 1
2583#define BCH_DECODE 0
2584
2585#ifndef __MIPS_ASSEMBLER
2586
2587#define REG_BCH_BHCR REG32(BCH_BHCR)
2588#define REG_BCH_BHCSR REG32(BCH_BHCSR)
2589#define REG_BCH_BHCCR REG32(BCH_BHCCR)
2590#define REG_BCH_BHCNT REG32(BCH_BHCNT)
2591#define REG_BCH_BHDR REG8(BCH_BHDR)
2592#define REG_BCH_BHPAR0 REG32(BCH_BHPAR0)
2593#define REG_BCH_BHPAR1 REG32(BCH_BHPAR1)
2594#define REG_BCH_BHPAR2 REG32(BCH_BHPAR2)
2595#define REG_BCH_BHPAR3 REG32(BCH_BHPAR3)
2596#define REG_BCH_BHPAR4 REG32(BCH_BHPAR4)
2597#define REG_BCH_BHPAR5 REG32(BCH_BHPAR5)
2598#define REG_BCH_BHPAR6 REG32(BCH_BHPAR6)
2599#define REG_BCH_BHPAR7 REG32(BCH_BHPAR7)
2600#define REG_BCH_BHPAR8 REG32(BCH_BHPAR8)
2601#define REG_BCH_BHPAR9 REG32(BCH_BHPAR9)
2602#define REG_BCH_BHERR0 REG32(BCH_BHERR0)
2603#define REG_BCH_BHERR1 REG32(BCH_BHERR1)
2604#define REG_BCH_BHERR2 REG32(BCH_BHERR2)
2605#define REG_BCH_BHERR3 REG32(BCH_BHERR3)
2606#define REG_BCH_BHERR4 REG32(BCH_BHERR4)
2607#define REG_BCH_BHERR5 REG32(BCH_BHERR5)
2608#define REG_BCH_BHERR6 REG32(BCH_BHERR6)
2609#define REG_BCH_BHERR7 REG32(BCH_BHERR7)
2610#define REG_BCH_BHERR8 REG32(BCH_BHERR8)
2611#define REG_BCH_BHERR9 REG32(BCH_BHERR9)
2612#define REG_BCH_BHERR10 REG32(BCH_BHERR10)
2613#define REG_BCH_BHERR11 REG32(BCH_BHERR11)
2614#define REG_BCH_BHINT REG32(BCH_BHINT)
2615#define REG_BCH_BHINTE REG32(BCH_BHINTE)
2616#define REG_BCH_BHINTEC REG32(BCH_BHINTEC)
2617#define REG_BCH_BHINTES REG32(BCH_BHINTES)
2618
2619#define __ecc_enable(encode, bit) \
2620do { \
2621 unsigned int tmp = BHCR_BRST | BHCR_BCHE; \
2622 if (encode) \
2623 tmp |= BHCR_ENCE; \
2624 tmp |= BHCR_BSEL(bit); \
2625 REG_BCH_BHCSR = tmp; \
2626 REG_BCH_BHCCR = ~tmp; \
2627} while (0)
2628#define __ecc_disable() (REG_BCH_BHCCR = BHCR_BCHE)
2629
2630#define __ecc_dma_enable() (REG_BCH_BHCSR = BHCR_DMAE)
2631#define __ecc_dma_disable() (REG_BCH_BHCCR = BHCR_DMAE)
2632
2633#define __ecc_cnt_enc(n) CMSREG32(BCH_BHCNT, (n) << BHCNT_ENC_LSB, BHCNT_ENC_MASK)
2634#define __ecc_cnt_dec(n) CMSREG32(BCH_BHCNT, (n) << BHCNT_DEC_LSB, BHCNT_DEC_MASK)
2635
2636#define __ecc_encode_sync() \
2637do { \
2638 unsigned int i = 1; \
2639 while (!(REG_BCH_BHINT & BHINT_ENCF) && i++); \
2640} while (0)
2641
2642#define __ecc_decode_sync() \
2643do { \
2644 unsigned int i = 1; \
2645 while (!(REG_BCH_BHINT & BHINT_DECF) && i++); \
2646} while (0)
2647
2648#endif /* __MIPS_ASSEMBLER */
2649
2650#define BDMAC_BASE 0xB3450000
2651
2652/*************************************************************************
2653 * BDMAC (BCH & NAND DMA Controller)
2654 *************************************************************************/
2655
2656/* n is the DMA channel index (0 - 2) */
2657#define BDMAC_DSAR(n) (BDMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
2658#define BDMAC_DTAR(n) (BDMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
2659#define BDMAC_DTCR(n) (BDMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
2660#define BDMAC_DRSR(n) (BDMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
2661#define BDMAC_DCCSR(n) (BDMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
2662#define BDMAC_DCMD(n) (BDMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
2663#define BDMAC_DDA(n) (BDMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
2664#define BDMAC_DSD(n) (BDMAC_BASE + (0x1c + (n) * 0x20)) /* DMA Stride Address */
2665#define BDMAC_DNT(n) (BDMAC_BASE + (0xc0 + (n) * 0x04)) /* NAND Detect Timer */
2666
2667#define BDMAC_DMACR (BDMAC_BASE + 0x0300) /* DMA control register */
2668#define BDMAC_DMAIPR (BDMAC_BASE + 0x0304) /* DMA interrupt pending */
2669#define BDMAC_DMADBR (BDMAC_BASE + 0x0308) /* DMA doorbell */
2670#define BDMAC_DMADBSR (BDMAC_BASE + 0x030C) /* DMA doorbell set */
2671#define BDMAC_DMACKE (BDMAC_BASE + 0x0310)
2672#define BDMAC_DMACKES (BDMAC_BASE + 0x0314)
2673#define BDMAC_DMACKEC (BDMAC_BASE + 0x0318)
2674
2675#define REG_BDMAC_DSAR(n) REG32(BDMAC_DSAR((n)))
2676#define REG_BDMAC_DTAR(n) REG32(BDMAC_DTAR((n)))
2677#define REG_BDMAC_DTCR(n) REG32(BDMAC_DTCR((n)))
2678#define REG_BDMAC_DRSR(n) REG32(BDMAC_DRSR((n)))
2679#define REG_BDMAC_DCCSR(n) REG32(BDMAC_DCCSR((n)))
2680#define REG_BDMAC_DCMD(n) REG32(BDMAC_DCMD((n)))
2681#define REG_BDMAC_DDA(n) REG32(BDMAC_DDA((n)))
2682#define REG_BDMAC_DSD(n) REG32(BDMAC_DSD(n))
2683#define REG_BDMAC_DNT(n) REG32(BDMAC_DNT(n))
2684
2685#define REG_BDMAC_DMACR REG32(BDMAC_DMACR)
2686#define REG_BDMAC_DMAIPR REG32(BDMAC_DMAIPR)
2687#define REG_BDMAC_DMADBR REG32(BDMAC_DMADBR)
2688#define REG_BDMAC_DMADBSR REG32(BDMAC_DMADBSR)
2689#define REG_BDMAC_DMACKE REG32(BDMAC_DMACKE)
2690#define REG_BDMAC_DMACKES REG32(BDMAC_DMACKES)
2691#define REG_BDMAC_DMACKEC REG32(BDMAC_DMACKEC)
2692
2693// BDMA request source register
2694#define BDMAC_DRSR_RS_BIT 0
2695 #define BDMAC_DRSR_RS_MASK (0x3f << DMAC_DRSR_RS_BIT)
2696 #define BDMAC_DRSR_RS_BCH_ENC (2 << DMAC_DRSR_RS_BIT)
2697 #define BDMAC_DRSR_RS_BCH_DEC (3 << DMAC_DRSR_RS_BIT)
2698 #define BDMAC_DRSR_RS_NAND0 (6 << DMAC_DRSR_RS_BIT)
2699 #define BDMAC_DRSR_RS_NAND1 (7 << DMAC_DRSR_RS_BIT)
2700 #define BDMAC_DRSR_RS_NAND (BDMAC_DRSR_RS_NAND0)
2701 #define BDMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
2702 #define BDMAC_DRSR_RS_EXT (12 << DMAC_DRSR_RS_BIT)
2703
2704// BDMA channel control/status register
2705#define BDMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
2706#define BDMAC_DCCSR_DES8 (1 << 30) /* Descriptor 8 Word */
2707#define BDMAC_DCCSR_DES4 (0 << 30) /* Descriptor 4 Word */
2708#define BDMAC_DCCSR_LASTMD_BIT 28
2709#define BDMAC_DCCSR_LASTMD_MASK (0x3 << BDMAC_DCCSR_LASTMD_BIT)
2710#define BDMAC_DCCSR_LASTMD0 (0 << 28) /* BCH Decoding last mode 0, there's one descriptor for decoding blcok*/
2711#define BDMAC_DCCSR_LASTMD1 (1 << 28) /* BCH Decoding last mode 1, there's two descriptor for decoding blcok*/
2712#define BDMAC_DCCSR_LASTMD2 (2 << 28) /* BCH Decoding last mode 2, there's three descriptor for decoding blcok*/
2713#define BDMAC_DCCSR_FRBS(n) ((n) << 24)
2714#define BDMAC_DCCSR_FRBS_BIT 24
2715#define BDMAC_DCCSR_FRBS_MASK (0x7 << BDMAC_DCCSR_FRBS_BIT)
2716#define BDMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
2717#define BDMAC_DCCSR_CDOA_MASK (0xff << BDMACC_DCCSR_CDOA_BIT)
2718#define BDMAC_DCCSR_BERR_BIT 7
2719#define BDMAC_DCCSR_BERR_MASK (0x1f << BDMAC_DCCSR_BERR_BIT)
2720#define BDMAC_DCCSR_BUERR (1 << 5)
2721#define BDMAC_DCCSR_AR (1 << 4) /* address error */
2722#define BDMAC_DCCSR_TT (1 << 3) /* transfer terminated */
2723#define BDMAC_DCCSR_HLT (1 << 2) /* DMA halted */
2724#define BDMAC_DCCSR_BAC (1 << 1)
2725#define BDMAC_DCCSR_EN (1 << 0) /* channel enable bit */
2726
2727// BDMA channel command register
2728#define BDMAC_DCMD_EACKS_LOW (1 << 31) /* External DACK Output Level Select, active low */
2729#define BDMAC_DCMD_EACKS_HIGH (0 << 31) /* External DACK Output Level Select, active high */
2730#define BDMAC_DCMD_EACKM_WRITE (1 << 30) /* External DACK Output Mode Select, output in write cycle */
2731#define BDMAC_DCMD_EACKM_READ (0 << 30) /* External DACK Output Mode Select, output in read cycle */
2732#define BDMAC_DCMD_ERDM_BIT 28 /* External DREQ Detection Mode Select */
2733 #define BDMAC_DCMD_ERDM_MASK (0x03 << BDMAC_DCMD_ERDM_BIT)
2734 #define BDMAC_DCMD_ERDM_LOW (0 << BDMAC_DCMD_ERDM_BIT)
2735 #define BDMAC_DCMD_ERDM_FALL (1 << BDMAC_DCMD_ERDM_BIT)
2736 #define BDMAC_DCMD_ERDM_HIGH (2 << BDMAC_DCMD_ERDM_BIT)
2737 #define BDMAC_DCMD_ERDM_RISE (3 << BDMAC_DCMD_ERDM_BIT)
2738#define BDMAC_DCMD_BLAST (1 << 25) /* BCH last */
2739#define BDMAC_DCMD_SAI (1 << 23) /* source address increment */
2740#define BDMAC_DCMD_DAI (1 << 22) /* dest address increment */
2741#define BDMAC_DCMD_SWDH_BIT 14 /* source port width */
2742 #define BDMAC_DCMD_SWDH_MASK (0x03 << BDMAC_DCMD_SWDH_BIT)
2743 #define BDMAC_DCMD_SWDH_32 (0 << BDMAC_DCMD_SWDH_BIT)
2744 #define BDMAC_DCMD_SWDH_8 (1 << BDMAC_DCMD_SWDH_BIT)
2745 #define BDMAC_DCMD_SWDH_16 (2 << BDMAC_DCMD_SWDH_BIT)
2746#define BDMAC_DCMD_DWDH_BIT 12 /* dest port width */
2747 #define BDMAC_DCMD_DWDH_MASK (0x03 << BDMAC_DCMD_DWDH_BIT)
2748 #define BDMAC_DCMD_DWDH_32 (0 << BDMAC_DCMD_DWDH_BIT)
2749 #define BDMAC_DCMD_DWDH_8 (1 << BDMAC_DCMD_DWDH_BIT)
2750 #define BDMAC_DCMD_DWDH_16 (2 << BDMAC_DCMD_DWDH_BIT)
2751#define BDMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
2752 #define BDMAC_DCMD_DS_MASK (0x07 << BDMAC_DCMD_DS_BIT)
2753 #define BDMAC_DCMD_DS_32BIT (0 << BDMAC_DCMD_DS_BIT)
2754 #define BDMAC_DCMD_DS_8BIT (1 << BDMAC_DCMD_DS_BIT)
2755 #define BDMAC_DCMD_DS_16BIT (2 << BDMAC_DCMD_DS_BIT)
2756 #define BDMAC_DCMD_DS_16BYTE (3 << BDMAC_DCMD_DS_BIT)
2757 #define BDMAC_DCMD_DS_32BYTE (4 << BDMAC_DCMD_DS_BIT)
2758 #define BDMAC_DCMD_DS_64BYTE (5 << BDMAC_DCMD_DS_BIT)
2759#define BDMAC_DCMD_NRD (1 << 7) /* NAND direct read */
2760#define BDMAC_DCMD_NWR (1 << 6) /* NAND direct write */
2761#define BDMAC_DCMD_NAC (1 << 5) /* NAND AL/CL enable */
2762#define BDMAC_DCMD_NSTA (1 << 4)
2763#define BDMAC_DCMD_STDE (1 << 2) /* Stride Disable/Enable */
2764#define BDMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
2765#define BDMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
2766
2767// BDMA descriptor address register
2768#define BDMAC_DDA_BASE_BIT 12 /* descriptor base address */
2769 #define BDMAC_DDA_BASE_MASK (0x0fffff << BDMAC_DDA_BASE_BIT)
2770#define BDMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
2771 #define BDMAC_DDA_OFFSET_MASK (0x0ff << BDMAC_DDA_OFFSET_BIT)
2772
2773// BDMA stride address register
2774#define BDMAC_DSD_TSD_BIT 16 /* target stride address */
2775 #define BDMAC_DSD_TSD_MASK (0xffff << BDMAC_DSD_TSD_BIT)
2776#define BDMAC_DSD_SSD_BIT 0 /* source stride address */
2777 #define BDMAC_DSD_SSD_MASK (0xffff << BDMAC_DSD_SSD_BIT)
2778
2779// BDMA NAND Detect timer register
2780#define BDMAC_NDTCTIMER_EN (1 << 15) /* enable detect timer */
2781#define BDMAC_TAILCNT_BIT 16
2782
2783// BDMA control register
2784#define BDMAC_DMACR_PR_BIT 8 /* channel priority mode */
2785 #define BDMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
2786 #define BDMAC_DMACR_PR_01_2 (0 << BDMAC_DMACR_PR_BIT)
2787 #define BDMAC_DMACR_PR_12_0 (1 << BDMAC_DMACR_PR_BIT)
2788 #define BDMAC_DMACR_PR_20_1 (2 << BDMAC_DMACR_PR_BIT)
2789 #define BDMAC_DMACR_PR_012 (3 << BDMAC_DMACR_PR_BIT)
2790#define BDMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
2791#define BDMAC_DMACR_AR (1 << 2) /* address error flag */
2792#define BDMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
2793
2794// BDMA interrupt pending register
2795#define BDMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
2796#define BDMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
2797#define BDMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
2798
2799// BDMA doorbell register
2800#define BDMAC_DMADBR_DB2 (1 << 2) /* doorbell for channel 2 */
2801#define BDMAC_DMADBR_DB1 (1 << 1) /* doorbell for channel 1 */
2802#define BDMAC_DMADBR_DB0 (1 << 0) /* doorbell for channel 0 */
2803
2804// BDMA doorbell set register
2805#define BDMAC_DMADBSR_DBS2 (1 << 2) /* enable doorbell for channel 2 */
2806#define BDMAC_DMADBSR_DBS1 (1 << 1) /* enable doorbell for channel 1 */
2807#define BDMAC_DMADBSR_DBS0 (1 << 0) /* enable doorbell for channel 0 */
2808
2809#ifndef __MIPS_ASSEMBLER
2810
2811/***************************************************************************
2812 * BCH & NAND DMAC
2813 ***************************************************************************/
2814
2815#define __bdmac_enable_module() \
2816 ( REG_BDMAC_DMACR |= BDMAC_DMACR_DMAE )
2817#define __bdmac_disable_module() \
2818 ( REG_BDMAC_DMACR &= ~BDMAC_DMACR_DMAE )
2819
2820/* n is the DMA channel index (0 - 2) */
2821
2822#define __bdmac_test_halt_error ( REG_BDMAC_DMACR & BDMAC_DMACR_HLT )
2823#define __bdmac_test_addr_error ( REG_BDMAC_DMACR & BDMAC_DMACR_AR )
2824
2825#define __bdmac_channel_enable_clk(n) \
2826 REG_BDMAC_DMACKES = 1 << (n);
2827
2828#define __bdmac_enable_descriptor(n) \
2829 ( REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_NDES )
2830#define __bdmac_disable_descriptor(n) \
2831 ( REG_BDMAC_DCCSR((n)) |= BDMAC_DCCSR_NDES )
2832
2833#define __bdmac_enable_channel(n) \
2834do { \
2835 REG_BDMAC_DCCSR((n)) |= BDMAC_DCCSR_EN; \
2836} while (0)
2837#define __bdmac_disable_channel(n) \
2838do { \
2839 REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_EN; \
2840} while (0)
2841
2842#define __bdmac_channel_enable_irq(n) \
2843 ( REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_TIE )
2844#define __bdmac_channel_disable_irq(n) \
2845 ( REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_TIE )
2846
2847#define __bdmac_channel_transmit_halt_detected(n) \
2848 ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_HLT )
2849#define __bdmac_channel_transmit_end_detected(n) \
2850 ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_TT )
2851/* Nand ops status error, only for channel 1 */
2852#define __bdmac_channel_status_error_detected() \
2853 ( REG_BDMAC_DCCSR(1) & BDMAC_DCCSR_NSERR )
2854#define __bdmac_channel_address_error_detected(n) \
2855 ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_AR )
2856#define __bdmac_channel_count_terminated_detected(n) \
2857 ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_CT )
2858#define __bdmac_channel_descriptor_invalid_detected(n) \
2859 ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_INV )
2860#define __bdmac_BCH_error_detected(n) \
2861 ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_BERR )
2862
2863#define __bdmac_channel_clear_transmit_halt(n) \
2864 do { \
2865 /* clear both channel halt error and globle halt error */ \
2866 REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_HLT; \
2867 REG_BDMAC_DMACR &= ~BDMAC_DMACR_HLT; \
2868 } while (0)
2869#define __bdmac_channel_clear_transmit_end(n) \
2870 ( REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_TT )
2871/* Nand ops status error, only for channel 1 */
2872#define __bdmac_channel_clear_status_error() \
2873 ( REG_BDMAC_DCCSR(1) &= ~BDMAC_DCCSR_NSERR )
2874#define __bdmac_channel_clear_address_error(n) \
2875 do { \
2876 REG_BDMAC_DDA(n) = 0; /* clear descriptor address register */ \
2877 REG_BDMAC_DSAR(n) = 0; /* clear source address register */ \
2878 REG_BDMAC_DTAR(n) = 0; /* clear target address register */ \
2879 /* clear both channel addr error and globle address error */ \
2880 REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_AR; \
2881 REG_BDMAC_DMACR &= ~BDMAC_DMACR_AR; \
2882 } while (0)
2883#define __bdmac_channel_clear_count_terminated(n) \
2884 ( REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_CT )
2885#define __bdmac_channel_clear_descriptor_invalid(n) \
2886 ( REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_INV )
2887
2888#define __bdmac_channel_set_transfer_unit_32bit(n) \
2889do { \
2890 REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK; \
2891 REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_32BIT; \
2892} while (0)
2893
2894#define __bdmac_channel_set_transfer_unit_16bit(n) \
2895do { \
2896 REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK; \
2897 REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_16BIT; \
2898} while (0)
2899
2900#define __bdmac_channel_set_transfer_unit_8bit(n) \
2901do { \
2902 REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK; \
2903 REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_8BIT; \
2904} while (0)
2905
2906#define __bdmac_channel_set_transfer_unit_16byte(n) \
2907do { \
2908 REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK; \
2909 REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_16BYTE; \
2910} while (0)
2911
2912#define __bdmac_channel_set_transfer_unit_32byte(n) \
2913do { \
2914 REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK; \
2915 REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_32BYTE; \
2916} while (0)
2917
2918/* w=8,16,32 */
2919#define __bdmac_channel_set_dest_port_width(n,w) \
2920do { \
2921 REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DWDH_MASK; \
2922 REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DWDH_##w; \
2923} while (0)
2924
2925/* w=8,16,32 */
2926#define __bdmac_channel_set_src_port_width(n,w) \
2927do { \
2928 REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_SWDH_MASK; \
2929 REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_SWDH_##w; \
2930} while (0)
2931
2932#define __bdmac_channel_dest_addr_fixed(n) \
2933 (REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DAI)
2934#define __bdmac_channel_dest_addr_increment(n) \
2935 (REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DAI)
2936
2937#define __bdmac_channel_src_addr_fixed(n) \
2938 (REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_SAI)
2939#define __bdmac_channel_src_addr_increment(n) \
2940 (REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_SAI)
2941
2942#define __bdmac_channel_set_doorbell(n) \
2943 (REG_BDMAC_DMADBSR = (1 << (n)))
2944
2945#define __bdmac_channel_irq_detected(n) (REG_BDMAC_DMAIPR & (1 << (n)))
2946#define __bdmac_channel_ack_irq(n) (REG_BDMAC_DMAIPR &= ~(1 <<(n)))
2947
2948static __inline__ int __bdmac_get_irq(void)
2949{
2950 int i;
2951 for (i = 0; i < MAX_BDMA_NUM; i++)
2952 if (__bdmac_channel_irq_detected(i))
2953 return i;
2954 return -1;
2955}
2956
2957#endif /* __MIPS_ASSEMBLER */
2958
2959#define CIM_BASE 0xB3060000
2960
2961/*************************************************************************
2962 * CIM
2963 *************************************************************************/
2964#define CIM_CFG (CIM_BASE + 0x0000)
2965#define CIM_CTRL (CIM_BASE + 0x0004)
2966#define CIM_STATE (CIM_BASE + 0x0008)
2967#define CIM_IID (CIM_BASE + 0x000C)
2968#define CIM_DA (CIM_BASE + 0x0020)
2969#define CIM_FA (CIM_BASE + 0x0024)
2970#define CIM_FID (CIM_BASE + 0x0028)
2971#define CIM_CMD (CIM_BASE + 0x002C)
2972#define CIM_SIZE (CIM_BASE + 0x0030)
2973#define CIM_OFFSET (CIM_BASE + 0x0034)
2974#define CIM_YFA (CIM_BASE + 0x0038)
2975#define CIM_YCMD (CIM_BASE + 0x003C)
2976#define CIM_CBFA (CIM_BASE + 0x0040)
2977#define CIM_CBCMD (CIM_BASE + 0x0044)
2978#define CIM_CRFA (CIM_BASE + 0x0048)
2979#define CIM_CRCMD (CIM_BASE + 0x004C)
2980#define CIM_CTRL2 (CIM_BASE + 0x0050)
2981
2982#define CIM_RAM_ADDR (CIM_BASE + 0x1000)
2983
2984#define REG_CIM_CFG REG32(CIM_CFG)
2985#define REG_CIM_CTRL REG32(CIM_CTRL)
2986#define REG_CIM_STATE REG32(CIM_STATE)
2987#define REG_CIM_IID REG32(CIM_IID)
2988#define REG_CIM_DA REG32(CIM_DA)
2989#define REG_CIM_FA REG32(CIM_FA)
2990#define REG_CIM_FID REG32(CIM_FID)
2991#define REG_CIM_CMD REG32(CIM_CMD)
2992#define REG_CIM_SIZE REG32(CIM_SIZE)
2993#define REG_CIM_OFFSET REG32(CIM_OFFSET)
2994#define REG_CIM_YFA REG32(CIM_YFA)
2995#define REG_CIM_YCMD REG32(CIM_YCMD)
2996#define REG_CIM_CBFA REG32(CIM_CBFA)
2997#define REG_CIM_CBCMD REG32(CIM_CBCMD)
2998#define REG_CIM_CRFA REG32(CIM_CRFA)
2999#define REG_CIM_CRCMD REG32(CIM_CRCMD)
3000#define REG_CIM_CTRL2 REG32(CIM_CTRL2)
3001
3002#define CIM_CFG_EEOFEN (1 << 31)
3003#define CIM_CFG_EXP (1 << 30)
3004
3005#define CIM_CFG_RXF_TRIG_BIT 24
3006#define CIM_CFG_RXF_TRIG_MASK (0x3f << CIM_CFG_RXF_TRIG_BIT)
3007
3008#define CIM_CFG_BW_BIT 22
3009#define CIM_CFG_BW_MASK (0x3 << CIM_CFG_BW_BIT)
3010
3011#define CIM_CFG_SEP (1 << 20)
3012
3013#define CIM_CFG_ORDER_BIT 18
3014#define CIM_CFG_ORDER_MASK (0x3 << CIM_CFG_ORDER_BIT)
3015#define CIM_CFG_ORDER_0 (0x0 << CIM_CFG_ORDER_BIT) /* Y0CbY1Cr; YCbCr */
3016#define CIM_CFG_ORDER_1 (0x1 << CIM_CFG_ORDER_BIT) /* Y0CrY1Cb; YCrCb */
3017#define CIM_CFG_ORDER_2 (0x2 << CIM_CFG_ORDER_BIT) /* CbY0CrY1; CbCrY */
3018#define CIM_CFG_ORDER_3 (0x3 << CIM_CFG_ORDER_BIT) /* CrY0CbY1; CrCbY */
3019
3020#define CIM_CFG_DF_BIT 16
3021#define CIM_CFG_DF_MASK (0x3 << CIM_CFG_DF_BIT)
3022#define CIM_CFG_DF_YUV444 (0x1 << CIM_CFG_DF_BIT) /* YCbCr444 */
3023#define CIM_CFG_DF_YUV422 (0x2 << CIM_CFG_DF_BIT) /* YCbCr422 */
3024#define CIM_CFG_DF_ITU656 (0x3 << CIM_CFG_DF_BIT) /* ITU656 YCbCr422 */
3025
3026#define CIM_CFG_INV_DAT (1 << 15)
3027#define CIM_CFG_VSP (1 << 14) /* VSYNC Polarity:0-rising edge active,1-falling edge active */
3028#define CIM_CFG_HSP (1 << 13) /* HSYNC Polarity:0-rising edge active,1-falling edge active */
3029#define CIM_CFG_PCP (1 << 12) /* PCLK working edge: 0-rising, 1-falling */
3030
3031#define CIM_CFG_DMA_BURST_TYPE_BIT 10
3032#define CIM_CFG_DMA_BURST_TYPE_MASK (0x3 << CIM_CFG_DMA_BURST_TYPE_BIT)
3033#define CIM_CFG_DMA_BURST_INCR4 (0 << CIM_CFG_DMA_BURST_TYPE_BIT)
3034#define CIM_CFG_DMA_BURST_INCR8 (1 << CIM_CFG_DMA_BURST_TYPE_BIT) /* Suggested */
3035#define CIM_CFG_DMA_BURST_INCR16 (2 << CIM_CFG_DMA_BURST_TYPE_BIT) /* Suggested High speed AHB*/
3036#define CIM_CFG_DMA_BURST_INCR32 (3 << CIM_CFG_DMA_BURST_TYPE_BIT) /* Suggested High speed AHB*/
3037
3038#define CIM_CFG_DUMMY_ZERO (1 << 9)
3039#define CIM_CFG_EXT_VSYNC (1 << 8) /* Only for ITU656 Progressive mode */
3040#define CIM_CFG_LM (1 << 7) /* Only for ITU656 Progressive mode */
3041#define CIM_CFG_PACK_BIT 4
3042#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
3043#define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) /* 11 22 33 44 0xY0CbY1Cr */
3044#define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) /* 22 33 44 11 0xCbY1CrY0 */
3045#define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) /* 33 44 11 22 0xY1CrY0Cb */
3046#define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) /* 44 11 22 33 0xCrY0CbY1 */
3047#define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) /* 44 33 22 11 0xCrY1CbY0 */
3048#define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) /* 33 22 11 44 0xY1CbY0Cr */
3049#define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) /* 22 11 44 33 0xCbY0CrY1 */
3050#define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) /* 11 44 33 22 0xY0CrY1Cb */
3051#define CIM_CFG_FP (1 << 3) /* Only for ITU656 Progressive mode */
3052#define CIM_CFG_BYPASS_BIT 2
3053#define CIM_CFG_BYPASS_MASK (1 << CIM_CFG_BYPASS_BIT)
3054#define CIM_CFG_BYPASS (1 << CIM_CFG_BYPASS_BIT)
3055#define CIM_CFG_DSM_BIT 0
3056#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
3057#define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
3058#define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
3059#define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
3060
3061/* CIM Control Register (CIM_CTRL) */
3062#define CIM_CTRL_EEOF_LINE_BIT 20
3063#define CIM_CTRL_EEOF_LINE_MASK (0xfff << CIM_CTRL_EEOF_LINE_BIT)
3064
3065#define CIM_CTRL_FRC_BIT 16
3066#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
3067#define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
3068#define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
3069#define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
3070#define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
3071#define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
3072#define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
3073#define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
3074#define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
3075#define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
3076#define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
3077#define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
3078#define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
3079#define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
3080#define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
3081#define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
3082#define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
3083
3084#define CIM_CTRL_DMA_EEOF (1 << 15) /* Enable EEOF interrupt */
3085#define CIM_CTRL_WIN_EN (1 << 14)
3086#define CIM_CTRL_VDDM (1 << 13) /* VDD interrupt enable */
3087#define CIM_CTRL_DMA_SOFM (1 << 12)
3088#define CIM_CTRL_DMA_EOFM (1 << 11)
3089#define CIM_CTRL_DMA_STOPM (1 << 10)
3090#define CIM_CTRL_RXF_TRIGM (1 << 9)
3091#define CIM_CTRL_RXF_OFM (1 << 8)
3092#define CIM_CTRL_DMA_SYNC (1 << 7) /*when change DA, do frame sync */
3093#define CIM_CTRL_H_SYNC (1 << 6) /*Enable horizental sync when CIMCFG.SEP is 1*/
3094
3095#define CIM_CTRL_PPW_BIT 3
3096#define CIM_CTRL_PPW_MASK (0x3 << CIM_CTRL_PPW_BIT)
3097
3098#define CIM_CTRL_DMA_EN (1 << 2) /* Enable DMA */
3099#define CIM_CTRL_RXF_RST (1 << 1) /* RxFIFO reset */
3100#define CIM_CTRL_ENA (1 << 0) /* Enable CIM */
3101
3102/* cim control2 */
3103#define CIM_CTRL2_OPG_BIT 4
3104#define CIM_CTRL2_OPG_MASK (0x3 << CIM_CTRL2_OPG_BIT)
3105#define CIM_CTRL2_OPE (1 << 2)
3106#define CIM_CTRL2_EME (1 << 1)
3107#define CIM_CTRL2_APM (1 << 0)
3108
3109/* CIM State Register (CIM_STATE) */
3110#define CIM_STATE_CR_RF_OF (1 << 27)
3111#define CIM_STATE_CR_RF_TRIG (1 << 26)
3112#define CIM_STATE_CR_RF_EMPTY (1 << 25)
3113#define CIM_STATE_CB_RF_OF (1 << 19)
3114#define CIM_STATE_CB_RF_TRIG (1 << 18)
3115#define CIM_STATE_CB_RF_EMPTY (1 << 17)
3116#define CIM_STATE_Y_RF_OF (1 << 11)
3117#define CIM_STATE_Y_RF_TRIG (1 << 10)
3118#define CIM_STATE_Y_RF_EMPTY (1 << 9)
3119#define CIM_STATE_DMA_EEOF (1 << 7) /* DMA Line EEOf irq */
3120#define CIM_STATE_DMA_SOF (1 << 6) /* DMA start irq */
3121#define CIM_STATE_DMA_EOF (1 << 5) /* DMA end irq */
3122#define CIM_STATE_DMA_STOP (1 << 4) /* DMA stop irq */
3123#define CIM_STATE_RXF_OF (1 << 3) /* RXFIFO over flow irq */
3124#define CIM_STATE_RXF_TRIG (1 << 2) /* RXFIFO triger meet irq */
3125#define CIM_STATE_RXF_EMPTY (1 << 1) /* RXFIFO empty irq */
3126#define CIM_STATE_VDD (1 << 0) /* CIM disabled irq */
3127
3128/* CIM DMA Command Register (CIM_CMD) */
3129
3130#define CIM_CMD_SOFINT (1 << 31) /* enable DMA start irq */
3131#define CIM_CMD_EOFINT (1 << 30) /* enable DMA end irq */
3132#define CIM_CMD_EEOFINT (1 << 29) /* enable DMA EEOF irq */
3133#define CIM_CMD_STOP (1 << 28) /* enable DMA stop irq */
3134#define CIM_CMD_OFRCV (1 << 27) /* enable recovery when TXFiFo overflow */
3135#define CIM_CMD_LEN_BIT 0
3136#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
3137
3138/* CIM Window-Image Size Register (CIM_SIZE) */
3139#define CIM_SIZE_LPF_BIT 16 /* Lines per freame for csc output image */
3140#define CIM_SIZE_LPF_MASK (0x1fff << CIM_SIZE_LPF_BIT)
3141#define CIM_SIZE_PPL_BIT 0 /* Pixels per line for csc output image, should be an even number */
3142#define CIM_SIZE_PPL_MASK (0x1fff << CIM_SIZE_PPL_BIT)
3143
3144/* CIM Image Offset Register (CIM_OFFSET) */
3145#define CIM_OFFSET_V_BIT 16 /* Vertical offset */
3146#define CIM_OFFSET_V_MASK (0xfff << CIM_OFFSET_V_BIT)
3147#define CIM_OFFSET_H_BIT 0 /* Horizontal offset, should be an enen number */
3148#define CIM_OFFSET_H_MASK (0xfff << CIM_OFFSET_H_BIT) /*OFFSET_H should be even number*/
3149
3150#define CIM_YCMD_SOFINT (1 << 31) /* enable DMA start irq */
3151#define CIM_YCMD_EOFINT (1 << 30) /* enable DMA end irq */
3152#define CIM_YCMD_EEOFINT (1 << 29) /* enable DMA EEOF irq */
3153#define CIM_YCMD_STOP (1 << 28) /* enable DMA stop irq */
3154#define CIM_YCMD_OFRCV (1 << 27) /* enable recovery when TXFiFo overflow */
3155#define CIM_YCMD_LEN_BIT 0
3156#define CIM_YCMD_LEN_MASK (0xffffff << CIM_YCMD_LEN_BIT)
3157
3158#define CIM_CBCMD_LEN_BIT 0
3159#define CIM_CBCMD_LEN_MASK (0xffffff << CIM_CBCMD_LEN_BIT)
3160
3161#define CIM_CRCMD_LEN_BIT 0
3162#define CIM_CRCMD_LEN_MASK (0xffffff << CIM_CRCMD_LEN_BIT)
3163
3164#ifndef __MIPS_ASSEMBLER
3165
3166/***************************************************************************
3167 * CIM
3168 ***************************************************************************/
3169
3170#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA )
3171#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA )
3172
3173#define __cim_enable_sep() (REG_CIM_CFG |= CIM_CFG_SEP)
3174#define __cim_disable_sep() (REG_CIM_CFG &= ~CIM_CFG_SEP)
3175
3176/* n = 0, 1, 2, 3 */
3177#define __cim_set_input_data_stream_order(n) \
3178 do { \
3179 REG_CIM_CFG &= ~CIM_CFG_ORDER_MASK; \
3180 REG_CIM_CFG |= ((n)<<CIM_CFG_ORDER_BIT)&CIM_CFG_ORDER_MASK; \
3181 } while (0)
3182
3183#define __cim_input_data_format_select_YUV444() \
3184 do { \
3185 REG_CIM_CFG &= ~CIM_CFG_DF_MASK; \
3186 REG_CIM_CFG |= CIM_CFG_DF_YUV444; \
3187 } while (0)
3188
3189#define __cim_input_data_format_select_YUV422() \
3190 do { \
3191 REG_CIM_CFG &= ~CIM_CFG_DF_MASK; \
3192 REG_CIM_CFG |= CIM_CFG_DF_YUV422; \
3193 } while (0)
3194
3195#define __cim_input_data_format_select_ITU656() \
3196 do { \
3197 REG_CIM_CFG &= ~CIM_CFG_DF_MASK; \
3198 REG_CIM_CFG |= CIM_CFG_DF_ITU656; \
3199 } while (0)
3200
3201#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT )
3202#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )
3203
3204#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP )
3205#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP )
3206
3207#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP )
3208#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP )
3209
3210#define __cim_sample_data_at_pclk_falling_edge() \
3211 ( REG_CIM_CFG |= CIM_CFG_PCP )
3212#define __cim_sample_data_at_pclk_rising_edge() \
3213 ( REG_CIM_CFG &= ~CIM_CFG_PCP )
3214
3215#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )
3216#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )
3217
3218#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )
3219#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )
3220
3221/* n=0-7 */
3222#define __cim_set_data_packing_mode(n) \
3223 do { \
3224 REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \
3225 REG_CIM_CFG |= (CIM_CFG_PACK_##n); \
3226 } while (0)
3227
3228#define __cim_enable_bypass_func() (REG_CIM_CFG &= ~CIM_CFG_BYPASS)
3229#define __cim_disable_bypass_func() (REG_CIM_CFG |= CIM_CFG_BYPASS)
3230
3231#define __cim_enable_ccir656_progressive_mode() \
3232 do { \
3233 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
3234 REG_CIM_CFG |= CIM_CFG_DSM_CPM; \
3235 } while (0)
3236
3237#define __cim_enable_ccir656_interlace_mode() \
3238 do { \
3239 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
3240 REG_CIM_CFG |= CIM_CFG_DSM_CIM; \
3241 } while (0)
3242
3243#define __cim_enable_gated_clock_mode() \
3244 do { \
3245 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
3246 REG_CIM_CFG |= CIM_CFG_DSM_GCM; \
3247 } while (0)
3248
3249#define __cim_enable_nongated_clock_mode() \
3250 do { \
3251 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
3252 REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \
3253 } while (0)
3254
3255/* n=1-16 */
3256#define __cim_set_frame_rate(n) \
3257 do { \
3258 REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \
3259 REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \
3260 } while (0)
3261
3262#define __cim_enable_size_func() \
3263 ( REG_CIM_CTRL |= CIM_CTRL_WIN_EN)
3264#define __cim_disable_size_func() \
3265 ( REG_CIM_CTRL &= ~CIM_CTRL_WIN_EN )
3266
3267#define __cim_enable_vdd_intr() \
3268 ( REG_CIM_CTRL |= CIM_CTRL_VDDM )
3269#define __cim_disable_vdd_intr() \
3270 ( REG_CIM_CTRL &= ~CIM_CTRL_VDDM )
3271
3272#define __cim_enable_sof_intr() \
3273 ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )
3274#define __cim_disable_sof_intr() \
3275 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )
3276
3277#define __cim_enable_eof_intr() \
3278 ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )
3279#define __cim_disable_eof_intr() \
3280 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )
3281
3282#define __cim_enable_eeof_intr() \
3283 ( REG_CIM_CTRL |= CIM_CTRL_DMA_EEOFM )
3284#define __cim_disable_eeof_intr() \
3285 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EEOFM )
3286
3287#define __cim_enable_stop_intr() \
3288 ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )
3289#define __cim_disable_stop_intr() \
3290 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )
3291
3292#define __cim_enable_trig_intr() \
3293 ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )
3294#define __cim_disable_trig_intr() \
3295 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )
3296
3297#define __cim_enable_rxfifo_overflow_intr() \
3298 ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )
3299#define __cim_disable_rxfifo_overflow_intr() \
3300 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )
3301
3302#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )
3303#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )
3304#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )
3305#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )
3306
3307/* cim control2 */
3308#define __cim_enable_priority_control() ( REG_CIM_CTRL2 |= CIM_CTRL2_OPE)
3309#define __cim_disable_priority_control() ( REG_CIM_CTRL2 &= ~CIM_CTRL2_OPE)
3310#define __cim_enable_auto_priority() ( REG_CIM_CTRL2 |= CIM_CTRL2_APM)
3311#define __cim_disable_auto_priority() ( REG_CIM_CTRL2 &= ~CIM_CTRL2_APM)
3312#define __cim_enable_emergency() ( REG_CIM_CTRL2 |= CIM_CTRL2_EME)
3313#define __cim_disable_emergency() ( REG_CIM_CTRL2 &= ~CIM_CTRL2_EME);
3314/* 0, 1, 2, 3
3315 ** 0: highest priority
3316 ** 3: lowest priority
3317 ** 1 maybe best for SEP=1
3318 ** 3 maybe best for SEP=0
3319 **/
3320#define __cim_set_opg(n) \
3321 do { \
3322 REG_CIM_CTRL2 &= ~CIM_CTRL2_OPG_MASK; \
3323 REG_CIM_CTRL2 |= ((n) << CIM_CTRL2_OPG_BIT) & CIM_CTRL2_OPG_MASK; \
3324 } while (0)
3325
3326#define __cim_clear_state() ( REG_CIM_STATE = 0 )
3327
3328#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD )
3329#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )
3330#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )
3331#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF )
3332#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )
3333#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP )
3334#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF )
3335#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF )
3336
3337#define __cim_get_iid() ( REG_CIM_IID )
3338#define __cim_get_fid() ( REG_CIM_FID )
3339//#define __cim_get_image_data() ( REG_CIM_RXFIFO )
3340#define __cim_get_dma_cmd() ( REG_CIM_CMD )
3341
3342#define __cim_set_da(a) ( REG_CIM_DA = (a) )
3343
3344#define __cim_set_line(a) ( REG_CIM_SIZE = (REG_CIM_SIZE&(~CIM_SIZE_LPF_MASK))|((a)<<CIM_SIZE_LPF_BIT) )
3345#define __cim_set_pixel(a) ( REG_CIM_SIZE = (REG_CIM_SIZE&(~CIM_SIZE_PPL_MASK))|((a)<<CIM_SIZE_PPL_BIT) )
3346#define __cim_get_line() ((REG_CIM_SIZE&CIM_SIZE_LPF_MASK)>>CIM_SIZE_LPF_BIT)
3347#define __cim_get_pixel() ((REG_CIM_SIZE&CIM_SIZE_PPL_MASK)>>CIM_SIZE_PPL_BIT)
3348
3349#define __cim_set_v_offset(a) ( REG_CIM_OFFSET = (REG_CIM_OFFSET&(~CIM_OFFSET_V_MASK)) | ((a)<<CIM_OFFSET_V_BIT) )
3350#define __cim_set_h_offset(a) ( REG_CIM_OFFSET = (REG_CIM_OFFSET&(~CIM_OFFSET_H_MASK)) | ((a)<<CIM_OFFSET_H_BIT) )
3351#define __cim_get_v_offset() ((REG_CIM_OFFSET&CIM_OFFSET_V_MASK)>>CIM_OFFSET_V_BIT)
3352#define __cim_get_h_offset() ((REG_CIM_OFFSET&CIM_OFFSET_H_MASK)>>CIM_OFFSET_H_BIT)
3353
3354#endif /* __MIPS_ASSEMBLER */
3355
3356/*
3357 * Clock reset and power controller module(CPM) address definition
3358 */
3359#define CPM_BASE 0xb0000000
3360
3361/*
3362 * CPM registers offset address definition
3363 */
3364#define CPM_CPCCR_OFFSET (0x00) /* rw, 32, 0x01011100 */
3365#define CPM_LCR_OFFSET (0x04) /* rw, 32, 0x000000f8 */
3366#define CPM_RSR_OFFSET (0x08) /* rw, 32, 0x???????? */
3367#define CPM_CPPCR0_OFFSET (0x10) /* rw, 32, 0x28080011 */
3368#define CPM_CPPSR_OFFSET (0x14) /* rw, 32, 0x80000000 */
3369#define CPM_CLKGR0_OFFSET (0x20) /* rw, 32, 0x3fffffe0 */
3370#define CPM_OPCR_OFFSET (0x24) /* rw, 32, 0x00001570 */
3371#define CPM_CLKGR1_OFFSET (0x28) /* rw, 32, 0x0000017f */
3372#define CPM_CPPCR1_OFFSET (0x30) /* rw, 32, 0x28080002 */
3373#define CPM_CPSPR_OFFSET (0x34) /* rw, 32, 0x???????? */
3374#define CPM_CPSPPR_OFFSET (0x38) /* rw, 32, 0x0000a5a5 */
3375#define CPM_USBPCR_OFFSET (0x3c) /* rw, 32, 0x42992198 */
3376#define CPM_USBRDT_OFFSET (0x40) /* rw, 32, 0x00000096 */
3377#define CPM_USBVBFIL_OFFSET (0x44) /* rw, 32, 0x00000080 */
3378#define CPM_USBCDR_OFFSET (0x50) /* rw, 32, 0x00000000 */
3379#define CPM_I2SCDR_OFFSET (0x60) /* rw, 32, 0x00000000 */
3380#define CPM_LPCDR_OFFSET (0x64) /* rw, 32, 0x00000000 */
3381#define CPM_MSCCDR_OFFSET (0x68) /* rw, 32, 0x00000000 */
3382#define CPM_UHCCDR_OFFSET (0x6c) /* rw, 32, 0x00000000 */
3383#define CPM_SSICDR_OFFSET (0x74) /* rw, 32, 0x00000000 */
3384#define CPM_CIMCDR_OFFSET (0x7c) /* rw, 32, 0x00000000 */
3385#define CPM_GPSCDR_OFFSET (0x80) /* rw, 32, 0x00000000 */
3386#define CPM_PCMCDR_OFFSET (0x84) /* rw, 32, 0x00000000 */
3387#define CPM_GPUCDR_OFFSET (0x88) /* rw, 32, 0x00000000 */
3388#define CPM_PSWC0ST_OFFSET (0x90) /* rw, 32, 0x00000000 */
3389#define CPM_PSWC1ST_OFFSET (0x94) /* rw, 32, 0x00000000 */
3390#define CPM_PSWC2ST_OFFSET (0x98) /* rw, 32, 0x00000000 */
3391#define CPM_PSWC3ST_OFFSET (0x9c) /* rw, 32, 0x00000000 */
3392
3393/*
3394 * CPM registers address definition
3395 */
3396#define CPM_CPCCR (CPM_BASE + CPM_CPCCR_OFFSET)
3397#define CPM_LCR (CPM_BASE + CPM_LCR_OFFSET)
3398#define CPM_RSR (CPM_BASE + CPM_RSR_OFFSET)
3399#define CPM_CPPCR0 (CPM_BASE + CPM_CPPCR0_OFFSET)
3400#define CPM_CPPSR (CPM_BASE + CPM_CPPSR_OFFSET)
3401#define CPM_CLKGR0 (CPM_BASE + CPM_CLKGR0_OFFSET)
3402#define CPM_OPCR (CPM_BASE + CPM_OPCR_OFFSET)
3403#define CPM_CLKGR1 (CPM_BASE + CPM_CLKGR1_OFFSET)
3404#define CPM_CPPCR1 (CPM_BASE + CPM_CPPCR1_OFFSET)
3405#define CPM_CPSPR (CPM_BASE + CPM_CPSPR_OFFSET)
3406#define CPM_CPSPPR (CPM_BASE + CPM_CPSPPR_OFFSET)
3407#define CPM_USBPCR (CPM_BASE + CPM_USBPCR_OFFSET)
3408#define CPM_USBRDT (CPM_BASE + CPM_USBRDT_OFFSET)
3409#define CPM_USBVBFIL (CPM_BASE + CPM_USBVBFIL_OFFSET)
3410#define CPM_USBCDR (CPM_BASE + CPM_USBCDR_OFFSET)
3411#define CPM_I2SCDR (CPM_BASE + CPM_I2SCDR_OFFSET)
3412#define CPM_LPCDR (CPM_BASE + CPM_LPCDR_OFFSET)
3413#define CPM_MSCCDR (CPM_BASE + CPM_MSCCDR_OFFSET)
3414#define CPM_UHCCDR (CPM_BASE + CPM_UHCCDR_OFFSET)
3415#define CPM_SSICDR (CPM_BASE + CPM_SSICDR_OFFSET)
3416#define CPM_CIMCDR (CPM_BASE + CPM_CIMCDR_OFFSET)
3417#define CPM_GPSCDR (CPM_BASE + CPM_GPSCDR_OFFSET)
3418#define CPM_PCMCDR (CPM_BASE + CPM_PCMCDR_OFFSET)
3419#define CPM_GPUCDR (CPM_BASE + CPM_GPUCDR_OFFSET)
3420#define CPM_PSWC0ST (CPM_BASE + CPM_PSWC0ST_OFFSET)
3421#define CPM_PSWC1ST (CPM_BASE + CPM_PSWC1ST_OFFSET)
3422#define CPM_PSWC2ST (CPM_BASE + CPM_PSWC2ST_OFFSET)
3423#define CPM_PSWC3ST (CPM_BASE + CPM_PSWC3ST_OFFSET)
3424
3425/*
3426 * CPM registers common define
3427 */
3428
3429/* Clock control register(CPCCR) */
3430#define CPCCR_ECS BIT31
3431#define CPCCR_MEM BIT30
3432#define CPCCR_CE BIT22
3433#define CPCCR_PCS BIT21
3434
3435#define CPCCR_SDIV_LSB 24
3436#define CPCCR_SDIV_MASK BITS_H2L(27, CPCCR_SDIV_LSB)
3437
3438#define CPCCR_H2DIV_LSB 16
3439#define CPCCR_H2DIV_MASK BITS_H2L(19, CPCCR_H2DIV_LSB)
3440
3441#define CPCCR_MDIV_LSB 12
3442#define CPCCR_MDIV_MASK BITS_H2L(15, CPCCR_MDIV_LSB)
3443
3444#define CPCCR_PDIV_LSB 8
3445#define CPCCR_PDIV_MASK BITS_H2L(11, CPCCR_PDIV_LSB)
3446
3447#define CPCCR_HDIV_LSB 4
3448#define CPCCR_HDIV_MASK BITS_H2L(7, CPCCR_HDIV_LSB)
3449
3450#define CPCCR_CDIV_LSB 0
3451#define CPCCR_CDIV_MASK BITS_H2L(3, CPCCR_CDIV_LSB)
3452
3453/* Low power control register(LCR) */
3454#define LCR_PDAHB1 BIT30
3455#define LCR_PDAHB1S BIT26
3456#define LCR_DOZE BIT2
3457
3458#define LCR_PST_LSB 8
3459#define LCR_PST_MASK BITS_H2L(19, LCR_PST_LSB)
3460
3461#define LCR_DUTY_LSB 3
3462#define LCR_DUTY_MASK BITS_H2L(7, LCR_DUTY_LSB)
3463
3464#define LCR_LPM_LSB 0
3465#define LCR_LPM_MASK BITS_H2L(1, LCR_LPM_LSB)
3466#define LCR_LPM_IDLE (0x0 << LCR_LPM_LSB)
3467#define LCR_LPM_SLEEP (0x1 << LCR_LPM_LSB)
3468
3469/* Reset status register(RSR) */
3470#define RSR_P0R BIT2
3471#define RSR_WR BIT1
3472#define RSR_PR BIT0
3473
3474/* PLL control register 0(CPPCR0) */
3475#define CPPCR0_LOCK BIT15 /* LOCK0 bit */
3476#define CPPCR0_PLLS BIT10
3477#define CPPCR0_PLLBP BIT9
3478#define CPPCR0_PLLEN BIT8
3479
3480#define CPPCR0_PLLM_LSB 24
3481#define CPPCR0_PLLM_MASK BITS_H2L(30, CPPCR0_PLLM_LSB)
3482
3483#define CPPCR0_PLLN_LSB 18
3484#define CPPCR0_PLLN_MASK BITS_H2L(21, CPPCR0_PLLN_LSB)
3485
3486#define CPPCR0_PLLOD_LSB 16
3487#define CPPCR0_PLLOD_MASK BITS_H2L(17, CPPCR0_PLLOD_LSB)
3488
3489#define CPPCR0_PLLST_LSB 0
3490#define CPPCR0_PLLST_MASK BITS_H2L(7, CPPCR0_PLLST_LSB)
3491
3492/* PLL switch and status register(CPPSR) */
3493#define CPPSR_PLLOFF BIT31
3494#define CPPSR_PLLBP BIT30
3495#define CPPSR_PLLON BIT29
3496#define CPPSR_PS BIT28
3497#define CPPSR_FS BIT27
3498#define CPPSR_CS BIT26
3499#define CPPSR_SM BIT2
3500#define CPPSR_PM BIT1
3501#define CPPSR_FM BIT0
3502
3503/* Clock gate register 0(CGR0) */
3504#define CLKGR0_AHB_MON BIT31
3505#define CLKGR0_DDR BIT30
3506#define CLKGR0_IPU BIT29
3507#define CLKGR0_LCD BIT28
3508#define CLKGR0_TVE BIT27
3509#define CLKGR0_CIM BIT26
3510#define CLKGR0_MDMA BIT25
3511#define CLKGR0_UHC BIT24
3512#define CLKGR0_MAC BIT23
3513#define CLKGR0_GPS BIT22
3514#define CLKGR0_DMAC BIT21
3515#define CLKGR0_SSI2 BIT20
3516#define CLKGR0_SSI1 BIT19
3517#define CLKGR0_UART3 BIT18
3518#define CLKGR0_UART2 BIT17
3519#define CLKGR0_UART1 BIT16
3520#define CLKGR0_UART0 BIT15
3521#define CLKGR0_SADC BIT14
3522#define CLKGR0_KBC BIT13
3523#define CLKGR0_MSC2 BIT12
3524#define CLKGR0_MSC1 BIT11
3525#define CLKGR0_OWI BIT10
3526#define CLKGR0_TSSI BIT9
3527#define CLKGR0_AIC BIT8
3528#define CLKGR0_SCC BIT7
3529#define CLKGR0_I2C1 BIT6
3530#define CLKGR0_I2C0 BIT5
3531#define CLKGR0_SSI0 BIT4
3532#define CLKGR0_MSC0 BIT3
3533#define CLKGR0_OTG BIT2
3534#define CLKGR0_BCH BIT1
3535#define CLKGR0_NEMC BIT0
3536
3537/* Oscillator and power control register(OPCR) */
3538#define OPCR_OTGPHY_ENABLE BIT7 /* SPENDN bit */
3539#define OPCR_GPSEN BIT6
3540#define OPCR_UHCPHY_DISABLE BIT5 /* SPENDH bit */
3541#define OPCR_O1SE BIT4
3542#define OPCR_PD BIT3
3543#define OPCR_ERCS BIT2
3544
3545#define OPCR_O1ST_LSB 8
3546#define OPCR_O1ST_MASK BITS_H2L(15, OPCR_O1ST_LSB)
3547
3548/* Clock gate register 1(CGR1) */
3549#define CLKGR1_AUX BIT11
3550#define CLKGR1_OSD BIT10
3551#define CLKGR1_GPU BIT9
3552#define CLKGR1_PCM BIT8
3553#define CLKGR1_AHB1 BIT7
3554#define CLKGR1_CABAC BIT6
3555#define CLKGR1_SRAM BIT5
3556#define CLKGR1_DCT BIT4
3557#define CLKGR1_ME BIT3
3558#define CLKGR1_DBLK BIT2
3559#define CLKGR1_MC BIT1
3560#define CLKGR1_BDMA BIT0
3561
3562/* PLL control register 1(CPPCR1) */
3563#define CPPCR1_P1SCS BIT15
3564#define CPPCR1_PLL1EN BIT7
3565#define CPPCR1_PLL1S BIT6
3566#define CPPCR1_LOCK BIT2 /* LOCK1 bit */
3567#define CPPCR1_PLL1OFF BIT1
3568#define CPPCR1_PLL1ON BIT0
3569
3570#define CPPCR1_PLL1M_LSB 24
3571#define CPPCR1_PLL1M_MASK BITS_H2L(30, CPPCR1_PLL1M_LSB)
3572
3573#define CPPCR1_PLL1N_LSB 18
3574#define CPPCR1_PLL1N_MASK BITS_H2L(21, CPPCR1_PLL1N_LSB)
3575
3576#define CPPCR1_PLL1OD_LSB 16
3577#define CPPCR1_PLL1OD_MASK BITS_H2L(17, CPPCR1_PLL1OD_LSB)
3578
3579#define CPPCR1_P1SDIV_LSB 9
3580#define CPPCR1_P1SDIV_MASK BITS_H2L(14, CPPCR1_P1SDIV_LSB)
3581
3582/* CPM scratch pad protected register(CPSPPR) */
3583#define CPSPPR_CPSPR_WRITABLE (0x00005a5a)
3584
3585/* OTG parameter control register(USBPCR) */
3586#define USBPCR_USB_MODE BIT31
3587#define USBPCR_AVLD_REG BIT30
3588#define USBPCR_INCRM BIT27 /* INCR_MASK bit */
3589#define USBPCR_CLK12_EN BIT26
3590#define USBPCR_COMMONONN BIT25
3591#define USBPCR_VBUSVLDEXT BIT24
3592#define USBPCR_VBUSVLDEXTSEL BIT23
3593#define USBPCR_POR BIT22
3594#define USBPCR_SIDDQ BIT21
3595#define USBPCR_OTG_DISABLE BIT20
3596#define USBPCR_TXPREEMPHTUNE BIT6
3597
3598#define USBPCR_IDPULLUP_LSB 28 /* IDPULLUP_MASK bit */
3599#define USBPCR_IDPULLUP_MASK BITS_H2L(29, USBPCR_USBPCR_IDPULLUP_LSB)
3600
3601#define USBPCR_COMPDISTUNE_LSB 17
3602#define USBPCR_COMPDISTUNE_MASK BITS_H2L(19, USBPCR_COMPDISTUNE_LSB)
3603
3604#define USBPCR_OTGTUNE_LSB 14
3605#define USBPCR_OTGTUNE_MASK BITS_H2L(16, USBPCR_OTGTUNE_LSB)
3606
3607#define USBPCR_SQRXTUNE_LSB 11
3608#define USBPCR_SQRXTUNE_MASK BITS_H2L(13, USBPCR_SQRXTUNE_LSB)
3609
3610#define USBPCR_TXFSLSTUNE_LSB 7
3611#define USBPCR_TXFSLSTUNE_MASK BITS_H2L(10, USBPCR_TXFSLSTUNE_LSB)
3612
3613#define USBPCR_TXRISETUNE_LSB 4
3614#define USBPCR_TXRISETUNE_MASK BITS_H2L(5, USBPCR_TXRISETUNE_LSB)
3615
3616#define USBPCR_TXVREFTUNE_LSB 0
3617#define USBPCR_TXVREFTUNE_MASK BITS_H2L(3, USBPCR_TXVREFTUNE_LSB)
3618
3619/* OTG reset detect timer register(USBRDT) */
3620#define USBRDT_HB_MASK BIT26
3621#define USBRDT_VBFIL_LD_EN BIT25
3622#define USBRDT_IDDIG_EN BIT24
3623#define USBRDT_IDDIG_REG BIT23
3624
3625#define USBRDT_USBRDT_LSB 0
3626#define USBRDT_USBRDT_MASK BITS_H2L(22, USBRDT_USBRDT_LSB)
3627
3628/* OTG PHY clock divider register(USBCDR) */
3629#define USBCDR_UCS BIT31
3630#define USBCDR_UPCS BIT30
3631
3632#define USBCDR_OTGDIV_LSB 0 /* USBCDR bit */
3633#define USBCDR_OTGDIV_MASK BITS_H2L(5, USBCDR_OTGDIV_LSB)
3634
3635/* I2S device clock divider register(I2SCDR) */
3636#define I2SCDR_I2CS BIT31
3637#define I2SCDR_I2PCS BIT30
3638
3639#define I2SCDR_I2SDIV_LSB 0 /* I2SCDR bit */
3640#define I2SCDR_I2SDIV_MASK BITS_H2L(8, I2SCDR_I2SDIV_LSB)
3641
3642/* LCD pix clock divider register(LPCDR) */
3643//#define LPCDR_LSCS BIT31
3644#define LPCDR_LTCS BIT30
3645#define LPCDR_LPCS BIT29
3646
3647#define LPCDR_PIXDIV_LSB 0 /* LPCDR bit */
3648#define LPCDR_PIXDIV_MASK BITS_H2L(10, LPCDR_PIXDIV_LSB)
3649
3650/* MSC clock divider register(MSCCDR) */
3651#define MSCCDR_MCS BIT31
3652
3653#define MSCCDR_MSCDIV_LSB 0 /* MSCCDR bit */
3654#define MSCCDR_MSCDIV_MASK BITS_H2L(4, MSCCDR_MSCDIV_LSB)
3655
3656/* UHC device clock divider register(UHCCDR) */
3657#define UHCCDR_UHPCS BIT31
3658
3659#define UHCCDR_UHCDIV_LSB 0 /* UHCCDR bit */
3660#define UHCCDR_UHCDIV_MASK BITS_H2L(3, UHCCDR_UHCDIV_LSB)
3661
3662/* SSI clock divider register(SSICDR) */
3663#define SSICDR_SCS BIT31
3664
3665#define SSICDR_SSIDIV_LSB 0 /* SSICDR bit */
3666#define SSICDR_SSIDIV_MASK BITS_H2L(3, SSICDR_SSIDIV_LSB)
3667
3668/* CIM mclk clock divider register(CIMCDR) */
3669#define CIMCDR_CIMDIV_LSB 0 /* CIMCDR bit */
3670#define CIMCDR_CIMDIV_MASK BITS_H2L(7, CIMCDR_CIMDIV_LSB)
3671
3672/* GPS clock divider register(GPSCDR) */
3673#define GPSCDR_GPCS BIT31
3674
3675#define GPSCDR_GPSDIV_LSB 0 /* GPSCDR bit */
3676#define GSPCDR_GPSDIV_MASK BITS_H2L(3, GPSCDR_GPSDIV_LSB)
3677
3678/* PCM device clock divider register(PCMCDR) */
3679#define PCMCDR_PCMS BIT31
3680#define PCMCDR_PCMPCS BIT30
3681
3682#define PCMCDR_PCMDIV_LSB 0 /* PCMCDR bit */
3683#define PCMCDR_PCMDIV_MASK BITS_H2L(8, PCMCDR_PCMDIV_LSB)
3684
3685/* GPU clock divider register */
3686#define GPUCDR_GPCS BIT31
3687#define GPUCDR_GPUDIV_LSB 0 /* GPUCDR bit */
3688#define GPUCDR_GPUDIV_MASK BITS_H2L(2, GPUCDR_GPUDIV_LSB)
3689
3690#ifndef __MIPS_ASSEMBLER
3691
3692#define REG_CPM_CPCCR REG32(CPM_CPCCR)
3693#define REG_CPM_RSR REG32(CPM_RSR)
3694#define REG_CPM_CPPCR0 REG32(CPM_CPPCR0)
3695#define REG_CPM_CPPSR REG32(CPM_CPPSR)
3696#define REG_CPM_CPPCR1 REG32(CPM_CPPCR1)
3697#define REG_CPM_CPSPR REG32(CPM_CPSPR)
3698#define REG_CPM_CPSPPR REG32(CPM_CPSPPR)
3699#define REG_CPM_USBPCR REG32(CPM_USBPCR)
3700#define REG_CPM_USBRDT REG32(CPM_USBRDT)
3701#define REG_CPM_USBVBFIL REG32(CPM_USBVBFIL)
3702#define REG_CPM_USBCDR REG32(CPM_USBCDR)
3703#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
3704#define REG_CPM_LPCDR REG32(CPM_LPCDR)
3705#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
3706#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
3707#define REG_CPM_SSICDR REG32(CPM_SSICDR)
3708#define REG_CPM_CIMCDR REG32(CPM_CIMCDR)
3709#define REG_CPM_GPSCDR REG32(CPM_GPSCDR)
3710#define REG_CPM_PCMCDR REG32(CPM_PCMCDR)
3711#define REG_CPM_GPUCDR REG32(CPM_GPUCDR)
3712
3713#define REG_CPM_PSWC0ST REG32(CPM_PSWC0ST)
3714#define REG_CPM_PSWC1ST REG32(CPM_PSWC1ST)
3715#define REG_CPM_PSWC2ST REG32(CPM_PSWC2ST)
3716#define REG_CPM_PSWC3ST REG32(CPM_PSWC3ST)
3717
3718#define REG_CPM_LCR REG32(CPM_LCR)
3719#define REG_CPM_CLKGR0 REG32(CPM_CLKGR0)
3720#define REG_CPM_OPCR REG32(CPM_OPCR)
3721#define REG_CPM_CLKGR1 REG32(CPM_CLKGR1)
3722#define REG_CPM_CLKGR REG32(CPM_CLKGR0)
3723
3724#define cpm_get_scrpad() INREG32(CPM_CPSPR)
3725#define cpm_set_scrpad(data) \
3726do { \
3727 OUTREG32(CPM_CPSPPR, CPSPPR_CPSPR_WRITABLE); \
3728 OUTREG32(CPM_CPSPR, data); \
3729 OUTREG32(CPM_CPSPPR, ~CPSPPR_CPSPR_WRITABLE); \
3730} while (0)
3731
3732#define CPM_POWER_ON 1
3733#define CPM_POWER_OFF 0
3734
3735/***************************************************************************
3736 * CPM *
3737 ***************************************************************************/
3738#define __cpm_get_pllm() \
3739 ((REG_CPM_CPPCR0 & CPPCR0_PLLM_MASK) >> CPPCR0_PLLM_LSB)
3740#define __cpm_get_plln() \
3741 ((REG_CPM_CPPCR0 & CPPCR0_PLLN_MASK) >> CPPCR0_PLLN_LSB)
3742#define __cpm_get_pllod() \
3743 ((REG_CPM_CPPCR0 & CPPCR0_PLLOD_MASK) >> CPPCR0_PLLOD_LSB)
3744
3745#define __cpm_get_pll1m() \
3746 ((REG_CPM_CPPCR1 & CPPCR1_PLL1M_MASK) >> CPPCR1_PLL1M_LSB)
3747#define __cpm_get_pll1n() \
3748 ((REG_CPM_CPPCR1 & CPPCR1_PLL1N_MASK) >> CPPCR1_PLL1N_LSB)
3749#define __cpm_get_pll1od() \
3750 ((REG_CPM_CPPCR1 & CPPCR1_PLL1OD_MASK) >> CPPCR1_PLL1OD_LSB)
3751
3752#define __cpm_get_cdiv() \
3753 ((REG_CPM_CPCCR & CPCCR_CDIV_MASK) >> CPCCR_CDIV_LSB)
3754#define __cpm_get_hdiv() \
3755 ((REG_CPM_CPCCR & CPCCR_HDIV_MASK) >> CPCCR_HDIV_LSB)
3756#define __cpm_get_h2div() \
3757 ((REG_CPM_CPCCR & CPCCR_H2DIV_MASK) >> CPCCR_H2DIV_LSB)
3758#define __cpm_get_pdiv() \
3759 ((REG_CPM_CPCCR & CPCCR_PDIV_MASK) >> CPCCR_PDIV_LSB)
3760#define __cpm_get_mdiv() \
3761 ((REG_CPM_CPCCR & CPCCR_MDIV_MASK) >> CPCCR_MDIV_LSB)
3762#define __cpm_get_sdiv() \
3763 ((REG_CPM_CPCCR & CPCCR_SDIV_MASK) >> CPCCR_SDIV_LSB)
3764#define __cpm_get_i2sdiv() \
3765 ((REG_CPM_I2SCDR & I2SCDR_I2SDIV_MASK) >> I2SCDR_I2SDIV_LSB)
3766#define __cpm_get_pixdiv() \
3767 ((REG_CPM_LPCDR & LPCDR_PIXDIV_MASK) >> LPCDR_PIXDIV_LSB)
3768#define __cpm_get_mscdiv() \
3769 ((REG_CPM_MSCCDR & MSCCDR_MSCDIV_MASK) >> MSCCDR_MSCDIV_LSB)
3770#define __cpm_get_ssidiv() \
3771 ((REG_CPM_SSICCDR & SSICDR_SSICDIV_MASK) >> SSICDR_SSIDIV_LSB)
3772#define __cpm_get_pcmdiv() \
3773 ((REG_CPM_PCMCDR & PCMCDR_PCMCD_MASK) >> PCMCDR_PCMCD_LSB)
3774#define __cpm_get_pll1div() \
3775 ((REG_CPM_CPPCR1 & CPCCR1_P1SDIV_MASK) >> CPCCR1_P1SDIV_LSB)
3776
3777#define __cpm_set_cdiv(v) \
3778 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_CDIV_MASK) | ((v) << (CPCCR_CDIV_LSB)))
3779#define __cpm_set_hdiv(v) \
3780 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_HDIV_MASK) | ((v) << (CPCCR_HDIV_LSB)))
3781#define __cpm_set_pdiv(v) \
3782 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_PDIV_MASK) | ((v) << (CPCCR_PDIV_LSB)))
3783#define __cpm_set_mdiv(v) \
3784 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_MDIV_MASK) | ((v) << (CPCCR_MDIV_LSB)))
3785#define __cpm_set_h1div(v) \
3786 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_H1DIV_MASK) | ((v) << (CPCCR_H1DIV_LSB)))
3787#define __cpm_set_udiv(v) \
3788 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_UDIV_MASK) | ((v) << (CPCCR_UDIV_LSB)))
3789#define __cpm_set_i2sdiv(v) \
3790 (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~I2SCDR_I2SDIV_MASK) | ((v) << (I2SCDR_I2SDIV_LSB)))
3791#define __cpm_set_pixdiv(v) \
3792 (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~LPCDR_PIXDIV_MASK) | ((v) << (LPCDR_PIXDIV_LSB)))
3793#define __cpm_set_mscdiv(v) \
3794 (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~MSCCDR_MSCDIV_MASK) | ((v) << (MSCCDR_MSCDIV_LSB)))
3795#define __cpm_set_ssidiv(v) \
3796 (REG_CPM_SSICDR = (REG_CPM_SSICDR & ~SSICDR_SSIDIV_MASK) | ((v) << (SSICDR_SSIDIV_LSB)))
3797#define __cpm_set_pcmdiv(v) \
3798 (REG_CPM_PCMCDR = (REG_CPM_PCMCDR & ~PCMCDR_PCMCD_MASK) | ((v) << (PCMCDR_PCMCD_LSB)))
3799#define __cpm_set_pll1div(v) \
3800 (REG_CPM_CPPCR1 = (REG_CPM_CPPCR1 & ~CPCCR1_P1SDIV_MASK) | ((v) << (CPCCR1_P1SDIV_LSB)))
3801
3802#define __cpm_select_i2sclk_pll1() (REG_CPM_I2SCDR |= I2SCDR_I2PCS)
3803#define __cpm_select_i2sclk_pll0() (REG_CPM_I2SCDR &= ~I2SCDR_I2PCS)
3804#define __cpm_select_otgclk_pll1() (REG_CPM_USBCDR |= USBCDR_UPCS)
3805#define __cpm_select_otgclk_pll0() (REG_CPM_USBCDR &= ~USBCDR_UPCS)
3806#define __cpm_select_lcdpclk_pll1() (REG_CPM_LPCDR |= LPCDR_LPCS)
3807#define __cpm_select_lcdpclk_pll0() (REG_CPM_LPCDR &= ~LPCDR_LPCS)
3808#define __cpm_select_uhcclk_pll1() (REG_CPM_UHCCDR |= UHCCDR_UHPCS)
3809#define __cpm_select_uhcclk_pll0() (REG_CPM_UHCCDR &= ~UHCCDR_UHPCS)
3810#define __cpm_select_gpsclk_pll1() (REG_CPM_GPSCDR |= GPSCDR_GPCS)
3811#define __cpm_select_gpsclk_pll0() (REG_CPM_GPSCDR &= ~GPSCDR_GPCS)
3812#define __cpm_select_pcmclk_pll1() (REG_CPM_PCMCDR |= PCMCDR_PCMPCS)
3813#define __cpm_select_pcmclk_pll0() (REG_CPM_PCMCDR &= ~PCMCDR_PCMPCS)
3814#define __cpm_select_gpuclk_pll1() (REG_CPM_GPUCDR |= GPUCDR_GPCS)
3815#define __cpm_select_gpuclk_pll0() (REG_CPM_GPUCDR &= ~GPUCDR_GPCS)
3816#define __cpm_select_clk_pll1() (REG_CPM_CDR |= CDR_PCS)
3817#define __cpm_select_clk_pll0() (REG_CPM_CDR &= ~CDR_PCS)
3818
3819
3820#define __cpm_select_pcmclk_pll() (REG_CPM_PCMCDR |= PCMCDR_PCMS)
3821#define __cpm_select_pcmclk_exclk() (REG_CPM_PCMCDR &= ~PCMCDR_PCMS)
3822#define __cpm_select_pixclk_ext() (REG_CPM_LPCDR |= LPCDR_LPCS)
3823#define __cpm_select_pixclk_pll() (REG_CPM_LPCDR &= ~LPCDR_LPCS)
3824#define __cpm_select_tveclk_exclk() (REG_CPM_LPCDR |= CPCCR_LSCS)
3825#define __cpm_select_tveclk_pll() (REG_CPM_LPCDR &= ~LPCDR_LSCS)
3826#define __cpm_select_pixclk_lcd() (REG_CPM_LPCDR &= ~LPCDR_LTCS)
3827#define __cpm_select_pixclk_tve() (REG_CPM_LPCDR |= LPCDR_LTCS)
3828#define __cpm_select_i2sclk_exclk() (REG_CPM_I2SCDR &= ~I2SCDR_I2CS)
3829#define __cpm_select_i2sclk_pll() (REG_CPM_I2SCDR |= I2SCDR_I2CS)
3830//#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPCCR_UCS)
3831//#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPCCR_UCS)
3832
3833#define __cpm_enable_cko()
3834#define __cpm_exclk_direct() (REG_CPM_CPCCR &= ~CPCCR_ECS)
3835#define __cpm_exclk_div2() (REG_CPM_CPCCR |= CPCCR_ECS)
3836#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPCCR_CE)
3837
3838#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPCCR_PCS)
3839#define __cpm_pll_enable() (REG_CPM_CPPCR0 |= CPPCR0_PLLEN)
3840
3841#define __cpm_pll1_enable() (REG_CPM_CPPCR1 |= CPPCR1_PLL1EN)
3842
3843#define __cpm_pll_is_off() (REG_CPM_CPPSR & CPPSR_PLLOFF)
3844#define __cpm_pll_is_on() (REG_CPM_CPPSR & CPPSR_PLLON)
3845#define __cpm_pll_bypass() (REG_CPM_CPPSR |= CPPSR_PLLBP)
3846
3847#define __cpm_get_cclk_doze_duty() \
3848 ((REG_CPM_LCR & LCR_DOZE_DUTY_MASK) >> LCR_DOZE_DUTY_LSB)
3849#define __cpm_set_cclk_doze_duty(v) \
3850 (REG_CPM_LCR = (REG_CPM_LCR & ~LCR_DOZE_DUTY_MASK) | ((v) << (LCR_DOZE_DUTY_LSB)))
3851
3852#define __cpm_doze_mode() (REG_CPM_LCR |= LCR_DOZE_ON)
3853#define __cpm_idle_mode() \
3854 (REG_CPM_LCR = (REG_CPM_LCR & ~LCR_LPM_MASK) | LCR_LPM_IDLE)
3855#define __cpm_sleep_mode() \
3856 (REG_CPM_LCR = (REG_CPM_LCR & ~LCR_LPM_MASK) | LCR_LPM_SLEEP)
3857
3858#define __cpm_stop_all() \
3859 do {\
3860 (REG_CPM_CLKGR0 = 0xffffffff);\
3861 (REG_CPM_CLKGR1 = 0x3ff);\
3862 }while(0)
3863#define __cpm_stop_emc() (REG_CPM_CLKGR0 |= CLKGR0_EMC)
3864#define __cpm_stop_ddr() (REG_CPM_CLKGR0 |= CLKGR0_DDR)
3865#define __cpm_stop_ipu() (REG_CPM_CLKGR0 |= CLKGR0_IPU)
3866#define __cpm_stop_lcd() (REG_CPM_CLKGR0 |= CLKGR0_LCD)
3867#define __cpm_stop_tve() (REG_CPM_CLKGR0 |= CLKGR0_TVE)
3868#define __cpm_stop_Cim() (REG_CPM_CLKGR0 |= CLKGR0_CIM)
3869#define __cpm_stop_mdma() (REG_CPM_CLKGR0 |= CLKGR0_MDMA)
3870#define __cpm_stop_uhc() (REG_CPM_CLKGR0 |= CLKGR0_UHC)
3871#define __cpm_stop_mac() (REG_CPM_CLKGR0 |= CLKGR0_MAC)
3872#define __cpm_stop_gps() (REG_CPM_CLKGR0 |= CLKGR0_GPS)
3873#define __cpm_stop_dmac() (REG_CPM_CLKGR0 |= CLKGR0_DMAC)
3874#define __cpm_stop_ssi2() (REG_CPM_CLKGR0 |= CLKGR0_SSI2)
3875#define __cpm_stop_ssi1() (REG_CPM_CLKGR0 |= CLKGR0_SSI1)
3876#define __cpm_stop_uart3() (REG_CPM_CLKGR0 |= CLKGR0_UART3)
3877#define __cpm_stop_uart2() (REG_CPM_CLKGR0 |= CLKGR0_UART2)
3878#define __cpm_stop_uart1() (REG_CPM_CLKGR0 |= CLKGR0_UART1)
3879#define __cpm_stop_uart0() (REG_CPM_CLKGR0 |= CLKGR0_UART0)
3880#define __cpm_stop_sadc() (REG_CPM_CLKGR0 |= CLKGR0_SADC)
3881#define __cpm_stop_kbc() (REG_CPM_CLKGR0 |= CLKGR0_KBC)
3882#define __cpm_stop_msc2() (REG_CPM_CLKGR0 |= CLKGR0_MSC2)
3883#define __cpm_stop_msc1() (REG_CPM_CLKGR0 |= CLKGR0_MSC1)
3884#define __cpm_stop_owi() (REG_CPM_CLKGR0 |= CLKGR0_OWI)
3885#define __cpm_stop_tssi() (REG_CPM_CLKGR0 |= CLKGR0_TSSI)
3886#define __cpm_stop_aic() (REG_CPM_CLKGR0 |= CLKGR0_AIC)
3887#define __cpm_stop_scc() (REG_CPM_CLKGR0 |= CLKGR0_SCC)
3888#define __cpm_stop_i2c1() (REG_CPM_CLKGR0 |= CLKGR0_I2C1)
3889#define __cpm_stop_i2c0() (REG_CPM_CLKGR0 |= CLKGR0_I2C0)
3890#define __cpm_stop_ssi0() (REG_CPM_CLKGR0 |= CLKGR0_SSI0)
3891#define __cpm_stop_msc0() (REG_CPM_CLKGR0 |= CLKGR0_MSC0)
3892#define __cpm_stop_otg() (REG_CPM_CLKGR0 |= CLKGR0_OTG)
3893#define __cpm_stop_bch() (REG_CPM_CLKGR0 |= CLKGR0_BCH)
3894#define __cpm_stop_nemc() (REG_CPM_CLKGR0 |= CLKGR0_NEMC)
3895#define __cpm_stop_gpu() (REG_CPM_CLKGR1 |= CLKGR1_GPU)
3896#define __cpm_stop_pcm() (REG_CPM_CLKGR1 |= CLKGR1_PCM)
3897#define __cpm_stop_ahb1() (REG_CPM_CLKGR1 |= CLKGR1_AHB1)
3898#define __cpm_stop_cabac() (REG_CPM_CLKGR1 |= CLKGR1_CABAC)
3899#define __cpm_stop_sram() (REG_CPM_CLKGR1 |= CLKGR1_SRAM)
3900#define __cpm_stop_dct() (REG_CPM_CLKGR1 |= CLKGR1_DCT)
3901#define __cpm_stop_me() (REG_CPM_CLKGR1 |= CLKGR1_ME)
3902#define __cpm_stop_dblk() (REG_CPM_CLKGR1 |= CLKGR1_DBLK)
3903#define __cpm_stop_mc() (REG_CPM_CLKGR1 |= CLKGR1_MC)
3904#define __cpm_stop_bdma() (REG_CPM_CLKGR1 |= CLKGR1_BDMA)
3905
3906#define __cpm_start_all() \
3907 do {\
3908 REG_CPM_CLKGR0 = 0x0;\
3909 REG_CPM_CLKGR1 = 0x0;\
3910 } while(0)
3911#define __cpm_start_emc() (REG_CPM_CLKGR0 &= ~CLKGR0_EMC)
3912#define __cpm_start_ddr() (REG_CPM_CLKGR0 &= ~CLKGR0_DDR)
3913#define __cpm_start_ipu() (REG_CPM_CLKGR0 &= ~CLKGR0_IPU)
3914#define __cpm_start_lcd() (REG_CPM_CLKGR0 &= ~CLKGR0_LCD)
3915#define __cpm_start_tve() (REG_CPM_CLKGR0 &= ~CLKGR0_TVE)
3916#define __cpm_start_Cim() (REG_CPM_CLKGR0 &= ~CLKGR0_CIM)
3917#define __cpm_start_mdma() (REG_CPM_CLKGR0 &= ~CLKGR0_MDMA)
3918#define __cpm_start_uhc() (REG_CPM_CLKGR0 &= ~CLKGR0_UHC)
3919#define __cpm_start_mac() (REG_CPM_CLKGR0 &= ~CLKGR0_MAC)
3920#define __cpm_start_gps() (REG_CPM_CLKGR0 &= ~CLKGR0_GPS)
3921#define __cpm_start_dmac() (REG_CPM_CLKGR0 &= ~CLKGR0_DMAC)
3922#define __cpm_start_ssi2() (REG_CPM_CLKGR0 &= ~CLKGR0_SSI2)
3923#define __cpm_start_ssi1() (REG_CPM_CLKGR0 &= ~CLKGR0_SSI1)
3924#define __cpm_start_uart3() (REG_CPM_CLKGR0 &= ~CLKGR0_UART3)
3925#define __cpm_start_uart2() (REG_CPM_CLKGR0 &= ~CLKGR0_UART2)
3926#define __cpm_start_uart1() (REG_CPM_CLKGR0 &= ~CLKGR0_UART1)
3927#define __cpm_start_uart0() (REG_CPM_CLKGR0 &= ~CLKGR0_UART0)
3928#define __cpm_start_sadc() (REG_CPM_CLKGR0 &= ~CLKGR0_SADC)
3929#define __cpm_start_kbc() (REG_CPM_CLKGR0 &= ~CLKGR0_KBC)
3930#define __cpm_start_msc2() (REG_CPM_CLKGR0 &= ~CLKGR0_MSC2)
3931#define __cpm_start_msc1() (REG_CPM_CLKGR0 &= ~CLKGR0_MSC1)
3932#define __cpm_start_owi() (REG_CPM_CLKGR0 &= ~CLKGR0_OWI)
3933#define __cpm_start_tssi() (REG_CPM_CLKGR0 &= ~CLKGR0_TSSI)
3934#define __cpm_start_aic() (REG_CPM_CLKGR0 &= ~CLKGR0_AIC)
3935#define __cpm_start_scc() (REG_CPM_CLKGR0 &= ~CLKGR0_SCC)
3936#define __cpm_start_i2c1() (REG_CPM_CLKGR0 &= ~CLKGR0_I2C1)
3937#define __cpm_start_i2c0() (REG_CPM_CLKGR0 &= ~CLKGR0_I2C0)
3938#define __cpm_start_ssi0() (REG_CPM_CLKGR0 &= ~CLKGR0_SSI0)
3939#define __cpm_start_msc0() (REG_CPM_CLKGR0 &= ~CLKGR0_MSC0)
3940#define __cpm_start_otg() (REG_CPM_CLKGR0 &= ~CLKGR0_OTG)
3941#define __cpm_start_bch() (REG_CPM_CLKGR0 &= ~CLKGR0_BCH)
3942#define __cpm_start_nemc() (REG_CPM_CLKGR0 &= ~CLKGR0_NEMC)
3943#define __cpm_start_gpu() (REG_CPM_CLKGR1 &= ~CLKGR1_GPU)
3944#define __cpm_start_pcm() (REG_CPM_CLKGR1 &= ~CLKGR1_PCM)
3945#define __cpm_start_ahb1() (REG_CPM_CLKGR1 &= ~CLKGR1_AHB1)
3946#define __cpm_start_cabac() (REG_CPM_CLKGR1 &= ~CLKGR1_CABAC)
3947#define __cpm_start_sram() (REG_CPM_CLKGR1 &= ~CLKGR1_SRAM)
3948#define __cpm_start_dct() (REG_CPM_CLKGR1 &= ~CLKGR1_DCT)
3949#define __cpm_start_me() (REG_CPM_CLKGR1 &= ~CLKGR1_ME)
3950#define __cpm_start_dblk() (REG_CPM_CLKGR1 &= ~CLKGR1_DBLK)
3951#define __cpm_start_mc() (REG_CPM_CLKGR1 &= ~CLKGR1_MC)
3952#define __cpm_start_bdma() (REG_CPM_CLKGR1 &= ~CLKGR1_BDMA)
3953
3954#define __cpm_get_o1st() \
3955 ((REG_CPM_OPCR & OPCR_O1ST_MASK) >> OPCR_O1ST_LSB)
3956#define __cpm_set_o1st(v) \
3957 (REG_CPM_OPCR = (REG_CPM_OPCR & ~OPCR_O1ST_MASK) | ((v) << (OPCR_O1ST_LSB)))
3958#define __cpm_suspend_otgphy() (REG_CPM_OPCR &= ~OPCR_OTGPHY_ENABLE)
3959#define __cpm_resume_otgphy() (REG_CPM_OPCR |= OPCR_OTGPHY_ENABLE)
3960#define __cpm_enable_osc_in_sleep() (REG_CPM_OPCR |= OPCR_OSC_ENABLE)
3961#define __cpm_select_rtcclk_rtc() (REG_CPM_OPCR |= OPCR_ERCS)
3962#define __cpm_select_rtcclk_exclk() (REG_CPM_OPCR &= ~OPCR_ERCS)
3963
3964#ifdef CFG_EXTAL
3965#define JZ_EXTAL CFG_EXTAL
3966#else
3967#define JZ_EXTAL 12000000
3968#endif
3969#define JZ_EXTAL2 32768 /* RTC clock */
3970
3971/* PLL output frequency */
3972static __inline__ unsigned int __cpm_get_pllout(void)
3973{
3974 unsigned long m, n, no, pllout;
3975 unsigned long cppcr = REG_CPM_CPPCR0;
3976 unsigned long od[4] = {1, 2, 4, 8};
3977 if ((cppcr & CPPCR0_PLLEN) && (!(cppcr & CPPCR0_PLLBP))) {
3978 m = __cpm_get_pllm() * 2;
3979 n = __cpm_get_plln();
3980 no = od[__cpm_get_pllod()];
3981 pllout = ((JZ_EXTAL) * m / (n * no));
3982 } else
3983 pllout = JZ_EXTAL;
3984 return pllout;
3985}
3986
3987/* PLL output frequency */
3988static __inline__ unsigned int __cpm_get_pll1out(void)
3989{
3990 unsigned long m, n, no, pllout;
3991 unsigned long cppcr1 = REG_CPM_CPPCR1;
3992 unsigned long od[4] = {1, 2, 4, 8};
3993 if (cppcr1 & CPPCR1_PLL1EN)
3994 {
3995 m = __cpm_get_pll1m() * 2;
3996 n = __cpm_get_pll1n();
3997 no = od[__cpm_get_pll1od()];
3998 if (cppcr1 & CPPCR1_P1SCS)
3999 pllout = ((__cpm_get_pllout()) * m / (n * no));
4000 else
4001 pllout = ((JZ_EXTAL) * m / (n * no));
4002
4003 } else
4004 pllout = JZ_EXTAL;
4005 return pllout;
4006}
4007
4008/* PLL output frequency for MSC/I2S/LCD/USB */
4009static __inline__ unsigned int __cpm_get_pllout2(void)
4010{
4011 if (REG_CPM_CPCCR & CPCCR_PCS)
4012 return __cpm_get_pllout();
4013 else
4014 return __cpm_get_pllout()/2;
4015}
4016
4017/* CPU core clock */
4018static __inline__ unsigned int __cpm_get_cclk(void)
4019{
4020 int div[] = {1, 2, 3, 4, 6, 8};
4021
4022 return __cpm_get_pllout() / div[__cpm_get_cdiv()];
4023}
4024
4025/* AHB system bus clock */
4026static __inline__ unsigned int __cpm_get_hclk(void)
4027{
4028 int div[] = {1, 2, 3, 4, 6, 8};
4029
4030 return __cpm_get_pllout() / div[__cpm_get_hdiv()];
4031}
4032
4033/* Memory bus clock */
4034static __inline__ unsigned int __cpm_get_mclk(void)
4035{
4036 int div[] = {1, 2, 3, 4, 6, 8};
4037
4038 return __cpm_get_pllout() / div[__cpm_get_mdiv()];
4039}
4040
4041/* APB peripheral bus clock */
4042static __inline__ unsigned int __cpm_get_pclk(void)
4043{
4044 int div[] = {1, 2, 3, 4, 6, 8};
4045
4046 return __cpm_get_pllout() / div[__cpm_get_pdiv()];
4047}
4048
4049/* AHB1 module clock */
4050static __inline__ unsigned int __cpm_get_h2clk(void)
4051{
4052 int div[] = {1, 2, 3, 4, 6, 8};
4053
4054 return __cpm_get_pllout() / div[__cpm_get_h2div()];
4055}
4056
4057/* LCD pixel clock */
4058static __inline__ unsigned int __cpm_get_pixclk(void)
4059{
4060 return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
4061}
4062
4063/* I2S clock */
4064static __inline__ unsigned int __cpm_get_i2sclk(void)
4065{
4066 if (REG_CPM_I2SCDR & I2SCDR_I2CS) {
4067 return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
4068 }
4069 else {
4070 return JZ_EXTAL;
4071 }
4072}
4073
4074/* USB clock */
4075/*
4076static __inline__ unsigned int __cpm_get_usbclk(void)
4077{
4078 if (REG_CPM_CPCCR & CPCCR_UCS) {
4079 return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
4080 }
4081 else {
4082 return JZ_EXTAL;
4083 }
4084}
4085*/
4086/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
4087static __inline__ unsigned int __cpm_get_extalclk(void)
4088{
4089 return JZ_EXTAL;
4090}
4091
4092/* RTC clock for CPM,INTC,RTC,TCU,WDT */
4093static __inline__ unsigned int __cpm_get_rtcclk(void)
4094{
4095 return JZ_EXTAL2;
4096}
4097
4098/*
4099 * Output 24MHz for SD and 16MHz for MMC.
4100 */
4101static inline void __cpm_select_msc_clk(int sd)
4102{
4103 unsigned int pllout2 = __cpm_get_pllout2();
4104 unsigned int div = 0;
4105
4106 if (sd) {
4107 div = pllout2 / 24000000;
4108 }
4109 else {
4110 div = pllout2 / 16000000;
4111 }
4112
4113 REG_CPM_MSCCDR = (div - 1)|(1<<31);
4114 REG_CPM_CPCCR |= CPCCR_CE;
4115}
4116
4117#endif /* __MIPS_ASSEMBLER */
4118
4119#define DDRC_BASE 0xB3020000
4120
4121/*************************************************************************
4122 * DDRC (DDR Controller)
4123 *************************************************************************/
4124#define DDRC_ST (DDRC_BASE + 0x0) /* DDR Status Register */
4125#define DDRC_CFG (DDRC_BASE + 0x4) /* DDR Configure Register */
4126#define DDRC_CTRL (DDRC_BASE + 0x8) /* DDR Control Register */
4127#define DDRC_LMR (DDRC_BASE + 0xc) /* DDR Load-Mode-Register */
4128#define DDRC_TIMING1 (DDRC_BASE + 0x10) /* DDR Timing Config Register 1 */
4129#define DDRC_TIMING2 (DDRC_BASE + 0x14) /* DDR Timing Config Register 2 */
4130#define DDRC_REFCNT (DDRC_BASE + 0x18) /* DDR Auto-Refresh Counter */
4131#define DDRC_DQS (DDRC_BASE + 0x1c) /* DDR DQS Delay Control Register */
4132#define DDRC_DQS_ADJ (DDRC_BASE + 0x20) /* DDR DQS Delay Adjust Register */
4133#define DDRC_MMAP0 (DDRC_BASE + 0x24) /* DDR Memory Map Config Register */
4134#define DDRC_MMAP1 (DDRC_BASE + 0x28) /* DDR Memory Map Config Register */
4135#define DDRC_DDELAYCTRL1 (DDRC_BASE + 0x2c)
4136#define DDRC_DDELAYCTRL2 (DDRC_BASE + 0x30)
4137#define DDRC_DSTRB (DDRC_BASE + 0x34)
4138#define DDRC_PMEMBS0 (DDRC_BASE + 0x50)
4139#define DDRC_PMEMBS1 (DDRC_BASE + 0x54)
4140#define DDRC_PMEMOSEL (DDRC_BASE + 0x58)
4141#define DDRC_PMEMOEN (DDRC_BASE + 0x5c)
4142
4143/* DDRC Register */
4144#define REG_DDRC_ST REG32(DDRC_ST)
4145#define REG_DDRC_CFG REG32(DDRC_CFG)
4146#define REG_DDRC_CTRL REG32(DDRC_CTRL)
4147#define REG_DDRC_LMR REG32(DDRC_LMR)
4148#define REG_DDRC_TIMING1 REG32(DDRC_TIMING1)
4149#define REG_DDRC_TIMING2 REG32(DDRC_TIMING2)
4150#define REG_DDRC_REFCNT REG32(DDRC_REFCNT)
4151#define REG_DDRC_DQS REG32(DDRC_DQS)
4152#define REG_DDRC_DQS_ADJ REG32(DDRC_DQS_ADJ)
4153#define REG_DDRC_MMAP0 REG32(DDRC_MMAP0)
4154#define REG_DDRC_MMAP1 REG32(DDRC_MMAP1)
4155#define REG_DDRC_DDELAYCTRL1 REG32(DDRC_DDELAYCTRL1)
4156#define REG_DDRC_DDELAYCTRL2 REG32(DDRC_DDELAYCTRL2)
4157#define REG_DDRC_DSTRB REG32(DDRC_DSTRB)
4158#define REG_DDRC_PMEMBS0 REG32(DDRC_PMEMBS0)
4159#define REG_DDRC_PMEMBS1 REG32(DDRC_PMEMBS1)
4160#define REG_DDRC_PMEMOSEL REG32(DDRC_PMEMOSEL)
4161#define REG_DDRC_PMEMOEN REG32(DDRC_PMEMOEN)
4162
4163/* DDRC Status Register */
4164#define DDRC_ST_ENDIAN (1 << 7) /* 0 Little data endian
4165 1 Big data endian */
4166#define DDRC_ST_MISS (1 << 6)
4167
4168#define DDRC_ST_DPDN (1 << 5) /* 0 DDR memory is NOT in deep-power-down state
4169 1 DDR memory is in deep-power-down state */
4170#define DDRC_ST_PDN (1 << 4) /* 0 DDR memory is NOT in power-down state
4171 1 DDR memory is in power-down state */
4172#define DDRC_ST_AREF (1 << 3) /* 0 DDR memory is NOT in auto-refresh state
4173 1 DDR memory is in auto-refresh state */
4174#define DDRC_ST_SREF (1 << 2) /* 0 DDR memory is NOT in self-refresh state
4175 1 DDR memory is in self-refresh state */
4176#define DDRC_ST_CKE1 (1 << 1) /* 0 CKE1 Pin is low
4177 1 CKE1 Pin is high */
4178#define DDRC_ST_CKE0 (1 << 0) /* 0 CKE0 Pin is low
4179 1 CKE0 Pin is high */
4180
4181/* DDRC Configure Register */
4182#define DDRC_CFG_RDPRI (1 << 29)
4183#define DDRC_CFG_ROW1_BIT 27 /* Row Address width. */
4184#define DDRC_CFG_COL1_BIT 25 /* Row Address width. */
4185#define DDRC_CFG_BA1 (1 << 24)
4186#define DDRC_CFG_IMBA (1 << 23)
4187#define DDRC_CFG_DQSMD (1 << 22)
4188#define DDRC_CFG_BTRUN (1 << 21)
4189
4190#define DDRC_CFG_MISPE (1 << 15)
4191
4192#define DDRC_CFG_TYPE_BIT 12
4193#define DDRC_CFG_TYPE_MASK (0x7 << DDRC_CFG_TYPE_BIT)
4194#define DDRC_CFG_TYPE_DDR1 (2 << DDRC_CFG_TYPE_BIT)
4195#define DDRC_CFG_TYPE_MDDR (3 << DDRC_CFG_TYPE_BIT)
4196#define DDRC_CFG_TYPE_DDR2 (4 << DDRC_CFG_TYPE_BIT)
4197
4198#define DDRC_CFG_ROW_BIT 10 /* Row Address width. */
4199#define DDRC_CFG_ROW_MASK (0x3 << DDRC_CFG_ROW_BIT)
4200#define DDRC_CFG_ROW_12 (0 << DDRC_CFG_ROW_BIT) /* 12-bit row address is used */
4201#define DDRC_CFG_ROW_13 (1 << DDRC_CFG_ROW_BIT) /* 13-bit row address is used */
4202#define DDRC_CFG_ROW_14 (2 << DDRC_CFG_ROW_BIT) /* 14-bit row address is used */
4203
4204#define DDRC_CFG_COL_BIT 8 /* Column Address width.
4205 Specify the Column address width of external DDR. */
4206#define DDRC_CFG_COL_MASK (0x3 << DDRC_CFG_COL_BIT)
4207#define DDRC_CFG_COL_8 (0 << DDRC_CFG_COL_BIT) /* 8-bit Column address is used */
4208#define DDRC_CFG_COL_9 (1 << DDRC_CFG_COL_BIT) /* 9-bit Column address is used */
4209#define DDRC_CFG_COL_10 (2 << DDRC_CFG_COL_BIT) /* 10-bit Column address is used */
4210#define DDRC_CFG_COL_11 (3 << DDRC_CFG_COL_BIT) /* 11-bit Column address is used */
4211
4212#define DDRC_CFG_CS1EN (1 << 7) /* 0 DDR Pin CS1 un-used
4213 1 There're DDR memory connected to CS1 */
4214#define DDRC_CFG_CS0EN (1 << 6) /* 0 DDR Pin CS0 un-used
4215 1 There're DDR memory connected to CS0 */
4216
4217#define DDRC_CFG_CL_BIT 2 /* CAS Latency */
4218#define DDRC_CFG_CL_MASK (0xf << DDRC_CFG_CL_BIT)
4219#define DDRC_CFG_CL_3 (0x0a << DDRC_CFG_CL_BIT) /* CL = 3 tCK */
4220#define DDRC_CFG_CL_4 (0x0b << DDRC_CFG_CL_BIT) /* CL = 4 tCK */
4221#define DDRC_CFG_CL_5 (0x0c << DDRC_CFG_CL_BIT) /* CL = 5 tCK */
4222#define DDRC_CFG_CL_6 (0x0d << DDRC_CFG_CL_BIT) /* CL = 6 tCK */
4223#define DDRC_CFG_CL_7 (0x0e << DDRC_CFG_CL_BIT) /* CL = 7 tCK */
4224
4225#define DDRC_CFG_BA (1 << 1) /* 0 4 bank device, Pin ba[1:0] valid, ba[2] un-used
4226 1 8 bank device, Pin ba[2:0] valid*/
4227#define DDRC_CFG_DW (1 << 0) /*0 External memory data width is 16-bit
4228 1 External memory data width is 32-bit */
4229
4230/* DDRC Control Register */
4231#define DDRC_CTRL_ACTPD (1 << 15) /* 0 Precharge all banks before entering power-down
4232 1 Do not precharge banks before entering power-down */
4233#define DDRC_CTRL_PDT_BIT 12 /* Power-Down Timer */
4234#define DDRC_CTRL_PDT_MASK (0x7 << DDRC_CTRL_PDT_BIT)
4235#define DDRC_CTRL_PDT_DIS (0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */
4236#define DDRC_CTRL_PDT_8 (1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */
4237#define DDRC_CTRL_PDT_16 (2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */
4238#define DDRC_CTRL_PDT_32 (3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */
4239#define DDRC_CTRL_PDT_64 (4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */
4240#define DDRC_CTRL_PDT_128 (5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */
4241
4242#define DDRC_CTRL_PRET_BIT 8 /* Precharge Timer */
4243#define DDRC_CTRL_PRET_MASK (0x7 << DDRC_CTRL_PRET_BIT) /* */
4244 #define DDRC_CTRL_PRET_DIS (0 << DDRC_CTRL_PRET_BIT) /* PRET function Disabled */
4245 #define DDRC_CTRL_PRET_8 (1 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 8 tCK idle */
4246 #define DDRC_CTRL_PRET_16 (2 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 16 tCK idle */
4247 #define DDRC_CTRL_PRET_32 (3 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 32 tCK idle */
4248 #define DDRC_CTRL_PRET_64 (4 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 64 tCK idle */
4249 #define DDRC_CTRL_PRET_128 (5 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 128 tCK idle */
4250
4251#define DDRC_CTRL_SR (1 << 5) /* 1 Drive external DDR device entering self-refresh mode
4252 0 Drive external DDR device exiting self-refresh mode */
4253#define DDRC_CTRL_UNALIGN (1 << 4) /* 0 Disable unaligned transfer on AXI BUS
4254 1 Enable unaligned transfer on AXI BUS */
4255#define DDRC_CTRL_ALH (1 << 3) /* Advanced Latency Hiding:
4256 0 Disable ALH
4257 1 Enable ALH */
4258#define DDRC_CTRL_CKE (1 << 1) /* 0 Not set CKE Pin High
4259 1 Set CKE Pin HIGH */
4260#define DDRC_CTRL_RESET (1 << 0) /* 0 End resetting ddrc_controller
4261 1 Resetting ddrc_controller */
4262
4263/* DDRC Load-Mode-Register */
4264#define DDRC_LMR_DDR_ADDR_BIT 16 /* When performing a DDR command, DDRC_ADDR[13:0]
4265 corresponding to external DDR address Pin A[13:0] */
4266#define DDRC_LMR_DDR_ADDR_MASK (0x3fff << DDRC_LMR_DDR_ADDR_BIT)
4267
4268#define DDRC_LMR_BA_BIT 8 /* When performing a DDR command, BA[2:0]
4269 corresponding to external DDR address Pin BA[2:0]. */
4270#define DDRC_LMR_BA_MASK (0x7 << DDRC_LMR_BA_BIT)
4271/* For DDR2 */
4272#define DDRC_LMR_BA_MRS (0 << DDRC_LMR_BA_BIT) /* Mode Register set */
4273#define DDRC_LMR_BA_EMRS1 (1 << DDRC_LMR_BA_BIT) /* Extended Mode Register1 set */
4274#define DDRC_LMR_BA_EMRS2 (2 << DDRC_LMR_BA_BIT) /* Extended Mode Register2 set */
4275#define DDRC_LMR_BA_EMRS3 (3 << DDRC_LMR_BA_BIT) /* Extended Mode Register3 set */
4276/* For mobile DDR */
4277#define DDRC_LMR_BA_M_MRS (0 << DDRC_LMR_BA_BIT) /* Mode Register set */
4278#define DDRC_LMR_BA_M_EMRS (2 << DDRC_LMR_BA_BIT) /* Extended Mode Register set */
4279#define DDRC_LMR_BA_M_SR (1 << DDRC_LMR_BA_BIT) /* Status Register set */
4280
4281#define DDRC_LMR_CMD_BIT 4
4282#define DDRC_LMR_CMD_MASK (0x3 << DDRC_LMR_CMD_BIT)
4283#define DDRC_LMR_CMD_PREC (0 << DDRC_LMR_CMD_BIT)/* Precharge one bank/All banks */
4284#define DDRC_LMR_CMD_AUREF (1 << DDRC_LMR_CMD_BIT)/* Auto-Refresh */
4285#define DDRC_LMR_CMD_LMR (2 << DDRC_LMR_CMD_BIT)/* Load Mode Register */
4286
4287#define DDRC_LMR_START (1 << 0) /* 0 No command is performed
4288 1 On the posedge of START, perform a command
4289 defined by CMD field */
4290/* DDRC Mode Register Set */
4291#define DDR_MRS_PD_BIT (1 << 10) /* Active power down exit time */
4292#define DDR_MRS_PD_MASK (1 << DDR_MRS_PD_BIT)
4293#define DDR_MRS_PD_FAST_EXIT (0 << 10)
4294#define DDR_MRS_PD_SLOW_EXIT (1 << 10)
4295#define DDR_MRS_WR_BIT (1 << 9) /* Write Recovery for autoprecharge */
4296#define DDR_MRS_WR_MASK (7 << DDR_MRS_WR_BIT)
4297#define DDR_MRS_DLL_RST (1 << 8) /* DLL Reset */
4298#define DDR_MRS_TM_BIT 7 /* Operating Mode */
4299#define DDR_MRS_TM_MASK (1 << DDR_MRS_OM_BIT)
4300#define DDR_MRS_TM_NORMAL (0 << DDR_MRS_OM_BIT)
4301#define DDR_MRS_TM_TEST (1 << DDR_MRS_OM_BIT)
4302#define DDR_MRS_CAS_BIT 4 /* CAS Latency */
4303#define DDR_MRS_CAS_MASK (7 << DDR_MRS_CAS_BIT)
4304#define DDR_MRS_BT_BIT 3 /* Burst Type */
4305#define DDR_MRS_BT_MASK (1 << DDR_MRS_BT_BIT)
4306#define DDR_MRS_BT_SEQ (0 << DDR_MRS_BT_BIT) /* Sequential */
4307#define DDR_MRS_BT_INT (1 << DDR_MRS_BT_BIT) /* Interleave */
4308#define DDR_MRS_BL_BIT 0 /* Burst Length */
4309#define DDR_MRS_BL_MASK (7 << DDR_MRS_BL_BIT)
4310#define DDR_MRS_BL_4 (2 << DDR_MRS_BL_BIT)
4311#define DDR_MRS_BL_8 (3 << DDR_MRS_BL_BIT)
4312
4313/* DDRC Extended Mode Register1 Set */
4314#define DDR_EMRS1_QOFF (1<<12) /* 0 Output buffer enabled
4315 1 Output buffer disabled */
4316#define DDR_EMRS1_RDQS_EN (1<<11) /* 0 Disable
4317 1 Enable */
4318#define DDR_EMRS1_DQS_DIS (1<<10) /* 0 Enable
4319 1 Disable */
4320#define DDR_EMRS1_OCD_BIT 7 /* Additive Latency 0 -> 6 */
4321#define DDR_EMRS1_OCD_MASK (0x7 << DDR_EMRS1_OCD_BIT)
4322#define DDR_EMRS1_OCD_EXIT (0 << DDR_EMRS1_OCD_BIT)
4323#define DDR_EMRS1_OCD_D0 (1 << DDR_EMRS1_OCD_BIT)
4324#define DDR_EMRS1_OCD_D1 (2 << DDR_EMRS1_OCD_BIT)
4325#define DDR_EMRS1_OCD_ADJ (4 << DDR_EMRS1_OCD_BIT)
4326#define DDR_EMRS1_OCD_DFLT (7 << DDR_EMRS1_OCD_BIT)
4327#define DDR_EMRS1_AL_BIT 3 /* Additive Latency 0 -> 6 */
4328#define DDR_EMRS1_AL_MASK (7 << DDR_EMRS1_AL_BIT)
4329#define DDR_EMRS1_RTT_BIT 2 /* */
4330#define DDR_EMRS1_RTT_MASK (0x11 << DDR_EMRS1_DIC_BIT) /* Bit 6, Bit 2 */
4331#define DDR_EMRS1_DIC_BIT 1 /* Output Driver Impedence Control */
4332#define DDR_EMRS1_DIC_MASK (1 << DDR_EMRS1_DIC_BIT) /* 100% */
4333#define DDR_EMRS1_DIC_NORMAL (0 << DDR_EMRS1_DIC_BIT) /* 60% */
4334#define DDR_EMRS1_DIC_HALF (1 << DDR_EMRS1_DIC_BIT)
4335#define DDR_EMRS1_DLL_BIT 0 /* DLL Enable */
4336#define DDR_EMRS1_DLL_MASK (1 << DDR_EMRS1_DLL_BIT)
4337#define DDR_EMRS1_DLL_EN (0 << DDR_EMRS1_DLL_BIT)
4338#define DDR_EMRS1_DLL_DIS (1 << DDR_EMRS1_DLL_BIT)
4339
4340/* Mobile SDRAM Extended Mode Register */
4341#define DDR_EMRS_DS_BIT 5 /* Driver strength */
4342#define DDR_EMRS_DS_MASK (7 << DDR_EMRS_DS_BIT)
4343#define DDR_EMRS_DS_FULL (0 << DDR_EMRS_DS_BIT) /*Full*/
4344#define DDR_EMRS_DS_HALF (1 << DDR_EMRS_DS_BIT) /*1/2 Strength*/
4345#define DDR_EMRS_DS_QUTR (2 << DDR_EMRS_DS_BIT) /*1/4 Strength*/
4346#define DDR_EMRS_DS_OCTANT (3 << DDR_EMRS_DS_BIT) /*1/8 Strength*/
4347#define DDR_EMRS_DS_QUTR3 (4 << DDR_EMRS_DS_BIT) /*3/4 Strength*/
4348
4349#define DDR_EMRS_PRSR_BIT 0 /* Partial Array Self Refresh */
4350#define DDR_EMRS_PRSR_MASK (7 << DDR_EMRS_PRSR_BIT)
4351#define DDR_EMRS_PRSR_ALL (0 << DDR_EMRS_PRSR_BIT) /*All Banks*/
4352#define DDR_EMRS_PRSR_HALF_TL (1 << DDR_EMRS_PRSR_BIT) /*Half of Total Bank*/
4353#define DDR_EMRS_PRSR_QUTR_TL (2 << DDR_EMRS_PRSR_BIT) /*Quarter of Total Bank*/
4354#define DDR_EMRS_PRSR_HALF_B0 (5 << DDR_EMRS_PRSR_BIT) /*Half of Bank0*/
4355#define DDR_EMRS_PRSR_QUTR_B0 (6 << DDR_EMRS_PRSR_BIT) /*Quarter of Bank0*/
4356
4357/* DDRC Timing Config Register 1 */
4358#define DDRC_TIMING1_TRAS_BIT 28 /* ACTIVE to PRECHARGE command period (2 * tRAS + 1) */
4359#define DDRC_TIMING1_TRAS_MASK (0xf << DDRC_TIMING1_TRAS_BIT)
4360
4361#define DDRC_TIMING1_TRTP_BIT 24 /* READ to PRECHARGE command period. */
4362#define DDRC_TIMING1_TRTP_MASK (0x3 << DDRC_TIMING1_TRTP_BIT)
4363
4364#define DDRC_TIMING1_TRP_BIT 20 /* PRECHARGE command period. */
4365#define DDRC_TIMING1_TRP_MASK (0x7 << DDRC_TIMING1_TRP_BIT)
4366
4367#define DDRC_TIMING1_TRCD_BIT 16 /* ACTIVE to READ or WRITE command period. */
4368#define DDRC_TIMING1_TRCD_MASK (0x7 << DDRC_TIMING1_TRCD_BIT)
4369
4370#define DDRC_TIMING1_TRC_BIT 12 /* ACTIVE to ACTIVE command period. */
4371#define DDRC_TIMING1_TRC_MASK (0xf << DDRC_TIMING1_TRC_BIT)
4372
4373#define DDRC_TIMING1_TRRD_BIT 8 /* ACTIVE bank A to ACTIVE bank B command period. */
4374#define DDRC_TIMING1_TRRD_MASK (0x3 << DDRC_TIMING1_TRRD_BIT)
4375#define DDRC_TIMING1_TRRD_DISABLE (0 << DDRC_TIMING1_TRRD_BIT)
4376#define DDRC_TIMING1_TRRD_2 (1 << DDRC_TIMING1_TRRD_BIT)
4377#define DDRC_TIMING1_TRRD_3 (2 << DDRC_TIMING1_TRRD_BIT)
4378#define DDRC_TIMING1_TRRD_4 (3 << DDRC_TIMING1_TRRD_BIT)
4379
4380#define DDRC_TIMING1_TWR_BIT 4 /* WRITE Recovery Time defined by register MR of DDR2 memory */
4381#define DDRC_TIMING1_TWR_MASK (0x7 << DDRC_TIMING1_TWR_BIT)
4382#define DDRC_TIMING1_TWR_1 (0 << DDRC_TIMING1_TWR_BIT)
4383#define DDRC_TIMING1_TWR_2 (1 << DDRC_TIMING1_TWR_BIT)
4384#define DDRC_TIMING1_TWR_3 (2 << DDRC_TIMING1_TWR_BIT)
4385#define DDRC_TIMING1_TWR_4 (3 << DDRC_TIMING1_TWR_BIT)
4386#define DDRC_TIMING1_TWR_5 (4 << DDRC_TIMING1_TWR_BIT)
4387#define DDRC_TIMING1_TWR_6 (5 << DDRC_TIMING1_TWR_BIT)
4388
4389#define DDRC_TIMING1_TWTR_BIT 0 /* WRITE to READ command delay. */
4390#define DDRC_TIMING1_TWTR_MASK (0x3 << DDRC_TIMING1_TWTR_BIT)
4391#define DDRC_TIMING1_TWTR_1 (0 << DDRC_TIMING1_TWTR_BIT)
4392#define DDRC_TIMING1_TWTR_2 (1 << DDRC_TIMING1_TWTR_BIT)
4393#define DDRC_TIMING1_TWTR_3 (2 << DDRC_TIMING1_TWTR_BIT)
4394#define DDRC_TIMING1_TWTR_4 (3 << DDRC_TIMING1_TWTR_BIT)
4395
4396/* DDRC Timing Config Register 2 */
4397#define DDRC_TIMING2_TRFC_BIT 24 /* AUTO-REFRESH command period. */
4398#define DDRC_TIMING2_TRFC_MASK (0xf << DDRC_TIMING2_TRFC_BIT)
4399#define DDRC_TIMING2_RWCOV_BIT 19 /* Equal to Tsel of MDELAY. */
4400#define DDRC_TIMING2_RWCOV_MASK (0x3 << DDRC_TIMING2_RWCOV_BIT)
4401#define DDRC_TIMING2_TCKE_BIT 16
4402#define DDRC_TIMING2_TCKE_MASK (0x7 << DDRC_TIMING2_TCKE_BIT)
4403#define DDRC_TIMING2_TMINSR_BIT 8 /* Minimum Self-Refresh / Deep-Power-Down time */
4404#define DDRC_TIMING2_TMINSR_MASK (0xf << DDRC_TIMING2_TMINSR_BIT)
4405#define DDRC_TIMING2_TXP_BIT 4 /* EXIT-POWER-DOWN to next valid command period. */
4406#define DDRC_TIMING2_TXP_MASK (0x7 << DDRC_TIMING2_TXP_BIT)
4407#define DDRC_TIMING2_TMRD_BIT 0 /* Load-Mode-Register to next valid command period. */
4408#define DDRC_TIMING2_TMRD_MASK (0x3 << DDRC_TIMING2_TMRD_BIT)
4409
4410/* DDRC Auto-Refresh Counter */
4411#define DDRC_REFCNT_CON_BIT 16 /* Constant value used to compare with CNT value. */
4412#define DDRC_REFCNT_CON_MASK (0xff << DDRC_REFCNT_CON_BIT)
4413#define DDRC_REFCNT_CNT_BIT 8 /* 8-bit counter */
4414#define DDRC_REFCNT_CNT_MASK (0xff << DDRC_REFCNT_CNT_BIT)
4415#define DDRC_REFCNT_CLKDIV_BIT 1 /* Clock Divider for auto-refresh counter. */
4416#define DDRC_REFCNT_CLKDIV_MASK (0x7 << DDRC_REFCNT_CLKDIV_BIT)
4417#define DDRC_REFCNT_REF_EN (1 << 0) /* Enable Refresh Counter */
4418
4419/* DDRC DQS Delay Control Register */
4420#define DDRC_DQS_ERROR (1 << 29) /* ahb_clk Delay Detect ERROR, read-only. */
4421#define DDRC_DQS_READY (1 << 28) /* ahb_clk Delay Detect READY, read-only. */
4422#define DDRC_DQS_SRDET (1 << 25)
4423#define DDRC_DQS_DET (1 << 24) /* Start delay detecting. */
4424#define DDRC_DQS_AUTO (1 << 23) /* Hardware auto-detect & set delay line */
4425#define DDRC_DQS_CLKD_BIT 16 /* CLKD is reference value for setting WDQS and RDQS.*/
4426#define DDRC_DQS_CLKD_MASK (0x3f << DDRC_DQS_CLKD_BIT)
4427#define DDRC_DQS_WDQS_BIT 8 /* Set delay element number to write DQS delay-line. */
4428#define DDRC_DQS_WDQS_MASK (0x3f << DDRC_DQS_WDQS_BIT)
4429#define DDRC_DQS_RDQS_BIT 0 /* Set delay element number to read DQS delay-line. */
4430#define DDRC_DQS_RDQS_MASK (0x3f << DDRC_DQS_RDQS_BIT)
4431
4432/* DDRC DQS Delay Adjust Register */
4433#define DDRC_DQS_ADJDQSCON_BIT 16
4434#define DDRC_DQS_ADJDQSCON_MASK (0xffff << DDRC_DQS_ADJDQSCON_BIT)
4435#define DDRC_DQS_ADJWSIGN (1 << 13)
4436#define DDRC_DQS_ADJWDQS_BIT 8 /* The adjust value for WRITE DQS delay */
4437#define DDRC_DQS_ADJWDQS_MASK (0x1f << DDRC_DQS_ADJWDQS_BIT)
4438#define DDRC_DQS_ADJRSIGN (1 << 5)
4439#define DDRC_DQS_ADJRDQS_BIT 0 /* The adjust value for READ DQS delay */
4440#define DDRC_DQS_ADJRDQS_MASK (0x1f << DDRC_DQS_ADJRDQS_BIT)
4441
4442/* DDRC Memory Map Config Register */
4443#define DDRC_MMAP_BASE_BIT 8 /* base address */
4444#define DDRC_MMAP_BASE_MASK (0xff << DDRC_MMAP_BASE_BIT)
4445#define DDRC_MMAP_MASK_BIT 0 /* address mask */
4446#define DDRC_MMAP_MASK_MASK (0xff << DDRC_MMAP_MASK_BIT)
4447
4448#define DDRC_MMAP0_BASE (0x20 << DDRC_MMAP_BASE_BIT)
4449#define DDRC_MMAP1_BASE_64M (0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
4450#define DDRC_MMAP1_BASE_128M (0x28 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
4451#define DDRC_MMAP1_BASE_256M (0x30 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
4452
4453#define DDRC_MMAP_MASK_64_64 (0xfc << DDRC_MMAP_MASK_BIT) /*mask for two 128M SDRAM*/
4454#define DDRC_MMAP_MASK_128_128 (0xf8 << DDRC_MMAP_MASK_BIT) /*mask for two 128M SDRAM*/
4455#define DDRC_MMAP_MASK_256_256 (0xf0 << DDRC_MMAP_MASK_BIT) /*mask for two 128M SDRAM*/
4456
4457/* DDRC Timing Configure Register 1 */
4458#define DDRC_DDELAYCTRL1_TSEL_BIT 18
4459#define DDRC_DDELAYCTRL1_TSEL_MASK (0x3 << DDRC_DDELAYCTRL1_TSEL_BIT)
4460#define DDRC_DDELAYCTRL1_MSEL_BIT 16
4461#define DDRC_DDELAYCTRL1_MSEL_MASK (0x3 << DDRC_DDELAYCTRL1_MSEL_BIT)
4462#define DDRC_DDELAYCTRL1_HL (1 << 15)
4463#define DDRC_DDELAYCTRL1_QUAR (1 << 14)
4464#define DDRC_DDELAYCTRL1_MAUTO (1 << 6)
4465#define DDRC_DDELAYCTRL1_MSIGN (1 << 5)
4466#define DDRC_DDELAYCTRL1_MASK_DELAY_SEL_ADJ_BIT 0
4467#define DDRC_DDELAYCTRL1_MASK_DELAY_SEL_ADJ_MASK (0x1f << DDRC_DDELAYCTRL1_MASK_DELAY_SEL_ADJ_BIT)
4468
4469/* DDRC Timing Configure Register 2 */
4470#define DDRC_DDELAYCTRL2_MASK_DELAY_SEL_BIT 0
4471#define DDRC_DDELAYCTRL2_MASK_DELAY_SEL_MASK (0x3f << DDRC_DDELAYCTRL2_MASK_DELAY_SEL_BIT)
4472
4473/* DDRC Multi-media stride Register */
4474#define DDRC_DSTRB_STRB0_BIT 16
4475#define DDRC_DSTRB_STRB0_MASK (0x1fff << DDRC_DSTRB_STRB0_BIT)
4476#define DDRC_DSTRB_STRB1_BIT 0
4477#define DDRC_DSTRB_STRB1_MASK (0x1fff << DDRC_DSTRB_STRB1_BIT)
4478/* DDRC IO pad control Register */
4479#define DDRC_PMEMBS0_PDDQS3 (1 << 31)
4480#define DDRC_PMEMBS0_PDDQS2 (1 << 30)
4481#define DDRC_PMEMBS0_PDDQS1 (1 << 29)
4482#define DDRC_PMEMBS0_PDDQS0 (1 << 28)
4483#define DDRC_PMEMBS0_PDDQ3 (1 << 27)
4484#define DDRC_PMEMBS0_PDDQ2 (1 << 26)
4485#define DDRC_PMEMBS0_PDDQ1 (1 << 25)
4486#define DDRC_PMEMBS0_PDDQ0 (1 << 24)
4487#define DDRC_PMEMBS0_STDQS3 (1 << 23)
4488#define DDRC_PMEMBS0_STDQS2 (1 << 22)
4489#define DDRC_PMEMBS0_STDQS1 (1 << 21)
4490#define DDRC_PMEMBS0_STDQS0 (1 << 20)
4491#define DDRC_PMEMBS0_STDQ3 (1 << 19)
4492#define DDRC_PMEMBS0_STDQ2 (1 << 18)
4493#define DDRC_PMEMBS0_STDQ1 (1 << 17)
4494#define DDRC_PMEMBS0_STDQ0 (1 << 16)
4495#define DDRC_PMEMBS0_PEDQS3 (1 << 15)
4496#define DDRC_PMEMBS0_PEDQS2 (1 << 14)
4497#define DDRC_PMEMBS0_PEDQS1 (1 << 13)
4498#define DDRC_PMEMBS0_PEDQS0 (1 << 12)
4499#define DDRC_PMEMBS0_PEDQ3 (1 << 11)
4500#define DDRC_PMEMBS0_PEDQ2 (1 << 10)
4501#define DDRC_PMEMBS0_PEDQ1 (1 << 9)
4502#define DDRC_PMEMBS0_PEDQ0 (1 << 8)
4503#define DDRC_PMEMBS0_PSDQS3 (1 << 7)
4504#define DDRC_PMEMBS0_PSDQS2 (1 << 6)
4505#define DDRC_PMEMBS0_PSDQS1 (1 << 5)
4506#define DDRC_PMEMBS0_PSDQS0 (1 << 4)
4507#define DDRC_PMEMBS0_PSDQ3 (1 << 3)
4508#define DDRC_PMEMBS0_PSDQ2 (1 << 2)
4509#define DDRC_PMEMBS0_PSDQ1 (1 << 1)
4510#define DDRC_PMEMBS0_PSDQ0 (1 << 0)
4511/* DDRC IO pad control Register */
4512#define DDRC_PMEMBS1_IENDQS3 (1 << 31)
4513#define DDRC_PMEMBS1_IENDQS2 (1 << 30)
4514#define DDRC_PMEMBS1_IENDQS1 (1 << 29)
4515#define DDRC_PMEMBS1_IENDQS0 (1 << 28)
4516#define DDRC_PMEMBS1_IENDQ3 (1 << 27)
4517#define DDRC_PMEMBS1_IENDQ2 (1 << 26)
4518#define DDRC_PMEMBS1_IENDQ1 (1 << 25)
4519#define DDRC_PMEMBS1_IENDQ0 (1 << 24)
4520#define DDRC_PMEMBS1_SSTL (1 << 16)
4521
4522#define DDRC_PMEMBS1_SSELDQS3_BIT 14
4523#define DDRC_PMEMBS1_SSELDQS3_MASK (0x3 << DDRC_PMEMBS1_SSELDQS3_BIT)
4524
4525#define DDRC_PMEMBS1_SSELDQS2_BIT 12
4526#define DDRC_PMEMBS1_SSELDQS2_MASK (0x3 << DDRC_PMEMBS1_SSELDQS2_BIT)
4527
4528#define DDRC_PMEMBS1_SSELDQS1_BIT 10
4529#define DDRC_PMEMBS1_SSELDQS1_MASK (0x3 << DDRC_PMEMBS1_SSELDQS1_BIT)
4530
4531#define DDRC_PMEMBS1_SSELDQS0_BIT 8
4532#define DDRC_PMEMBS1_SSELDQS0_MASK (0x3 << DDRC_PMEMBS1_SSELDQS0_BIT)
4533
4534#define DDRC_PMEMBS1_SSELDQ3_BIT 6
4535#define DDRC_PMEMBS1_SSELDQ3_MASK (0x3 << DDRC_PMEMBS1_SSELDQ3_BIT)
4536
4537#define DDRC_PMEMBS1_SSELDQ2_BIT 4
4538#define DDRC_PMEMBS1_SSELDQ2_MASK (0x3 << DDRC_PMEMBS1_SSELDQ2_BIT)
4539
4540#define DDRC_PMEMBS1_SSELDQ1_BIT 2
4541#define DDRC_PMEMBS1_SSELDQ1_MASK (0x3 << DDRC_PMEMBS1_SSELDQ1_BIT)
4542
4543#define DDRC_PMEMBS1_SSELDQ0_BIT 0
4544#define DDRC_PMEMBS1_SSELDQ0_MASK (0x3 << DDRC_PMEMBS1_SSELDQ0_BIT)
4545
4546/* DDRC IO pad control Register */
4547#define DDRC_PMEMOSEL_CKSSEL_BIT 18
4548#define DDRC_PMEMOSEL_CKSSEL_MASK (0x3 << DDRC_PMEMOSEL_CKSSEL_BIT)
4549
4550#define DDRC_PMEMOSEL_CKESSEL_BIT 16
4551#define DDRC_PMEMOSEL_CKESSEL_MASK (0x3 << DDRC_PMEMOSEL_CKESSEL_BIT)
4552
4553#define DDRC_PMEMOSEL_ADDRSSEL_BIT 14
4554#define DDRC_PMEMOSEL_ADDRSSEL_MASK (0x3 << DDRC_PMEMOSEL_ADDRSSEL_BIT)
4555
4556#define DDRC_PMEMOSEL_DMSSEL3_BIT 12
4557#define DDRC_PMEMOSEL_DMSSEL3_MASK (0x3 << DDRC_PMEMOSEL_DMSSEL3_BIT)
4558
4559#define DDRC_PMEMOSEL_DMSSEL2_BIT 10
4560#define DDRC_PMEMOSEL_DMSSEL2_MASK (0x3 << DDRC_PMEMOSEL_DMSSEL2_BIT)
4561
4562#define DDRC_PMEMOSEL_DMSSEL1_BIT 8
4563#define DDRC_PMEMOSEL_DMSSEL1_MASK (0x3 << DDRC_PMEMOSEL_DMSSEL1_BIT)
4564
4565#define DDRC_PMEMOSEL_DMSSEL0_BIT 6
4566#define DDRC_PMEMOSEL_DMSSEL0_MASK (0x3 << DDRC_PMEMOSEL_DMSSEL0_BIT)
4567
4568#define DDRC_PMEMOSEL_CMDSSEL_BIT 4
4569#define DDRC_PMEMOSEL_CMDSSEL_MASK (0x3 << DDRC_PMEMOSEL_CMDSSEL_BIT)
4570
4571#define DDRC_PMEMOSEL_CSSSEL1_BIT 2
4572#define DDRC_PMEMOSEL_CSSSEL1_MASK (0x3 << DDRC_PMEMOSEL_CSSSEL1_BIT)
4573
4574#define DDRC_PMEMOSEL_CSSSEL0_BIT 0
4575#define DDRC_PMEMOSEL_CSSSEL0_MASK (0x3 << DDRC_PMEMOSEL_CSSSEL0_BIT)
4576
4577/* DDRC IO pad control Register */
4578#define DDRC_PMEMOEN_CKOEN (1 << 14)
4579#define DDRC_PMEMOEN_BAOEN2 (1 << 13)
4580#define DDRC_PMEMOEN_BAOEN1 (1 << 12)
4581#define DDRC_PMEMOEN_BAOEN0 (1 << 11)
4582#define DDRC_PMEMOEN_AOEN13 (1 << 10)
4583#define DDRC_PMEMOEN_AOEN12 (1 << 9)
4584#define DDRC_PMEMOEN_AOEN11_0 (1 << 8)
4585#define DDRC_PMEMOEN_DMOEN3 (1 << 7)
4586#define DDRC_PMEMOEN_DMOEN2 (1 << 6)
4587#define DDRC_PMEMOEN_DMOEN1 (1 << 5)
4588#define DDRC_PMEMOEN_DMOEN0 (1 << 4)
4589#define DDRC_PMEMOEN_CMDOEN (1 << 3)
4590#define DDRC_PMEMOEN_CSOEN1 (1 << 2)
4591#define DDRC_PMEMOEN_CSOEN0 (1 << 1)
4592#define DDRC_PMEMOEN_CKEOEN (1 << 0)
4593
4594#ifndef __MIPS_ASSEMBLER
4595
4596#define DDR_GET_VALUE(x, y) \
4597({ \
4598 unsigned long value, tmp; \
4599 tmp = x * 1000; \
4600 value = (tmp % y == 0) ? (tmp / y) : (tmp / y + 1); \
4601 value; \
4602})
4603
4604#endif /* __MIPS_ASSEMBLER */
4605
4606#define EMC_BASE 0xB3410000
4607
4608/*************************************************************************
4609 * EMC (External Memory Controller)
4610 *************************************************************************/
4611#define EMC_BCR (EMC_BASE + 0x00) /* Bus Control Register */
4612#define EMC_PMEMBS1 (EMC_BASE + 0x6004)
4613#define EMC_PMEMBS0 (EMC_BASE + 0x6008)
4614#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 ??? */
4615#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */
4616#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */
4617#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */
4618#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */
4619#define EMC_SMCR5 (EMC_BASE + 0x24) /* Static Memory Control Register 5 */
4620#define EMC_SMCR6 (EMC_BASE + 0x28) /* Static Memory Control Register 6 */
4621#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */
4622#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
4623#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
4624#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
4625#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
4626#define EMC_SACR5 (EMC_BASE + 0x44) /* Static Memory Bank 5 Addr Config Reg */
4627#define EMC_SACR6 (EMC_BASE + 0x48) /* Static Memory Bank 6 Addr Config Reg */
4628#define EMC_NFCSR (EMC_BASE + 0x50) /* NAND Flash Control/Status Register */
4629#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
4630#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
4631#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
4632#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
4633#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
4634#define EMC_DMAR1 (EMC_BASE + 0x94) /* SDRAM Bank 1 Addr Config Register */
4635#define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
4636
4637#define REG_EMC_BCR REG32(EMC_BCR)
4638#define REG_EMC_PMEMBS1 REG32(EMC_PMEMBS1)
4639#define REG_EMC_PMEMBS0 REG32(EMC_PMEMBS0)
4640#define REG_EMC_SMCR0 REG32(EMC_SMCR0) // ???
4641#define REG_EMC_SMCR1 REG32(EMC_SMCR1)
4642#define REG_EMC_SMCR2 REG32(EMC_SMCR2)
4643#define REG_EMC_SMCR3 REG32(EMC_SMCR3)
4644#define REG_EMC_SMCR4 REG32(EMC_SMCR4)
4645#define REG_EMC_SMCR5 REG32(EMC_SMCR5)
4646#define REG_EMC_SMCR6 REG32(EMC_SMCR6)
4647#define REG_EMC_SACR0 REG32(EMC_SACR0)
4648#define REG_EMC_SACR1 REG32(EMC_SACR1)
4649#define REG_EMC_SACR2 REG32(EMC_SACR2)
4650#define REG_EMC_SACR3 REG32(EMC_SACR3)
4651#define REG_EMC_SACR4 REG32(EMC_SACR4)
4652
4653#define REG_EMC_NFCSR REG32(EMC_NFCSR)
4654
4655#define REG_EMC_DMCR REG32(EMC_DMCR)
4656#define REG_EMC_RTCSR REG16(EMC_RTCSR)
4657#define REG_EMC_RTCNT REG16(EMC_RTCNT)
4658#define REG_EMC_RTCOR REG16(EMC_RTCOR)
4659#define REG_EMC_DMAR0 REG32(EMC_DMAR0)
4660#define REG_EMC_DMAR1 REG32(EMC_DMAR1)
4661
4662/* Bus Control Register */
4663#define EMC_BCR_BT_SEL_BIT 30
4664#define EMC_BCR_BT_SEL_MASK (0x3 << EMC_BCR_BT_SEL_BIT)
4665#define EMC_BCR_PK_SEL (1 << 24)
4666#define EMC_BCR_BSR_MASK (1 << 2) /* Nand and SDRAM Bus Share Select: 0, share; 1, unshare */
4667 #define EMC_BCR_BSR_SHARE (0 << 2)
4668 #define EMC_BCR_BSR_UNSHARE (1 << 2)
4669#define EMC_BCR_BRE (1 << 1)
4670#define EMC_BCR_ENDIAN (1 << 0)
4671
4672/* Static Memory Control Register */
4673#define EMC_SMCR_STRV_BIT 24
4674#define EMC_SMCR_STRV_MASK (0x1f << EMC_SMCR_STRV_BIT)
4675#define EMC_SMCR_TAW_BIT 20
4676#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
4677#define EMC_SMCR_TBP_BIT 16
4678#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
4679#define EMC_SMCR_TAH_BIT 12
4680#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
4681#define EMC_SMCR_TAS_BIT 8
4682#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
4683#define EMC_SMCR_BW_BIT 6
4684#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
4685 #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
4686 #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
4687 #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
4688#define EMC_SMCR_BCM (1 << 3)
4689#define EMC_SMCR_BL_BIT 1
4690#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
4691 #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
4692 #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
4693 #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
4694 #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
4695#define EMC_SMCR_SMT (1 << 0)
4696
4697/* Static Memory Bank Addr Config Reg */
4698#define EMC_SACR_BASE_BIT 8
4699#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
4700#define EMC_SACR_MASK_BIT 0
4701#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
4702
4703/* NAND Flash Control/Status Register */
4704#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
4705#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
4706#define EMC_NFCSR_NFCE3 (1 << 5)
4707#define EMC_NFCSR_NFE3 (1 << 4)
4708#define EMC_NFCSR_NFCE2 (1 << 3)
4709#define EMC_NFCSR_NFE2 (1 << 2)
4710#define EMC_NFCSR_NFCE1 (1 << 1)
4711#define EMC_NFCSR_NFE1 (1 << 0)
4712#define EMC_NFCSR_NFE(n) (1 << (((n)-1)*2))
4713#define EMC_NFCSR_NFCE(n) (1 << (((n)*2)-1))
4714
4715/* DRAM Control Register */
4716#define EMC_DMCR_BW_BIT 31
4717#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
4718#define EMC_DMCR_CA_BIT 26
4719#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
4720 #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
4721 #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
4722 #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
4723 #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
4724 #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
4725#define EMC_DMCR_RMODE (1 << 25)
4726#define EMC_DMCR_RFSH (1 << 24)
4727#define EMC_DMCR_MRSET (1 << 23)
4728#define EMC_DMCR_RA_BIT 20
4729#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
4730 #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
4731 #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
4732 #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
4733#define EMC_DMCR_BA_BIT 19
4734#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
4735#define EMC_DMCR_PDM (1 << 18)
4736#define EMC_DMCR_EPIN (1 << 17)
4737#define EMC_DMCR_MBSEL (1 << 16)
4738#define EMC_DMCR_TRAS_BIT 13
4739#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
4740#define EMC_DMCR_RCD_BIT 11
4741#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
4742#define EMC_DMCR_TPC_BIT 8
4743#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
4744#define EMC_DMCR_TRWL_BIT 5
4745#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
4746#define EMC_DMCR_TRC_BIT 2
4747#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
4748#define EMC_DMCR_TCL_BIT 0
4749#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
4750
4751/* Refresh Time Control/Status Register */
4752#define EMC_RTCSR_SFR (1 << 8) /* self refresh flag */
4753#define EMC_RTCSR_CMF (1 << 7)
4754#define EMC_RTCSR_CKS_BIT 0
4755#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
4756 #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
4757 #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
4758 #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
4759 #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
4760 #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
4761 #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
4762 #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
4763 #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
4764
4765/* SDRAM Bank Address Configuration Register */
4766#define EMC_DMAR_BASE_BIT 8
4767#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
4768#define EMC_DMAR_MASK_BIT 0
4769#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
4770
4771/* Mode Register of SDRAM bank 0 */
4772#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
4773#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
4774#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
4775 #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
4776#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
4777#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
4778 #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
4779 #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
4780 #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
4781#define EMC_SDMR_BT_BIT 3 /* Burst Type */
4782#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
4783 #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
4784 #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
4785#define EMC_SDMR_BL_BIT 0 /* Burst Length */
4786#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
4787 #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
4788 #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
4789 #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
4790 #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
4791
4792#define EMC_SDMR_CAS2_16BIT \
4793 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
4794#define EMC_SDMR_CAS2_32BIT \
4795 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
4796#define EMC_SDMR_CAS3_16BIT \
4797 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
4798#define EMC_SDMR_CAS3_32BIT \
4799 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
4800
4801#define I2C0_BASE 0xB0050000
4802#define I2C1_BASE 0xB0051000
4803
4804/*************************************************************************
4805 * I2C
4806 *************************************************************************/
4807#define I2C_CTRL(n) (I2C0_BASE + (n)*0x1000 + 0x00)
4808#define I2C_TAR(n) (I2C0_BASE + (n)*0x1000 + 0x04)
4809#define I2C_SAR(n) (I2C0_BASE + (n)*0x1000 + 0x08)
4810#define I2C_DC(n) (I2C0_BASE + (n)*0x1000 + 0x10)
4811#define I2C_SHCNT(n) (I2C0_BASE + (n)*0x1000 + 0x14)
4812#define I2C_SLCNT(n) (I2C0_BASE + (n)*0x1000 + 0x18)
4813#define I2C_FHCNT(n) (I2C0_BASE + (n)*0x1000 + 0x1C)
4814#define I2C_FLCNT(n) (I2C0_BASE + (n)*0x1000 + 0x20)
4815#define I2C_INTST(n) (I2C0_BASE + (n)*0x1000 + 0x2C)
4816#define I2C_INTM(n) (I2C0_BASE + (n)*0x1000 + 0x30)
4817#define I2C_RXTL(n) (I2C0_BASE + (n)*0x1000 + 0x38)
4818#define I2C_TXTL(n) (I2C0_BASE + (n)*0x1000 + 0x3c)
4819#define I2C_CINTR(n) (I2C0_BASE + (n)*0x1000 + 0x40)
4820#define I2C_CRXUF(n) (I2C0_BASE + (n)*0x1000 + 0x44)
4821#define I2C_CRXOF(n) (I2C0_BASE + (n)*0x1000 + 0x48)
4822#define I2C_CTXOF(n) (I2C0_BASE + (n)*0x1000 + 0x4C)
4823#define I2C_CRXREQ(n) (I2C0_BASE + (n)*0x1000 + 0x50)
4824#define I2C_CTXABRT(n) (I2C0_BASE + (n)*0x1000 + 0x54)
4825#define I2C_CRXDONE(n) (I2C0_BASE + (n)*0x1000 + 0x58)
4826#define I2C_CACT(n) (I2C0_BASE + (n)*0x1000 + 0x5C)
4827#define I2C_CSTP(n) (I2C0_BASE + (n)*0x1000 + 0x60)
4828#define I2C_CSTT(n) (I2C0_BASE + (n)*0x1000 + 0x64)
4829#define I2C_CGC(n) (I2C0_BASE + (n)*0x1000 + 0x68)
4830#define I2C_ENB(n) (I2C0_BASE + (n)*0x1000 + 0x6C)
4831#define I2C_STA(n) (I2C0_BASE + (n)*0x1000 + 0x70)
4832#define I2C_TXABRT(n) (I2C0_BASE + (n)*0x1000 + 0x80)
4833#define I2C_DMACR(n) (I2C0_BASE + (n)*0x1000 + 0x88)
4834#define I2C_DMATDLR(n) (I2C0_BASE + (n)*0x1000 + 0x8c)
4835#define I2C_DMARDLR(n) (I2C0_BASE + (n)*0x1000 + 0x90)
4836#define I2C_SDASU(n) (I2C0_BASE + (n)*0x1000 + 0x94)
4837#define I2C_ACKGC(n) (I2C0_BASE + (n)*0x1000 + 0x98)
4838#define I2C_ENSTA(n) (I2C0_BASE + (n)*0x1000 + 0x9C)
4839
4840#define REG_I2C_CTRL(n) REG8(I2C_CTRL(n)) /* I2C Control Register (I2C_CTRL) */
4841#define REG_I2C_TAR(n) REG16(I2C_TAR(n)) /* I2C target address (I2C_TAR) */
4842#define REG_I2C_SAR(n) REG16(I2C_SAR(n))
4843#define REG_I2C_DC(n) REG16(I2C_DC(n))
4844#define REG_I2C_SHCNT(n) REG16(I2C_SHCNT(n))
4845#define REG_I2C_SLCNT(n) REG16(I2C_SLCNT(n))
4846#define REG_I2C_FHCNT(n) REG16(I2C_FHCNT(n))
4847#define REG_I2C_FLCNT(n) REG16(I2C_FLCNT(n))
4848#define REG_I2C_INTST(n) REG16(I2C_INTST(n)) /* i2c interrupt status (I2C_INTST) */
4849#define REG_I2C_INTM(n) REG16(I2C_INTM(n)) /* i2c interrupt mask status (I2C_INTM) */
4850#define REG_I2C_RXTL(n) REG8(I2C_RXTL(n))
4851#define REG_I2C_TXTL(n) REG8(I2C_TXTL(n))
4852#define REG_I2C_CINTR(n) REG8(I2C_CINTR(n))
4853#define REG_I2C_CRXUF(n) REG8(I2C_CRXUF(n))
4854#define REG_I2C_CRXOF(n) REG8(I2C_CRXOF(n))
4855#define REG_I2C_CTXOF(n) REG8(I2C_CTXOF(n))
4856#define REG_I2C_CRXREQ(n) REG8(I2C_CRXREQ(n))
4857#define REG_I2C_CTXABRT(n) REG8(I2C_CTXABRT(n))
4858#define REG_I2C_CRXDONE(n) REG8(I2C_CRXDONE(n))
4859#define REG_I2C_CACT(n) REG8(I2C_CACT(n))
4860#define REG_I2C_CSTP(n) REG8(I2C_CSTP(n))
4861#define REG_I2C_CSTT(n) REG16(I2C_CSTT(n))
4862#define REG_I2C_CGC(n) REG8(I2C_CGC(n))
4863#define REG_I2C_ENB(n) REG8(I2C_ENB(n))
4864#define REG_I2C_STA(n) REG8(I2C_STA(n))
4865#define REG_I2C_TXABRT(n) REG16(I2C_TXABRT(n))
4866#define REG_I2C_DMACR(n) REG8(I2C_DMACR(n))
4867#define REG_I2C_DMATDLR(n) REG8(I2C_DMATDLR(n))
4868#define REG_I2C_DMARDLR(n) REG8(I2C_DMARDLR(n))
4869#define REG_I2C_SDASU(n) REG8(I2C_SDASU(n))
4870#define REG_I2C_ACKGC(n) REG8(I2C_ACKGC(n))
4871#define REG_I2C_ENSTA(n) REG8(I2C_ENSTA(n))
4872
4873/* I2C Control Register (I2C_CTRL) */
4874
4875#define I2C_CTRL_STPHLD (1 << 7) /* Stop Hold Enable bit: when tx fifo empty, 0: send stop 1: never send stop*/
4876#define I2C_CTRL_SLVDIS (1 << 6) /* after reset slave is disabled*/
4877#define I2C_CTRL_REST (1 << 5)
4878#define I2C_CTRL_MATP (1 << 4) /* 1: 10bit address 0: 7bit addressing*/
4879#define I2C_CTRL_SATP (1 << 3) /* 1: 10bit address 0: 7bit address*/
4880#define I2C_CTRL_SPDF (2 << 1) /* fast mode 400kbps */
4881#define I2C_CTRL_SPDS (1 << 1) /* standard mode 100kbps */
4882#define I2C_CTRL_MD (1 << 0) /* master enabled*/
4883
4884/* I2C target address (I2C_TAR) */
4885
4886#define I2C_TAR_MATP (1 << 12)
4887#define I2C_TAR_SPECIAL (1 << 11)
4888#define I2C_TAR_GC_OR_START (1 << 10)
4889#define I2C_TAR_I2CTAR_BIT 0
4890#define I2C_TAR_I2CTAR_MASK (0x3ff << I2C_TAR_I2CTAR_BIT)
4891
4892/* I2C slave address */
4893#define I2C_SAR_I2CSAR_BIT 0
4894#define I2C_SAR_I2CSAR_MASK (0x3ff << I2C_SAR_I2CSAR_BIT)
4895
4896/* I2C data buffer and command (I2C_DC) */
4897
4898#define I2C_DC_CMD (1 << 8) /* 1 read 0 write*/
4899#define I2C_DC_DAT_BIT 0
4900#define I2C_DC_DAT_MASK (0xff << I2C_DC_DAT_BIT) /* 1 read 0 write*/
4901
4902/* i2c interrupt status (I2C_INTST) */
4903
4904#define I2C_INTST_IGC (1 << 11) /* */
4905#define I2C_INTST_ISTT (1 << 10)
4906#define I2C_INTST_ISTP (1 << 9)
4907#define I2C_INTST_IACT (1 << 8)
4908#define I2C_INTST_RXDN (1 << 7)
4909#define I2C_INTST_TXABT (1 << 6)
4910#define I2C_INTST_RDREQ (1 << 5)
4911#define I2C_INTST_TXEMP (1 << 4)
4912#define I2C_INTST_TXOF (1 << 3)
4913#define I2C_INTST_RXFL (1 << 2)
4914#define I2C_INTST_RXOF (1 << 1)
4915#define I2C_INTST_RXUF (1 << 0)
4916
4917/* i2c interrupt mask status (I2C_INTM) */
4918
4919#define I2C_INTM_MIGC (1 << 11) /* */
4920#define I2C_INTM_MISTT (1 << 10)
4921#define I2C_INTM_MISTP (1 << 9)
4922#define I2C_INTM_MIACT (1 << 8)
4923#define I2C_INTM_MRXDN (1 << 7)
4924#define I2C_INTM_MTXABT (1 << 6)
4925#define I2C_INTM_MRDREQ (1 << 5)
4926#define I2C_INTM_MTXEMP (1 << 4)
4927#define I2C_INTM_MTXOF (1 << 3)
4928#define I2C_INTM_MRXFL (1 << 2)
4929#define I2C_INTM_MRXOF (1 << 1)
4930#define I2C_INTM_MRXUF (1 << 0)
4931
4932/* I2C Clear Combined and Individual Interrupts (I2C_CINTR) */
4933
4934#define I2C_CINTR_CINT (1 << 0)
4935
4936/* I2C Clear TX_OVER Interrupt */
4937/* I2C Clear RDREQ Interrupt */
4938/* I2C Clear TX_ABRT Interrupt */
4939/* I2C Clear RX_DONE Interrupt */
4940/* I2C Clear ACTIVITY Interrupt */
4941/* I2C Clear STOP Interrupts */
4942/* I2C Clear START Interrupts */
4943/* I2C Clear GEN_CALL Interrupts */
4944
4945/* I2C Enable (I2C_ENB) */
4946
4947#define I2C_ENB_I2CENB (1 << 0) /* Enable the i2c */
4948
4949/* I2C Status Register (I2C_STA) */
4950
4951#define I2C_STA_SLVACT (1 << 6) /* Slave FSM is not in IDLE state */
4952#define I2C_STA_MSTACT (1 << 5) /* Master FSM is not in IDLE state */
4953#define I2C_STA_RFF (1 << 4) /* RFIFO if full */
4954#define I2C_STA_RFNE (1 << 3) /* RFIFO is not empty */
4955#define I2C_STA_TFE (1 << 2) /* TFIFO is empty */
4956#define I2C_STA_TFNF (1 << 1) /* TFIFO is not full */
4957#define I2C_STA_ACT (1 << 0) /* I2C Activity Status */
4958
4959/* I2C Transmit Abort Status Register (I2C_TXABRT) */
4960
4961#define I2C_TXABRT_SLVRD_INTX (1 << 15)
4962#define I2C_TXABRT_SLV_ARBLOST (1 << 14)
4963#define I2C_TXABRT_SLVFLUSH_TXFIFO (1 << 13)
4964#define I2C_TXABRT_ARB_LOST (1 << 12)
4965#define I2C_TXABRT_ABRT_MASTER_DIS (1 << 11)
4966#define I2C_TXABRT_ABRT_10B_RD_NORSTRT (1 << 10)
4967#define I2C_TXABRT_SBYTE_NORSTRT (1 << 9)
4968#define I2C_TXABRT_ABRT_HS_NORSTRT (1 << 8)
4969#define I2C_TXABRT_SBYTE_ACKDET (1 << 7)
4970#define I2C_TXABRT_ABRT_HS_ACKD (1 << 6)
4971#define I2C_TXABRT_ABRT_GCALL_READ (1 << 5)
4972#define I2C_TXABRT_ABRT_GCALL_NOACK (1 << 4)
4973#define I2C_TXABRT_ABRT_XDATA_NOACK (1 << 3)
4974#define I2C_TXABRT_ABRT_10ADDR2_NOACK (1 << 2)
4975#define I2C_TXABRT_ABRT_10ADDR1_NOACK (1 << 1)
4976#define I2C_TXABRT_ABRT_7B_ADDR_NOACK (1 << 0)
4977
4978/* */
4979#define I2C_DMACR_TDEN (1 << 1)
4980#define I2C_DMACR_RDEN (1 << 0)
4981
4982/* */
4983#define I2C_DMATDLR_TDLR_BIT 0
4984#define I2C_DMATDLR_TDLR_MASK (0x1f << I2C_DMATDLR_TDLR_BIT)
4985
4986/* */
4987#define I2C_DMARDLR_RDLR_BIT 0
4988#define I2C_DMARDLR_RDLR_MASK (0x1f << I2C_DMARDLR_RDLR_BIT)
4989
4990/* I2C Enable Status Register (I2C_ENSTA) */
4991
4992#define I2C_ENSTA_SLVRDLST (1 << 2)
4993#define I2C_ENSTA_SLVDISB (1 << 1)
4994#define I2C_ENSTA_I2CEN (1 << 0) /* when read as 1, i2c is deemed to be in an enabled state
4995 when read as 0, i2c is deemed completely inactive. The cpu can
4996 safely read this bit anytime .When this bit is read as 0 ,the cpu can
4997 safely read SLVRDLST and SLVDISB */
4998
4999/* I2C standard mode high count register(I2CSHCNT) */
5000#define I2CSHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
5001
5002/* I2C standard mode low count register(I2CSLCNT) */
5003#define I2CSLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
5004
5005/* I2C fast mode high count register(I2CFHCNT) */
5006#define I2CFHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
5007
5008/* I2C fast mode low count register(I2CFLCNT) */
5009#define I2CFLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
5010
5011#ifndef __MIPS_ASSEMBLER
5012
5013/***************************************************************************
5014 * I2C
5015 ***************************************************************************/
5016
5017#define __i2c_enable(n) ( REG_I2C_ENB(n) = 1 )
5018#define __i2c_disable(n) ( REG_I2C_ENB(n) = 0 )
5019
5020#define __i2c_is_enable(n) ( REG_I2C_ENSTA(n) & I2C_ENB_I2CENB )
5021#define __i2c_is_disable(n) ( !(REG_I2C_ENSTA(n) & I2C_ENB_I2CENB) )
5022
5023#define __i2c_abrt(n) ( REG_I2C_TXABRT(n) != 0 )
5024#define __i2c_abrt_intr(n) (REG_I2C_INTST(n) & I2C_INTST_TXABT)
5025#define __i2c_master_active(n) ( REG_I2C_STA(n) & I2C_STA_MSTACT )
5026#define __i2c_abrt_7b_addr_nack(n) ( REG_I2C_TXABRT(n) & I2C_TXABRT_ABRT_7B_ADDR_NOACK )
5027#define __i2c_txfifo_is_empty(n) ( REG_I2C_STA(n) & I2C_STA_TFE )
5028#define __i2c_clear_interrupts(ret,n) ( ret = REG_I2C_CINTR(n) )
5029
5030#define __i2c_dma_rd_enable(n) SETREG8(I2C_DMACR(n),1 << 0)
5031#define __i2c_dma_rd_disable(n) CLRREG8(I2C_DMACR(n),1 << 0)
5032#define __i2c_dma_td_enable(n) SETREG8(I2C_DMACR(n),1 << 1)
5033#define __i2c_dma_td_disable(n) CLRREG8(I2C_DMACR(n),1 << 1)
5034
5035#define __i2c_send_stop(n) CLRREG8(I2C_CTRL(n), I2C_CTRL_STPHLD)
5036#define __i2c_nsend_stop(n) SETREG8(I2C_CTRL(n), I2C_CTRL_STPHLD)
5037
5038#define __i2c_set_dma_td_level(n,data) OUTREG8(I2C_DMATDLR(n),data)
5039#define __i2c_set_dma_rd_level(n,data) OUTREG8(I2C_DMARDLR(n),data)
5040
5041/*
5042#define __i2c_set_clk(dev_clk, i2c_clk) \
5043 ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
5044*/
5045
5046#define __i2c_read(n) ( REG_I2C_DC(n) & 0xff )
5047#define __i2c_write(val,n) ( REG_I2C_DC(n) = (val) )
5048
5049#endif /* __MIPS_ASSEMBLER */
5050
5051#define IPU_BASE 0xB3080000
5052
5053/*************************************************************************
5054 * IPU (Image Processing Unit)
5055 *************************************************************************/
5056#define IPU_V_BASE 0xB3080000
5057#define IPU_P_BASE 0x13080000
5058
5059/* Register offset */
5060#define REG_CTRL 0x0 /* IPU Control Register */
5061#define REG_STATUS 0x4 /* IPU Status Register */
5062#define REG_D_FMT 0x8 /* Data Format Register */
5063#define REG_Y_ADDR 0xc /* Input Y or YUV422 Packaged Data Address Register */
5064#define REG_U_ADDR 0x10 /* Input U Data Address Register */
5065#define REG_V_ADDR 0x14 /* Input V Data Address Register */
5066#define REG_IN_FM_GS 0x18 /* Input Geometric Size Register */
5067#define REG_Y_STRIDE 0x1c /* Input Y Data Line Stride Register */
5068#define REG_UV_STRIDE 0x20 /* Input UV Data Line Stride Register */
5069#define REG_OUT_ADDR 0x24 /* Output Frame Start Address Register */
5070#define REG_OUT_GS 0x28 /* Output Geometric Size Register */
5071#define REG_OUT_STRIDE 0x2c /* Output Data Line Stride Register */
5072#define REG_RSZ_COEF_INDEX 0x30 /* Resize Coefficients Table Index Register */
5073#define REG_CSC_CO_COEF 0x34 /* CSC C0 Coefficient Register */
5074#define REG_CSC_C1_COEF 0x38 /* CSC C1 Coefficient Register */
5075#define REG_CSC_C2_COEF 0x3c /* CSC C2 Coefficient Register */
5076#define REG_CSC_C3_COEF 0x40 /* CSC C3 Coefficient Register */
5077#define REG_CSC_C4_COEF 0x44 /* CSC C4 Coefficient Register */
5078#define HRSZ_LUT_BASE 0x48 /* Horizontal Resize Coefficients Look Up Table Register group */
5079#define VRSZ_LUT_BASE 0x4c /* Virtical Resize Coefficients Look Up Table Register group */
5080#define REG_CSC_OFSET_PARA 0x50 /* CSC Offset Parameter Register */
5081#define REG_Y_PHY_T_ADDR 0x54 /* Input Y Physical Table Address Register */
5082#define REG_U_PHY_T_ADDR 0x58 /* Input U Physical Table Address Register */
5083#define REG_V_PHY_T_ADDR 0x5c /* Input V Physical Table Address Register */
5084#define REG_OUT_PHY_T_ADDR 0x60 /* Output Physical Table Address Register */
5085
5086/* REG_CTRL: IPU Control Register */
5087#define IPU_CE_SFT 0x0
5088#define IPU_CE_MSK 0x1
5089#define IPU_RUN_SFT 0x1
5090#define IPU_RUN_MSK 0x1
5091#define HRSZ_EN_SFT 0x2
5092#define HRSZ_EN_MSK 0x1
5093#define VRSZ_EN_SFT 0x3
5094#define VRSZ_EN_MSK 0x1
5095#define CSC_EN_SFT 0x4
5096#define CSC_EN_MSK 0x1
5097#define FM_IRQ_EN_SFT 0x5
5098#define FM_IRQ_EN_MSK 0x1
5099#define IPU_RST_SFT 0x6
5100#define IPU_RST_MSK 0x1
5101#define H_SCALE_SFT 0x8
5102#define H_SCALE_MSK 0x1
5103#define V_SCALE_SFT 0x9
5104#define V_SCALE_MSK 0x1
5105#define PKG_SEL_SFT 0xA
5106#define PKG_SEL_MSK 0x1
5107#define LCDC_SEL_SFT 0xB
5108#define LCDC_SEL_MSK 0x1
5109#define SPAGE_MAP_SFT 0xC
5110#define SPAGE_MAP_MSK 0x1
5111#define DPAGE_SEL_SFT 0xD
5112#define DPAGE_SEL_MSK 0x1
5113#define DISP_SEL_SFT 0xE
5114#define DISP_SEL_MSK 0x1
5115#define FIELD_CONF_EN_SFT 15
5116#define FIELD_CONF_EN_MSK 1
5117#define FIELD_SEL_SFT 16
5118#define FIELD_SEL_MSK 1
5119#define DFIX_SEL_SFT 17
5120#define DFIX_SEL_MSK 1
5121
5122/* REG_STATUS: IPU Status Register */
5123#define OUT_END_SFT 0x0
5124#define OUT_END_MSK 0x1
5125#define FMT_ERR_SFT 0x1
5126#define FMT_ERR_MSK 0x1
5127#define SIZE_ERR_SFT 0x2
5128#define SIZE_ERR_MSK 0x1
5129
5130/* D_FMT: Data Format Register */
5131#define IN_FMT_SFT 0x0
5132#define IN_FMT_MSK 0x3
5133#define IN_OFT_SFT 0x2
5134#define IN_OFT_MSK 0x3
5135#define YUV_PKG_OUT_SFT 0x10
5136#define YUV_PKG_OUT_MSK 0x7
5137#define OUT_FMT_SFT 0x13
5138#define OUT_FMT_MSK 0x3
5139#define RGB_OUT_OFT_SFT 0x15
5140#define RGB_OUT_OFT_MSK 0x7
5141#define RGB888_FMT_SFT 0x18
5142#define RGB888_FMT_MSK 0x1
5143
5144/* IN_FM_GS: Input Geometric Size Register */
5145#define IN_FM_H_SFT 0x0
5146#define IN_FM_H_MSK 0xFFF
5147#define IN_FM_W_SFT 0x10
5148#define IN_FM_W_MSK 0xFFF
5149
5150/* Y_STRIDE: Input Y Data Line Stride Register */
5151#define Y_S_SFT 0x0
5152#define Y_S_MSK 0x3FFF
5153
5154/* UV_STRIDE: Input UV Data Line Stride Register */
5155#define V_S_SFT 0x0
5156#define V_S_MSK 0x1FFF
5157#define U_S_SFT 0x10
5158#define U_S_MSK 0x1FFF
5159
5160/* OUT_GS: Output Geometric Size Register */
5161#define OUT_FM_H_SFT 0x0
5162#define OUT_FM_H_MSK 0x1FFF
5163#define OUT_FM_W_SFT 0x10
5164#define OUT_FM_W_MSK 0x7FFF
5165
5166/* OUT_STRIDE: Output Data Line Stride Register */
5167#define OUT_S_SFT 0x0
5168#define OUT_S_MSK 0xFFFF
5169
5170/* RSZ_COEF_INDEX: Resize Coefficients Table Index Register */
5171#define VE_IDX_SFT 0x0
5172#define VE_IDX_MSK 0x1F
5173#define HE_IDX_SFT 0x10
5174#define HE_IDX_MSK 0x1F
5175
5176/* CSC_CX_COEF: CSC CX Coefficient Register */
5177#define CX_COEF_SFT 0x0
5178#define CX_COEF_MSK 0xFFF
5179
5180/* HRSZ_LUT_BASE, VRSZ_LUT_BASE: Resize Coefficients Look Up Table Register group */
5181#define LUT_LEN 20
5182
5183#define OUT_N_SFT 0x0
5184#define OUT_N_MSK 0x1
5185#define IN_N_SFT 0x1
5186#define IN_N_MSK 0x1
5187#define W_COEF_SFT 0x2
5188#define W_COEF_MSK 0x3FF
5189
5190/* CSC_OFSET_PARA: CSC Offset Parameter Register */
5191#define CHROM_OF_SFT 0x10
5192#define CHROM_OF_MSK 0xFF
5193#define LUMA_OF_SFT 0x00
5194#define LUMA_OF_MSK 0xFF
5195
5196#ifndef __MIPS_ASSEMBLER
5197
5198#if 0
5199/*************************************************************************
5200 * IPU (Image Processing Unit)
5201 *************************************************************************/
5202#define u32 volatile unsigned long
5203
5204#define write_reg(reg, val) \
5205do { \
5206 *(u32 *)(reg) = (val); \
5207} while(0)
5208
5209#define read_reg(reg, off) (*(u32 *)((reg)+(off)))
5210
5211#define set_ipu_fmt(rgb_888_out_fmt, rgb_out_oft, out_fmt, yuv_pkg_out, in_oft, in_fmt ) \
5212({ write_reg( (IPU_V_BASE + REG_D_FMT), ((in_fmt) & IN_FMT_MSK)<<IN_FMT_SFT \
5213| ((in_oft) & IN_OFT_MSK)<< IN_OFT_SFT \
5214| ((out_fmt) & OUT_FMT_MSK)<<OUT_FMT_SFT \
5215| ((yuv_pkg_out) & YUV_PKG_OUT_MSK ) << YUV_PKG_OUT_SFT \
5216| ((rgb_888_out_fmt) & RGB888_FMT_MSK ) << RGB888_FMT_SFT \
5217| ((rgb_out_oft) & RGB_OUT_OFT_MSK ) << RGB_OUT_OFT_SFT); \
5218})
5219#define set_y_addr(y_addr) \
5220({ write_reg( (IPU_V_BASE + REG_Y_ADDR), y_addr); \
5221})
5222#define set_u_addr(u_addr) \
5223({ write_reg( (IPU_V_BASE + REG_U_ADDR), u_addr); \
5224})
5225
5226#define set_v_addr(v_addr) \
5227({ write_reg( (IPU_V_BASE + REG_V_ADDR), v_addr); \
5228})
5229
5230#define set_y_phy_t_addr(y_phy_t_addr) \
5231({ write_reg( (IPU_V_BASE + REG_Y_PHY_T_ADDR), y_phy_t_addr); \
5232})
5233
5234#define set_u_phy_t_addr(u_phy_t_addr) \
5235({ write_reg( (IPU_V_BASE + REG_U_PHY_T_ADDR), u_phy_t_addr); \
5236})
5237
5238#define set_v_phy_t_addr(v_phy_t_addr) \
5239({ write_reg( (IPU_V_BASE + REG_V_PHY_T_ADDR), v_phy_t_addr); \
5240})
5241
5242#define set_out_phy_t_addr(out_phy_t_addr) \
5243({ write_reg( (IPU_V_BASE + REG_OUT_PHY_T_ADDR), out_phy_t_addr); \
5244})
5245
5246#define set_inframe_gsize(width, height, y_stride, u_stride, v_stride) \
5247({ write_reg( (IPU_V_BASE + REG_IN_FM_GS), ((width) & IN_FM_W_MSK)<<IN_FM_W_SFT \
5248| ((height) & IN_FM_H_MSK)<<IN_FM_H_SFT); \
5249 write_reg( (IPU_V_BASE + REG_Y_STRIDE), ((y_stride) & Y_S_MSK)<<Y_S_SFT); \
5250 write_reg( (IPU_V_BASE + REG_UV_STRIDE), ((u_stride) & U_S_MSK)<<U_S_SFT \
5251| ((v_stride) & V_S_MSK)<<V_S_SFT); \
5252})
5253#define set_out_addr(out_addr) \
5254({ write_reg( (IPU_V_BASE + REG_OUT_ADDR), out_addr); \
5255})
5256#define set_outframe_gsize(width, height, o_stride) \
5257({ write_reg( (IPU_V_BASE + REG_OUT_GS), ((width) & OUT_FM_W_MSK)<<OUT_FM_W_SFT \
5258| ((height) & OUT_FM_H_MSK)<<OUT_FM_H_SFT); \
5259 write_reg( (IPU_V_BASE + REG_OUT_STRIDE), ((o_stride) & OUT_S_MSK)<<OUT_S_SFT); \
5260})
5261#define set_rsz_lut_end(h_end, v_end) \
5262({ write_reg( (IPU_V_BASE + REG_RSZ_COEF_INDEX), ((h_end) & HE_IDX_MSK)<<HE_IDX_SFT \
5263| ((v_end) & VE_IDX_MSK)<<VE_IDX_SFT); \
5264})
5265#define set_csc_c0(c0_coeff) \
5266({ write_reg( (IPU_V_BASE + REG_CSC_CO_COEF), ((c0_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \
5267})
5268#define set_csc_c1(c1_coeff) \
5269({ write_reg( (IPU_V_BASE + REG_CSC_C1_COEF), ((c1_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \
5270})
5271#define set_csc_c2(c2_coeff) \
5272({ write_reg( (IPU_V_BASE + REG_CSC_C2_COEF), ((c2_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \
5273})
5274#define set_csc_c3(c3_coeff) \
5275({ write_reg( (IPU_V_BASE + REG_CSC_C3_COEF), ((c3_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \
5276})
5277#define set_csc_c4(c4_coeff) \
5278({ write_reg( (IPU_V_BASE + REG_CSC_C4_COEF), ((c4_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \
5279})
5280#define set_hrsz_lut_coef(coef, in_n, out_n) \
5281({ write_reg( (IPU_V_BASE + HRSZ_LUT_BASE ), ((coef) & W_COEF_MSK)<<W_COEF_SFT \
5282| ((in_n) & IN_N_MSK)<<IN_N_SFT | ((out_n) & OUT_N_MSK)<<OUT_N_SFT); \
5283})
5284#define set_vrsz_lut_coef(coef, in_n, out_n) \
5285({ write_reg( (IPU_V_BASE + VRSZ_LUT_BASE), ((coef) & W_COEF_MSK)<<W_COEF_SFT \
5286| ((in_n) & IN_N_MSK)<<IN_N_SFT | ((out_n) & OUT_N_MSK)<<OUT_N_SFT); \
5287})
5288
5289#define set_primary_ctrl(vrsz_en, hrsz_en,csc_en, irq_en) \
5290({ write_reg( (IPU_V_BASE + REG_CTRL), ((irq_en) & FM_IRQ_EN_MSK)<<FM_IRQ_EN_SFT \
5291| ((vrsz_en) & VRSZ_EN_MSK)<<VRSZ_EN_SFT \
5292| ((hrsz_en) & HRSZ_EN_MSK)<<HRSZ_EN_SFT \
5293| ((csc_en) & CSC_EN_MSK)<<CSC_EN_SFT \
5294| (read_reg(IPU_V_BASE, REG_CTRL)) \
5295& ~(CSC_EN_MSK<<CSC_EN_SFT | FM_IRQ_EN_MSK<<FM_IRQ_EN_SFT | VRSZ_EN_MSK<<VRSZ_EN_SFT | HRSZ_EN_MSK<<HRSZ_EN_SFT ) ); \
5296})
5297
5298#define set_source_ctrl(pkg_sel, spage_sel) \
5299({ write_reg( (IPU_V_BASE + REG_CTRL), ((pkg_sel) & PKG_SEL_MSK )<< PKG_SEL_SFT \
5300| ((spage_sel) & SPAGE_MAP_MSK )<< SPAGE_MAP_SFT \
5301| (read_reg(IPU_V_BASE, REG_CTRL)) \
5302& ~(SPAGE_MAP_MSK << SPAGE_MAP_SFT | PKG_SEL_MSK << PKG_SEL_SFT ) ) ; \
5303})
5304
5305#define set_out_ctrl(lcdc_sel, dpage_sel, disp_sel) \
5306({ write_reg( (IPU_V_BASE + REG_CTRL), ((lcdc_sel) & LCDC_SEL_MSK )<< LCDC_SEL_SFT \
5307| ((dpage_sel) & DPAGE_SEL_MSK )<< DPAGE_SEL_SFT \
5308| ((disp_sel) & DISP_SEL_MSK )<< DISP_SEL_SFT \
5309| (read_reg(IPU_V_BASE, REG_CTRL)) \
5310& ~(LCDC_SEL_MSK<< LCDC_SEL_SFT | DPAGE_SEL_MSK << DPAGE_SEL_SFT | DISP_SEL_MSK << DISP_SEL_SFT ) ); \
5311})
5312
5313#define set_scale_ctrl(v_scal, h_scal) \
5314({ write_reg( (IPU_V_BASE + REG_CTRL), ((v_scal) & V_SCALE_MSK)<<V_SCALE_SFT \
5315| ((h_scal) & H_SCALE_MSK)<<H_SCALE_SFT \
5316| (read_reg(IPU_V_BASE, REG_CTRL)) & ~(V_SCALE_MSK<<V_SCALE_SFT | H_SCALE_MSK<<H_SCALE_SFT ) ); \
5317})
5318
5319#define set_csc_ofset_para(chrom_oft, luma_oft) \
5320({ write_reg( (IPU_V_BASE + REG_CSC_OFSET_PARA ), ((chrom_oft) & CHROM_OF_MSK ) << CHROM_OF_SFT \
5321| ((luma_oft) & LUMA_OF_MSK ) << LUMA_OF_SFT ) ; \
5322})
5323
5324#define sw_reset_ipu() \
5325({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) \
5326| IPU_RST_MSK<<IPU_RST_SFT); \
5327})
5328#define enable_ipu() \
5329({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) | 0x1); \
5330})
5331#define disable_ipu() \
5332({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) & ~0x1); \
5333})
5334#define run_ipu() \
5335({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) | 0x2); \
5336})
5337#define stop_ipu() \
5338({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) & ~0x2); \
5339})
5340
5341#define polling_end_flag() \
5342({ (read_reg(IPU_V_BASE, REG_STATUS)) & 0x01; \
5343})
5344
5345#define start_vlut_coef_write() \
5346({ write_reg( (IPU_V_BASE + VRSZ_LUT_BASE), ( 0x1<<12 ) ); \
5347})
5348
5349#define start_hlut_coef_write() \
5350({ write_reg( (IPU_V_BASE + HRSZ_LUT_BASE), ( 0x01<<12 ) ); \
5351})
5352
5353#define clear_end_flag() \
5354({ write_reg( (IPU_V_BASE + REG_STATUS), 0); \
5355})
5356#endif /* #if 0 */
5357
5358#endif /* __MIPS_ASSEMBLER */
5359
5360#define LCD_BASE 0xB3050000
5361#define SLCD_BASE 0xB3050000
5362
5363/*************************************************************************
5364 * SLCD (Smart LCD Controller)
5365 *************************************************************************/
5366
5367#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
5368#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
5369#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
5370#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
5371
5372#define REG_SLCD_CFG REG32(SLCD_CFG)
5373#define REG_SLCD_CTRL REG8(SLCD_CTRL)
5374#define REG_SLCD_STATE REG8(SLCD_STATE)
5375#define REG_SLCD_DATA REG32(SLCD_DATA)
5376
5377/* SLCD Configure Register */
5378#define SLCD_CFG_DWIDTH_BIT 10
5379#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
5380 #define SLCD_CFG_DWIDTH_18BIT (0 << SLCD_CFG_DWIDTH_BIT)
5381 #define SLCD_CFG_DWIDTH_16BIT (1 << SLCD_CFG_DWIDTH_BIT)
5382 #define SLCD_CFG_DWIDTH_8BIT_x3 (2 << SLCD_CFG_DWIDTH_BIT)
5383 #define SLCD_CFG_DWIDTH_8BIT_x2 (3 << SLCD_CFG_DWIDTH_BIT)
5384 #define SLCD_CFG_DWIDTH_8BIT_x1 (4 << SLCD_CFG_DWIDTH_BIT)
5385 #define SLCD_CFG_DWIDTH_24BIT (5 << SLCD_CFG_DWIDTH_BIT)
5386 #define SLCD_CFG_DWIDTH_9BIT_x2 (7 << SLCD_CFG_DWIDTH_BIT)
5387#define SLCD_CFG_CWIDTH_BIT (8)
5388#define SLCD_CFG_CWIDTH_MASK (0x3 << SLCD_CFG_CWIDTH_BIT)
5389#define SLCD_CFG_CWIDTH_16BIT (0 << SLCD_CFG_CWIDTH_BIT)
5390#define SLCD_CFG_CWIDTH_8BIT (1 << SLCD_CFG_CWIDTH_BIT)
5391#define SLCD_CFG_CWIDTH_18BIT (2 << SLCD_CFG_CWIDTH_BIT)
5392#define SLCD_CFG_CWIDTH_24BIT (3 << SLCD_CFG_CWIDTH_BIT)
5393#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
5394#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
5395#define SLCD_CFG_RS_CMD_LOW (0 << 3)
5396#define SLCD_CFG_RS_CMD_HIGH (1 << 3)
5397#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1)
5398#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1)
5399#define SLCD_CFG_TYPE_PARALLEL (0 << 0)
5400#define SLCD_CFG_TYPE_SERIAL (1 << 0)
5401
5402/* SLCD Control Register */
5403#define SLCD_CTRL_DMA_MODE (1 << 2)
5404#define SLCD_CTRL_DMA_START (1 << 1)
5405#define SLCD_CTRL_DMA_EN (1 << 0)
5406
5407/* SLCD Status Register */
5408#define SLCD_STATE_BUSY (1 << 0)
5409
5410/* SLCD Data Register */
5411#define SLCD_DATA_RS_DATA (0 << 31)
5412#define SLCD_DATA_RS_COMMAND (1 << 31)
5413
5414/*************************************************************************
5415 * LCD (LCD Controller)
5416 *************************************************************************/
5417#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
5418#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
5419#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
5420
5421#define LCD_OSDC (LCD_BASE + 0x100) /* LCD OSD Configure Register */
5422#define LCD_OSDCTRL (LCD_BASE + 0x104) /* LCD OSD Control Register */
5423#define LCD_OSDS (LCD_BASE + 0x108) /* LCD OSD Status Register */
5424#define LCD_BGC (LCD_BASE + 0x10C) /* LCD Background Color Register */
5425#define LCD_KEY0 (LCD_BASE + 0x110) /* LCD Foreground Color Key Register 0 */
5426#define LCD_KEY1 (LCD_BASE + 0x114) /* LCD Foreground Color Key Register 1 */
5427#define LCD_ALPHA (LCD_BASE + 0x118) /* LCD ALPHA Register */
5428#define LCD_IPUR (LCD_BASE + 0x11C) /* LCD IPU Restart Register */
5429#define LCD_RGBC (LCD_BASE + 0x90) /* RGB Controll Register */
5430
5431#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
5432#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
5433#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
5434
5435#define LCD_XYP0 (LCD_BASE + 0x120) /* Foreground 0 XY Position Register */
5436#define LCD_XYP0_PART2 (LCD_BASE + 0x1F0) /* Foreground 0 PART2 XY Position Register */
5437#define LCD_XYP1 (LCD_BASE + 0x124) /* Foreground 1 XY Position Register */
5438#define LCD_SIZE0 (LCD_BASE + 0x128) /* Foreground 0 Size Register */
5439#define LCD_SIZE0_PART2 (LCD_BASE + 0x1F4) /*Foreground 0 PART2 Size Register */
5440#define LCD_SIZE1 (LCD_BASE + 0x12C) /* Foreground 1 Size Register */
5441
5442#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
5443#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
5444#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
5445#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
5446#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
5447#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
5448#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
5449#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
5450#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
5451#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
5452#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
5453
5454#define LCD_OFFS0 (LCD_BASE + 0x60) /* DMA Offsize Register 0 */
5455#define LCD_PW0 (LCD_BASE + 0x64) /* DMA Page Width Register 0 */
5456#define LCD_CNUM0 (LCD_BASE + 0x68) /* DMA Command Counter Register 0 */
5457#define LCD_DESSIZE0 (LCD_BASE + 0x6C) /* Foreground Size in Descriptor 0 Register*/
5458
5459#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
5460#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
5461#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
5462#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
5463#define LCD_OFFS1 (LCD_BASE + 0x70) /* DMA Offsize Register 1 */
5464#define LCD_PW1 (LCD_BASE + 0x74) /* DMA Page Width Register 1 */
5465#define LCD_CNUM1 (LCD_BASE + 0x78) /* DMA Command Counter Register 1 */
5466#define LCD_DESSIZE1 (LCD_BASE + 0x7C) /* Foreground Size in Descriptor 1 Register*/
5467
5468#define LCD_DA0_PART2 (LCD_BASE + 0x1C0) /* Descriptor Address Register PART2 */
5469#define LCD_SA0_PART2 (LCD_BASE + 0x1C4) /* Source Address Register PART2 */
5470#define LCD_FID0_PART2 (LCD_BASE + 0x1C8) /* Frame ID Register PART2 */
5471#define LCD_CMD0_PART2 (LCD_BASE + 0x1CC) /* DMA Command Register PART2 */
5472#define LCD_OFFS0_PART2 (LCD_BASE + 0x1E0) /* DMA Offsize Register PART2 */
5473#define LCD_PW0_PART2 (LCD_BASE + 0x1E4) /* DMA Command Counter Register PART2 */
5474#define LCD_CNUM0_PART2 (LCD_BASE + 0x1E8) /* Foreground Size in Descriptor PART2 Register */
5475#define LCD_DESSIZE0_PART2 (LCD_BASE + 0x1EC) /* */
5476#define LCD_PCFG (LCD_BASE + 0x2C0)
5477
5478#define REG_LCD_CFG REG32(LCD_CFG)
5479#define REG_LCD_CTRL REG32(LCD_CTRL)
5480#define REG_LCD_STATE REG32(LCD_STATE)
5481
5482#define REG_LCD_OSDC REG16(LCD_OSDC)
5483#define REG_LCD_OSDCTRL REG16(LCD_OSDCTRL)
5484#define REG_LCD_OSDS REG16(LCD_OSDS)
5485#define REG_LCD_BGC REG32(LCD_BGC)
5486#define REG_LCD_KEY0 REG32(LCD_KEY0)
5487#define REG_LCD_KEY1 REG32(LCD_KEY1)
5488#define REG_LCD_ALPHA REG8(LCD_ALPHA)
5489#define REG_LCD_IPUR REG32(LCD_IPUR)
5490
5491#define REG_LCD_VAT REG32(LCD_VAT)
5492#define REG_LCD_DAH REG32(LCD_DAH)
5493#define REG_LCD_DAV REG32(LCD_DAV)
5494
5495#define REG_LCD_XYP0 REG32(LCD_XYP0)
5496#define REG_LCD_XYP0_PART2 REG32(LCD_XYP0_PART2)
5497#define REG_LCD_XYP1 REG32(LCD_XYP1)
5498#define REG_LCD_SIZE0 REG32(LCD_SIZE0)
5499#define REG_LCD_SIZE0_PART2 REG32(LCD_SIZE0_PART2)
5500#define REG_LCD_SIZE1 REG32(LCD_SIZE1)
5501
5502#define REG_LCD_RGBC REG16(LCD_RGBC)
5503
5504#define REG_LCD_VSYNC REG32(LCD_VSYNC)
5505#define REG_LCD_HSYNC REG32(LCD_HSYNC)
5506#define REG_LCD_PS REG32(LCD_PS)
5507#define REG_LCD_CLS REG32(LCD_CLS)
5508#define REG_LCD_SPL REG32(LCD_SPL)
5509#define REG_LCD_REV REG32(LCD_REV)
5510#define REG_LCD_IID REG32(LCD_IID)
5511#define REG_LCD_DA0 REG32(LCD_DA0)
5512#define REG_LCD_SA0 REG32(LCD_SA0)
5513#define REG_LCD_FID0 REG32(LCD_FID0)
5514#define REG_LCD_CMD0 REG32(LCD_CMD0)
5515
5516#define REG_LCD_OFFS0 REG32(LCD_OFFS0)
5517#define REG_LCD_PW0 REG32(LCD_PW0)
5518#define REG_LCD_CNUM0 REG32(LCD_CNUM0)
5519#define REG_LCD_DESSIZE0 REG32(LCD_DESSIZE0)
5520
5521#define REG_LCD_DA0_PART2 REG32(LCD_DA0_PART2)
5522#define REG_LCD_SA0_PART2 REG32(LCD_SA0_PART2)
5523#define REG_LCD_FID0_PART2 REG32(LCD_FID0_PART2)
5524#define REG_LCD_CMD0_PART2 REG32(LCD_CMD0_PART2)
5525#define REG_LCD_OFFS0_PART2 REG32(LCD_OFFS0_PART2)
5526#define REG_LCD_PW0_PART2 REG32(LCD_PW0_PART2)
5527#define REG_LCD_CNUM0_PART2 REG32(LCD_CNUM0_PART2)
5528#define REG_LCD_DESSIZE0_PART2 REG32(LCD_DESSIZE0_PART2)
5529
5530#define REG_LCD_DA1 REG32(LCD_DA1)
5531#define REG_LCD_SA1 REG32(LCD_SA1)
5532#define REG_LCD_FID1 REG32(LCD_FID1)
5533#define REG_LCD_CMD1 REG32(LCD_CMD1)
5534#define REG_LCD_OFFS1 REG32(LCD_OFFS1)
5535#define REG_LCD_PW1 REG32(LCD_PW1)
5536#define REG_LCD_CNUM1 REG32(LCD_CNUM1)
5537#define REG_LCD_DESSIZE1 REG32(LCD_DESSIZE1)
5538#define REG_LCD_PCFG REG32(LCD_PCFG)
5539
5540/* LCD Configure Register */
5541#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
5542#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT)
5543 #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT)
5544 #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT)
5545#define LCD_CFG_TVEPEH (1 << 30) /* TVE PAL enable extra halfline signal */
5546//#define LCD_CFG_FUHOLD (1 << 29) /* hold pixel clock when outFIFO underrun */
5547#define LCD_CFG_NEWDES (1 << 28) /* use new descripter. old: 4words, new:8words */
5548#define LCD_CFG_PALBP (1 << 27) /* bypass data format and alpha blending */
5549#define LCD_CFG_TVEN (1 << 26) /* indicate the terminal is lcd or tv */
5550#define LCD_CFG_RECOVER (1 << 25) /* Auto recover when output fifo underrun */
5551#define LCD_CFG_DITHER (1 << 24) /* Dither function */
5552#define LCD_CFG_PSM (1 << 23) /* PS signal mode */
5553#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */
5554#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */
5555#define LCD_CFG_REVM (1 << 20) /* REV signal mode */
5556#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */
5557#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */
5558#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */
5559#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */
5560#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */
5561#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */
5562#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */
5563#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */
5564#define LCD_CFG_HSP (1 << 11) /* HSYNC polarity:0-active high,1-active low */
5565#define LCD_CFG_PCP (1 << 10) /* PCLK polarity:0-rising,1-falling */
5566#define LCD_CFG_DEP (1 << 9) /* DE polarity:0-active high,1-active low */
5567#define LCD_CFG_VSP (1 << 8) /* VSYNC polarity:0-rising,1-falling */
5568#define LCD_CFG_MODE_TFT_18BIT (1 << 7) /* 18bit TFT */
5569#define LCD_CFG_MODE_TFT_16BIT (0 << 7) /* 16bit TFT */
5570#define LCD_CFG_MODE_TFT_24BIT (1 << 6) /* 24bit TFT */
5571#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */
5572#define LCD_CFG_PDW_MASK (0x3 << LCD_CFG_PDW_BIT)
5573#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
5574 #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
5575 #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
5576 #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
5577#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */
5578#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT)
5579 #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
5580 #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT)
5581 #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT)
5582 #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT)
5583 #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
5584 #define LCD_CFG_MODE_INTER_CCIR656 (6 << LCD_CFG_MODE_BIT)
5585 #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT)
5586 #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT)
5587 #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT)
5588 #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT)
5589 #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
5590 #define LCD_CFG_MODE_LCM (13 << LCD_CFG_MODE_BIT)
5591 #define LCD_CFG_MODE_SLCD LCD_CFG_MODE_LCM
5592
5593/* LCD Control Register */
5594#define LCD_CTRL_PINMD (1 << 31) /* This register set Pin distribution in 16-bit parallel mode
5595 0: 16-bit data correspond with LCD_D[15:0]
5596 1: 16-bit data correspond with LCD_D[17:10], LCD_D[8:1] */
5597#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
5598#define LCD_CTRL_BST_MASK (0x7 << LCD_CTRL_BST_BIT)
5599 #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
5600 #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
5601 #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
5602 #define LCD_CTRL_BST_32 (3 << LCD_CTRL_BST_BIT) /* 32-word */
5603 #define LCD_CTRL_BST_C16 (5 << LCD_CTRL_BST_BIT) /* 32-word */
5604 #define LCD_CTRL_BST_64 (4 << LCD_CTRL_BST_BIT) /* 32-word */
5605#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode(foreground 0 in OSD mode) */
5606#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode(foreground 0 in OSD mode) */
5607#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
5608#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
5609#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
5610 #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
5611 #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
5612 #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
5613#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */
5614#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
5615//#define LCD_CTRL_VGA (1 << 15) /* VGA interface enable */
5616#define LCD_CTRL_DACTE (1 << 14) /* DAC loop back test */
5617#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
5618#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
5619#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
5620#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
5621#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
5622#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
5623#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
5624#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
5625#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
5626#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
5627#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
5628#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
5629#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
5630 #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
5631 #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
5632 #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
5633 #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
5634 #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
5635 #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
5636 #define LCD_CTRL_BPP_CMPS_24 (6 << LCD_CTRL_BPP_BIT) /* 24 compress bpp */
5637 #define LCD_CTRL_BPP_30 (7 << LCD_CTRL_BPP_BIT) /* 30 bpp */
5638
5639/* LCD Status Register */
5640#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */
5641#define LCD_STATE_EOF (1 << 5) /* EOF Flag */
5642#define LCD_STATE_SOF (1 << 4) /* SOF Flag */
5643#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */
5644#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */
5645#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */
5646#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */
5647
5648/* OSD Configure Register */
5649#define LCD_OSDC_SOFM1 (1 << 15) /* Start of frame interrupt mask for foreground 1 */
5650#define LCD_OSDC_EOFM1 (1 << 14) /* End of frame interrupt mask for foreground 1 */
5651#define LCD_OSDC_OSDIV (1 << 12)
5652#define LCD_OSDC_SOFM0 (1 << 11) /* Start of frame interrupt mask for foreground 0 */
5653#define LCD_OSDC_EOFM0 (1 << 10) /* End of frame interrupt mask for foreground 0 */
5654#if 0
5655#define LCD_OSDC_ENDM (1 << 9) /* End of frame interrupt mask for panel. */
5656#define LCD_OSDC_F0DIVMD (1 << 8) /* Divide Foreground 0 into 2 parts.
5657 * 0: Foreground 0 only has one part. */
5658#define LCD_OSDC_F0P1EN (1 << 7) /* 1: Foreground 0 PART1 is enabled.
5659 * 0: Foreground 0 PART1 is disabled. */
5660#define LCD_OSDC_F0P2MD (1 << 6) /* 1: PART 1&2 same level and same heighth
5661 * 0: PART 1&2 have no same line */
5662#define LCD_OSDC_F0P2EN (1 << 5) /* 1: Foreground 0 PART2 is enabled.
5663 * 0: Foreground 0 PART2 is disabled.*/
5664#endif
5665#define LCD_OSDC_F1EN (1 << 4) /* enable foreground 1 */
5666#define LCD_OSDC_F0EN (1 << 3) /* enable foreground 0 */
5667#define LCD_OSDC_ALPHAEN (1 << 2) /* enable alpha blending */
5668#define LCD_OSDC_ALPHAMD (1 << 1) /* alpha blending mode */
5669#define LCD_OSDC_OSDEN (1 << 0) /* OSD mode enable */
5670
5671/* OSD Controll Register */
5672#define LCD_OSDCTRL_IPU (1 << 15) /* input data from IPU */
5673#define LCD_OSDCTRL_RGB565 (0 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */
5674#define LCD_OSDCTRL_RGB555 (1 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */
5675#define LCD_OSDCTRL_CHANGES (1 << 3) /* Change size flag */
5676#define LCD_OSDCTRL_OSDBPP_BIT 0 /* Bits Per Pixel of OSD Channel 1 */
5677#define LCD_OSDCTRL_OSDBPP_MASK (0x7<<LCD_OSDCTRL_OSDBPP_BIT) /* Bits Per Pixel of OSD Channel 1's MASK */
5678 #define LCD_OSDCTRL_OSDBPP_16 (4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/
5679 #define LCD_OSDCTRL_OSDBPP_15_16 (4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/
5680 #define LCD_OSDCTRL_OSDBPP_18_24 (5 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 18,24 bit*/
5681 #define LCD_OSDCTRL_OSDBPP_CMPS_24 (6 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB compress 24 bit*/
5682 #define LCD_OSDCTRL_OSDBPP_30 (7 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 30 bit*/
5683
5684/* OSD State Register */
5685#define LCD_OSDS_SOF1 (1 << 15) /* Start of frame flag for foreground 1 */
5686#define LCD_OSDS_EOF1 (1 << 14) /* End of frame flag for foreground 1 */
5687#define LCD_OSDS_SOF0 (1 << 11) /* Start of frame flag for foreground 0 */
5688#define LCD_OSDS_EOF0 (1 << 10) /* End of frame flag for foreground 0 */
5689#define LCD_OSDS_READY (1 << 0) /* Read for accept the change */
5690
5691/* Background Color Register */
5692#define LCD_BGC_RED_OFFSET (1 << 16) /* Red color offset */
5693#define LCD_BGC_RED_MASK (0xFF<<LCD_BGC_RED_OFFSET)
5694#define LCD_BGC_GREEN_OFFSET (1 << 8) /* Green color offset */
5695#define LCD_BGC_GREEN_MASK (0xFF<<LCD_BGC_GREEN_OFFSET)
5696#define LCD_BGC_BLUE_OFFSET (1 << 0) /* Blue color offset */
5697#define LCD_BGC_BLUE_MASK (0xFF<<LCD_BGC_BLUE_OFFSET)
5698
5699/* Foreground Color Key Register 0,1(foreground 0, foreground 1) */
5700#define LCD_KEY_KEYEN (1 << 31) /* enable color key */
5701#define LCD_KEY_KEYMD (1 << 30) /* color key mode */
5702#define LCD_KEY_RED_OFFSET 16 /* Red color offset */
5703#define LCD_KEY_RED_MASK (0xFF<<LCD_KEY_RED_OFFSET)
5704#define LCD_KEY_GREEN_OFFSET 8 /* Green color offset */
5705#define LCD_KEY_GREEN_MASK (0xFF<<LCD_KEY_GREEN_OFFSET)
5706#define LCD_KEY_BLUE_OFFSET 0 /* Blue color offset */
5707#define LCD_KEY_BLUE_MASK (0xFF<<LCD_KEY_BLUE_OFFSET)
5708#define LCD_KEY_MASK (LCD_KEY_RED_MASK|LCD_KEY_GREEN_MASK|LCD_KEY_BLUE_MASK)
5709
5710/* IPU Restart Register */
5711#define LCD_IPUR_IPUREN (1 << 31) /* IPU restart function enable*/
5712#define LCD_IPUR_IPURMASK (0xFFFFFF) /* IPU restart value mask*/
5713
5714/* RGB Control Register */
5715#define LCD_RGBC_RGBDM (1 << 15) /* enable RGB Dummy data */
5716#define LCD_RGBC_DMM (1 << 14) /* RGB Dummy mode */
5717#define LCD_RGBC_YCC (1 << 8) /* RGB to YCC */
5718#define LCD_RGBC_ODDRGB_BIT 4 /* odd line serial RGB data arrangement */
5719#define LCD_RGBC_ODDRGB_MASK (0x7<<LCD_RGBC_ODDRGB_BIT)
5720 #define LCD_RGBC_ODD_RGB 0
5721 #define LCD_RGBC_ODD_RBG 1
5722 #define LCD_RGBC_ODD_GRB 2
5723 #define LCD_RGBC_ODD_GBR 3
5724 #define LCD_RGBC_ODD_BRG 4
5725 #define LCD_RGBC_ODD_BGR 5
5726#define LCD_RGBC_EVENRGB_BIT 0 /* even line serial RGB data arrangement */
5727#define LCD_RGBC_EVENRGB_MASK (0x7<<LCD_RGBC_EVENRGB_BIT)
5728 #define LCD_RGBC_EVEN_RGB 0
5729 #define LCD_RGBC_EVEN_RBG 1
5730 #define LCD_RGBC_EVEN_GRB 2
5731 #define LCD_RGBC_EVEN_GBR 3
5732 #define LCD_RGBC_EVEN_BRG 4
5733 #define LCD_RGBC_EVEN_BGR 5
5734
5735/* Vertical Synchronize Register */
5736#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */
5737#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
5738#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */
5739#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
5740
5741/* Horizontal Synchronize Register */
5742#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */
5743#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
5744#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */
5745#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
5746
5747/* Virtual Area Setting Register */
5748#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */
5749#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
5750#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */
5751#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
5752
5753/* Display Area Horizontal Start/End Point Register */
5754#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */
5755#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
5756#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */
5757#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
5758
5759/* Display Area Vertical Start/End Point Register */
5760#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */
5761#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
5762#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */
5763#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
5764
5765/* Foreground XY Position Register */
5766#define LCD_XYP_YPOS_BIT 16 /* Y position bit of foreground 0 or 1 */
5767#define LCD_XYP_YPOS_MASK (0xffff << LCD_XYP_YPOS_BIT)
5768#define LCD_XYP_XPOS_BIT 0 /* X position bit of foreground 0 or 1 */
5769#define LCD_XYP_XPOS_MASK (0xffff << LCD_XYP_XPOS_BIT)
5770
5771/* PS Signal Setting */
5772#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */
5773#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT)
5774#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */
5775#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT)
5776
5777/* CLS Signal Setting */
5778#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */
5779#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT)
5780#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */
5781#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT)
5782
5783/* SPL Signal Setting */
5784#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */
5785#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT)
5786#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */
5787#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT)
5788
5789/* REV Signal Setting */
5790#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */
5791#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT)
5792
5793/* DMA Command Register */
5794#define LCD_CMD_SOFINT (1 << 31)
5795#define LCD_CMD_EOFINT (1 << 30)
5796#define LCD_CMD_CMD (1 << 29) /* indicate command in slcd mode */
5797#define LCD_CMD_PAL (1 << 28)
5798#define LCD_CMD_UNCOMP_EN (1 << 27)
5799#define LCD_CMD_UNCOMPRESS_WITHOUT_ALPHA (1 << 26)
5800#define LCD_CMD_LEN_BIT 0
5801#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
5802
5803/* DMA Offsize Register 0,1 */
5804
5805/* DMA Page Width Register 0,1 */
5806
5807/* DMA Command Counter Register 0,1 */
5808
5809/* Foreground 0,1 Size Register */
5810#define LCD_DESSIZE_HEIGHT_BIT 16 /* height of foreground 1 */
5811#define LCD_DESSIZE_HEIGHT_MASK (0xffff << LCD_DESSIZE_HEIGHT_BIT)
5812#define LCD_DESSIZE_WIDTH_BIT 0 /* width of foreground 1 */
5813#define LCD_DESSIZE_WIDTH_MASK (0xffff << LCD_DESSIZE_WIDTH_BIT)
5814
5815/* Priority level threshold configure Register */
5816#define LCD_PCFG_LCD_PRI_MD (1 << 31)
5817#define LCD_PCFG_HP_BST_BIT 28
5818#define LCD_PCFG_HP_BST_MASK (0x7 << LCD_PCFG_HP_BST_BIT)
5819#define LCD_PCFG_PCFG2_BIT 8
5820#define LCD_PCFG_PCFG2_MASK (0xf << LCD_PCFG_PCFG2_BIT)
5821#define LCD_PCFG_PCFG1_BIT 4
5822#define LCD_PCFG_PCFG1_MASK (0xf << LCD_PCFG_PCFG1_BIT)
5823#define LCD_PCFG_PCFG0_BIT 0
5824#define LCD_PCFG_PCFG0_MASK (0xf << LCD_PCFG_PCFG0_BIT)
5825
5826#ifndef __MIPS_ASSEMBLER
5827
5828/*************************************************************************
5829 * SLCD (Smart LCD Controller)
5830 *************************************************************************/
5831#define __slcd_set_data_18bit() \
5832 ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_18BIT )
5833#define __slcd_set_data_16bit() \
5834 ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_16BIT )
5835#define __slcd_set_data_8bit_x3() \
5836 ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_8BIT_x3 )
5837#define __slcd_set_data_8bit_x2() \
5838 ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_8BIT_x2 )
5839#define __slcd_set_data_8bit_x1() \
5840 ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_8BIT_x1 )
5841#define __slcd_set_data_24bit() \
5842 ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_24BIT )
5843#define __slcd_set_data_9bit_x2() \
5844 ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_9BIT_x2 )
5845
5846#define __slcd_set_cmd_16bit() \
5847 ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_16BIT )
5848#define __slcd_set_cmd_8bit() \
5849 ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_8BIT )
5850#define __slcd_set_cmd_18bit() \
5851 ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_18BIT )
5852#define __slcd_set_cmd_24bit() \
5853 ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_24BIT )
5854
5855#define __slcd_set_cs_high() ( REG_SLCD_CFG |= SLCD_CFG_CS_ACTIVE_HIGH )
5856#define __slcd_set_cs_low() ( REG_SLCD_CFG &= ~SLCD_CFG_CS_ACTIVE_HIGH )
5857
5858#define __slcd_set_rs_high() ( REG_SLCD_CFG |= SLCD_CFG_RS_CMD_HIGH )
5859#define __slcd_set_rs_low() ( REG_SLCD_CFG &= ~SLCD_CFG_RS_CMD_HIGH )
5860
5861#define __slcd_set_clk_falling() ( REG_SLCD_CFG &= ~SLCD_CFG_CLK_ACTIVE_RISING )
5862#define __slcd_set_clk_rising() ( REG_SLCD_CFG |= SLCD_CFG_CLK_ACTIVE_RISING )
5863
5864#define __slcd_set_parallel_type() ( REG_SLCD_CFG &= ~SLCD_CFG_TYPE_SERIAL )
5865#define __slcd_set_serial_type() ( REG_SLCD_CFG |= SLCD_CFG_TYPE_SERIAL )
5866
5867/* SLCD Control Register */
5868#define __slcd_enable_dma() ( REG_SLCD_CTRL |= SLCD_CTRL_DMA_EN )
5869#define __slcd_disable_dma() ( REG_SLCD_CTRL &= ~SLCD_CTRL_DMA_EN )
5870
5871/* SLCD Status Register */
5872#define __slcd_is_busy() ( REG_SLCD_STATE & SLCD_STATE_BUSY )
5873
5874/* SLCD Data Register */
5875#define __slcd_set_cmd_rs() ( REG_SLCD_DATA |= SLCD_DATA_RS_COMMAND)
5876#define __slcd_set_data_rs() ( REG_SLCD_DATA &= ~SLCD_DATA_RS_COMMAND)
5877
5878/***************************************************************************
5879 * LCD
5880 ***************************************************************************/
5881#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= ( LCD_CFG_LCDPIN_SLCD | LCD_CFG_MODE_SLCD))
5882#define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~( LCD_CFG_LCDPIN_SLCD | LCD_CFG_MODE_SLCD))
5883
5884#define __lcd_enable_tvepeh() ( REG_LCD_CFG |= LCD_CFG_TVEPEH )
5885#define __lcd_disable_tvepeh() ( REG_LCD_CFG &= ~LCD_CFG_TVEPEH )
5886
5887#define __lcd_enable_fuhold() ( REG_LCD_CFG |= LCD_CFG_FUHOLD )
5888#define __lcd_disable_fuhold() ( REG_LCD_CFG &= ~LCD_CFG_FUHOLD )
5889
5890#define __lcd_des_8word() ( REG_LCD_CFG |= LCD_CFG_NEWDES )
5891#define __lcd_des_4word() ( REG_LCD_CFG &= ~LCD_CFG_NEWDES )
5892
5893#define __lcd_enable_bypass_pal() ( REG_LCD_CFG |= LCD_CFG_PALBP )
5894#define __lcd_disable_bypass_pal() ( REG_LCD_CFG &= ~LCD_CFG_PALBP )
5895
5896#define __lcd_set_lcdpnl_term() ( REG_LCD_CFG |= LCD_CFG_TVEN )
5897#define __lcd_set_tv_term() ( REG_LCD_CFG &= ~LCD_CFG_TVEN )
5898
5899#define __lcd_enable_auto_recover() ( REG_LCD_CFG |= LCD_CFG_RECOVER )
5900#define __lcd_disable_auto_recover() ( REG_LCD_CFG &= ~LCD_CFG_RECOVER )
5901
5902#define __lcd_enable_dither() ( REG_LCD_CFG |= LCD_CFG_DITHER )
5903#define __lcd_disable_dither() ( REG_LCD_CFG &= ~LCD_CFG_DITHER )
5904
5905#define __lcd_disable_ps_mode() ( REG_LCD_CFG |= LCD_CFG_PSM )
5906#define __lcd_enable_ps_mode() ( REG_LCD_CFG &= ~LCD_CFG_PSM )
5907
5908#define __lcd_disable_cls_mode() ( REG_LCD_CFG |= LCD_CFG_CLSM )
5909#define __lcd_enable_cls_mode() ( REG_LCD_CFG &= ~LCD_CFG_CLSM )
5910
5911#define __lcd_disable_spl_mode() ( REG_LCD_CFG |= LCD_CFG_SPLM )
5912#define __lcd_enable_spl_mode() ( REG_LCD_CFG &= ~LCD_CFG_SPLM )
5913
5914#define __lcd_disable_rev_mode() ( REG_LCD_CFG |= LCD_CFG_REVM )
5915#define __lcd_enable_rev_mode() ( REG_LCD_CFG &= ~LCD_CFG_REVM )
5916
5917#define __lcd_disable_hsync_mode() ( REG_LCD_CFG |= LCD_CFG_HSYNM )
5918#define __lcd_enable_hsync_mode() ( REG_LCD_CFG &= ~LCD_CFG_HSYNM )
5919
5920#define __lcd_disable_pclk_mode() ( REG_LCD_CFG |= LCD_CFG_PCLKM )
5921#define __lcd_enable_pclk_mode() ( REG_LCD_CFG &= ~LCD_CFG_PCLKM )
5922
5923#define __lcd_normal_outdata() ( REG_LCD_CFG &= ~LCD_CFG_INVDAT )
5924#define __lcd_inverse_outdata() ( REG_LCD_CFG |= LCD_CFG_INVDAT )
5925
5926#define __lcd_sync_input() ( REG_LCD_CFG |= LCD_CFG_SYNDIR_IN )
5927#define __lcd_sync_output() ( REG_LCD_CFG &= ~LCD_CFG_SYNDIR_IN )
5928
5929#define __lcd_hsync_active_high() ( REG_LCD_CFG &= ~LCD_CFG_HSP )
5930#define __lcd_hsync_active_low() ( REG_LCD_CFG |= LCD_CFG_HSP )
5931
5932#define __lcd_pclk_rising() ( REG_LCD_CFG &= ~LCD_CFG_PCP )
5933#define __lcd_pclk_falling() ( REG_LCD_CFG |= LCD_CFG_PCP )
5934
5935#define __lcd_de_active_high() ( REG_LCD_CFG &= ~LCD_CFG_DEP )
5936#define __lcd_de_active_low() ( REG_LCD_CFG |= LCD_CFG_DEP )
5937
5938#define __lcd_vsync_rising() ( REG_LCD_CFG &= ~LCD_CFG_VSP )
5939#define __lcd_vsync_falling() ( REG_LCD_CFG |= LCD_CFG_VSP )
5940
5941#define __lcd_set_16_tftpnl() \
5942 ( REG_LCD_CFG = (REG_LCD_CFG & ~LCD_CFG_MODE_TFT_MASK) | LCD_CFG_MODE_TFT_16BIT )
5943
5944#define __lcd_set_18_tftpnl() \
5945 ( REG_LCD_CFG = (REG_LCD_CFG & ~LCD_CFG_MODE_TFT_MASK) | LCD_CFG_MODE_TFT_18BIT )
5946
5947#define __lcd_set_24_tftpnl() ( REG_LCD_CFG |= LCD_CFG_MODE_TFT_24BIT )
5948
5949/*
5950 * n=1,2,4,8 for single mono-STN
5951 * n=4,8 for dual mono-STN
5952 */
5953#define __lcd_set_panel_datawidth(n) \
5954do { \
5955 REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \
5956 REG_LCD_CFG |= LCD_CFG_PDW_n##; \
5957} while (0)
5958
5959/* m = LCD_CFG_MODE_GENERUIC_TFT_xxx */
5960#define __lcd_set_panel_mode(m) \
5961do { \
5962 REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \
5963 REG_LCD_CFG |= (m); \
5964} while(0)
5965
5966/* n=4,8,16 */
5967#define __lcd_set_burst_length(n) \
5968do { \
5969 REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \
5970 REG_LCD_CTRL |= LCD_CTRL_BST_n##; \
5971} while (0)
5972
5973#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
5974#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
5975
5976#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
5977#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
5978
5979/* n=2,4,16 */
5980#define __lcd_set_stn_frc(n) \
5981do { \
5982 REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \
5983 REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \
5984} while (0)
5985
5986#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
5987#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
5988
5989#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
5990#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
5991
5992#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
5993#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
5994
5995#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
5996#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
5997
5998#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
5999#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
6000
6001#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
6002#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
6003
6004#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM )
6005#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
6006
6007#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
6008#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
6009
6010#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
6011#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
6012
6013#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS )
6014#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
6015
6016#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA )
6017#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
6018
6019/* n=1,2,4,8,16 */
6020#define __lcd_set_bpp(n) \
6021 ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
6022
6023/* LCD status register indication */
6024
6025#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD )
6026#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD )
6027#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 )
6028#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 )
6029#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU )
6030#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF )
6031#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF )
6032
6033#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU )
6034#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF )
6035#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF )
6036
6037/* OSD functions */
6038#define __lcd_enable_osd() (REG_LCD_OSDC |= LCD_OSDC_OSDEN)
6039#define __lcd_enable_f0() (REG_LCD_OSDC |= LCD_OSDC_F0EN)
6040#define __lcd_enable_f1() (REG_LCD_OSDC |= LCD_OSDC_F1EN)
6041#define __lcd_enable_alpha() (REG_LCD_OSDC |= LCD_OSDC_ALPHAEN)
6042#define __lcd_enable_alphamd() (REG_LCD_OSDC |= LCD_OSDC_ALPHAMD)
6043
6044#define __lcd_disable_osd() (REG_LCD_OSDC &= ~LCD_OSDC_OSDEN)
6045#define __lcd_disable_f0() (REG_LCD_OSDC &= ~LCD_OSDC_F0EN)
6046#define __lcd_disable_f1() (REG_LCD_OSDC &= ~LCD_OSDC_F1EN)
6047#define __lcd_disable_alpha() (REG_LCD_OSDC &= ~LCD_OSDC_ALPHAEN)
6048#define __lcd_disable_alphamd() (REG_LCD_OSDC &= ~LCD_OSDC_ALPHAMD)
6049
6050/* OSD Controll Register */
6051#define __lcd_fg1_use_ipu() (REG_LCD_OSDCTRL |= LCD_OSDCTRL_IPU)
6052#define __lcd_fg1_use_dma_chan1() (REG_LCD_OSDCTRL &= ~LCD_OSDCTRL_IPU)
6053#define __lcd_fg1_unuse_ipu() __lcd_fg1_use_dma_chan1()
6054#define __lcd_osd_rgb555_mode() ( REG_LCD_OSDCTRL |= LCD_OSDCTRL_RGB555 )
6055#define __lcd_osd_rgb565_mode() ( REG_LCD_OSDCTRL &= ~LCD_OSDCTRL_RGB555 )
6056#define __lcd_osd_change_size() ( REG_LCD_OSDCTRL |= LCD_OSDCTRL_CHANGES )
6057#define __lcd_osd_bpp_15_16() \
6058 ( REG_LCD_OSDCTRL = (REG_LCD_OSDCTRL & ~LCD_OSDCTRL_OSDBPP_MASK) | LCD_OSDCTRL_OSDBPP_15_16 )
6059#define __lcd_osd_bpp_18_24() \
6060 ( REG_LCD_OSDCTRL = (REG_LCD_OSDCTRL & ~LCD_OSDCTRL_OSDBPP_MASK) | LCD_OSDCTRL_OSDBPP_18_24 )
6061
6062/* OSD State Register */
6063#define __lcd_start_of_fg1() ( REG_LCD_STATE & LCD_OSDS_SOF1 )
6064#define __lcd_end_of_fg1() ( REG_LCD_STATE & LCD_OSDS_EOF1 )
6065#define __lcd_start_of_fg0() ( REG_LCD_STATE & LCD_OSDS_SOF0 )
6066#define __lcd_end_of_fg0() ( REG_LCD_STATE & LCD_OSDS_EOF0 )
6067#define __lcd_change_is_rdy() ( REG_LCD_STATE & LCD_OSDS_READY )
6068
6069/* Foreground Color Key Register 0,1(foreground 0, foreground 1) */
6070#define __lcd_enable_colorkey0() (REG_LCD_KEY0 |= LCD_KEY_KEYEN)
6071#define __lcd_enable_colorkey1() (REG_LCD_KEY1 |= LCD_KEY_KEYEN)
6072#define __lcd_enable_colorkey0_md() (REG_LCD_KEY0 |= LCD_KEY_KEYMD)
6073#define __lcd_enable_colorkey1_md() (REG_LCD_KEY1 |= LCD_KEY_KEYMD)
6074#define __lcd_set_colorkey0(key) (REG_LCD_KEY0 = (REG_LCD_KEY0&~0xFFFFFF)|(key))
6075#define __lcd_set_colorkey1(key) (REG_LCD_KEY1 = (REG_LCD_KEY1&~0xFFFFFF)|(key))
6076
6077#define __lcd_disable_colorkey0() (REG_LCD_KEY0 &= ~LCD_KEY_KEYEN)
6078#define __lcd_disable_colorkey1() (REG_LCD_KEY1 &= ~LCD_KEY_KEYEN)
6079#define __lcd_disable_colorkey0_md() (REG_LCD_KEY0 &= ~LCD_KEY_KEYMD)
6080#define __lcd_disable_colorkey1_md() (REG_LCD_KEY1 &= ~LCD_KEY_KEYMD)
6081
6082/* IPU Restart Register */
6083#define __lcd_enable_ipu_restart() (REG_LCD_IPUR |= LCD_IPUR_IPUREN)
6084#define __lcd_disable_ipu_restart() (REG_LCD_IPUR &= ~LCD_IPUR_IPUREN)
6085#define __lcd_set_ipu_restart_triger(n) (REG_LCD_IPUR = (REG_LCD_IPUR&(~0xFFFFFF))|(n))
6086
6087/* RGB Control Register */
6088#define __lcd_enable_rgb_dummy() (REG_LCD_RGBC |= LCD_RGBC_RGBDM)
6089#define __lcd_disable_rgb_dummy() (REG_LCD_RGBC &= ~LCD_RGBC_RGBDM)
6090
6091#define __lcd_dummy_rgb() (REG_LCD_RGBC |= LCD_RGBC_DMM)
6092#define __lcd_rgb_dummy() (REG_LCD_RGBC &= ~LCD_RGBC_DMM)
6093
6094#define __lcd_rgb2ycc() (REG_LCD_RGBC |= LCD_RGBC_YCC)
6095#define __lcd_notrgb2ycc() (REG_LCD_RGBC &= ~LCD_RGBC_YCC)
6096
6097#define __lcd_odd_mode_rgb() \
6098 ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_RGB )
6099#define __lcd_odd_mode_rbg() \
6100 ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_RBG )
6101#define __lcd_odd_mode_grb() \
6102 ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_GRB)
6103
6104#define __lcd_odd_mode_gbr() \
6105 ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_GBR)
6106#define __lcd_odd_mode_brg() \
6107 ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_BRG)
6108#define __lcd_odd_mode_bgr() \
6109 ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_BGR)
6110
6111#define __lcd_even_mode_rgb() \
6112 ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_RGB )
6113#define __lcd_even_mode_rbg() \
6114 ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_RBG )
6115#define __lcd_even_mode_grb() \
6116 ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_GRB)
6117
6118#define __lcd_even_mode_gbr() \
6119 ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_GBR)
6120#define __lcd_even_mode_brg() \
6121 ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_BRG)
6122#define __lcd_even_mode_bgr() \
6123 ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_BGR)
6124
6125/* Vertical Synchronize Register */
6126#define __lcd_vsync_get_vps() \
6127 ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
6128
6129#define __lcd_vsync_get_vpe() \
6130 ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
6131#define __lcd_vsync_set_vpe(n) \
6132do { \
6133 REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \
6134 REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \
6135} while (0)
6136
6137#define __lcd_hsync_get_hps() \
6138 ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
6139#define __lcd_hsync_set_hps(n) \
6140do { \
6141 REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \
6142 REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \
6143} while (0)
6144
6145#define __lcd_hsync_get_hpe() \
6146 ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
6147#define __lcd_hsync_set_hpe(n) \
6148do { \
6149 REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \
6150 REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \
6151} while (0)
6152
6153#define __lcd_vat_get_ht() \
6154 ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
6155#define __lcd_vat_set_ht(n) \
6156do { \
6157 REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \
6158 REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \
6159} while (0)
6160
6161#define __lcd_vat_get_vt() \
6162 ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
6163#define __lcd_vat_set_vt(n) \
6164do { \
6165 REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \
6166 REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \
6167} while (0)
6168
6169#define __lcd_dah_get_hds() \
6170 ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
6171#define __lcd_dah_set_hds(n) \
6172do { \
6173 REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \
6174 REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \
6175} while (0)
6176
6177#define __lcd_dah_get_hde() \
6178 ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
6179#define __lcd_dah_set_hde(n) \
6180do { \
6181 REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \
6182 REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \
6183} while (0)
6184
6185#define __lcd_dav_get_vds() \
6186 ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
6187#define __lcd_dav_set_vds(n) \
6188do { \
6189 REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \
6190 REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \
6191} while (0)
6192
6193#define __lcd_dav_get_vde() \
6194 ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
6195#define __lcd_dav_set_vde(n) \
6196do { \
6197 REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \
6198 REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \
6199} while (0)
6200
6201/* DMA Command Register */
6202#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
6203#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
6204#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
6205#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
6206
6207#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
6208#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
6209#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
6210#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
6211
6212#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL )
6213#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
6214
6215#define __lcd_cmd0_get_len() \
6216 ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
6217#define __lcd_cmd1_get_len() \
6218 ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
6219
6220#endif /* __MIPS_ASSEMBLER */
6221
6222/*
6223 * Motion compensation module(MC) address definition
6224 */
6225#define MC_BASE 0xb3250000
6226
6227/*
6228 * MC registers offset address definition
6229 */
6230#define MC_MCCR_OFFSET (0x00) /* rw, 32, 0x???????? */
6231#define MC_MCSR_OFFSET (0x04) /* rw, 32, 0x???????? */
6232#define MC_MCRBAR_OFFSET (0x08) /* rw, 32, 0x???????? */
6233#define MC_MCT1LFCR_OFFSET (0x0c) /* rw, 32, 0x???????? */
6234#define MC_MCT2LFCR_OFFSET (0x10) /* rw, 32, 0x???????? */
6235#define MC_MCCBAR_OFFSET (0x14) /* rw, 32, 0x???????? */
6236#define MC_MCIIR_OFFSET (0x18) /* rw, 32, 0x???????? */
6237#define MC_MCSIR_OFFSET (0x1c) /* rw, 32, 0x???????? */
6238#define MC_MCT1MFCR_OFFSET (0x20) /* rw, 32, 0x???????? */
6239#define MC_MCT2MFCR_OFFSET (0x24) /* rw, 32, 0x???????? */
6240#define MC_MCFGIR_OFFSET (0x28) /* rw, 32, 0x???????? */
6241#define MC_MCFCIR_OFFSET (0x2c) /* rw, 32, 0x???????? */
6242#define MC_MCRNDTR_OFFSET (0x40) /* rw, 32, 0x???????? */
6243
6244#define MC_MC2CR_OFFSET (0x8000) /* rw, 32, 0x???????? */
6245#define MC_MC2SR_OFFSET (0x8004) /* rw, 32, 0x???????? */
6246#define MC_MC2RBAR_OFFSET (0x8008) /* rw, 32, 0x???????? */
6247#define MC_MC2CBAR_OFFSET (0x800c) /* rw, 32, 0x???????? */
6248#define MC_MC2IIR_OFFSET (0x8010) /* rw, 32, 0x???????? */
6249#define MC_MC2TFCR_OFFSET (0x8014) /* rw, 32, 0x???????? */
6250#define MC_MC2SIR_OFFSET (0x8018) /* rw, 32, 0x???????? */
6251#define MC_MC2FCIR_OFFSET (0x801c) /* rw, 32, 0x???????? */
6252#define MC_MC2RNDTR_OFFSET (0x8040) /* rw, 32, 0x???????? */
6253
6254/*
6255 * MC registers address definition
6256 */
6257#define MC_MCCR (MC_BASE + MC_MCCR_OFFSET)
6258#define MC_MCSR (MC_BASE + MC_MCSR_OFFSET)
6259#define MC_MCRBAR (MC_BASE + MC_MCRBAR_OFFSET)
6260#define MC_MCT1LFCR (MC_BASE + MC_MCT1LFCR_OFFSET)
6261#define MC_MCT2LFCR (MC_BASE + MC_MCT2LFCR_OFFSET)
6262#define MC_MCCBAR (MC_BASE + MC_MCCBAR_OFFSET)
6263#define MC_MCIIR (MC_BASE + MC_MCIIR_OFFSET)
6264#define MC_MCSIR (MC_BASE + MC_MCSIR_OFFSET)
6265#define MC_MCT1MFCR (MC_BASE + MC_MCT1MFCR_OFFSET)
6266#define MC_MCT2MFCR (MC_BASE + MC_MCT2MFCR_OFFSET)
6267#define MC_MCFGIR (MC_BASE + MC_MCFGIR_OFFSET)
6268#define MC_MCFCIR (MC_BASE + MC_MCFCIR_OFFSET)
6269#define MC_MCRNDTR (MC_BASE + MC_MCRNDTR_OFFSET)
6270
6271#define MC_MC2CR (MC_BASE + MC_MC2CR_OFFSET)
6272#define MC_MC2SR (MC_BASE + MC_MC2SR_OFFSET)
6273#define MC_MC2RBAR (MC_BASE + MC_MC2RBAR_OFFSET)
6274#define MC_MC2CBAR (MC_BASE + MC_MC2CBAR_OFFSET)
6275#define MC_MC2IIR (MC_BASE + MC_MC2IIR_OFFSET)
6276#define MC_MC2TFCR (MC_BASE + MC_MC2TFCR_OFFSET)
6277#define MC_MC2SIR (MC_BASE + MC_MC2SIR_OFFSET)
6278#define MC_MC2FCIR (MC_BASE + MC_MC2FCIR_OFFSET)
6279#define MC_MC2RNDTR (MC_BASE + MC_MC2RNDTR_OFFSET)
6280
6281/*
6282 * MC registers common define
6283 */
6284
6285/* MC Control Register(MCCR) */
6286#define MCCR_RETE BIT16
6287#define MCCR_DIPE BIT7
6288#define MCCR_CKGEN BIT6
6289#define MCCR_FDDEN BIT5
6290#define MCCR_DINSE BIT3
6291#define MCCR_FAE BIT2
6292#define MCCR_RST BIT1
6293#define MCCR_CHEN BIT0
6294
6295#define MCCR_FDDPGN_LSB 8
6296#define MCCR_FDDPGN_MASK BITS_H2L(15, MCCR_FDDPGN_LSB)
6297
6298/* MC Status Register(MCSR) */
6299#define MCSR_DLEND BIT1
6300#define MCSR_BKLEND BIT0
6301
6302#ifndef __MIPS_ASSEMBLER
6303
6304#define REG_MC_MCCR REG32(REG_MC_MCCR)
6305#define REG_MC_MCSR REG32(REG_MC_MCSR)
6306#define REG_MC_MCRBAR REG32(REG_MC_MCRBAR)
6307#define REG_MC_MCT1LFCR REG32(REG_MC_MCT1LFCR)
6308#define REG_MC_MCT2LFCR REG32(REG_MC_MCT2LFCR)
6309#define REG_MC_MCCBAR REG32(REG_MC_MCCBAR)
6310#define REG_MC_MCIIR REG32(REG_MC_MCIIR)
6311#define REG_MC_MCSIR REG32(REG_MC_MCSIR)
6312#define REG_MC_MCT1MFCR REG32(REG_MC_MCT1MFCR)
6313#define REG_MC_MCT2MFCR REG32(REG_MC_MCT2MFCR)
6314#define REG_MC_MCFGIR REG32(REG_MC_MCFGIR)
6315#define REG_MC_MCFCIR REG32(REG_MC_MCFCIR)
6316#define REG_MC_MCRNDTR REG32(REG_MC_MCRNDTR)
6317
6318#define REG_MC_MC2CR REG32(REG_MC_MC2CR)
6319#define REG_MC_MC2SR REG32(REG_MC_MC2SR)
6320#define REG_MC_MC2RBAR REG32(REG_MC_MC2RBAR)
6321#define REG_MC_MC2CBAR REG32(REG_MC_MC2CBAR)
6322#define REG_MC_MC2IIR REG32(REG_MC_MC2IIR)
6323#define REG_MC_MC2TFCR REG32(REG_MC_MC2TFCR)
6324#define REG_MC_MC2SIR REG32(REG_MC_MC2SIR)
6325#define REG_MC_MC2FCIR REG32(REG_MC_MC2FCIR)
6326#define REG_MC_MC2RNDTR REG32(REG_MC_MC2RNDTR)
6327
6328#endif /* __MIPS_ASSEMBLER */
6329
6330#define MDMAC_BASE 0xB3030000 /* Memory Copy DMAC */
6331
6332/*************************************************************************
6333 * MDMAC (MEM Copy DMA Controller)
6334 *************************************************************************/
6335
6336/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
6337
6338#define MDMAC_DSAR(n) (MDMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
6339#define MDMAC_DTAR(n) (MDMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
6340#define MDMAC_DTCR(n) (MDMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
6341#define MDMAC_DRSR(n) (MDMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
6342#define MDMAC_DCCSR(n) (MDMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
6343#define MDMAC_DCMD(n) (MDMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
6344#define MDMAC_DDA(n) (MDMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
6345#define MDMAC_DSD(n) (MDMAC_BASE + (0x1c + (n) * 0x20)) /* DMA Stride Address */
6346
6347#define MDMAC_DMACR (MDMAC_BASE + 0x0300) /* DMA control register */
6348#define MDMAC_DMAIPR (MDMAC_BASE + 0x0304) /* DMA interrupt pending */
6349#define MDMAC_DMADBR (MDMAC_BASE + 0x0308) /* DMA doorbell */
6350#define MDMAC_DMADBSR (MDMAC_BASE + 0x030C) /* DMA doorbell set */
6351#define MDMAC_DMACKE (MDMAC_BASE + 0x0310)
6352#define MDMAC_DMACKES (MDMAC_BASE + 0x0314)
6353#define MDMAC_DMACKEC (MDMAC_BASE + 0x0318)
6354
6355#define REG_MDMAC_DSAR(n) REG32(MDMAC_DSAR((n)))
6356#define REG_MDMAC_DTAR(n) REG32(MDMAC_DTAR((n)))
6357#define REG_MDMAC_DTCR(n) REG32(MDMAC_DTCR((n)))
6358#define REG_MDMAC_DRSR(n) REG32(MDMAC_DRSR((n)))
6359#define REG_MDMAC_DCCSR(n) REG32(MDMAC_DCCSR((n)))
6360#define REG_MDMAC_DCMD(n) REG32(MDMAC_DCMD((n)))
6361#define REG_MDMAC_DDA(n) REG32(MDMAC_DDA((n)))
6362#define REG_MDMAC_DSD(n) REG32(MDMAC_DSD(n))
6363#define REG_MDMAC_DMACR REG32(MDMAC_DMACR)
6364#define REG_MDMAC_DMAIPR REG32(MDMAC_DMAIPR)
6365#define REG_MDMAC_DMADBR REG32(MDMAC_DMADBR)
6366#define REG_MDMAC_DMADBSR REG32(MDMAC_DMADBSR)
6367#define REG_MDMAC_DMACKE REG32(MDMAC_DMACKE)
6368#define REG_MDMAC_DMACKES REG32(MDMAC_DMACKES)
6369#define REG_MDMAC_DMACKEC REG32(MDMAC_DMACKEC)
6370
6371// DMA control register
6372#define DMAC_MDMACR_HLT (1 << 3) /* DMA halt flag */
6373#define DMAC_MDMACR_AR (1 << 2) /* address error flag */
6374#define DMAC_MDMACR_DMAE (1 << 0) /* DMA enable bit */
6375
6376#ifndef __MIPS_ASSEMBLER
6377
6378/***************************************************************************
6379 * Mem Copy DMAC
6380 ***************************************************************************/
6381
6382#define __mdmac_enable_module() \
6383 ( REG_MDMAC_DMACR |= DMAC_MDMACR_DMAE )
6384#define __mdmac_disable_module() \
6385 ( REG_MDMAC_DMACR &= ~DMAC_MDMACR_DMAE )
6386
6387#define __mdmac_test_halt_error ( REG_MDMAC_DMACR & DMAC_MDMACR_HLT )
6388#define __mdmac_test_addr_error ( REG_MDMAC_DMACR & DMAC_MDMACR_AR )
6389
6390#define __mdmac_channel_enable_clk \
6391 REG_MDMAC_DMACKES = 1 << (n);
6392
6393#define __mdmac_channel_disable_clk \
6394 REG_MDMAC_DMACKEC = 1 << (n);
6395
6396#define __mdmac_enable_descriptor(n) \
6397 ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
6398#define __mdmac_disable_descriptor(n) \
6399 ( REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
6400
6401#define __mdmac_enable_channel(n) \
6402do { \
6403 REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_EN; \
6404} while (0)
6405#define __mdmac_disable_channel(n) \
6406do { \
6407 REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN; \
6408} while (0)
6409#define __mdmac_channel_enabled(n) \
6410 ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_EN )
6411
6412#define __mdmac_channel_enable_irq(n) \
6413 ( REG_MDMAC_DCMD((n)) |= DMAC_DCMD_TIE )
6414#define __mdmac_channel_disable_irq(n) \
6415 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
6416
6417#define __mdmac_channel_transmit_halt_detected(n) \
6418 ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
6419#define __mdmac_channel_transmit_end_detected(n) \
6420 ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_TT )
6421#define __mdmac_channel_address_error_detected(n) \
6422 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
6423#define __mdmac_channel_count_terminated_detected(n) \
6424 ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_CT )
6425#define __mdmac_channel_descriptor_invalid_detected(n) \
6426 ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_INV )
6427
6428#define __mdmac_channel_clear_transmit_halt(n) \
6429 do { \
6430 /* clear both channel halt error and globle halt error */ \
6431 REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT; \
6432 REG_MDMAC_DMACR &= ~DMAC_DMACR_HLT; \
6433 } while (0)
6434#define __mdmac_channel_clear_transmit_end(n) \
6435 ( REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
6436#define __mdmac_channel_clear_address_error(n) \
6437 do { \
6438 REG_MDMAC_DDA(n) = 0; /* clear descriptor address register */ \
6439 REG_MDMAC_DSAR(n) = 0; /* clear source address register */ \
6440 REG_MDMAC_DTAR(n) = 0; /* clear target address register */ \
6441 /* clear both channel addr error and globle address error */ \
6442 REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_AR; \
6443 REG_MDMAC_DMACR &= ~DMAC_DMACR_AR; \
6444 } while (0)
6445#define __mdmac_channel_clear_count_terminated(n) \
6446 ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
6447#define __mdmac_channel_clear_descriptor_invalid(n) \
6448 ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
6449
6450#define __mdmac_channel_set_transfer_unit_32bit(n) \
6451do { \
6452 REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
6453 REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \
6454} while (0)
6455
6456#define __mdmac_channel_set_transfer_unit_16bit(n) \
6457do { \
6458 REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
6459 REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
6460} while (0)
6461
6462#define __mdmac_channel_set_transfer_unit_8bit(n) \
6463do { \
6464 REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
6465 REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
6466} while (0)
6467
6468#define __mdmac_channel_set_transfer_unit_16byte(n) \
6469do { \
6470 REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
6471 REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
6472} while (0)
6473
6474#define __mdmac_channel_set_transfer_unit_32byte(n) \
6475do { \
6476 REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
6477 REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
6478} while (0)
6479
6480/* w=8,16,32 */
6481#define __mdmac_channel_set_dest_port_width(n,w) \
6482do { \
6483 REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
6484 REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
6485} while (0)
6486
6487/* w=8,16,32 */
6488#define __mdmac_channel_set_src_port_width(n,w) \
6489do { \
6490 REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
6491 REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
6492} while (0)
6493
6494/* v=0-15 */
6495#define __mdmac_channel_set_rdil(n,v) \
6496do { \
6497 REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
6498 REG_MDMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \
6499} while (0)
6500
6501#define __mdmac_channel_dest_addr_fixed(n) \
6502 (REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DAI)
6503#define __mdmac_channel_dest_addr_increment(n) \
6504 (REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DAI)
6505
6506#define __mdmac_channel_src_addr_fixed(n) \
6507 (REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SAI)
6508#define __mdmac_channel_src_addr_increment(n) \
6509 (REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SAI)
6510
6511#define __mdmac_channel_set_doorbell(n) \
6512 (REG_MDMAC_DMADBSR = (1 << (n)))
6513
6514#define __mdmac_channel_irq_detected(n) (REG_MDMAC_DMAIPR & (1 << (n)))
6515#define __mdmac_channel_ack_irq(n) (REG_MDMAC_DMAIPR &= ~(1 <<(n)))
6516
6517static __inline__ int __mdmac_get_irq(void)
6518{
6519 int i;
6520 for (i = 0; i < MAX_MDMA_NUM; i++)
6521 if (__mdmac_channel_irq_detected(i))
6522 return i;
6523 return -1;
6524}
6525
6526#endif /* __MIPS_ASSEMBLER */
6527
6528/*
6529 * Motion estimation module(ME) address definition
6530 */
6531#define ME_BASE 0xb3260000
6532
6533/*
6534 * ME registers offset address definition
6535 */
6536#define ME_MECR_OFFSET (0x00) /* rw, 32, 0x???????0 */
6537#define ME_MERBAR_OFFSET (0x04) /* rw, 32, 0x???????? */
6538#define ME_MECBAR_OFFSET (0x08) /* rw, 32, 0x???????? */
6539#define ME_MEDAR_OFFSET (0x0c) /* rw, 32, 0x???????? */
6540#define ME_MERFSR_OFFSET (0x10) /* rw, 32, 0x???????? */
6541#define ME_MECFSR_OFFSET (0x14) /* rw, 32, 0x???????? */
6542#define ME_MEDFSR_OFFSET (0x18) /* rw, 32, 0x???????? */
6543#define ME_MESR_OFFSET (0x1c) /* rw, 32, 0x???????? */
6544#define ME_MEMR_OFFSET (0x20) /* rw, 32, 0x???????? */
6545#define ME_MEFR_OFFSET (0x24) /* rw, 32, 0x???????? */
6546
6547/*
6548 * ME registers address definition
6549 */
6550#define ME_MECR (ME_BASE + ME_MECR_OFFSET)
6551#define ME_MERBAR (ME_BASE + ME_MERBAR_OFFSET)
6552#define ME_MECBAR (ME_BASE + ME_MECBAR_OFFSET)
6553#define ME_MEDAR (ME_BASE + ME_MEDAR_OFFSET)
6554#define ME_MERFSR (ME_BASE + ME_MERFSR_OFFSET)
6555#define ME_MECFSR (ME_BASE + ME_MECFSR_OFFSET)
6556#define ME_MEDFSR (ME_BASE + ME_MEDFSR_OFFSET)
6557#define ME_MESR (ME_BASE + ME_MESR_OFFSET)
6558#define ME_MEMR (ME_BASE + ME_MEMR_OFFSET)
6559#define ME_MEFR (ME_BASE + ME_MEFR_OFFSET)
6560
6561/*
6562 * ME registers common define
6563 */
6564
6565/* ME control register(MECR) */
6566#define MECR_FLUSH BIT2
6567#define MECR_RESET BIT1
6568#define MECR_ENABLE BIT0
6569
6570/* ME settings register(MESR) */
6571#define MESR_GATE_LSB 16
6572#define MESR_GATE_MASK BITS_H2L(31, MESR_GATE_LSB)
6573
6574#define MESR_NUM_LSB 0
6575#define MESR_NUM_MASK BITS_H2L(5, MESR_NUM_LSB)
6576
6577/* ME MVD register(MEMR) */
6578#define MEMR_MVDY_LSB 16
6579#define MESR_MVDY_MASK BITS_H2L(31, MEMR_MVDY_LSB)
6580
6581#define MEMR_MVDX_LSB 0
6582#define MESR_MVDX_MASK BITS_H2L(15, MEMR_MVDX_LSB)
6583
6584/* ME flag register(MEFR) */
6585#define MEFR_INTRA BIT1
6586#define MEFR_COMPLETED BIT0
6587
6588#ifndef __MIPS_ASSEMBLER
6589
6590#define REG_ME_MECR REG32(ME_MECR)
6591#define REG_ME_MERBAR REG32(ME_MERBAR)
6592#define REG_ME_MECBAR REG32(ME_MECBAR)
6593#define REG_ME_MEDAR REG32(ME_MEDAR)
6594#define REG_ME_MERFSR REG32(ME_MERFSR)
6595#define REG_ME_MECFSR REG32(ME_MECFSR)
6596#define REG_ME_MEDFSR REG32(ME_MEDFSR)
6597#define REG_ME_MESR REG32(ME_MESR)
6598#define REG_ME_MEMR REG32(ME_MEMR)
6599#define REG_ME_MEFR REG32(ME_MEFR)
6600
6601#endif /* __MIPS_ASSEMBLER */
6602
6603#define MSC0_BASE 0xB0021000
6604#define MSC1_BASE 0xB0022000
6605#define MSC2_BASE 0xB0023000
6606
6607/*************************************************************************
6608 * MSC
6609 ************************************************************************/
6610/* n = 0, 1 (MSC0, MSC1) */
6611#define MSC_STRPCL(n) (MSC0_BASE + (n)*0x1000 + 0x000)
6612#define MSC_STAT(n) (MSC0_BASE + (n)*0x1000 + 0x004)
6613#define MSC_CLKRT(n) (MSC0_BASE + (n)*0x1000 + 0x008)
6614#define MSC_CMDAT(n) (MSC0_BASE + (n)*0x1000 + 0x00C)
6615#define MSC_RESTO(n) (MSC0_BASE + (n)*0x1000 + 0x010)
6616#define MSC_RDTO(n) (MSC0_BASE + (n)*0x1000 + 0x014)
6617#define MSC_BLKLEN(n) (MSC0_BASE + (n)*0x1000 + 0x018)
6618#define MSC_NOB(n) (MSC0_BASE + (n)*0x1000 + 0x01C)
6619#define MSC_SNOB(n) (MSC0_BASE + (n)*0x1000 + 0x020)
6620#define MSC_IMASK(n) (MSC0_BASE + (n)*0x1000 + 0x024)
6621#define MSC_IREG(n) (MSC0_BASE + (n)*0x1000 + 0x028)
6622#define MSC_CMD(n) (MSC0_BASE + (n)*0x1000 + 0x02C)
6623#define MSC_ARG(n) (MSC0_BASE + (n)*0x1000 + 0x030)
6624#define MSC_RES(n) (MSC0_BASE + (n)*0x1000 + 0x034)
6625#define MSC_RXFIFO(n) (MSC0_BASE + (n)*0x1000 + 0x038)
6626#define MSC_TXFIFO(n) (MSC0_BASE + (n)*0x1000 + 0x03C)
6627#define MSC_LPM(n) (MSC0_BASE + (n)*0x1000 + 0x040)
6628
6629#define REG_MSC_STRPCL(n) REG16(MSC_STRPCL(n))
6630#define REG_MSC_STAT(n) REG32(MSC_STAT(n))
6631#define REG_MSC_CLKRT(n) REG16(MSC_CLKRT(n))
6632#define REG_MSC_CMDAT(n) REG32(MSC_CMDAT(n))
6633#define REG_MSC_RESTO(n) REG16(MSC_RESTO(n))
6634#define REG_MSC_RDTO(n) REG32(MSC_RDTO(n))
6635#define REG_MSC_BLKLEN(n) REG16(MSC_BLKLEN(n))
6636#define REG_MSC_NOB(n) REG16(MSC_NOB(n))
6637#define REG_MSC_SNOB(n) REG16(MSC_SNOB(n))
6638#define REG_MSC_IMASK(n) REG32(MSC_IMASK(n))
6639#define REG_MSC_IREG(n) REG16(MSC_IREG(n))
6640#define REG_MSC_CMD(n) REG8(MSC_CMD(n))
6641#define REG_MSC_ARG(n) REG32(MSC_ARG(n))
6642#define REG_MSC_RES(n) REG16(MSC_RES(n))
6643#define REG_MSC_RXFIFO(n) REG32(MSC_RXFIFO(n))
6644#define REG_MSC_TXFIFO(n) REG32(MSC_TXFIFO(n))
6645#define REG_MSC_LPM(n) REG32(MSC_LPM(n))
6646
6647/* MSC Clock and Control Register (MSC_STRPCL) */
6648#define MSC_STRPCL_SEND_CCSD (1 << 15) /*send command completion signal disable to ceata */
6649#define MSC_STRPCL_SEND_AS_CCSD (1 << 14) /*send internally generated stop after sending ccsd */
6650#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
6651#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
6652#define MSC_STRPCL_START_READWAIT (1 << 5)
6653#define MSC_STRPCL_STOP_READWAIT (1 << 4)
6654#define MSC_STRPCL_RESET (1 << 3)
6655#define MSC_STRPCL_START_OP (1 << 2)
6656#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
6657#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
6658 #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
6659 #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
6660
6661/* MSC Status Register (MSC_STAT) */
6662#define MSC_STAT_AUTO_CMD_DONE (1 << 31) /*12 is internally generated by controller has finished */
6663#define MSC_STAT_IS_RESETTING (1 << 15)
6664#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
6665#define MSC_STAT_PRG_DONE (1 << 13)
6666#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
6667#define MSC_STAT_END_CMD_RES (1 << 11)
6668#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
6669#define MSC_STAT_IS_READWAIT (1 << 9)
6670#define MSC_STAT_CLK_EN (1 << 8)
6671#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
6672#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
6673#define MSC_STAT_CRC_RES_ERR (1 << 5)
6674#define MSC_STAT_CRC_READ_ERROR (1 << 4)
6675#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
6676#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
6677 #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
6678 #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
6679 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
6680#define MSC_STAT_TIME_OUT_RES (1 << 1)
6681#define MSC_STAT_TIME_OUT_READ (1 << 0)
6682
6683/* MSC Bus Clock Control Register (MSC_CLKRT) */
6684#define MSC_CLKRT_CLK_DIV_BIT 14
6685#define MSC_CLKRT_CLK_DIV_MASK (0x3 << MSC_CLKRT_CLK_DIV_BIT)
6686#define MSC_CLKRT_CLK_SRC_DIV_1 (0x0 << MSC_CLKRT_CLK_DIV_BIT) /* CLK_SRC */
6687#define MSC_CLKRT_CLK_SRC_DIV_2 (0x1 << MSC_CLKRT_CLK_DIV_BIT) /* 1/2 of CLK_SRC */
6688#define MSC_CLKRT_CLK_SRC_DIV_3 (0x2 << MSC_CLKRT_CLK_DIV_BIT) /* 1/3 of CLK_SRC */
6689#define MSC_CLKRT_CLK_SRC_DIV_4 (0x3 << MSC_CLKRT_CLK_DIV_BIT) /* 1/4 of CLK_SRC */
6690
6691#define MSC_CLKRT_CLK_RATE_BIT 0
6692#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
6693#define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
6694#define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
6695#define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
6696#define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
6697#define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
6698#define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
6699#define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
6700#define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
6701
6702/* MSC Command Sequence Control Register (MSC_CMDAT) */
6703#define MSC_CMDAT_CCS_EXPECTED (1 << 31) /* interrupts are enabled in ce-ata */
6704#define MSC_CMDAT_READ_CEATA (1 << 30)
6705#define MSC_CMDAT_SDIO_PRDT (1 << 17) /* exact 2 cycle */
6706#define MSC_CMDAT_SEND_AS_STOP (1 << 16)
6707#define MSC_CMDAT_RTRG_BIT 14
6708#define MSC_CMDAT_RTRG_EQUALT_8 (0x0 << MSC_CMDAT_RTRG_BIT) /*reset value*/
6709 #define MSC_CMDAT_RTRG_EQUALT_16 (0x1 << MSC_CMDAT_RTRG_BIT)
6710 #define MSC_CMDAT_RTRG_EQUALT_24 (0x2 << MSC_CMDAT_RTRG_BIT)
6711
6712#define MSC_CMDAT_TTRG_BIT 12
6713#define MSC_CMDAT_TTRG_LESS_8 (0x0 << MSC_CMDAT_TTRG_BIT) /*reset value*/
6714 #define MSC_CMDAT_TTRG_LESS_16 (0x1 << MSC_CMDAT_TTRG_BIT)
6715 #define MSC_CMDAT_TTRG_LESS_24 (0x2 << MSC_CMDAT_TTRG_BIT)
6716#define MSC_CMDAT_STOP_ABORT (1 << 11)
6717#define MSC_CMDAT_BUS_WIDTH_BIT 9
6718#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
6719 #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
6720 #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
6721 #define MSC_CMDAT_BUS_WIDTH_8BIT (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) /* 8-bit data bus */
6722#define MSC_CMDAT_DMA_EN (1 << 8)
6723#define MSC_CMDAT_INIT (1 << 7)
6724#define MSC_CMDAT_BUSY (1 << 6)
6725#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
6726#define MSC_CMDAT_WRITE (1 << 4)
6727#define MSC_CMDAT_READ (0 << 4)
6728#define MSC_CMDAT_DATA_EN (1 << 3)
6729#define MSC_CMDAT_RESPONSE_BIT 0
6730#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
6731 #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
6732 #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
6733 #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
6734 #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
6735 #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
6736 #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
6737 #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
6738 #define MSC_CMDAT_RESRONSE_R7 (0x7 << MSC_CMDAT_RESPONSE_BIT) /* Format R7 */
6739
6740#define CMDAT_DMA_EN (1 << 8)
6741#define CMDAT_INIT (1 << 7)
6742#define CMDAT_BUSY (1 << 6)
6743#define CMDAT_STREAM (1 << 5)
6744#define CMDAT_WRITE (1 << 4)
6745#define CMDAT_DATA_EN (1 << 3)
6746
6747/* MSC Interrupts Mask Register (MSC_IMASK) */
6748#define MSC_IMASK_AUTO_CMD_DONE (1 << 15)
6749#define MSC_IMASK_DATA_FIFO_FULL (1 << 14)
6750#define MSC_IMASK_DATA_FIFO_EMP (1 << 13)
6751#define MSC_IMASK_CRC_RES_ERR (1 << 12)
6752#define MSC_IMASK_CRC_READ_ERR (1 << 11)
6753#define MSC_IMASK_CRC_WRITE_ERR (1 << 10)
6754#define MSC_IMASK_TIME_OUT_RES (1 << 9)
6755#define MSC_IMASK_TIME_OUT_READ (1 << 8)
6756#define MSC_IMASK_SDIO (1 << 7)
6757#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
6758#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
6759#define MSC_IMASK_END_CMD_RES (1 << 2)
6760#define MSC_IMASK_PRG_DONE (1 << 1)
6761#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
6762
6763/* MSC Interrupts Status Register (MSC_IREG) */
6764#define MSC_IREG_AUTO_CMD_DONE (1 << 15)
6765#define MSC_IREG_DATA_FIFO_FULL (1 << 14)
6766#define MSC_IREG_DATA_FIFO_EMP (1 << 13)
6767#define MSC_IREG_CRC_RES_ERR (1 << 12)
6768#define MSC_IREG_CRC_READ_ERR (1 << 11)
6769#define MSC_IREG_CRC_WRITE_ERR (1 << 10)
6770#define MSC_IREG_TIMEOUT_RES (1 << 9)
6771#define MSC_IREG_TIMEOUT_READ (1 << 8)
6772#define MSC_IREG_SDIO (1 << 7)
6773#define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
6774#define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
6775#define MSC_IREG_END_CMD_RES (1 << 2)
6776#define MSC_IREG_PRG_DONE (1 << 1)
6777#define MSC_IREG_DATA_TRAN_DONE (1 << 0)
6778
6779/* MSC Low Power Mode Register (MSC_LPM) */
6780#define MSC_SET_HISPD (1 << 31)
6781#define MSC_SET_LPM (1 << 0)
6782
6783#ifndef __MIPS_ASSEMBLER
6784
6785/***************************************************************************
6786 * MSC
6787 ***************************************************************************/
6788/* n = 0, 1 (MSC0, MSC1) */
6789
6790#define __msc_start_op(n) \
6791 ( REG_MSC_STRPCL(n) = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
6792
6793#define __msc_set_resto(n, to) ( REG_MSC_RESTO(n) = to )
6794#define __msc_set_rdto(n, to) ( REG_MSC_RDTO(n) = to )
6795#define __msc_set_cmd(n, cmd) ( REG_MSC_CMD(n) = cmd )
6796#define __msc_set_arg(n, arg) ( REG_MSC_ARG(n) = arg )
6797#define __msc_set_nob(n, nob) ( REG_MSC_NOB(n) = nob )
6798#define __msc_get_nob(n) ( REG_MSC_NOB(n) )
6799#define __msc_set_blklen(n, len) ( REG_MSC_BLKLEN(n) = len )
6800#define __msc_set_cmdat(n, cmdat) ( REG_MSC_CMDAT(n) = cmdat )
6801
6802#define __msc_set_cmdat_bus_width1(n) \
6803do { \
6804 REG_MSC_CMDAT(n) &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
6805 REG_MSC_CMDAT(n) |= MSC_CMDAT_BUS_WIDTH_1BIT; \
6806} while(0)
6807
6808#define __msc_set_cmdat_bus_width4(n) \
6809do { \
6810 REG_MSC_CMDAT(n) &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
6811 REG_MSC_CMDAT(n) |= MSC_CMDAT_BUS_WIDTH_4BIT; \
6812} while(0)
6813
6814#define __msc_set_cmdat_dma_en(n) ( REG_MSC_CMDAT(n) |= MSC_CMDAT_DMA_EN )
6815#define __msc_set_cmdat_init(n) ( REG_MSC_CMDAT(n) |= MSC_CMDAT_INIT )
6816#define __msc_set_cmdat_busy(n) ( REG_MSC_CMDAT(n) |= MSC_CMDAT_BUSY )
6817#define __msc_set_cmdat_stream(n) ( REG_MSC_CMDAT(n) |= MSC_CMDAT_STREAM_BLOCK )
6818#define __msc_set_cmdat_block(n) ( REG_MSC_CMDAT(n) &= ~MSC_CMDAT_STREAM_BLOCK )
6819#define __msc_set_cmdat_read(n) ( REG_MSC_CMDAT(n) &= ~MSC_CMDAT_WRITE )
6820#define __msc_set_cmdat_write(n) ( REG_MSC_CMDAT(n) |= MSC_CMDAT_WRITE )
6821#define __msc_set_cmdat_data_en(n) ( REG_MSC_CMDAT(n) |= MSC_CMDAT_DATA_EN )
6822
6823/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
6824#define __msc_set_cmdat_res_format(n, r) \
6825do { \
6826 REG_MSC_CMDAT(n) &= ~MSC_CMDAT_RESPONSE_MASK; \
6827 REG_MSC_CMDAT(n) |= (r); \
6828} while(0)
6829
6830#define __msc_clear_cmdat(n) \
6831 REG_MSC_CMDAT(n) &= ~( MSC_CMDAT_STOP_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
6832 MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE | \
6833 MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_MASK )
6834
6835#define __msc_get_imask(n) ( REG_MSC_IMASK(n) )
6836#define __msc_mask_all_intrs(n) ( REG_MSC_IMASK(n) = 0xff )
6837#define __msc_unmask_all_intrs(n) ( REG_MSC_IMASK(n) = 0x00 )
6838#define __msc_mask_rd(n) ( REG_MSC_IMASK(n) |= MSC_IMASK_RXFIFO_RD_REQ )
6839#define __msc_unmask_rd(n) ( REG_MSC_IMASK(n) &= ~MSC_IMASK_RXFIFO_RD_REQ )
6840#define __msc_mask_wr(n) ( REG_MSC_IMASK(n) |= MSC_IMASK_TXFIFO_WR_REQ )
6841#define __msc_unmask_wr(n) ( REG_MSC_IMASK(n) &= ~MSC_IMASK_TXFIFO_WR_REQ )
6842#define __msc_mask_endcmdres(n) ( REG_MSC_IMASK(n) |= MSC_IMASK_END_CMD_RES )
6843#define __msc_unmask_endcmdres(n) ( REG_MSC_IMASK(n) &= ~MSC_IMASK_END_CMD_RES )
6844#define __msc_mask_datatrandone(n) ( REG_MSC_IMASK(n) |= MSC_IMASK_DATA_TRAN_DONE )
6845#define __msc_unmask_datatrandone(n) ( REG_MSC_IMASK(n) &= ~MSC_IMASK_DATA_TRAN_DONE )
6846#define __msc_mask_prgdone(n) ( REG_MSC_IMASK(n) |= MSC_IMASK_PRG_DONE )
6847#define __msc_unmask_prgdone(n) ( REG_MSC_IMASK(n) &= ~MSC_IMASK_PRG_DONE )
6848
6849/* m=0,1,2,3,4,5,6,7 */
6850#define __msc_set_clkrt(n, m) \
6851do { \
6852 REG_MSC_CLKRT(n) = m; \
6853} while(0)
6854
6855#define __msc_get_ireg(n) ( REG_MSC_IREG(n) )
6856#define __msc_ireg_rd(n) ( REG_MSC_IREG(n) & MSC_IREG_RXFIFO_RD_REQ )
6857#define __msc_ireg_wr(n) ( REG_MSC_IREG(n) & MSC_IREG_TXFIFO_WR_REQ )
6858#define __msc_ireg_end_cmd_res(n) ( REG_MSC_IREG(n) & MSC_IREG_END_CMD_RES )
6859#define __msc_ireg_data_tran_done(n) ( REG_MSC_IREG(n) & MSC_IREG_DATA_TRAN_DONE )
6860#define __msc_ireg_prg_done(n) ( REG_MSC_IREG(n) & MSC_IREG_PRG_DONE )
6861#define __msc_ireg_clear_end_cmd_res(n) ( REG_MSC_IREG(n) = MSC_IREG_END_CMD_RES )
6862#define __msc_ireg_clear_data_tran_done(n) ( REG_MSC_IREG(n) = MSC_IREG_DATA_TRAN_DONE )
6863#define __msc_ireg_clear_prg_done(n) ( REG_MSC_IREG(n) = MSC_IREG_PRG_DONE )
6864
6865#define __msc_get_stat(n) ( REG_MSC_STAT(n) )
6866#define __msc_stat_not_end_cmd_res(n) ( (REG_MSC_STAT(n) & MSC_STAT_END_CMD_RES) == 0)
6867#define __msc_stat_crc_err(n) \
6868 ( REG_MSC_STAT(n) & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
6869#define __msc_stat_res_crc_err(n) ( REG_MSC_STAT(n) & MSC_STAT_CRC_RES_ERR )
6870#define __msc_stat_rd_crc_err(n) ( REG_MSC_STAT(n) & MSC_STAT_CRC_READ_ERROR )
6871#define __msc_stat_wr_crc_err(n) ( REG_MSC_STAT(n) & MSC_STAT_CRC_WRITE_ERROR_YES )
6872#define __msc_stat_resto_err(n) ( REG_MSC_STAT(n) & MSC_STAT_TIME_OUT_RES )
6873#define __msc_stat_rdto_err(n) ( REG_MSC_STAT(n) & MSC_STAT_TIME_OUT_READ )
6874
6875#define __msc_rd_resfifo(n) ( REG_MSC_RES(n) )
6876#define __msc_rd_rxfifo(n) ( REG_MSC_RXFIFO(n) )
6877#define __msc_wr_txfifo(n, v) ( REG_MSC_TXFIFO(n) = v )
6878
6879#define __msc_reset(n) \
6880do { \
6881 REG_MSC_STRPCL(n) = MSC_STRPCL_RESET; \
6882 while (REG_MSC_STAT(n) & MSC_STAT_IS_RESETTING); \
6883} while (0)
6884
6885#define __msc_start_clk(n) \
6886do { \
6887 REG_MSC_STRPCL(n) = MSC_STRPCL_CLOCK_CONTROL_START; \
6888} while (0)
6889
6890#define __msc_stop_clk(n) \
6891do { \
6892 REG_MSC_STRPCL(n) = MSC_STRPCL_CLOCK_CONTROL_STOP; \
6893} while (0)
6894
6895#define MMC_CLK 19169200
6896#define SD_CLK 24576000
6897
6898/* msc_clk should little than pclk and little than clk retrieve from card */
6899#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \
6900do { \
6901 unsigned int rate, pclk, i; \
6902 pclk = dev_clk; \
6903 rate = type?SD_CLK:MMC_CLK; \
6904 if (msc_clk && msc_clk < pclk) \
6905 pclk = msc_clk; \
6906 i = 0; \
6907 while (pclk < rate) \
6908 { \
6909 i ++; \
6910 rate >>= 1; \
6911 } \
6912 lv = i; \
6913} while(0)
6914
6915/* divide rate to little than or equal to 400kHz */
6916#define __msc_calc_slow_clk_divisor(type, lv) \
6917do { \
6918 unsigned int rate, i; \
6919 rate = (type?SD_CLK:MMC_CLK)/1000/400; \
6920 i = 0; \
6921 while (rate > 0) \
6922 { \
6923 rate >>= 1; \
6924 i ++; \
6925 } \
6926 lv = i; \
6927} while(0)
6928
6929#endif /* __MIPS_ASSEMBLER */
6930
6931#define NEMC_BASE 0xB3410000
6932
6933/*************************************************************************
6934 * NEMC (External Memory Controller for NAND)
6935 *************************************************************************/
6936
6937#define NEMC_NFCSR (NEMC_BASE + 0x50) /* NAND Flash Control/Status Register */
6938#define NEMC_SMCR (NEMC_BASE + 0x14) /* Static Memory Control Register 1 */
6939#define NEMC_PNCR (NEMC_BASE + 0x100)
6940#define NEMC_PNDR (NEMC_BASE + 0x104)
6941#define NEMC_BITCNT (NEMC_BASE + 0x108)
6942
6943#define REG_NEMC_NFCSR REG32(NEMC_NFCSR)
6944#define REG_NEMC_SMCR1 REG32(NEMC_SMCR)
6945#define REG_NEMC_PNCR REG32(NEMC_PNCR)
6946#define REG_NEMC_PNDR REG32(NEMC_PNDR)
6947#define REG_NEMC_BITCNT REG32(NEMC_BITCNT)
6948
6949/* NAND Flash Control/Status Register */
6950#define NEMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
6951#define NEMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
6952#define NEMC_NFCSR_NFCE3 (1 << 5)
6953#define NEMC_NFCSR_NFE3 (1 << 4)
6954#define NEMC_NFCSR_NFCE2 (1 << 3)
6955#define NEMC_NFCSR_NFE2 (1 << 2)
6956#define NEMC_NFCSR_NFCE1 (1 << 1)
6957#define NEMC_NFCSR_NFE1 (1 << 0)
6958
6959#define UDC_BASE 0xB3440000
6960
6961/*************************************************************************
6962 * USB Device
6963 *************************************************************************/
6964#define USB_BASE UDC_BASE
6965
6966#define USB_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */
6967#define USB_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */
6968#define USB_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */
6969#define USB_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
6970#define USB_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */
6971#define USB_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
6972#define USB_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
6973#define USB_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
6974#define USB_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */
6975#define USB_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */
6976#define USB_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */
6977
6978#define USB_CSR0 (USB_BASE + 0x12) /* EP0 CSR 16-bit */
6979#define USB_COUNT0 (USB_BASE + 0x18) /* EP0 OUT FIFO count 8-bit */
6980
6981#define USB_INMAXP (USB_BASE + 0x10) /* EP1-15 IN Max Pkt Size 16-bit */
6982#define USB_INCSR (USB_BASE + 0x12) /* EP1-15 IN CSR LSB 8/16bit */
6983#define USB_INCSRH (USB_BASE + 0x13) /* EP1-15 IN CSR MSB 8-bit */
6984#define USB_OUTMAXP (USB_BASE + 0x14) /* EP1-15 OUT Max Pkt Size 16-bit */
6985#define USB_OUTCSR (USB_BASE + 0x16) /* EP1-15 OUT CSR LSB 8/16bit */
6986#define USB_OUTCSRH (USB_BASE + 0x17) /* EP1-15 OUT CSR MSB 8-bit */
6987#define USB_OUTCOUNT (USB_BASE + 0x18) /* EP1-15 OUT FIFO count 16-bit */
6988
6989#define USB_FIFO_EP(n) (USB_BASE + (n)*4 + 0x20)
6990
6991#define USB_EPINFO (USB_BASE + 0x78) /* Endpoint information */
6992#define USB_RAMINFO (USB_BASE + 0x79) /* RAM information */
6993
6994#define USB_INTR (USB_BASE + 0x200) /* DMA pending interrupts */
6995#define USB_CNTL(n) (USB_BASE + (n)*0x10 + 0x204) /* DMA channel n control */
6996#define USB_ADDR(n) (USB_BASE + (n)*0x10 + 0x208) /* DMA channel n AHB memory addr */
6997#define USB_COUNT(n) (USB_BASE + (n)*0x10 + 0x20c) /* DMA channel n byte count */
6998
6999/* Power register bit masks */
7000#define USB_POWER_SUSPENDM 0x01
7001#define USB_POWER_RESUME 0x04
7002#define USB_POWER_HSMODE 0x10
7003#define USB_POWER_HSENAB 0x20
7004#define USB_POWER_SOFTCONN 0x40
7005
7006/* Interrupt register bit masks */
7007#define USB_INTR_SUSPEND 0x01
7008#define USB_INTR_RESUME 0x02
7009#define USB_INTR_RESET 0x04
7010
7011#define USB_INTR_EP(n) (1 << (n))
7012
7013/* CSR0 bit masks */
7014#define USB_CSR0_OUTPKTRDY 0x01
7015#define USB_CSR0_INPKTRDY 0x02
7016#define USB_CSR0_SENTSTALL 0x04
7017#define USB_CSR0_DATAEND 0x08
7018#define USB_CSR0_SETUPEND 0x10
7019#define USB_CSR0_SENDSTALL 0x20
7020#define USB_CSR0_SVDOUTPKTRDY 0x40
7021#define USB_CSR0_SVDSETUPEND 0x80
7022#define USB_CSR0_FLUSHFIFO 0x100
7023
7024/* Endpoint CSR register bits */
7025#define USB_INCSRH_AUTOSET 0x80
7026#define USB_INCSRH_ISO 0x40
7027#define USB_INCSRH_MODE 0x20
7028#define USB_INCSRH_DMAREQENAB 0x10
7029#define USB_INCSRH_FRCDATATOG 0x08
7030#define USB_INCSRH_DMAREQMODE 0x04
7031#define USB_INCSR_CDT 0x40
7032#define USB_INCSR_SENTSTALL 0x20
7033#define USB_INCSR_SENDSTALL 0x10
7034#define USB_INCSR_FF 0x08
7035#define USB_INCSR_UNDERRUN 0x04
7036#define USB_INCSR_FFNOTEMPT 0x02
7037#define USB_INCSR_INPKTRDY 0x01
7038#define USB_OUTCSRH_AUTOCLR 0x80
7039#define USB_OUTCSRH_ISO 0x40
7040#define USB_OUTCSRH_DMAREQENAB 0x20
7041#define USB_OUTCSRH_DNYT 0x10
7042#define USB_OUTCSRH_DMAREQMODE 0x08
7043#define USB_OUTCSR_CDT 0x80
7044#define USB_OUTCSR_SENTSTALL 0x40
7045#define USB_OUTCSR_SENDSTALL 0x20
7046#define USB_OUTCSR_FF 0x10
7047#define USB_OUTCSR_DATAERR 0x08
7048#define USB_OUTCSR_OVERRUN 0x04
7049#define USB_OUTCSR_FFFULL 0x02
7050#define USB_OUTCSR_OUTPKTRDY 0x01
7051
7052/* Testmode register bits */
7053#define USB_TEST_SE0NAK 0x01
7054#define USB_TEST_J 0x02
7055#define USB_TEST_K 0x04
7056#define USB_TEST_PACKET 0x08
7057#define USB_TEST_FORCE_HS 0x10
7058#define USB_TEST_FORCE_FS 0x20
7059#define USB_TEST_ALL ( USB_TEST_SE0NAK | USB_TEST_J \
7060 | USB_TEST_K | USB_TEST_PACKET \
7061 | USB_TEST_FORCE_HS | USB_TEST_FORCE_FS)
7062
7063/* DMA control bits */
7064#define USB_CNTL_ENA 0x01
7065#define USB_CNTL_DIR_IN 0x02
7066#define USB_CNTL_MODE_1 0x04
7067#define USB_CNTL_INTR_EN 0x08
7068#define USB_CNTL_EP(n) ((n) << 4)
7069#define USB_CNTL_BURST_0 (0 << 9)
7070#define USB_CNTL_BURST_4 (1 << 9)
7071#define USB_CNTL_BURST_8 (2 << 9)
7072#define USB_CNTL_BURST_16 (3 << 9)
7073
7074/* DMA interrupt bits */
7075#define USB_INTR_DMA_BULKIN 1
7076#define USB_INTR_DMA_BULKOUT 2
7077
7078#define REG_USB_FADDR REG8(USB_FADDR)
7079#define REG_USB_POWER REG8(USB_POWER)
7080#define REG_USB_INTRIN REG16(USB_INTRIN)
7081#define REG_USB_INTROUT REG16(USB_INTROUT)
7082#define REG_USB_INTRINE REG16(USB_INTRINE)
7083#define REG_USB_INTROUTE REG16(USB_INTROUTE)
7084#define REG_USB_INTRUSB REG8(USB_INTRUSB)
7085#define REG_USB_INTRUSBE REG8(USB_INTRUSBE)
7086#define REG_USB_FRAME REG16(USB_FRAME)
7087#define REG_USB_INDEX REG8(USB_INDEX)
7088#define REG_USB_TESTMODE REG8(USB_TESTMODE)
7089
7090#define REG_USB_CSR0 REG16(USB_CSR0)
7091#define REG_USB_COUNT0 REG8(USB_COUNT0)
7092
7093#define REG_USB_INMAXP REG16(USB_INMAXP)
7094#define REG_USB_INCSR REG16(USB_INCSR)
7095#define REG_USB_INCSRH REG8(USB_INCSRH)
7096#define REG_USB_OUTMAXP REG16(USB_OUTMAXP)
7097#define REG_USB_OUTCSR REG16(USB_OUTCSR)
7098#define REG_USB_OUTCSRH REG8(USB_OUTCSRH)
7099#define REG_USB_OUTCOUNT REG16(USB_OUTCOUNT)
7100
7101#define REG_USB_FIFO_EP(n) REG32(USB_FIFO_EP(n))
7102
7103#define REG_USB_INTR REG8(USB_INTR)
7104#define REG_USB_CNTL(n) REG16(USB_CNTL(n))
7105#define REG_USB_ADDR(n) REG32(USB_ADDR(n))
7106#define REG_USB_COUNT(n) REG32(USB_COUNT(n))
7107
7108#define REG_USB_EPINFO REG8(USB_EPINFO)
7109#define REG_USB_RAMINFO REG8(USB_RAMINFO)
7110
7111/*
7112 * One wire bus interface(OWI) address definition
7113 */
7114#define OWI_BASE 0xb0072000
7115
7116/*
7117 * OWI registers offset address definition
7118 */
7119#define OWI_OWICFG_OFFSET (0x00) /* rw, 8, 0x00 */
7120#define OWI_OWICTL_OFFSET (0x04) /* rw, 8, 0x00 */
7121#define OWI_OWISTS_OFFSET (0x08) /* rw, 8, 0x00 */
7122#define OWI_OWIDAT_OFFSET (0x0c) /* rw, 8, 0x00 */
7123#define OWI_OWIDIV_OFFSET (0x10) /* rw, 8, 0x00 */
7124
7125/*
7126 * OWI registers address definition
7127 */
7128#define OWI_OWICFG (OWI_BASE + OWI_OWICFG_OFFSET)
7129#define OWI_OWICTL (OWI_BASE + OWI_OWICTL_OFFSET)
7130#define OWI_OWISTS (OWI_BASE + OWI_OWISTS_OFFSET)
7131#define OWI_OWIDAT (OWI_BASE + OWI_OWIDAT_OFFSET)
7132#define OWI_OWIDIV (OWI_BASE + OWI_OWIDIV_OFFSET)
7133
7134/*
7135 * OWI registers common define
7136 */
7137
7138/* OWI configure register(OWICFG) */
7139#define OWICFG_MODE BIT7
7140#define OWICFG_RDDATA BIT6
7141#define OWICFG_WRDATA BIT5
7142#define OWICFG_RDST BIT4
7143#define OWICFG_WR1RD BIT3
7144#define OWICFG_WR0 BIT2
7145#define OWICFG_RST BIT1
7146#define OWICFG_ENA BIT0
7147
7148/* OWI control register(OWICTL) */
7149#define OWICTL_EBYTE BIT2
7150#define OWICTL_EBIT BIT1
7151#define OWICTL_ERST BIT0
7152
7153/* OWI status register(OWISTS) */
7154#define OWISTS_PST BIT7
7155#define OWISTS_BYTE_RDY BIT2
7156#define OWISTS_BIT_RDY BIT1
7157#define OWISTS_PST_RDY BIT0
7158
7159/* OWI clock divide register(OWIDIV) */
7160#define OWIDIV_CLKDIV_LSB 0
7161#define OWIDIV_CLKDIV_MASK BITS_H2L(5, OWIDIV_CLKDIV_LSB)
7162
7163#ifndef __MIPS_ASSEMBLER
7164
7165/* Basic ops */
7166#define REG_OWI_OWICFG REG8(OWI_OWICFG)
7167#define REG_OWI_OWICTL REG8(OWI_OWICTL)
7168#define REG_OWI_OWISTS REG8(OWI_OWISTS)
7169#define REG_OWI_OWIDAT REG8(OWI_OWIDAT)
7170#define REG_OWI_OWIDIV REG8(OWI_OWIDIV)
7171
7172#endif /* __MIPS_ASSEMBLER */
7173
7174/*
7175 * Pulse-code modulation module(PCM) address definition
7176 */
7177#define PCM_BASE 0xb0071000
7178
7179/*
7180 * pcm number, jz4760x has only PCM0
7181 */
7182
7183#define PCM0 0
7184#define PCM1 1
7185
7186/* PCM groups offset */
7187#define PCM_GOS 0x3000
7188
7189/*
7190 * PCM registers offset address definition
7191 */
7192#define PCM_PCTL_OFFSET (0x00) /* rw, 32, 0x00000000 */
7193#define PCM_PCFG_OFFSET (0x04) /* rw, 32, 0x00000110 */
7194#define PCM_PDP_OFFSET (0x08) /* rw, 32, 0x00000000 */
7195#define PCM_PINTC_OFFSET (0x0c) /* rw, 32, 0x00000000 */
7196#define PCM_PINTS_OFFSET (0x10) /* rw, 32, 0x00000100 */
7197#define PCM_PDIV_OFFSET (0x14) /* rw, 32, 0x00000001 */
7198
7199/*
7200 * PCM registers address definition
7201 */
7202#define PCM_PCTL(n) (PCM_BASE + (n) * PCM_GOS + PCM_PCTL_OFFSET)
7203#define PCM_PCFG(n) (PCM_BASE + (n) * PCM_GOS + PCM_PCFG_OFFSET)
7204#define PCM_PDP(n) (PCM_BASE + (n) * PCM_GOS + PCM_PDP_OFFSET)
7205#define PCM_PINTC(n) (PCM_BASE + (n) * PCM_GOS + PCM_PINTC_OFFSET)
7206#define PCM_PINTS(n) (PCM_BASE + (n) * PCM_GOS + PCM_PINTS_OFFSET)
7207#define PCM_PDIV(n) (PCM_BASE + (n) * PCM_GOS + PCM_PDIV_OFFSET)
7208
7209/*
7210 * CPM registers common define
7211 */
7212
7213/* PCM controller control register (PCTL) */
7214#define PCTL_ERDMA BIT9
7215#define PCTL_ETDMA BIT8
7216#define PCTL_LSMP BIT7
7217#define PCTL_ERPL BIT6
7218#define PCTL_EREC BIT5
7219#define PCTL_FLUSH BIT4
7220#define PCTL_RST BIT3
7221#define PCTL_CLKEN BIT1
7222#define PCTL_PCMEN BIT0
7223
7224/* PCM controller configure register (PCFG) */
7225#define PCFG_ISS_16BIT BIT12
7226#define PCFG_OSS_16BIT BIT11
7227#define PCFG_IMSBPOS BIT10
7228#define PCFG_OMSBPOS BIT9
7229#define PCFG_MODE_SLAVE BIT0
7230
7231#define PCFG_SLOT_LSB 13
7232#define PCFG_SLOT_MASK BITS_H2L(14, PCFG_SLOT_LSB)
7233#define PCFG_SLOT(val) ((val) << PCFG_SLOT_LSB)
7234
7235#define PCFG_RFTH_LSB 5
7236#define PCFG_RFTH_MASK BITS_H2L(8, PCFG_RFTH_LSB)
7237
7238#define PCFG_TFTH_LSB 1
7239#define PCFG_TFTH_MASK BITS_H2L(4, PCFG_TFTH_LSB)
7240
7241/* PCM controller interrupt control register(PINTC) */
7242#define PINTC_ETFS BIT3
7243#define PINTC_ETUR BIT2
7244#define PINTC_ERFS BIT1
7245#define PINTC_EROR BIT0
7246
7247/* PCM controller interrupt status register(PINTS) */
7248#define PINTS_RSTS BIT14
7249#define PINTS_TFS BIT8
7250#define PINTS_TUR BIT7
7251#define PINTS_RFS BIT1
7252#define PINTS_ROR BIT0
7253
7254#define PINTS_TFL_LSB 9
7255#define PINTS_TFL_MASK BITS_H2L(13, PINTS_TFL_LSB)
7256
7257#define PINTS_RFL_LSB 2
7258#define PINTS_RFL_MASK BITS_H2L(6, PINTS_RFL_LSB)
7259
7260/* PCM controller clock division register(PDIV) */
7261#define PDIV_SYNL_LSB 11
7262#define PDIV_SYNL_MASK BITS_H2L(16, PDIV_SYNL_LSB)
7263
7264#define PDIV_SYNDIV_LSB 6
7265#define PDIV_SYNDIV_MASK BITS_H2L(10, PDIV_SYNDIV_LSB)
7266
7267#define PDIV_CLKDIV_LSB 0
7268#define PDIV_CLKDIV_MASK BITS_H2L(5, PDIV_CLKDIV_LSB)
7269
7270#ifndef __MIPS_ASSEMBLER
7271
7272#define REG_PCM_PCTL(n) REG32(PCM_PCTL(n))
7273#define REG_PCM_PCFG(n) REG32(PCM_PCFG(n))
7274#define REG_PCM_PDP(n) REG32(PCM_PDP(n))
7275#define REG_PCM_PINTC(n) REG32(PCM_PINTC(n))
7276#define REG_PCM_PINTS(n) REG32(PCM_PINTS(n))
7277#define REG_PCM_PDIV(n) REG32(PCM_PDIV(n))
7278
7279/*
7280 * PCM_DIN, PCM_DOUT, PCM_CLK, PCM_SYN
7281 */
7282#define __gpio_as_pcm(n) \
7283do { \
7284 switch(n) { \
7285 case PCM0: __gpio_as_pcm0();break; \
7286 case PCM1: __gpio_as_pcm1();break; \
7287 } \
7288 \
7289} while (0)
7290
7291#define __pcm_enable(n) (REG_PCM_PCTL(n) |= PCTL_PCMEN)
7292#define __pcm_disable(n) (REG_PCM_PCTL(n) &= ~PCTL_PCMEN)
7293
7294#define __pcm_clk_enable(n) (REG_PCM_PCTL(n) |= PCTL_CLKEN)
7295#define __pcm_clk_disable(n) (REG_PCM_PCTL(n) &= ~PCTL_CLKEN)
7296
7297#define __pcm_reset(n) (REG_PCM_PCTL(n) |= PCTL_RST)
7298#define __pcm_flush_fifo(n) (REG_PCM_PCTL(n) |= PCTL_FLUSH)
7299
7300#define __pcm_enable_record(n) (REG_PCM_PCTL(n) |= PCTL_EREC)
7301#define __pcm_disable_record(n) (REG_PCM_PCTL(n) &= ~PCTL_EREC)
7302#define __pcm_enable_playback(n) (REG_PCM_PCTL(n) |= PCTL_ERPL)
7303#define __pcm_disable_playback(n) (REG_PCM_PCTL(n) &= ~PCTL_ERPL)
7304
7305#define __pcm_enable_rxfifo(n) __pcm_enable_record(n)
7306#define __pcm_disable_rxfifo(n) __pcm_disable_record(n)
7307#define __pcm_enable_txfifo(n) __pcm_enable_playback(n)
7308#define __pcm_disable_txfifo(n) __pcm_disable_playback(n)
7309
7310#define __pcm_last_sample(n) (REG_PCM_PCTL(n) |= PCTL_LSMP)
7311#define __pcm_zero_sample(n) (REG_PCM_PCTL(n) &= ~PCTL_LSMP)
7312
7313#define __pcm_enable_transmit_dma(n) (REG_PCM_PCTL(n) |= PCTL_ETDMA)
7314#define __pcm_disable_transmit_dma(n) (REG_PCM_PCTL(n) &= ~PCTL_ETDMA)
7315#define __pcm_enable_receive_dma(n) (REG_PCM_PCTL(n) |= PCTL_ERDMA)
7316#define __pcm_disable_receive_dma(n) (REG_PCM_PCTL(n) &= ~PCTL_ERDMA)
7317
7318#define __pcm_as_master(n) (REG_PCM_PCFG(n) &= ~PCFG_MODE_SLAVE)
7319#define __pcm_as_slave(n) (REG_PCM_PCFG(n) |= PCFG_MODE_SLAVE)
7320
7321#define __pcm_set_transmit_trigger(n, val) \
7322do { \
7323 REG_PCM_PCFG(n) &= ~PCFG_TFTH_MASK; \
7324 REG_PCM_PCFG(n) |= ((val) << PCFG_TFTH_LSB); \
7325 \
7326} while(0)
7327
7328#define __pcm_set_receive_trigger(n, val) \
7329do { \
7330 REG_PCM_PCFG(n) &= ~PCFG_RFTH_MASK; \
7331 REG_PCM_PCFG(n) |= ((val) << PCFG_RFTH_LSB); \
7332 \
7333} while(0)
7334
7335#define __pcm_omsb_same_sync(n) (REG_PCM_PCFG(n) &= ~PCFG_OMSBPOS)
7336#define __pcm_omsb_next_sync(n) (REG_PCM_PCFG(n) |= PCFG_OMSBPOS)
7337
7338#define __pcm_imsb_same_sync(n) (REG_PCM_PCFG(n) &= ~PCFG_IMSBPOS)
7339#define __pcm_imsb_next_sync(n) (REG_PCM_PCFG(n) |= PCFG_IMSBPOS)
7340
7341#define __pcm_set_iss(n, val) \
7342do { \
7343 if ((val) == 16) \
7344 REG_PCM_PCFG(n) |= PCFG_ISS_16BIT; \
7345 else \
7346 REG_PCM_PCFG(n) &= ~PCFG_ISS_16BIT; \
7347 \
7348} while (0)
7349
7350#define __pcm_set_oss(n, val) \
7351do { \
7352 if ((val) == 16) \
7353 REG_PCM_PCFG(n) |= PCFG_OSS_16BIT; \
7354 else \
7355 REG_PCM_PCFG(n) &= ~PCFG_OSS_16BIT; \
7356 \
7357} while (0) \
7358
7359#define __pcm_set_valid_slot(n, val) \
7360 (REG_PCM_PCFG(n) = (REG_PCM_PCFG(n) & ~PCFG_SLOT_MASK) | PCFG_SLOT(val))
7361
7362#define __pcm_write_data(n, val) (REG_PCM_PDP(n) = (val))
7363#define __pcm_read_data(n) (REG_PCM_PDP(n))
7364
7365#define __pcm_enable_tfs_intr(n) (REG_PCM_PINTC(n) |= PINTC_ETFS)
7366#define __pcm_disable_tfs_intr(n) (REG_PCM_PINTC(n) &= ~PINTC_ETFS)
7367
7368#define __pcm_enable_tur_intr(n) (REG_PCM_PINTC(n) |= PINTC_ETUR)
7369#define __pcm_disable_tur_intr(n) (REG_PCM_PINTC(n) &= ~PINTC_ETUR)
7370
7371#define __pcm_enable_rfs_intr(n) (REG_PCM_PINTC(n) |= PINTC_ERFS)
7372#define __pcm_disable_rfs_intr(n) (REG_PCM_PINTC(n) &= ~PINTC_ERFS)
7373
7374#define __pcm_enable_ror_intr(n) (REG_PCM_PINTC(n) |= PINTC_EROR)
7375#define __pcm_disable_ror_intr(n) (REG_PCM_PINTC(n) &= ~PINTC_EROR)
7376
7377#define __pcm_ints_valid_tx(n) (((REG_PCM_PINTS(n) & PINTS_TFL_MASK) >> PINTS_TFL_LSB))
7378#define __pcm_ints_valid_rx(n) (((REG_PCM_PINTS(n) & PINTS_RFL_MASK) >> PINTS_RFL_LSB))
7379
7380#define __pcm_set_clk_div(n, val) \
7381 (REG_PCM_PDIV(n) = (REG_PCM_PDIV(n) & ~PDIV_CLKDIV_MASK) | ((val) << PDIV_CLKDIV_LSB))
7382
7383#define __pcm_set_clk_rate(n, sysclk, pcmclk) \
7384 __pcm_set_clk_div((n), ((sysclk) / (pcmclk) - 1))
7385
7386#define __pcm_set_sync_div(n, val) \
7387 (REG_PCM_PDIV(n) = (REG_PCM_PDIV(n) & ~PDIV_SYNDIV_MASK) | ((val) << PDIV_SYNDIV_LSB))
7388
7389#define __pcm_set_sync_rate(n, pcmclk, sync) \
7390 __pcm_set_sync_div((n), ((pcmclk) / (8 * (sync)) - 1))
7391
7392#define __pcm_set_sync_len(n, val) \
7393 (REG_PCM_PDIV(n) = (REG_PCM_PDIV(n) & ~PDIV_SYNL_MASK) | ((val) << PDIV_SYNL_LSB))
7394
7395#endif /* __MIPS_ASSEMBLER */
7396
7397/*
7398 * Real time clock module(RTC) address definition
7399 */
7400#define RTC_BASE 0xb0003000
7401
7402/*
7403 * RTC registers offset address definition
7404 */
7405#define RTC_RTCCR_OFFSET (0x00) /* rw, 32, 0x00000081 */
7406#define RTC_RTCSR_OFFSET (0x04) /* rw, 32, 0x???????? */
7407#define RTC_RTCSAR_OFFSET (0x08) /* rw, 32, 0x???????? */
7408#define RTC_RTCGR_OFFSET (0x0c) /* rw, 32, 0x0??????? */
7409
7410#define RTC_HCR_OFFSET (0x20) /* rw, 32, 0x00000000 */
7411#define RTC_HWFCR_OFFSET (0x24) /* rw, 32, 0x0000???0 */
7412#define RTC_HRCR_OFFSET (0x28) /* rw, 32, 0x00000??0 */
7413#define RTC_HWCR_OFFSET (0x2c) /* rw, 32, 0x00000008 */
7414#define RTC_HWRSR_OFFSET (0x30) /* rw, 32, 0x00000000 */
7415#define RTC_HSPR_OFFSET (0x34) /* rw, 32, 0x???????? */
7416#define RTC_WENR_OFFSET (0x3c) /* rw, 32, 0x00000000 */
7417
7418/*
7419 * RTC registers address definition
7420 */
7421#define RTC_RTCCR (RTC_BASE + RTC_RTCCR_OFFSET)
7422#define RTC_RTCSR (RTC_BASE + RTC_RTCSR_OFFSET)
7423#define RTC_RTCSAR (RTC_BASE + RTC_RTCSAR_OFFSET)
7424#define RTC_RTCGR (RTC_BASE + RTC_RTCGR_OFFSET)
7425
7426#define RTC_HCR (RTC_BASE + RTC_HCR_OFFSET)
7427#define RTC_HWFCR (RTC_BASE + RTC_HWFCR_OFFSET)
7428#define RTC_HRCR (RTC_BASE + RTC_HRCR_OFFSET)
7429#define RTC_HWCR (RTC_BASE + RTC_HWCR_OFFSET)
7430#define RTC_HWRSR (RTC_BASE + RTC_HWRSR_OFFSET)
7431#define RTC_HSPR (RTC_BASE + RTC_HSPR_OFFSET)
7432#define RTC_WENR (RTC_BASE + RTC_WENR_OFFSET)
7433
7434/*
7435 * RTC registers common define
7436 */
7437
7438/* RTC control register(RTCCR) */
7439#define RTCCR_WRDY BIT7
7440#define RTCCR_1HZ BIT6
7441#define RTCCR_1HZIE BIT5
7442#define RTCCR_AF BIT4
7443#define RTCCR_AIE BIT3
7444#define RTCCR_AE BIT2
7445#define RTCCR_SELEXC BIT1
7446#define RTCCR_RTCE BIT0
7447
7448/* RTC regulator register(RTCGR) */
7449#define RTCGR_LOCK BIT31
7450
7451#define RTCGR_ADJC_LSB 16
7452#define RTCGR_ADJC_MASK BITS_H2L(25, RTCGR_ADJC_LSB)
7453
7454#define RTCGR_NC1HZ_LSB 0
7455#define RTCGR_NC1HZ_MASK BITS_H2L(15, RTCGR_NC1HZ_LSB)
7456
7457/* Hibernate control register(HCR) */
7458#define HCR_PD BIT0
7459
7460/* Hibernate wakeup filter counter register(HWFCR) */
7461#define HWFCR_LSB 5
7462#define HWFCR_MASK BITS_H2L(15, HWFCR_LSB)
7463#define HWFCR_WAIT_TIME(ms) (((ms) << HWFCR_LSB) > HWFCR_MASK ? HWFCR_MASK : ((ms) << HWFCR_LSB))
7464
7465/* Hibernate reset counter register(HRCR) */
7466#define HRCR_LSB 5
7467#define HRCR_MASK BITS_H2L(11, HRCR_LSB)
7468#define HRCR_WAIT_TIME(ms) (((ms) << HRCR_LSB) > HRCR_MASK ? HRCR_MASK : ((ms) << HRCR_LSB))
7469
7470/* Hibernate wakeup control register(HWCR) */
7471#define HWCR_EPDET BIT3
7472#define HWCR_WKUPVL BIT2
7473#define HWCR_EALM BIT0
7474
7475/* Hibernate wakeup status register(HWRSR) */
7476#define HWRSR_APD BIT8
7477#define HWRSR_HR BIT5
7478#define HWRSR_PPR BIT4
7479#define HWRSR_PIN BIT1
7480#define HWRSR_ALM BIT0
7481
7482/* write enable pattern register(WENR) */
7483#define WENR_WEN BIT31
7484
7485#define WENR_WENPAT_LSB 0
7486#define WENR_WENPAT_MASK BITS_H2L(15, WENR_WENPAT_LSB)
7487#define WENR_WENPAT_WRITABLE (0xa55a)
7488
7489/* Hibernate scratch pattern register(HSPR) */
7490#define HSPR_RTCV 0x52544356 /* The value is 'RTCV', means rtc is valid */
7491
7492#ifndef __MIPS_ASSEMBLER
7493
7494/* Waiting for the RTC register writing finish */
7495#define __wait_write_ready() \
7496do { \
7497 int timeout = 0x1000; \
7498 while (!(rtc_read_reg(RTC_RTCCR) & RTCCR_WRDY) && timeout--); \
7499}while(0);
7500
7501/* Waiting for the RTC register writable */
7502#define __wait_writable() \
7503do { \
7504 int timeout = 0x1000; \
7505 __wait_write_ready(); \
7506 OUTREG32(RTC_WENR, WENR_WENPAT_WRITABLE); \
7507 __wait_write_ready(); \
7508 while (!(rtc_read_reg(RTC_WENR) & WENR_WEN) && timeout--); \
7509}while(0);
7510
7511/* Basic RTC ops */
7512#define rtc_read_reg(reg) \
7513({ \
7514 unsigned int data, timeout = 0x10000; \
7515 do { \
7516 data = INREG32(reg); \
7517 } while (INREG32(reg) != data && timeout--); \
7518 data; \
7519})
7520
7521#define rtc_write_reg(reg, data) \
7522do { \
7523 __wait_writable(); \
7524 OUTREG32(reg, data); \
7525 __wait_write_ready(); \
7526}while(0);
7527
7528#define rtc_set_reg(reg, data) rtc_write_reg(reg, rtc_read_reg(reg) | (data))
7529#define rtc_clr_reg(reg, data) rtc_write_reg(reg, rtc_read_reg(reg) & ~(data))
7530
7531#endif /* __MIPS_ASSEMBLER */
7532
7533/*
7534 * SAR A/D Controller(SADC) address definition
7535 */
7536#define SADC_BASE 0xb0070000
7537
7538/*
7539 * SADC registers offset definition
7540 */
7541#define SADC_ADENA_OFFSET (0x00) /* rw, 8, 0x00 */
7542#define SADC_ADCFG_OFFSET (0x04) /* rw, 32, 0x0002000c */
7543#define SADC_ADCTRL_OFFSET (0x08) /* rw, 8, 0x3f */
7544#define SADC_ADSTATE_OFFSET (0x0c) /* rw, 8, 0x00 */
7545#define SADC_ADSAME_OFFSET (0x10) /* rw, 16, 0x0000 */
7546#define SADC_ADWAIT_OFFSET (0x14) /* rw, 16, 0x0000 */
7547#define SADC_ADTCH_OFFSET (0x18) /* rw, 32, 0x00000000 */
7548#define SADC_ADVDAT_OFFSET (0x1c) /* rw, 16, 0x0000 */
7549#define SADC_ADADAT_OFFSET (0x20) /* rw, 16, 0x0000 */
7550#define SADC_ADFLT_OFFSET (0x24) /* rw, 16, 0x0000 */
7551#define SADC_ADCLK_OFFSET (0x28) /* rw, 32, 0x00000000 */
7552
7553/*
7554 * SADC registers address definition
7555 */
7556#define SADC_ADENA (SADC_BASE + SADC_ADENA_OFFSET) /* ADC Enable Register */
7557#define SADC_ADCFG (SADC_BASE + SADC_ADCFG_OFFSET) /* ADC Configure Register */
7558#define SADC_ADCTRL (SADC_BASE + SADC_ADCTRL_OFFSET) /* ADC Control Register */
7559#define SADC_ADSTATE (SADC_BASE + SADC_ADSTATE_OFFSET)/* ADC Status Register*/
7560#define SADC_ADSAME (SADC_BASE + SADC_ADSAME_OFFSET) /* ADC Same Point Time Register */
7561#define SADC_ADWAIT (SADC_BASE + SADC_ADWAIT_OFFSET) /* ADC Wait Time Register */
7562#define SADC_ADTCH (SADC_BASE + SADC_ADTCH_OFFSET) /* ADC Touch Screen Data Register */
7563#define SADC_ADVDAT (SADC_BASE + SADC_ADVDAT_OFFSET) /* ADC VBAT Data Register */
7564#define SADC_ADADAT (SADC_BASE + SADC_ADADAT_OFFSET) /* ADC AUX Data Register */
7565#define SADC_ADFLT (SADC_BASE + SADC_ADFLT_OFFSET) /* ADC Filter Register */
7566#define SADC_ADCLK (SADC_BASE + SADC_ADCLK_OFFSET) /* ADC Clock Divide Register */
7567
7568/*
7569 * SADC registers common define
7570 */
7571
7572/* ADC Enable Register (ADENA) */
7573#define ADENA_POWER BIT7
7574#define ADENA_SLP_MD BIT6
7575#define ADENA_PENDEN BIT3
7576#define ADENA_TCHEN BIT2
7577#define ADENA_VBATEN BIT1
7578#define ADENA_AUXEN BIT0
7579
7580/* ADC Configure Register (ADCFG) */
7581#define ADCFG_SPZZ BIT31
7582#define ADCFG_VBAT_SEL BIT30
7583#define ADCFG_DMA_EN BIT15
7584
7585#define ADCFG_XYZ_LSB 13
7586#define ADCFG_XYZ_MASK BITS_H2L(14, ADCFG_XYZ_LSB)
7587 #define ADCFG_XYZ_XYS (0x0 << ADCFG_XYZ_LSB)
7588 #define ADCFG_XYZ_XYD (0x1 << ADCFG_XYZ_LSB)
7589 #define ADCFG_XYZ_XYZ1Z2 (0x2 << ADCFG_XYZ_LSB)
7590
7591#define ADCFG_SNUM_LSB 10
7592#define ADCFG_SNUM_MASK BITS_H2L(12, ADCFG_SNUM_LSB)
7593 #define ADCFG_SNUM(n) (((n) <= 6 ? ((n)-1) : ((n)-2)) << ADCFG_SNUM_LSB)
7594
7595#define ADCFG_CMD_LSB 0
7596#define ADCFG_CMD_MASK BITS_H2L(1, ADCFG_CMD_LSB)
7597 #define ADCFG_CMD_AUX(n) ((n) << ADCFG_CMD_LSB)
7598
7599/* ADC Control Register (ADCCTRL) */
7600#define ADCTRL_SLPENDM BIT5
7601#define ADCTRL_PENDM BIT4
7602#define ADCTRL_PENUM BIT3
7603#define ADCTRL_DTCHM BIT2
7604#define ADCTRL_VRDYM BIT1
7605#define ADCTRL_ARDYM BIT0
7606#define ADCTRL_MASK_ALL (ADCTRL_SLPENDM | ADCTRL_PENDM | ADCTRL_PENUM \
7607 | ADCTRL_DTCHM | ADCTRL_VRDYM | ADCTRL_ARDYM)
7608
7609/* ADC Status Register (ADSTATE) */
7610#define ADSTATE_SLP_RDY BIT7
7611#define ADSTATE_SLPEND BIT5
7612#define ADSTATE_PEND BIT4
7613#define ADSTATE_PENU BIT3
7614#define ADSTATE_DTCH BIT2
7615#define ADSTATE_VRDY BIT1
7616#define ADSTATE_ARDY BIT0
7617
7618/* ADC Same Point Time Register (ADSAME) */
7619#define ADSAME_SCNT_LSB 0
7620#define ADSAME_SCNT_MASK BITS_H2L(15, ADSAME_SCNT_LSB)
7621
7622/* ADC Wait Pen Down Time Register (ADWAIT) */
7623#define ADWAIT_WCNT_LSB 0
7624#define ADWAIT_WCNT_MASK BITS_H2L(15, ADWAIT_WCNT_LSB)
7625
7626/* ADC Touch Screen Data Register (ADTCH) */
7627#define ADTCH_TYPE1 BIT31
7628#define ADTCH_TYPE0 BIT15
7629
7630#define ADTCH_DATA1_LSB 16
7631#define ADTCH_DATA1_MASK BITS_H2L(27, ADTCH_DATA1_LSB)
7632
7633#define ADTCH_DATA0_LSB 0
7634#define ADTCH_DATA0_MASK BITS_H2L(11, ADTCH_DATA0_LSB)
7635
7636/* ADC VBAT Date Register (ADVDAT) */
7637#define ADVDAT_VDATA_LSB 0
7638#define ADVDAT_VDATA_MASK BITS_H2L(11, ADVDAT_VDATA_LSB)
7639
7640/* ADC AUX Data Register (ADADAT) */
7641#define ADADAT_ADATA_LSB 0
7642#define ADADAT_ADATA_MASK BITS_H2L(11, ADADAT_ADATA_LSB)
7643
7644/* ADC Clock Divide Register (ADCLK) */
7645#define ADCLK_CLKDIV_MS_LSB 16
7646#define ADCLK_CLKDIV_MS_MASK BITS_H2L(31, ADCLK_CLKDIV_MS_LSB)
7647
7648#define ADCLK_CLKDIV_US_LSB 8
7649#define ADCLK_CLKDIV_US_MASK BITS_H2L(15, ADCLK_CLKDIV_US_LSB)
7650
7651#define ADCLK_CLKDIV_LSB 0
7652#define ADCLK_CLKDIV_MASK BITS_H2L(7, ADCLK_CLKDIV_LSB)
7653
7654/* ADC Filter Register (ADFLT) */
7655#define ADFLT_FLT_EN BIT15
7656
7657#define ADFLT_FLT_D_LSB 0
7658#define ADFLT_FLT_D_MASK BITS_H2L(11, ADFLT_FLT_D_LSB)
7659
7660#ifndef __MIPS_ASSEMBLER
7661
7662#define REG_SADC_ADENA REG8(SADC_ADENA)
7663#define REG_SADC_ADCFG REG32(SADC_ADCFG)
7664#define REG_SADC_ADCTRL REG8(SADC_ADCTRL)
7665#define REG_SADC_ADSTATE REG8(SADC_ADSTATE)
7666#define REG_SADC_ADSAME REG16(SADC_ADSAME)
7667#define REG_SADC_ADWAIT REG16(SADC_ADWAIT)
7668#define REG_SADC_ADTCH REG32(SADC_ADTCH)
7669#define REG_SADC_ADVDAT REG16(SADC_ADVDAT)
7670#define REG_SADC_ADADAT REG16(SADC_ADADAT)
7671#define REG_SADC_ADFLT REG16(SADC_ADFLT)
7672#define REG_SADC_ADCLK REG32(SADC_ADCLK)
7673
7674#endif /* __MIPS_ASSEMBLER */
7675
7676#define SCC_BASE 0xB0040000
7677
7678/*************************************************************************
7679 * SCC
7680 *************************************************************************/
7681#define SCC_DR (SCC_BASE + 0x000)
7682#define SCC_FDR (SCC_BASE + 0x004)
7683#define SCC_CR (SCC_BASE + 0x008)
7684#define SCC_SR (SCC_BASE + 0x00C)
7685#define SCC_TFR (SCC_BASE + 0x010)
7686#define SCC_EGTR (SCC_BASE + 0x014)
7687#define SCC_ECR (SCC_BASE + 0x018)
7688#define SCC_RTOR (SCC_BASE + 0x01C)
7689
7690#define REG_SCC_DR REG8(SCC_DR)
7691#define REG_SCC_FDR REG8(SCC_FDR)
7692#define REG_SCC_CR REG32(SCC_CR)
7693#define REG_SCC_SR REG16(SCC_SR)
7694#define REG_SCC_TFR REG16(SCC_TFR)
7695#define REG_SCC_EGTR REG8(SCC_EGTR)
7696#define REG_SCC_ECR REG32(SCC_ECR)
7697#define REG_SCC_RTOR REG8(SCC_RTOR)
7698
7699/* SCC FIFO Data Count Register (SCC_FDR) */
7700
7701#define SCC_FDR_EMPTY 0x00
7702#define SCC_FDR_FULL 0x10
7703
7704/* SCC Control Register (SCC_CR) */
7705
7706#define SCC_CR_SCCE (1 << 31)
7707#define SCC_CR_TRS (1 << 30)
7708#define SCC_CR_T2R (1 << 29)
7709#define SCC_CR_FDIV_BIT 24
7710#define SCC_CR_FDIV_MASK (0x3 << SCC_CR_FDIV_BIT)
7711 #define SCC_CR_FDIV_1 (0 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is the same as device clock */
7712 #define SCC_CR_FDIV_2 (1 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is half of device clock */
7713#define SCC_CR_FLUSH (1 << 23)
7714#define SCC_CR_TRIG_BIT 16
7715#define SCC_CR_TRIG_MASK (0x3 << SCC_CR_TRIG_BIT)
7716 #define SCC_CR_TRIG_1 (0 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 1 */
7717 #define SCC_CR_TRIG_4 (1 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 4 */
7718 #define SCC_CR_TRIG_8 (2 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 8 */
7719 #define SCC_CR_TRIG_14 (3 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 14 */
7720#define SCC_CR_TP (1 << 15)
7721#define SCC_CR_CONV (1 << 14)
7722#define SCC_CR_TXIE (1 << 13)
7723#define SCC_CR_RXIE (1 << 12)
7724#define SCC_CR_TENDIE (1 << 11)
7725#define SCC_CR_RTOIE (1 << 10)
7726#define SCC_CR_ECIE (1 << 9)
7727#define SCC_CR_EPIE (1 << 8)
7728#define SCC_CR_RETIE (1 << 7)
7729#define SCC_CR_EOIE (1 << 6)
7730#define SCC_CR_TSEND (1 << 3)
7731#define SCC_CR_PX_BIT 1
7732#define SCC_CR_PX_MASK (0x3 << SCC_CR_PX_BIT)
7733 #define SCC_CR_PX_NOT_SUPPORT (0 << SCC_CR_PX_BIT) /* SCC does not support clock stop */
7734 #define SCC_CR_PX_STOP_LOW (1 << SCC_CR_PX_BIT) /* SCC_CLK stops at state low */
7735 #define SCC_CR_PX_STOP_HIGH (2 << SCC_CR_PX_BIT) /* SCC_CLK stops at state high */
7736#define SCC_CR_CLKSTP (1 << 0)
7737
7738/* SCC Status Register (SCC_SR) */
7739
7740#define SCC_SR_TRANS (1 << 15)
7741#define SCC_SR_ORER (1 << 12)
7742#define SCC_SR_RTO (1 << 11)
7743#define SCC_SR_PER (1 << 10)
7744#define SCC_SR_TFTG (1 << 9)
7745#define SCC_SR_RFTG (1 << 8)
7746#define SCC_SR_TEND (1 << 7)
7747#define SCC_SR_RETR_3 (1 << 4)
7748#define SCC_SR_ECNTO (1 << 0)
7749
7750#ifndef __MIPS_ASSEMBLER
7751
7752/***************************************************************************
7753 * SCC
7754 ***************************************************************************/
7755
7756#define __scc_enable() ( REG_SCC_CR |= SCC_CR_SCCE )
7757#define __scc_disable() ( REG_SCC_CR &= ~SCC_CR_SCCE )
7758
7759#define __scc_set_tx_mode() ( REG_SCC_CR |= SCC_CR_TRS )
7760#define __scc_set_rx_mode() ( REG_SCC_CR &= ~SCC_CR_TRS )
7761
7762#define __scc_enable_t2r() ( REG_SCC_CR |= SCC_CR_T2R )
7763#define __scc_disable_t2r() ( REG_SCC_CR &= ~SCC_CR_T2R )
7764
7765#define __scc_clk_as_devclk() \
7766do { \
7767 REG_SCC_CR &= ~SCC_CR_FDIV_MASK; \
7768 REG_SCC_CR |= SCC_CR_FDIV_1; \
7769} while (0)
7770
7771#define __scc_clk_as_half_devclk() \
7772do { \
7773 REG_SCC_CR &= ~SCC_CR_FDIV_MASK; \
7774 REG_SCC_CR |= SCC_CR_FDIV_2; \
7775} while (0)
7776
7777/* n=1,4,8,14 */
7778#define __scc_set_fifo_trigger(n) \
7779do { \
7780 REG_SCC_CR &= ~SCC_CR_TRIG_MASK; \
7781 REG_SCC_CR |= SCC_CR_TRIG_##n; \
7782} while (0)
7783
7784#define __scc_set_protocol(p) \
7785do { \
7786 if (p) \
7787 REG_SCC_CR |= SCC_CR_TP; \
7788 else \
7789 REG_SCC_CR &= ~SCC_CR_TP; \
7790} while (0)
7791
7792#define __scc_flush_fifo() ( REG_SCC_CR |= SCC_CR_FLUSH )
7793
7794#define __scc_set_invert_mode() ( REG_SCC_CR |= SCC_CR_CONV )
7795#define __scc_set_direct_mode() ( REG_SCC_CR &= ~SCC_CR_CONV )
7796
7797#define SCC_ERR_INTRS \
7798 ( SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE )
7799#define SCC_ALL_INTRS \
7800 ( SCC_CR_TXIE | SCC_CR_RXIE | SCC_CR_TENDIE | SCC_CR_RTOIE | \
7801 SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE )
7802
7803#define __scc_enable_err_intrs() ( REG_SCC_CR |= SCC_ERR_INTRS )
7804#define __scc_disable_err_intrs() ( REG_SCC_CR &= ~SCC_ERR_INTRS )
7805
7806#define SCC_ALL_ERRORS \
7807 ( SCC_SR_ORER | SCC_SR_RTO | SCC_SR_PER | SCC_SR_RETR_3 | SCC_SR_ECNTO)
7808
7809#define __scc_clear_errors() ( REG_SCC_SR &= ~SCC_ALL_ERRORS )
7810
7811#define __scc_enable_all_intrs() ( REG_SCC_CR |= SCC_ALL_INTRS )
7812#define __scc_disable_all_intrs() ( REG_SCC_CR &= ~SCC_ALL_INTRS )
7813
7814#define __scc_enable_tx_intr() ( REG_SCC_CR |= SCC_CR_TXIE | SCC_CR_TENDIE )
7815#define __scc_disable_tx_intr() ( REG_SCC_CR &= ~(SCC_CR_TXIE | SCC_CR_TENDIE) )
7816
7817#define __scc_enable_rx_intr() ( REG_SCC_CR |= SCC_CR_RXIE)
7818#define __scc_disable_rx_intr() ( REG_SCC_CR &= ~SCC_CR_RXIE)
7819
7820#define __scc_set_tsend() ( REG_SCC_CR |= SCC_CR_TSEND )
7821#define __scc_clear_tsend() ( REG_SCC_CR &= ~SCC_CR_TSEND )
7822
7823#define __scc_set_clockstop() ( REG_SCC_CR |= SCC_CR_CLKSTP )
7824#define __scc_clear_clockstop() ( REG_SCC_CR &= ~SCC_CR_CLKSTP )
7825
7826#define __scc_clockstop_low() \
7827do { \
7828 REG_SCC_CR &= ~SCC_CR_PX_MASK; \
7829 REG_SCC_CR |= SCC_CR_PX_STOP_LOW; \
7830} while (0)
7831
7832#define __scc_clockstop_high() \
7833do { \
7834 REG_SCC_CR &= ~SCC_CR_PX_MASK; \
7835 REG_SCC_CR |= SCC_CR_PX_STOP_HIGH; \
7836} while (0)
7837
7838/* SCC status checking */
7839#define __scc_check_transfer_status() ( REG_SCC_SR & SCC_SR_TRANS )
7840#define __scc_check_rx_overrun_error() ( REG_SCC_SR & SCC_SR_ORER )
7841#define __scc_check_rx_timeout() ( REG_SCC_SR & SCC_SR_RTO )
7842#define __scc_check_parity_error() ( REG_SCC_SR & SCC_SR_PER )
7843#define __scc_check_txfifo_trigger() ( REG_SCC_SR & SCC_SR_TFTG )
7844#define __scc_check_rxfifo_trigger() ( REG_SCC_SR & SCC_SR_RFTG )
7845#define __scc_check_tx_end() ( REG_SCC_SR & SCC_SR_TEND )
7846#define __scc_check_retx_3() ( REG_SCC_SR & SCC_SR_RETR_3 )
7847#define __scc_check_ecnt_overflow() ( REG_SCC_SR & SCC_SR_ECNTO )
7848
7849#endif /* __MIPS_ASSEMBLER */
7850
7851#define SSI0_BASE 0xB0043000
7852#define SSI1_BASE 0xB0044000
7853#define SSI2_BASE 0xB0045000
7854
7855/*************************************************************************
7856 * SSI (Synchronous Serial Interface)
7857 *************************************************************************/
7858/* n = 0, 1 (SSI0, SSI1) */
7859#define SSI_DR(n) (SSI0_BASE + 0x000 + (n)*0x1000)
7860#define SSI_CR0(n) (SSI0_BASE + 0x004 + (n)*0x1000)
7861#define SSI_CR1(n) (SSI0_BASE + 0x008 + (n)*0x1000)
7862#define SSI_SR(n) (SSI0_BASE + 0x00C + (n)*0x1000)
7863#define SSI_ITR(n) (SSI0_BASE + 0x010 + (n)*0x1000)
7864#define SSI_ICR(n) (SSI0_BASE + 0x014 + (n)*0x1000)
7865#define SSI_GR(n) (SSI0_BASE + 0x018 + (n)*0x1000)
7866
7867#define REG_SSI_DR(n) REG32(SSI_DR(n))
7868#define REG_SSI_CR0(n) REG16(SSI_CR0(n))
7869#define REG_SSI_CR1(n) REG32(SSI_CR1(n))
7870#define REG_SSI_SR(n) REG32(SSI_SR(n))
7871#define REG_SSI_ITR(n) REG16(SSI_ITR(n))
7872#define REG_SSI_ICR(n) REG8(SSI_ICR(n))
7873#define REG_SSI_GR(n) REG16(SSI_GR(n))
7874
7875/* SSI Data Register (SSI_DR) */
7876
7877#define SSI_DR_GPC_BIT 0
7878#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
7879
7880#define SSI_MAX_FIFO_ENTRIES 128 /* 128 txfifo and 128 rxfifo */
7881
7882/* SSI Control Register 0 (SSI_CR0) */
7883
7884#define SSI_CR0_SSIE (1 << 15)
7885#define SSI_CR0_TIE (1 << 14)
7886#define SSI_CR0_RIE (1 << 13)
7887#define SSI_CR0_TEIE (1 << 12)
7888#define SSI_CR0_REIE (1 << 11)
7889#define SSI_CR0_LOOP (1 << 10)
7890#define SSI_CR0_RFINE (1 << 9)
7891#define SSI_CR0_RFINC (1 << 8)
7892#define SSI_CR0_EACLRUN (1 << 7) /* hardware auto clear underrun when TxFifo no empty */
7893#define SSI_CR0_FSEL (1 << 6)
7894#define SSI_CR0_TFLUSH (1 << 2)
7895#define SSI_CR0_RFLUSH (1 << 1)
7896#define SSI_CR0_DISREV (1 << 0)
7897
7898/* SSI Control Register 1 (SSI_CR1) */
7899
7900#define SSI_CR1_FRMHL_BIT 30
7901#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
7902 #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
7903 #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
7904 #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
7905 #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
7906#define SSI_CR1_TFVCK_BIT 28
7907#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
7908 #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
7909 #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
7910 #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
7911 #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
7912#define SSI_CR1_TCKFI_BIT 26
7913#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
7914 #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
7915 #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
7916 #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
7917 #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
7918#define SSI_CR1_LFST (1 << 25)
7919#define SSI_CR1_ITFRM (1 << 24)
7920#define SSI_CR1_UNFIN (1 << 23)
7921#define SSI_CR1_MULTS (1 << 22)
7922#define SSI_CR1_FMAT_BIT 20
7923#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
7924 #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
7925 #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
7926 #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
7927 #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
7928#define SSI_CR1_TTRG_BIT 16 /* SSI1 TX trigger */
7929#define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT)
7930#define SSI_CR1_MCOM_BIT 12
7931#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
7932 #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
7933 #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
7934 #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
7935 #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
7936 #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
7937 #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
7938 #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
7939 #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
7940 #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
7941 #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
7942 #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
7943 #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
7944 #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
7945 #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
7946 #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
7947 #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
7948#define SSI_CR1_RTRG_BIT 8 /* SSI RX trigger */
7949#define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT)
7950#define SSI_CR1_FLEN_BIT 4
7951#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
7952 #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
7953 #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
7954 #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
7955 #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
7956 #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
7957 #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
7958 #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
7959 #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
7960 #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
7961 #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
7962 #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
7963 #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
7964 #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
7965 #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
7966 #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
7967 #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
7968#define SSI_CR1_PHA (1 << 1)
7969#define SSI_CR1_POL (1 << 0)
7970
7971/* SSI Status Register (SSI_SR) */
7972
7973#define SSI_SR_TFIFONUM_BIT 16
7974#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT)
7975#define SSI_SR_RFIFONUM_BIT 8
7976#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT)
7977#define SSI_SR_END (1 << 7)
7978#define SSI_SR_BUSY (1 << 6)
7979#define SSI_SR_TFF (1 << 5)
7980#define SSI_SR_RFE (1 << 4)
7981#define SSI_SR_TFHE (1 << 3)
7982#define SSI_SR_RFHF (1 << 2)
7983#define SSI_SR_UNDR (1 << 1)
7984#define SSI_SR_OVER (1 << 0)
7985
7986/* SSI Interval Time Control Register (SSI_ITR) */
7987
7988#define SSI_ITR_CNTCLK (1 << 15)
7989#define SSI_ITR_IVLTM_BIT 0
7990#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
7991
7992/*
7993 * SSI Character-per-frame Control Register (SSI_ICR)
7994 * SSI_ICR is ignored for SSI_ICR1.FMT != 00b
7995*/
7996
7997#ifndef __MIPS_ASSEMBLER
7998
7999/***************************************************************************
8000 * SSI (Synchronous Serial Interface)
8001 ***************************************************************************/
8002/* n = 0, 1 (SSI0, SSI1) */
8003#define __ssi_enable(n) ( REG_SSI_CR0(n) |= SSI_CR0_SSIE )
8004#define __ssi_disable(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_SSIE )
8005#define __ssi_select_ce(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_FSEL )
8006
8007#define __ssi_normal_mode(n) ( REG_SSI_ITR(n) &= ~SSI_ITR_IVLTM_MASK )
8008
8009#define __ssi_select_ce2(n) \
8010do { \
8011 REG_SSI_CR0(n) |= SSI_CR0_FSEL; \
8012 REG_SSI_CR1(n) &= ~SSI_CR1_MULTS; \
8013} while (0)
8014
8015#define __ssi_select_gpc(n) \
8016do { \
8017 REG_SSI_CR0(n) &= ~SSI_CR0_FSEL; \
8018 REG_SSI_CR1(n) |= SSI_CR1_MULTS; \
8019} while (0)
8020
8021#define __ssi_underrun_auto_clear(n) \
8022do { \
8023 REG_SSI_CR0(n) |= SSI_CR0_EACLRUN; \
8024} while (0)
8025
8026#define __ssi_underrun_clear_manually(n) \
8027do { \
8028 REG_SSI_CR0(n) &= ~SSI_CR0_EACLRUN; \
8029} while (0)
8030
8031#define __ssi_enable_tx_intr(n) \
8032 ( REG_SSI_CR0(n) |= SSI_CR0_TIE | SSI_CR0_TEIE )
8033
8034#define __ssi_disable_tx_intr(n) \
8035 ( REG_SSI_CR0(n) &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
8036
8037#define __ssi_enable_rx_intr(n) \
8038 ( REG_SSI_CR0(n) |= SSI_CR0_RIE | SSI_CR0_REIE )
8039
8040#define __ssi_disable_rx_intr(n) \
8041 ( REG_SSI_CR0(n) &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )
8042
8043#define __ssi_enable_txfifo_half_empty_intr(n) \
8044 ( REG_SSI_CR0(n) |= SSI_CR0_TIE )
8045#define __ssi_disable_txfifo_half_empty_intr(n) \
8046 ( REG_SSI_CR0(n) &= ~SSI_CR0_TIE )
8047#define __ssi_enable_tx_error_intr(n) \
8048 ( REG_SSI_CR0(n) |= SSI_CR0_TEIE )
8049#define __ssi_disable_tx_error_intr(n) \
8050 ( REG_SSI_CR0(n) &= ~SSI_CR0_TEIE )
8051#define __ssi_enable_rxfifo_half_full_intr(n) \
8052 ( REG_SSI_CR0(n) |= SSI_CR0_RIE )
8053#define __ssi_disable_rxfifo_half_full_intr(n) \
8054 ( REG_SSI_CR0(n) &= ~SSI_CR0_RIE )
8055#define __ssi_enable_rx_error_intr(n) \
8056 ( REG_SSI_CR0(n) |= SSI_CR0_REIE )
8057#define __ssi_disable_rx_error_intr(n) \
8058 ( REG_SSI_CR0(n) &= ~SSI_CR0_REIE )
8059
8060#define __ssi_enable_loopback(n) ( REG_SSI_CR0(n) |= SSI_CR0_LOOP )
8061#define __ssi_disable_loopback(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_LOOP )
8062
8063#define __ssi_enable_receive(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_DISREV )
8064#define __ssi_disable_receive(n) ( REG_SSI_CR0(n) |= SSI_CR0_DISREV )
8065
8066#define __ssi_finish_receive(n) \
8067 ( REG_SSI_CR0(n) |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )
8068
8069#define __ssi_disable_recvfinish(n) \
8070 ( REG_SSI_CR0(n) &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )
8071
8072#define __ssi_flush_txfifo(n) ( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH )
8073#define __ssi_flush_rxfifo(n) ( REG_SSI_CR0(n) |= SSI_CR0_RFLUSH )
8074
8075#define __ssi_flush_fifo(n) \
8076 ( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )
8077
8078#define __ssi_finish_transmit(n) ( REG_SSI_CR1(n) &= ~SSI_CR1_UNFIN )
8079#define __ssi_wait_transmit(n) ( REG_SSI_CR1(n) |= SSI_CR1_UNFIN )
8080#define __ssi_use_busy_wait_mode(n) __ssi_wait_transmit(n)
8081#define __ssi_unset_busy_wait_mode(n) __ssi_finish_transmit(n)
8082
8083#define __ssi_spi_format(n) \
8084 do { \
8085 REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK; \
8086 REG_SSI_CR1(n) |= SSI_CR1_FMAT_SPI; \
8087 REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \
8088 REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \
8089 } while (0)
8090
8091/* TI's SSP format, must clear SSI_CR1.UNFIN */
8092#define __ssi_ssp_format(n) \
8093 do { \
8094 REG_SSI_CR1(n) &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \
8095 REG_SSI_CR1(n) |= SSI_CR1_FMAT_SSP; \
8096 } while (0)
8097
8098/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */
8099#define __ssi_microwire_format(n) \
8100 do { \
8101 REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK; \
8102 REG_SSI_CR1(n) |= SSI_CR1_FMAT_MW1; \
8103 REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \
8104 REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \
8105 REG_SSI_CR0(n) &= ~SSI_CR0_RFINE; \
8106 } while (0)
8107
8108/* CE# level (FRMHL), CE# in interval time (ITFRM),
8109 clock phase and polarity (PHA POL),
8110 interval time (SSIITR), interval characters/frame (SSIICR) */
8111
8112/* frmhl,endian,mcom,flen,pha,pol MASK */
8113#define SSICR1_MISC_MASK \
8114 ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \
8115 | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL )
8116
8117#define __ssi_spi_set_misc(n,frmhl,endian,flen,mcom,pha,pol) \
8118 do { \
8119 REG_SSI_CR1(n) &= ~SSICR1_MISC_MASK; \
8120 REG_SSI_CR1(n) |= ((frmhl) << 30) | ((endian) << 25) | \
8121 (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \
8122 ((pha) << 1) | (pol); \
8123 } while(0)
8124
8125/* Transfer with MSB or LSB first */
8126#define __ssi_set_msb(n) ( REG_SSI_CR1(n) &= ~SSI_CR1_LFST )
8127#define __ssi_set_lsb(n) ( REG_SSI_CR1(n) |= SSI_CR1_LFST )
8128
8129#define __ssi_set_frame_length(n, m) \
8130 REG_SSI_CR1(n) = (REG_SSI_CR1(n) & ~SSI_CR1_FLEN_MASK) | (((m) - 2) << 4)
8131
8132/* m = 1 - 16 */
8133#define __ssi_set_microwire_command_length(n,m) \
8134 ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##m##BIT) )
8135
8136/* Set the clock phase for SPI */
8137#define __ssi_set_spi_clock_phase(n, m) \
8138 ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_PHA) | (((m)&0x1)<< 1)))
8139
8140/* Set the clock polarity for SPI */
8141#define __ssi_set_spi_clock_polarity(n, p) \
8142 ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_POL) | ((p)&0x1)) )
8143
8144/* SSI tx trigger, m = i x 8 */
8145#define __ssi_set_tx_trigger(n, m) \
8146 do { \
8147 REG_SSI_CR1(n) &= ~SSI_CR1_TTRG_MASK; \
8148 REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_TTRG_BIT; \
8149 } while (0)
8150
8151/* SSI rx trigger, m = i x 8 */
8152#define __ssi_set_rx_trigger(n, m) \
8153 do { \
8154 REG_SSI_CR1(n) &= ~SSI_CR1_RTRG_MASK; \
8155 REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_RTRG_BIT; \
8156 } while (0)
8157
8158#define __ssi_get_txfifo_count(n) \
8159 ( (REG_SSI_SR(n) & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )
8160
8161#define __ssi_get_rxfifo_count(n) \
8162 ( (REG_SSI_SR(n) & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )
8163
8164#define __ssi_transfer_end(n) ( REG_SSI_SR(n) & SSI_SR_END )
8165#define __ssi_is_busy(n) ( REG_SSI_SR(n) & SSI_SR_BUSY )
8166
8167#define __ssi_txfifo_full(n) ( REG_SSI_SR(n) & SSI_SR_TFF )
8168#define __ssi_rxfifo_empty(n) ( REG_SSI_SR(n) & SSI_SR_RFE )
8169#define __ssi_rxfifo_half_full(n) ( REG_SSI_SR(n) & SSI_SR_RFHF )
8170#define __ssi_txfifo_half_empty(n) ( REG_SSI_SR(n) & SSI_SR_TFHE )
8171#define __ssi_underrun(n) ( REG_SSI_SR(n) & SSI_SR_UNDR )
8172#define __ssi_overrun(n) ( REG_SSI_SR(n) & SSI_SR_OVER )
8173#define __ssi_clear_underrun(n) ( REG_SSI_SR(n) = ~SSI_SR_UNDR )
8174#define __ssi_clear_overrun(n) ( REG_SSI_SR(n) = ~SSI_SR_OVER )
8175#define __ssi_clear_errors(n) ( REG_SSI_SR(n) &= ~(SSI_SR_UNDR | SSI_SR_OVER) )
8176
8177#define __ssi_set_clk(n, dev_clk, ssi_clk) \
8178 ( REG_SSI_GR(n) = (dev_clk) / (2*(ssi_clk)) - 1 )
8179
8180#define __ssi_receive_data(n) REG_SSI_DR(n)
8181#define __ssi_transmit_data(n, v) (REG_SSI_DR(n) = (v))
8182
8183#endif /* __MIPS_ASSEMBLER */
8184
8185/*
8186 * Timer and counter unit module(TCU) address definition
8187 */
8188#define TCU_BASE 0xb0002000
8189
8190/* TCU group offset */
8191#define TCU_GOS 0x10
8192
8193/* TCU total channel number */
8194#define TCU_CHANNEL_NUM 8
8195
8196/*
8197 * TCU registers offset definition
8198 */
8199#define TCU_TER_OFFSET (0x10) /* r, 16, 0x0000 */
8200#define TCU_TESR_OFFSET (0x14) /* w, 16, 0x???? */
8201#define TCU_TECR_OFFSET (0x18) /* w, 16, 0x???? */
8202
8203#define TCU_TSR_OFFSET (0x1c) /* r, 32, 0x00000000 */
8204#define TCU_TSSR_OFFSET (0x2c) /* w, 32, 0x00000000 */
8205#define TCU_TSCR_OFFSET (0x3c) /* w, 32, 0x0000 */
8206
8207#define TCU_TFR_OFFSET (0x20) /* r, 32, 0x003F003F */
8208#define TCU_TFSR_OFFSET (0x24) /* w, 32, 0x???????? */
8209#define TCU_TFCR_OFFSET (0x28) /* w, 32, 0x???????? */
8210
8211#define TCU_TMR_OFFSET (0x30) /* r, 32, 0x00000000 */
8212#define TCU_TMSR_OFFSET (0x34) /* w, 32, 0x???????? */
8213#define TCU_TMCR_OFFSET (0x38) /* w, 32, 0x???????? */
8214
8215#define TCU_TSTR_OFFSET (0xf0) /* r, 32, 0x00000000 */
8216#define TCU_TSTSR_OFFSET (0xf4) /* w, 32, 0x???????? */
8217#define TCU_TSTCR_OFFSET (0xf8) /* w, 32, 0x???????? */
8218
8219#define TCU_TDFR_OFFSET (0x40) /* rw,16, 0x???? */
8220#define TCU_TDHR_OFFSET (0x44) /* rw,16, 0x???? */
8221#define TCU_TCNT_OFFSET (0x48) /* rw,16, 0x???? */
8222#define TCU_TCSR_OFFSET (0x4c) /* rw,16, 0x0000 */
8223
8224/*
8225 * TCU registers address definition
8226 */
8227#define TCU_TER (TCU_BASE + TCU_TER_OFFSET)
8228#define TCU_TESR (TCU_BASE + TCU_TESR_OFFSET)
8229#define TCU_TECR (TCU_BASE + TCU_TECR_OFFSET)
8230#define TCU_TSR (TCU_BASE + TCU_TSR_OFFSET)
8231#define TCU_TFR (TCU_BASE + TCU_TFR_OFFSET)
8232#define TCU_TFSR (TCU_BASE + TCU_TFSR_OFFSET)
8233#define TCU_TFCR (TCU_BASE + TCU_TFCR_OFFSET)
8234#define TCU_TSSR (TCU_BASE + TCU_TSSR_OFFSET)
8235#define TCU_TMR (TCU_BASE + TCU_TMR_OFFSET)
8236#define TCU_TMSR (TCU_BASE + TCU_TMSR_OFFSET)
8237#define TCU_TMCR (TCU_BASE + TCU_TMCR_OFFSET)
8238#define TCU_TSCR (TCU_BASE + TCU_TSCR_OFFSET)
8239#define TCU_TSTR (TCU_BASE + TCU_TSTR_OFFSET)
8240#define TCU_TSTSR (TCU_BASE + TCU_TSTSR_OFFSET)
8241#define TCU_TSTCR (TCU_BASE + TCU_TSTCR_OFFSET)
8242
8243/* n is the TCU channel index (0 - 7) */
8244#define TCU_TDFR(n) (TCU_BASE + (n) * TCU_GOS + TCU_TDFR_OFFSET)
8245#define TCU_TDHR(n) (TCU_BASE + (n) * TCU_GOS + TCU_TDHR_OFFSET)
8246#define TCU_TCNT(n) (TCU_BASE + (n) * TCU_GOS + TCU_TCNT_OFFSET)
8247#define TCU_TCSR(n) (TCU_BASE + (n) * TCU_GOS + TCU_TCSR_OFFSET)
8248
8249/*
8250 * TCU registers bit field common define
8251 */
8252
8253/* When n is NOT less than TCU_CHANNEL_NUM, change to TCU_CHANNEL_NUM - 1 */
8254#define __TIMER(n) (1 << ((n) < TCU_CHANNEL_NUM ? (n) : (TCU_CHANNEL_NUM - 1))
8255
8256/* Timer counter enable register(TER) */
8257#define TER_OSTEN BIT15
8258#define TER_TCEN(n) __TIMER(n)
8259
8260/* Timer counter enable set register(TESR) */
8261#define TESR_OST BIT15
8262#define TESR_TIMER(n) __TIMER(n)
8263
8264/* Timer counter enable clear register(TECR) */
8265#define TECR_OST BIT15
8266#define TECR_TIMER(n) __TIMER(n)
8267
8268/* Timer stop register(TSR) */
8269#define TSR_WDT_STOP BIT16
8270#define TSR_OST_STOP BIT15
8271#define TSR_TIMER_STOP(n) __TIMER(n)
8272
8273/* Timer stop set register(TSSR) */
8274#define TSSR_WDT BIT16
8275#define TSSR_OST BIT15
8276#define TSSR_TIMER(n) __TIMER(n)
8277
8278/* Timer stop clear register(TSCR) */
8279#define TSCR_WDT BIT16
8280#define TSCR_OST BIT15
8281#define TSSR_TIMER(n) __TIMER(n)
8282
8283/* Timer flag register(TFR) */
8284#define TFR_HFLAG(n) (__TIMER(n) << 16)
8285#define TFR_OSTFLAG BIT15
8286#define TFR_FFLAG(n) __TIMER(n)
8287
8288/* Timer flag set register(TFSR) */
8289#define TFSR_HFLAG(n) (__TIMER(n) << 16)
8290#define TFSR_OSTFLAG BIT15
8291#define TFSR_FFLAG(n) __TIMER(n)
8292
8293/* Timer flag clear register(TFCR) */
8294#define TFCR_HFLAG(n) (__TIMER(n) << 16)
8295#define TFCR_OSTFLAG BIT15
8296#define TFCR_FFLAG(n) (__TIMER(n))
8297
8298/* Timer mast register(TMR) */
8299#define TMR_HMASK(n) (__TIMER(n) << 16)
8300#define TMR_OSTMASK BIT15
8301#define TMR_FMASK(n) (__TIMER(n))
8302
8303/* Timer mask set register(TMSR) */
8304#define TMSR_HMASK(n) (__TIMER(n) << 16)
8305#define TMSR_OSTMASK BIT15
8306#define TMSR_FMASK(n) (__TIMER(n))
8307
8308/* Timer mask clear register(TMCR) */
8309#define TMCR_HMASK(n) (__TIMER(n) << 16)
8310#define TMCR_OSTMASK BIT15
8311#define TMCR_FMASK(n) (__TIMER(n))
8312
8313/* Timer control register(TCSR) */
8314#define TCSR_BYPASS BIT11
8315#define TCSR_CLRZ BIT10
8316#define TCSR_SD_ABRUPT BIT9
8317#define TCSR_INITL_HIGH BIT8
8318#define TCSR_PWM_EN BIT7
8319#define TCSR_PWM_IN_EN BIT6
8320#define TCSR_EXT_EN BIT2
8321#define TCSR_RTC_EN BIT1
8322#define TCSR_PCK_EN BIT0
8323
8324#define TCSR_PRESCALE_LSB 3
8325#define TCSR_PRESCALE_MASK BITS_H2L(5, TCSR_PRESCALE_LSB)
8326#define TCSR_PRESCALE1 (0x0 << TCSR_PRESCALE_LSB)
8327#define TCSR_PRESCALE4 (0x1 << TCSR_PRESCALE_LSB)
8328#define TCSR_PRESCALE16 (0x2 << TCSR_PRESCALE_LSB)
8329#define TCSR_PRESCALE64 (0x3 << TCSR_PRESCALE_LSB)
8330#define TCSR_PRESCALE256 (0x4 << TCSR_PRESCALE_LSB)
8331#define TCSR_PRESCALE1024 (0x5 << TCSR_PRESCALE_LSB)
8332
8333/* Timer data full register(TDFR) */
8334#define TDFR_TDFR_LSB 0
8335#define TDFR_TDFR_MASK BITS_H2L(15, TDFR_TDFR_LSB)
8336
8337/* Timer data half register(TDHR) */
8338#define TDHR_TDHR_LSB 0
8339#define TDHR_TDHR_MASK BITS_H2L(15, TDHR_TDHR_LSB)
8340
8341/* Timer counter register(TCNT) */
8342#define TCNT_TCNT_LSB 0
8343#define TCNT_TCNT_MASK BITS_H2L(15, TCNT_TCNT_LSB)
8344
8345/* Timer status register(TSTR) */
8346#define TSTR_REAL2 BIT18
8347#define TSTR_REAL1 BIT17
8348#define TSTR_BUSY2 BIT2
8349#define TSTR_BUSY1 BIT1
8350
8351/* Timer status set register(TSTSR) */
8352#define TSTSR_REALS2 BIT18
8353#define TSTSR_REALS1 BIT17
8354#define TSTSR_BUSYS2 BIT2
8355#define TSTSR_BUSYS1 BIT1
8356
8357/* Timer status clear register(TSTCR) */
8358#define TSTCR_REALC2 BIT18
8359#define TSTCR_REALC1 BIT17
8360#define TSTCR_BUSYC2 BIT2
8361#define TSTCR_BUSYC1 BIT1
8362
8363#ifndef __MIPS_ASSEMBLER
8364
8365#define REG_TCU_TER REG16(TCU_TER)
8366#define REG_TCU_TESR REG16(TCU_TESR)
8367#define REG_TCU_TECR REG16(TCU_TECR)
8368#define REG_TCU_TSR REG32(TCU_TSR)
8369#define REG_TCU_TFR REG32(TCU_TFR)
8370#define REG_TCU_TFSR REG32(TCU_TFSR)
8371#define REG_TCU_TFCR REG32(TCU_TFCR)
8372#define REG_TCU_TSSR REG32(TCU_TSSR)
8373#define REG_TCU_TMR REG32(TCU_TMR)
8374#define REG_TCU_TMSR REG32(TCU_TMSR)
8375#define REG_TCU_TMCR REG32(TCU_TMCR)
8376#define REG_TCU_TSCR REG32(TCU_TSCR)
8377#define REG_TCU_TSTR REG32(TCU_TSTR)
8378#define REG_TCU_TSTSR REG32(TCU_TSTSR)
8379#define REG_TCU_TSTCR REG32(TCU_TSTCR)
8380
8381#define REG_TCU_TDFR(n) REG16(TCU_TDFR(n))
8382#define REG_TCU_TDHR(n) REG16(TCU_TDHR(n))
8383#define REG_TCU_TCNT(n) REG16(TCU_TCNT(n))
8384#define REG_TCU_TCSR(n) REG16(TCU_TCSR(n))
8385
8386// where 'n' is the TCU channel
8387#define __tcu_select_extalclk(n) \
8388 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCSR_EXT_EN | TCSR_RTC_EN | TCSR_PCK_EN)) | TCSR_EXT_EN)
8389#define __tcu_select_rtcclk(n) \
8390 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCSR_EXT_EN | TCSR_RTC_EN | TCSR_PCK_EN)) | TCSR_RTC_EN)
8391#define __tcu_select_pclk(n) \
8392 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCSR_EXT_EN | TCSR_RTC_EN | TCSR_PCK_EN)) | TCSR_PCK_EN)
8393#define __tcu_disable_pclk(n) \
8394 REG_TCU_TCSR(n) = (REG_TCU_TCSR((n)) & ~TCSR_PCK_EN);
8395#define __tcu_select_clk_div1(n) \
8396 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE1)
8397#define __tcu_select_clk_div4(n) \
8398 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE4)
8399#define __tcu_select_clk_div16(n) \
8400 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE16)
8401#define __tcu_select_clk_div64(n) \
8402 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE64)
8403#define __tcu_select_clk_div256(n) \
8404 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE256)
8405#define __tcu_select_clk_div1024(n) \
8406 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE1024)
8407
8408#define __tcu_enable_pwm_output(n) (REG_TCU_TCSR((n)) |= TCSR_PWM_EN)
8409#define __tcu_disable_pwm_output(n) (REG_TCU_TCSR((n)) &= ~TCSR_PWM_EN)
8410
8411#define __tcu_init_pwm_output_high(n) (REG_TCU_TCSR((n)) |= TCSR_INITL_HIGH)
8412#define __tcu_init_pwm_output_low(n) (REG_TCU_TCSR((n)) &= ~TCSR_INITL_HIGH)
8413
8414#define __tcu_set_pwm_output_shutdown_graceful(n) (REG_TCU_TCSR((n)) &= ~TCSR_SD_ABRUPT)
8415#define __tcu_set_pwm_output_shutdown_abrupt(n) (REG_TCU_TCSR((n)) |= TCSR_SD_ABRUPT)
8416
8417#define __tcu_clear_counter_to_zero(n) (REG_TCU_TCSR((n)) |= TCSR_CLRZ)
8418
8419#define __tcu_ost_enabled() (REG_TCU_TER & TER_OSTEN)
8420#define __tcu_enable_ost() (REG_TCU_TESR = TESR_OST)
8421#define __tcu_disable_ost() (REG_TCU_TECR = TECR_OST)
8422
8423#define __tcu_counter_enabled(n) (REG_TCU_TER & (1 << (n)))
8424#define __tcu_start_counter(n) (REG_TCU_TESR |= (1 << (n)))
8425#define __tcu_stop_counter(n) (REG_TCU_TECR |= (1 << (n)))
8426
8427#define __tcu_half_match_flag(n) (REG_TCU_TFR & (1 << ((n) + 16)))
8428#define __tcu_full_match_flag(n) (REG_TCU_TFR & (1 << (n)))
8429#define __tcu_set_half_match_flag(n) (REG_TCU_TFSR = (1 << ((n) + 16)))
8430#define __tcu_set_full_match_flag(n) (REG_TCU_TFSR = (1 << (n)))
8431#define __tcu_clear_half_match_flag(n) (REG_TCU_TFCR = (1 << ((n) + 16)))
8432#define __tcu_clear_full_match_flag(n) (REG_TCU_TFCR = (1 << (n)))
8433#define __tcu_mask_half_match_irq(n) (REG_TCU_TMSR = (1 << ((n) + 16)))
8434#define __tcu_mask_full_match_irq(n) (REG_TCU_TMSR = (1 << (n)))
8435#define __tcu_unmask_half_match_irq(n) (REG_TCU_TMCR = (1 << ((n) + 16)))
8436#define __tcu_unmask_full_match_irq(n) (REG_TCU_TMCR = (1 << (n)))
8437
8438#define __tcu_ost_match_flag() (REG_TCU_TFR & TFR_OSTFLAG)
8439#define __tcu_set_ost_match_flag() (REG_TCU_TFSR = TFSR_OSTFLAG)
8440#define __tcu_clear_ost_match_flag() (REG_TCU_TFCR = TFCR_OSTFLAG)
8441#define __tcu_ost_match_irq_masked() (REG_TCU_TMR & TMR_OSTMASK)
8442#define __tcu_mask_ost_match_irq() (REG_TCU_TMSR = TMSR_OSTMASK)
8443#define __tcu_unmask_ost_match_irq() (REG_TCU_TMCR = TMCR_OSTMASK)
8444
8445#define __tcu_wdt_clock_stopped() (REG_TCU_TSR & TSR_WDT_STOP)
8446#define __tcu_ost_clock_stopped() (REG_TCU_TSR & TSR_OST_STOP)
8447#define __tcu_timer_clock_stopped(n) (REG_TCU_TSR & (1 << (n)))
8448
8449#define __tcu_start_wdt_clock() (REG_TCU_TSCR = TSCR_WDT)
8450#define __tcu_start_ost_clock() (REG_TCU_TSCR = TSCR_OST)
8451#define __tcu_start_timer_clock(n) (REG_TCU_TSCR = (1 << (n)))
8452
8453#define __tcu_stop_wdt_clock() (REG_TCU_TSSR = TSSR_WDT)
8454#define __tcu_stop_ost_clock() (REG_TCU_TSSR = TSSR_OST)
8455#define __tcu_stop_timer_clock(n) (REG_TCU_TSSR = (1 << (n)))
8456
8457#define __tcu_get_count(n) (REG_TCU_TCNT((n)))
8458#define __tcu_set_count(n,v) (REG_TCU_TCNT((n)) = (v))
8459#define __tcu_set_full_data(n,v) (REG_TCU_TDFR((n)) = (v))
8460#define __tcu_set_half_data(n,v) (REG_TCU_TDHR((n)) = (v))
8461
8462/* TCU2, counter 1, 2*/
8463#define __tcu_read_real_value(n) (REG_TCU_TSTR & (1 << ((n) + 16)))
8464#define __tcu_read_false_value(n) (REG_TCU_TSTR & (1 << ((n) + 16)))
8465#define __tcu_counter_busy(n) (REG_TCU_TSTR & (1 << (n)))
8466#define __tcu_counter_ready(n) (REG_TCU_TSTR & (1 << (n)))
8467
8468#define __tcu_set_read_real_value(n) (REG_TCU_TSTSR = (1 << ((n) + 16)))
8469#define __tcu_set_read_false_value(n) (REG_TCU_TSTCR = (1 << ((n) + 16)))
8470#define __tcu_set_counter_busy(n) (REG_TCU_TSTSR = (1 << (n)))
8471#define __tcu_set_counter_ready(n) (REG_TCU_TSTCR = (1 << (n)))
8472
8473#endif /* __MIPS_ASSEMBLER */
8474
8475#define TSSI0_BASE 0xB0073000
8476
8477/*************************************************************************
8478 * TSSI MPEG 2-TS slave interface
8479 *************************************************************************/
8480#define TSSI_ENA ( TSSI0_BASE + 0x00 ) /* TSSI enable register */
8481#define TSSI_CFG ( TSSI0_BASE + 0x04 ) /* TSSI configure register */
8482#define TSSI_CTRL ( TSSI0_BASE + 0x08 ) /* TSSI control register */
8483#define TSSI_STAT ( TSSI0_BASE + 0x0c ) /* TSSI state register */
8484#define TSSI_FIFO ( TSSI0_BASE + 0x10 ) /* TSSI FIFO register */
8485#define TSSI_PEN ( TSSI0_BASE + 0x14 ) /* TSSI PID enable register */
8486#define TSSI_NUM ( TSSI0_BASE + 0x18 )
8487#define TSSI_DTR ( TSSI0_BASE + 0x1c )
8488#define TSSI_PID(n) ( TSSI0_BASE + 0x20 + 4*(n) ) /* TSSI PID filter register */
8489#define TSSI_PID0 ( TSSI0_BASE + 0x20 )
8490#define TSSI_PID1 ( TSSI0_BASE + 0x24 )
8491#define TSSI_PID2 ( TSSI0_BASE + 0x28 )
8492#define TSSI_PID3 ( TSSI0_BASE + 0x2c )
8493#define TSSI_PID4 ( TSSI0_BASE + 0x30 )
8494#define TSSI_PID5 ( TSSI0_BASE + 0x34 )
8495#define TSSI_PID6 ( TSSI0_BASE + 0x38 )
8496#define TSSI_PID7 ( TSSI0_BASE + 0x3c )
8497#define TSSI_PID8 ( TSSI0_BASE + 0x40 )
8498#define TSSI_PID9 ( TSSI0_BASE + 0x44 )
8499#define TSSI_PID10 ( TSSI0_BASE + 0x48 )
8500#define TSSI_PID11 ( TSSI0_BASE + 0x4c )
8501#define TSSI_PID12 ( TSSI0_BASE + 0x50 )
8502#define TSSI_PID13 ( TSSI0_BASE + 0x54 )
8503#define TSSI_PID14 ( TSSI0_BASE + 0x58 )
8504#define TSSI_PID15 ( TSSI0_BASE + 0x5c )
8505#define TSSI_PID_MAX 16 /* max PID: 15 */
8506
8507#define TSSI_DDA ( TSSI0_BASE + 0x60 )
8508#define TSSI_DTA ( TSSI0_BASE + 0x64 )
8509#define TSSI_DID ( TSSI0_BASE + 0x68 )
8510#define TSSI_DCMD ( TSSI0_BASE + 0x6c )
8511#define TSSI_DST ( TSSI0_BASE + 0x70 )
8512#define TSSI_TC ( TSSI0_BASE + 0x74 )
8513
8514#define REG_TSSI_ENA REG8( TSSI_ENA )
8515#define REG_TSSI_CFG REG16( TSSI_CFG )
8516#define REG_TSSI_CTRL REG8( TSSI_CTRL )
8517#define REG_TSSI_STAT REG8( TSSI_STAT )
8518#define REG_TSSI_FIFO REG32( TSSI_FIFO )
8519#define REG_TSSI_PEN REG32( TSSI_PEN )
8520#define REG_TSSI_NUM REG32( TSSI_NUM )
8521#define REG_TSSI_DTR REG32( TSSI_DTR )
8522#define REG_TSSI_PID(n) REG32( TSSI_PID(n) )
8523#define REG_TSSI_PID0 REG32( TSSI_PID0 )
8524#define REG_TSSI_PID1 REG32( TSSI_PID1 )
8525#define REG_TSSI_PID2 REG32( TSSI_PID2 )
8526#define REG_TSSI_PID3 REG32( TSSI_PID3 )
8527#define REG_TSSI_PID4 REG32( TSSI_PID4 )
8528#define REG_TSSI_PID5 REG32( TSSI_PID5 )
8529#define REG_TSSI_PID6 REG32( TSSI_PID6 )
8530#define REG_TSSI_PID7 REG32( TSSI_PID7 )
8531#define REG_TSSI_PID8 REG32( TSSI_PID8 )
8532#define REG_TSSI_PID9 REG32( TSSI_PID9 )
8533#define REG_TSSI_PID10 REG32( TSSI_PID10 )
8534#define REG_TSSI_PID11 REG32( TSSI_PID11 )
8535#define REG_TSSI_PID12 REG32( TSSI_PID12 )
8536#define REG_TSSI_PID13 REG32( TSSI_PID13 )
8537#define REG_TSSI_PID14 REG32( TSSI_PID14 )
8538#define REG_TSSI_PID15 REG32( TSSI_PID15 )
8539
8540/* TSSI enable register */
8541#define TSSI_ENA_SFT_RST ( 1 << 7 ) /* soft reset bit */
8542#define TSSI_ENA_PID_EN ( 1 << 2 ) /* soft filtering function enable bit */
8543#define TSSI_ENA_FAIL ( 1 << 4 ) /* fail signal bit */
8544#define TSSI_ENA_PEN_0 ( 1 << 3 ) /* PID filter enable bit for PID */
8545#define TSSI_ENA_DMA_EN ( 1 << 1 ) /* DMA enable bit */
8546#define TSSI_ENA_ENA ( 1 << 0 ) /* TSSI enable bit */
8547
8548/* TSSI configure register */
8549#define TSSI_CFG_TRIG_BIT 14 /* fifo trig number */
8550#define TSSI_CFG_TRIG_MASK ( 0x7 << TSSI_CFG_TRIG_BIT)
8551#define TSSI_CFG_TRIG_4 ( 0 << TSSI_CFG_TRIG_BIT)
8552#define TSSI_CFG_TRIG_8 ( 1 << TSSI_CFG_TRIG_BIT)
8553#define TSSI_CFG_TRIG_16 ( 2 << TSSI_CFG_TRIG_BIT)
8554#define TSSI_CFG_TRIG_32 ( 3 << TSSI_CFG_TRIG_BIT)
8555#define TSSI_CFG_TRIG_48 ( 4 << TSSI_CFG_TRIG_BIT)
8556#define TSSI_CFG_TRIG_64 ( 5 << TSSI_CFG_TRIG_BIT)
8557#define TSSI_CFG_TRIG_80 ( 6 << TSSI_CFG_TRIG_BIT)
8558#define TSSI_CFG_TRIG_96 ( 7 << TSSI_CFG_TRIG_BIT)
8559
8560/* mode of adding data 0 select bit */
8561#define TSSI_CFG_TRANS_MD_BIT 10
8562#define TSSI_CFG_TRANS_MD_MASK ( 0x3 << TSSI_CFG_TRANS_MD_BIT)
8563#define TSSI_CFG_TRANS_MD_0 (0 << TSSI_CFG_TRANS_MD_BIT)
8564#define TSSI_CFG_TRANS_MD_1 (1 << TSSI_CFG_TRANS_MD_BIT)
8565#define TSSI_CFG_TRANS_MD_2 (2 << TSSI_CFG_TRANS_MD_BIT)
8566
8567#define TSSI_CFG_END_WD ( 1 << 9 ) /* order of data in word */
8568#define TSSI_CFG_END_BT ( 1 << 8 ) /* order of data in byte */
8569
8570#define TSSI_CFG_TSDI_H ( 1 << 7 ) /* data pin polarity */
8571#define TSSI_CFG_USE_0 ( 1 << 6 ) /* serial mode data pin select */
8572#define TSSI_CFG_USE_TSDI0 ( 1 << 6 ) /* TSDI0 as serial mode data pin */
8573#define TSSI_CFG_USE_TSDI7 ( 0 << 6 ) /* TSDI7 as serial mode data pin */
8574#define TSSI_CFG_TSCLK_CH ( 1 << 5 ) /* clk channel select */
8575#define TSSI_CFG_PARAL ( 1 << 4 ) /* mode select */
8576#define TSSI_CFG_PARAL_MODE ( 1 << 4 ) /* parallel select */
8577#define TSSI_CFG_SERIAL_MODE ( 0 << 4 ) /* serial select */
8578#define TSSI_CFG_TSCLK_P ( 1 << 3 ) /* clk edge select */
8579#define TSSI_CFG_TSFRM_H ( 1 << 2 ) /* TSFRM polarity select */
8580#define TSSI_CFG_TSSTR_H ( 1 << 1 ) /* TSSTR polarity select */
8581#define TSSI_CFG_TSFAIL_H ( 1 << 0 ) /* TSFAIL polarity select */
8582
8583/* TSSI control register */
8584#define TSSI_CTRL_DTRM ( 1 << 2 ) /* FIFO data trigger interrupt mask bit */
8585#define TSSI_CTRL_OVRNM ( 1 << 1 ) /* FIFO overrun interrupt mask bit */
8586#define TSSI_CTRL_TRIGM ( 1 << 0 ) /* FIFO trigger interrupt mask bit */
8587
8588/* TSSI state register */
8589#define TSSI_STAT_DTR ( 1 << 2 ) /* FIFO data trigger interrupt flag bit */
8590#define TSSI_STAT_OVRN ( 1 << 1 ) /* FIFO overrun interrupt flag bit */
8591#define TSSI_STAT_TRIG ( 1 << 0 ) /* FIFO trigger interrupt flag bit */
8592
8593/* TSSI PID enable register */
8594#define TSSI_PEN_EN00 ( 1 << 0 ) /* enable PID n */
8595#define TSSI_PEN_EN10 ( 1 << 1 )
8596#define TSSI_PEN_EN20 ( 1 << 2 )
8597#define TSSI_PEN_EN30 ( 1 << 3 )
8598#define TSSI_PEN_EN40 ( 1 << 4 )
8599#define TSSI_PEN_EN50 ( 1 << 5 )
8600#define TSSI_PEN_EN60 ( 1 << 6 )
8601#define TSSI_PEN_EN70 ( 1 << 7 )
8602#define TSSI_PEN_EN80 ( 1 << 8 )
8603#define TSSI_PEN_EN90 ( 1 << 9 )
8604#define TSSI_PEN_EN100 ( 1 << 10 )
8605#define TSSI_PEN_EN110 ( 1 << 11 )
8606#define TSSI_PEN_EN120 ( 1 << 12 )
8607#define TSSI_PEN_EN130 ( 1 << 13 )
8608#define TSSI_PEN_EN140 ( 1 << 14 )
8609#define TSSI_PEN_EN150 ( 1 << 15 )
8610#define TSSI_PEN_EN01 ( 1 << 16 )
8611#define TSSI_PEN_EN11 ( 1 << 17 )
8612#define TSSI_PEN_EN21 ( 1 << 18 )
8613#define TSSI_PEN_EN31 ( 1 << 19 )
8614#define TSSI_PEN_EN41 ( 1 << 20 )
8615#define TSSI_PEN_EN51 ( 1 << 21 )
8616#define TSSI_PEN_EN61 ( 1 << 22 )
8617#define TSSI_PEN_EN71 ( 1 << 23 )
8618#define TSSI_PEN_EN81 ( 1 << 24 )
8619#define TSSI_PEN_EN91 ( 1 << 25 )
8620#define TSSI_PEN_EN101 ( 1 << 26 )
8621#define TSSI_PEN_EN111 ( 1 << 27 )
8622#define TSSI_PEN_EN121 ( 1 << 28 )
8623#define TSSI_PEN_EN131 ( 1 << 29 )
8624#define TSSI_PEN_EN141 ( 1 << 30 )
8625#define TSSI_PEN_EN151 ( 1 << 31 )
8626//#define TSSI_PEN_PID0 ( 1 << 31 ) /* PID filter enable PID0 */
8627
8628/* TSSI Data Number Registers */
8629#define TSSI_DNUM_BIT 0
8630#define TSSI_DNUM_MASK (0x7f << TSSI_DNUM_BIT)
8631
8632/* TSSI Data Trigger Register */
8633#define TSSI_DTRG_BIT 0
8634#define TSSI_DTRG_MASK (0x7f << TSSI_DTRG_BIT)
8635
8636/* TSSI PID Filter Registers */
8637#define TSSI_PID_PID1_BIT 16
8638#define TSSI_PID_PID1_MASK (0x1fff<<TSSI_PID_PID1_BIT)
8639#define TSSI_PID_PID0_BIT 0
8640#define TSSI_PID_PID0_MASK (0x1fff<<TSSI_PID_PID0_BIT)
8641
8642/* TSSI DMA Identifier Registers */
8643#define TSSI_DMA_ID_BIT 0
8644#define TSSI_DMA_ID_MASK (0xffff << TSSI_DMA_ID_BIT)
8645
8646/* TSSI DMA Command Registers */
8647#define TSSI_DCMD_TLEN_BIT 8
8648#define TSSI_DCMD_TLEN_MASK (0xff << TSSI_DCMD_TLEN_BIT)
8649#define TSSI_DCMD_TEFE (1 << 4)
8650#define TSSI_DCMD_TSZ_BIT 2
8651#define TSSI_DCMD_TSZ_MASK (0x3 << TSSI_DCMD_TSZ_BIT)
8652#define TSSI_DCMD_TSZ_4 (0 << TSSI_DCMD_TSZ_BIT)
8653#define TSSI_DCMD_TSZ_8 (1 << TSSI_DCMD_TSZ_BIT)
8654#define TSSI_DCMD_TSZ_16 (2 << TSSI_DCMD_TSZ_BIT)
8655#define TSSI_DCMD_TSZ_32 (3 << TSSI_DCMD_TSZ_BIT)
8656#define TSSI_DCMD_TEIE (1 << 1)
8657#define TSSI_DCMD_LINK (1 << 0)
8658
8659/* TSSI DMA Status Registers */
8660#define TSSI_DST_DID_BIT 16
8661#define TSSI_DST_DID_MASK (0xffff << 16)
8662#define TSSI_DST_TEND (1 << 0)
8663
8664/* TSSI Transfer Control Registers */
8665#define TSSI_TC_OP_BIT 4
8666#define TSSI_TC_OP_MASK (0x3 << TSSI_TC_OP_BIT)
8667//////////////////#define TSSI_TC_OP_0 (
8668#define TSSI_TC_OPE (1 << 2)
8669#define TSSI_TC_EME (1 << 1)
8670#define TSSI_TC_APM (1 << 0)
8671#ifndef __MIPS_ASSEMBLER
8672
8673/*************************************************************************
8674 * TSSI MPEG 2-TS slave interface operation
8675 *************************************************************************/
8676#define __tssi_enable() ( REG_TSSI_ENA |= TSSI_ENA_ENA )
8677#define __tssi_disable() ( REG_TSSI_ENA &= ~TSSI_ENA_ENA )
8678#define __tssi_soft_reset() ( REG_TSSI_ENA |= TSSI_ENA_SFT_RST )
8679#define __tssi_filter_enable_pid0() ( REG_TSSI_ENA |= TSSI_ENA_PEN_0)
8680#define __tssi_filter_disable_pid0() ( REG_TSSI_ENA &= ~TSSI_ENA_PEN_0)
8681#define __tssi_dma_enable() ( REG_TSSI_ENA |= TSSI_ENA_DMA_EN )
8682#define __tssi_dma_disable() ( REG_TSSI_ENA &= ~TSSI_ENA_DMA_EN )
8683#define __tssi_filter_enable() ( REG_TSSI_ENA |= TSSI_ENA_PID_EN )
8684#define __tssi_filter_disable() ( REG_TSSI_ENA &= ~TSSI_ENA_PID_EN )
8685
8686/* n = 4, 8, 16 */
8687#define __tssi_set_tigger_num(n) \
8688 do { \
8689 REG_TSSI_CFG &= ~TSSI_CFG_TRIG_MASK; \
8690 REG_TSSI_CFG |= TSSI_CFG_TRIG_##n; \
8691 } while (0)
8692
8693#define __tssi_set_data0_mode(n) \
8694 do { \
8695 REG_TSSI_CFG &= ~ TSSI_CFG_TRANS_MD_MASK; \
8696 REG_TSSI_CFG |= TSSI_CFG_TRANS_MD_##n; \
8697 } while(0)
8698
8699#define __tssi_set_wd_1() ( REG_TSSI_CFG |= TSSI_CFG_END_WD )
8700#define __tssi_set_wd_0() ( REG_TSSI_CFG &= ~TSSI_CFG_END_WD )
8701
8702#define __tssi_set_bt_1() ( REG_TSSI_CFG |= TSSI_CFG_END_BD )
8703#define __tssi_set_bt_0() ( REG_TSSI_CFG &= ~TSSI_CFG_END_BD )
8704
8705#define __tssi_set_data_pola_high() ( REG_TSSI_CFG |= TSSI_CFG_TSDI_H )
8706#define __tssi_set_data_pola_low() ( REG_TSSI_CFG &= ~TSSI_CFG_TSDI_H )
8707
8708#define __tssi_set_data_use_data0() ( REG_TSSI_CFG |= TSSI_CFG_USE_0 )
8709#define __tssi_set_data_use_data7() ( REG_TSSI_CFG &= ~TSSI_CFG_USE_0 )
8710
8711#define __tssi_select_clk_fast() ( REG_TSSI_CFG &= ~TSSI_CFG_TSCLK_CH )
8712#define __tssi_select_clk_slow() ( REG_TSSI_CFG |= TSSI_CFG_TSCLK_CH )
8713
8714#define __tssi_select_serail_mode() ( REG_TSSI_CFG &= ~TSSI_CFG_PARAL )
8715#define __tssi_select_paral_mode() ( REG_TSSI_CFG |= TSSI_CFG_PARAL )
8716
8717#define __tssi_select_clk_nega_edge() ( REG_TSSI_CFG &= ~TSSI_CFG_TSCLK_P )
8718#define __tssi_select_clk_posi_edge() ( REG_TSSI_CFG |= TSSI_CFG_TSCLK_P )
8719
8720#define __tssi_select_frm_act_high() ( REG_TSSI_CFG |= TSSI_CFG_TSFRM_H )
8721#define __tssi_select_frm_act_low() ( REG_TSSI_CFG &= ~TSSI_CFG_TSFRM_H )
8722
8723#define __tssi_select_str_act_high() ( REG_TSSI_CFG |= TSSI_CFG_TSSTR_H )
8724#define __tssi_select_str_act_low() ( REG_TSSI_CFG &= ~TSSI_CFG_TSSTR_H )
8725
8726#define __tssi_select_fail_act_high() ( REG_TSSI_CFG |= TSSI_CFG_TSFAIL_H )
8727#define __tssi_select_fail_act_low() ( REG_TSSI_CFG &= ~TSSI_CFG_TSFAIL_H )
8728
8729#define __tssi_enable_data_trigger_irq() (REG_TSSI_CTRL &= ~TSSI_CTRL_DTRM)
8730#define __tssi_disable_data_trigger_irq() (REG_TSSI_CTRL |= TSSI_CTRL_DTRM)
8731
8732#define __tssi_enable_ovrn_irq() ( REG_TSSI_CTRL &= ~TSSI_CTRL_OVRNM )
8733#define __tssi_disable_ovrn_irq() ( REG_TSSI_CTRL |= TSSI_CTRL_OVRNM )
8734
8735#define __tssi_enable_trig_irq() ( REG_TSSI_CTRL &= ~TSSI_CTRL_TRIGM )
8736#define __tssi_disable_trig_irq() ( REG_TSSI_CTRL |= TSSI_CTRL_TRIGM )
8737
8738#define __tssi_state_is_dtr() ( REG_TSSI_STAT & TSSI_STAT_DTR )
8739#define __tssi_state_is_overrun() ( REG_TSSI_STAT & TSSI_STAT_OVRN )
8740#define __tssi_state_trigger_meet() ( REG_TSSI_STAT & TSSI_STAT_TRIG )
8741#define __tssi_clear_state() ( REG_TSSI_STAT = 0 ) /* write 0??? */
8742#define __tssi_state_clear_overrun() ( REG_TSSI_STAT = TSSI_STAT_OVRN ) //??????? xyma
8743
8744//#define __tssi_enable_filte_pid0() ( REG_TSSI_PEN |= TSSI_PEN_PID0 )
8745//#define __tssi_disable_filte_pid0() ( REG_TSSI_PEN &= ~TSSI_PEN_PID0 )
8746
8747/* m = 0, ..., 31 */
8748////////////////???????????????????????????????????????????????????????????
8749
8750#define __tssi_enable_pid_filter(m) \
8751 do { \
8752 int n = (m); \
8753 if ( n>=0 && n <(TSSI_PID_MAX*2) ) { \
8754 REG_TSSI_PEN |= ( 1 << n ); \
8755 } \
8756 } while (0)
8757
8758/* m = 0, ..., 31 */
8759#define __tssi_disable_pid_filter(m) \
8760 do { \
8761 int n = (m); \
8762 if ( n>=0 && n <(TSSI_PID_MAX*2) ) { \
8763 REG_TSSI_PEN &= ~( 1 << n ); \
8764 } \
8765 } while (0)
8766
8767/* n = 0, ..., 15 */
8768#define __tssi_set_pid0(n, pid0) \
8769 do { \
8770 REG_TSSI_PID(n) &= ~TSSI_PID_PID0_MASK; \
8771 REG_TSSI_PID(n) |= ((pid0)<<TSSI_PID_PID0_BIT)&TSSI_PID_PID0_MASK; \
8772 }while (0)
8773/* n = 0, ..., 15 */
8774#define __tssi_set_pid1(n, pid1) \
8775 do { \
8776 REG_TSSI_PID(n) &= ~TSSI_PID_PID1_MASK; \
8777 REG_TSSI_PID(n) |= ((pid1)<<TSSI_PID_PID1_BIT)&TSSI_PID_PID1_MASK; \
8778 }while (0)
8779
8780/* n = 0, ..., 15 */
8781#define __tssi_set_pid(n, pid) \
8782 do { \
8783 if ( n>=0 && n < TSSI_PID_MAX*2) { \
8784 if ( n < TSSI_PID_MAX ) \
8785 __tssi_set_pid0(n, pid); \
8786 else \
8787 __tssi_set_pid1(n-TSSI_PID_MAX, pid); \
8788 } \
8789 }while (0)
8790
8791#endif /* __MIPS_ASSEMBLER */
8792
8793#define TVE_BASE 0xB3050100
8794
8795/*************************************************************************
8796 * TVE (TV Encoder Controller)
8797 *************************************************************************/
8798#define TVE_CTRL (TVE_BASE + 0x40) /* TV Encoder Control register */
8799#define TVE_FRCFG (TVE_BASE + 0x44) /* Frame configure register */
8800#define TVE_SLCFG1 (TVE_BASE + 0x50) /* TV signal level configure register 1 */
8801#define TVE_SLCFG2 (TVE_BASE + 0x54) /* TV signal level configure register 2*/
8802#define TVE_SLCFG3 (TVE_BASE + 0x58) /* TV signal level configure register 3*/
8803#define TVE_LTCFG1 (TVE_BASE + 0x60) /* Line timing configure register 1 */
8804#define TVE_LTCFG2 (TVE_BASE + 0x64) /* Line timing configure register 2 */
8805#define TVE_CFREQ (TVE_BASE + 0x70) /* Chrominance sub-carrier frequency configure register */
8806#define TVE_CPHASE (TVE_BASE + 0x74) /* Chrominance sub-carrier phase configure register */
8807#define TVE_CBCRCFG (TVE_BASE + 0x78) /* Chrominance filter configure register */
8808#define TVE_WSSCR (TVE_BASE + 0x80) /* Wide screen signal control register */
8809#define TVE_WSSCFG1 (TVE_BASE + 0x84) /* Wide screen signal configure register 1 */
8810#define TVE_WSSCFG2 (TVE_BASE + 0x88) /* Wide screen signal configure register 2 */
8811#define TVE_WSSCFG3 (TVE_BASE + 0x8c) /* Wide screen signal configure register 3 */
8812
8813#define REG_TVE_CTRL REG32(TVE_CTRL)
8814#define REG_TVE_FRCFG REG32(TVE_FRCFG)
8815#define REG_TVE_SLCFG1 REG32(TVE_SLCFG1)
8816#define REG_TVE_SLCFG2 REG32(TVE_SLCFG2)
8817#define REG_TVE_SLCFG3 REG32(TVE_SLCFG3)
8818#define REG_TVE_LTCFG1 REG32(TVE_LTCFG1)
8819#define REG_TVE_LTCFG2 REG32(TVE_LTCFG2)
8820#define REG_TVE_CFREQ REG32(TVE_CFREQ)
8821#define REG_TVE_CPHASE REG32(TVE_CPHASE)
8822#define REG_TVE_CBCRCFG REG32(TVE_CBCRCFG)
8823#define REG_TVE_WSSCR REG32(TVE_WSSCR)
8824#define REG_TVE_WSSCFG1 REG32(TVE_WSSCFG1)
8825#define REG_TVE_WSSCFG2 REG32(TVE_WSSCFG2)
8826#define REG_TVE_WSSCFG3 REG32(TVE_WSSCFG3)
8827
8828/* TV Encoder Control register */
8829#define TVE_CTRL_EYCBCR (1 << 25) /* YCbCr_enable */
8830#define TVE_CTRL_ECVBS (1 << 24) /* 1: cvbs_enable 0: s-video*/
8831#define TVE_CTRL_DAPD3 (1 << 23) /* DAC 3 power down */
8832#define TVE_CTRL_DAPD2 (1 << 22) /* DAC 2 power down */
8833#define TVE_CTRL_DAPD1 (1 << 21) /* DAC 1 power down */
8834#define TVE_CTRL_DAPD (1 << 20) /* power down all DACs */
8835#define TVE_CTRL_YCDLY_BIT 16
8836#define TVE_CTRL_YCDLY_MASK (0x7 << TVE_CTRL_YCDLY_BIT)
8837#define TVE_CTRL_CGAIN_BIT 14
8838#define TVE_CTRL_CGAIN_MASK (0x3 << TVE_CTRL_CGAIN_BIT)
8839 #define TVE_CTRL_CGAIN_FULL (0 << TVE_CTRL_CGAIN_BIT) /* gain = 1 */
8840 #define TVE_CTRL_CGAIN_QUTR (1 << TVE_CTRL_CGAIN_BIT) /* gain = 1/4 */
8841 #define TVE_CTRL_CGAIN_HALF (2 << TVE_CTRL_CGAIN_BIT) /* gain = 1/2 */
8842 #define TVE_CTRL_CGAIN_THREE_QURT (3 << TVE_CTRL_CGAIN_BIT) /* gain = 3/4 */
8843#define TVE_CTRL_CBW_BIT 12
8844#define TVE_CTRL_CBW_MASK (0x3 << TVE_CTRL_CBW_BIT)
8845 #define TVE_CTRL_CBW_NARROW (0 << TVE_CTRL_CBW_BIT) /* Narrow band */
8846 #define TVE_CTRL_CBW_WIDE (1 << TVE_CTRL_CBW_BIT) /* Wide band */
8847 #define TVE_CTRL_CBW_EXTRA (2 << TVE_CTRL_CBW_BIT) /* Extra wide band */
8848 #define TVE_CTRL_CBW_ULTRA (3 << TVE_CTRL_CBW_BIT) /* Ultra wide band */
8849#define TVE_CTRL_SYNCT (1 << 9)
8850#define TVE_CTRL_PAL (1 << 8) /* 1: PAL, 0: NTSC */
8851#define TVE_CTRL_FINV (1 << 7) /* invert_top:1-invert top and bottom fields. */
8852#define TVE_CTRL_ZBLACK (1 << 6) /* bypass_yclamp:1-Black of luminance (Y) input is 0.*/
8853#define TVE_CTRL_CR1ST (1 << 5) /* uv_order:0-Cb before Cr,1-Cr before Cb */
8854#define TVE_CTRL_CLBAR (1 << 4) /* Color bar mode:0-Output input video to TV,1-Output color bar to TV */
8855#define TVE_CTRL_SWRST (1 << 0) /* Software reset:1-TVE is reset */
8856
8857/* Signal level configure register 1 */
8858#define TVE_SLCFG1_BLACKL_BIT 0
8859#define TVE_SLCFG1_BLACKL_MASK (0x3ff << TVE_SLCFG1_BLACKL_BIT)
8860#define TVE_SLCFG1_WHITEL_BIT 16
8861#define TVE_SLCFG1_WHITEL_MASK (0x3ff << TVE_SLCFG1_WHITEL_BIT)
8862
8863/* Signal level configure register 2 */
8864#define TVE_SLCFG2_BLANKL_BIT 0
8865#define TVE_SLCFG2_BLANKL_MASK (0x3ff << TVE_SLCFG2_BLANKL_BIT)
8866#define TVE_SLCFG2_VBLANKL_BIT 16
8867#define TVE_SLCFG2_VBLANKL_MASK (0x3ff << TVE_SLCFG2_VBLANKL_BIT)
8868
8869/* Signal level configure register 3 */
8870#define TVE_SLCFG3_SYNCL_BIT 0
8871#define TVE_SLCFG3_SYNCL_MASK (0xff << TVE_SLCFG3_SYNCL_BIT)
8872
8873/* Line timing configure register 1 */
8874#define TVE_LTCFG1_BACKP_BIT 0
8875#define TVE_LTCFG1_BACKP_MASK (0x7f << TVE_LTCFG1_BACKP_BIT)
8876#define TVE_LTCFG1_HSYNCW_BIT 8
8877#define TVE_LTCFG1_HSYNCW_MASK (0x7f << TVE_LTCFG1_HSYNCW_BIT)
8878#define TVE_LTCFG1_FRONTP_BIT 16
8879#define TVE_LTCFG1_FRONTP_MASK (0x1f << TVE_LTCFG1_FRONTP_BIT)
8880
8881/* Line timing configure register 2 */
8882#define TVE_LTCFG2_BURSTW_BIT 0
8883#define TVE_LTCFG2_BURSTW_MASK (0x3f << TVE_LTCFG2_BURSTW_BIT)
8884#define TVE_LTCFG2_PREBW_BIT 8
8885#define TVE_LTCFG2_PREBW_MASK (0x1f << TVE_LTCFG2_PREBW_BIT)
8886#define TVE_LTCFG2_ACTLIN_BIT 16
8887#define TVE_LTCFG2_ACTLIN_MASK (0x7ff << TVE_LTCFG2_ACTLIN_BIT)
8888
8889/* Chrominance sub-carrier phase configure register */
8890#define TVE_CPHASE_CCRSTP_BIT 0
8891#define TVE_CPHASE_CCRSTP_MASK (0x3 << TVE_CPHASE_CCRSTP_BIT)
8892 #define TVE_CPHASE_CCRSTP_8 (0 << TVE_CPHASE_CCRSTP_BIT) /* Every 8 field */
8893 #define TVE_CPHASE_CCRSTP_4 (1 << TVE_CPHASE_CCRSTP_BIT) /* Every 4 field */
8894 #define TVE_CPHASE_CCRSTP_2 (2 << TVE_CPHASE_CCRSTP_BIT) /* Every 2 lines */
8895 #define TVE_CPHASE_CCRSTP_0 (3 << TVE_CPHASE_CCRSTP_BIT) /* Never */
8896#define TVE_CPHASE_ACTPH_BIT 16
8897#define TVE_CPHASE_ACTPH_MASK (0xff << TVE_CPHASE_ACTPH_BIT)
8898#define TVE_CPHASE_INITPH_BIT 24
8899#define TVE_CPHASE_INITPH_MASK (0xff << TVE_CPHASE_INITPH_BIT)
8900
8901/* Chrominance filter configure register */
8902#define TVE_CBCRCFG_CRGAIN_BIT 0
8903#define TVE_CBCRCFG_CRGAIN_MASK (0xff << TVE_CBCRCFG_CRGAIN_BIT)
8904#define TVE_CBCRCFG_CBGAIN_BIT 8
8905#define TVE_CBCRCFG_CBGAIN_MASK (0xff << TVE_CBCRCFG_CBGAIN_BIT)
8906#define TVE_CBCRCFG_CRBA_BIT 16
8907#define TVE_CBCRCFG_CRBA_MASK (0xff << TVE_CBCRCFG_CRBA_BIT)
8908#define TVE_CBCRCFG_CBBA_BIT 24
8909#define TVE_CBCRCFG_CBBA_MASK (0xff << TVE_CBCRCFG_CBBA_BIT)
8910
8911/* Frame configure register */
8912#define TVE_FRCFG_NLINE_BIT 0
8913#define TVE_FRCFG_NLINE_MASK (0x3ff << TVE_FRCFG_NLINE_BIT)
8914#define TVE_FRCFG_L1ST_BIT 16
8915#define TVE_FRCFG_L1ST_MASK (0xff << TVE_FRCFG_L1ST_BIT)
8916
8917/* Wide screen signal control register */
8918#define TVE_WSSCR_EWSS0_BIT 0
8919#define TVE_WSSCR_EWSS1_BIT 1
8920#define TVE_WSSCR_WSSTP_BIT 2
8921#define TVE_WSSCR_WSSCKBP_BIT 3
8922#define TVE_WSSCR_WSSEDGE_BIT 4
8923#define TVE_WSSCR_WSSEDGE_MASK (0x7 << TVE_WSSCR_WSSEDGE_BIT)
8924#define TVE_WSSCR_ENCH_BIT 8
8925#define TVE_WSSCR_NCHW_BIT 9
8926#define TVE_WSSCR_NCHFREQ_BIT 12
8927#define TVE_WSSCR_NCHFREQ_MASK (0x7 << TVE_WSSCR_NCHFREQ_BIT)
8928
8929#ifndef __MIPS_ASSEMBLER
8930
8931/*************************************************************************
8932 * TVE (TV Encoder Controller) ops
8933 *************************************************************************/
8934/* TV Encoder Control register ops */
8935#define __tve_soft_reset() (REG_TVE_CTRL |= TVE_CTRL_SWRST)
8936
8937#define __tve_output_colorbar() (REG_TVE_CTRL |= TVE_CTRL_CLBAR)
8938#define __tve_output_video() (REG_TVE_CTRL &= ~TVE_CTRL_CLBAR)
8939
8940#define __tve_input_cr_first() (REG_TVE_CTRL |= TVE_CTRL_CR1ST)
8941#define __tve_input_cb_first() (REG_TVE_CTRL &= ~TVE_CTRL_CR1ST)
8942
8943#define __tve_set_0_as_black() (REG_TVE_CTRL |= TVE_CTRL_ZBLACK)
8944#define __tve_set_16_as_black() (REG_TVE_CTRL &= ~TVE_CTRL_ZBLACK)
8945
8946#define __tve_ena_invert_top_bottom() (REG_TVE_CTRL |= TVE_CTRL_FINV)
8947#define __tve_dis_invert_top_bottom() (REG_TVE_CTRL &= ~TVE_CTRL_FINV)
8948
8949#define __tve_set_pal_mode() (REG_TVE_CTRL |= TVE_CTRL_PAL)
8950#define __tve_set_ntsc_mode() (REG_TVE_CTRL &= ~TVE_CTRL_PAL)
8951
8952#define __tve_set_pal_dura() (REG_TVE_CTRL |= TVE_CTRL_SYNCT)
8953#define __tve_set_ntsc_dura() (REG_TVE_CTRL &= ~TVE_CTRL_SYNCT)
8954
8955/* n = 0 ~ 3 */
8956#define __tve_set_c_bandwidth(n) \
8957do {\
8958 REG_TVE_CTRL &= ~TVE_CTRL_CBW_MASK;\
8959 REG_TVE_CTRL |= (n) << TVE_CTRL_CBW_BIT; \
8960}while(0)
8961
8962/* n = 0 ~ 3 */
8963#define __tve_set_c_gain(n) \
8964do {\
8965 REG_TVE_CTRL &= ~TVE_CTRL_CGAIN_MASK;\
8966 (REG_TVE_CTRL |= (n) << TVE_CTRL_CGAIN_BIT; \
8967}while(0)
8968
8969/* n = 0 ~ 7 */
8970#define __tve_set_yc_delay(n) \
8971do { \
8972 REG_TVE_CTRL &= ~TVE_CTRL_YCDLY_MASK \
8973 REG_TVE_CTRL |= ((n) << TVE_CTRL_YCDLY_BIT); \
8974} while(0)
8975
8976#define __tve_disable_all_dacs() (REG_TVE_CTRL |= TVE_CTRL_DAPD)
8977#define __tve_disable_dac1() (REG_TVE_CTRL |= TVE_CTRL_DAPD1)
8978#define __tve_enable_dac1() (REG_TVE_CTRL &= ~TVE_CTRL_DAPD1)
8979#define __tve_disable_dac2() (REG_TVE_CTRL |= TVE_CTRL_DAPD2)
8980#define __tve_enable_dac2() (REG_TVE_CTRL &= ~TVE_CTRL_DAPD2)
8981#define __tve_disable_dac3() (REG_TVE_CTRL |= TVE_CTRL_DAPD3)
8982#define __tve_enable_dac3() (REG_TVE_CTRL &= ~TVE_CTRL_DAPD3)
8983
8984#define __tve_enable_svideo_fmt() (REG_TVE_CTRL |= TVE_CTRL_ECVBS)
8985#define __tve_enable_cvbs_fmt() (REG_TVE_CTRL &= ~TVE_CTRL_ECVBS)
8986
8987/* TV Encoder Frame Configure register ops */
8988/* n = 0 ~ 255 */
8989#define __tve_set_first_video_line(n) \
8990do {\
8991 REG_TVE_FRCFG &= ~TVE_FRCFG_L1ST_MASK;\
8992 REG_TVE_FRCFG |= (n) << TVE_FRCFG_L1ST_BIT;\
8993} while(0)
8994/* n = 0 ~ 1023 */
8995#define __tve_set_line_num_per_frm(n) \
8996do {\
8997 REG_TVE_FRCFG &= ~TVE_FRCFG_NLINE_MASK;\
8998 REG_TVE_CFG |= (n) << TVE_FRCFG_NLINE_BIT;\
8999} while(0)
9000#define __tve_get_video_line_num()\
9001 (((REG_TVE_FRCFG & TVE_FRCFG_NLINE_MASK) >> TVE_FRCFG_NLINE_BIT) - 1 - 2 * ((REG_TVE_FRCFG & TVE_FRCFG_L1ST_MASK) >> TVE_FRCFG_L1ST_BIT))
9002
9003/* TV Encoder Signal Level Configure register ops */
9004/* n = 0 ~ 1023 */
9005#define __tve_set_white_level(n) \
9006do {\
9007 REG_TVE_SLCFG1 &= ~TVE_SLCFG1_WHITEL_MASK;\
9008 REG_TVE_SLCFG1 |= (n) << TVE_SLCFG1_WHITEL_BIT;\
9009} while(0)
9010/* n = 0 ~ 1023 */
9011#define __tve_set_black_level(n) \
9012do {\
9013 REG_TVE_SLCFG1 &= ~TVE_SLCFG1_BLACKL_MASK;\
9014 REG_TVE_SLCFG1 |= (n) << TVE_SLCFG1_BLACKL_BIT;\
9015} while(0)
9016/* n = 0 ~ 1023 */
9017#define __tve_set_blank_level(n) \
9018do {\
9019 REG_TVE_SLCFG2 &= ~TVE_SLCFG2_BLANKL_MASK;\
9020 REG_TVE_SLCFG2 |= (n) << TVE_SLCFG2_BLANKL_BIT;\
9021} while(0)
9022/* n = 0 ~ 1023 */
9023#define __tve_set_vbi_blank_level(n) \
9024do {\
9025 REG_TVE_SLCFG2 &= ~TVE_SLCFG2_VBLANKL_MASK;\
9026 REG_TVE_SLCFG2 |= (n) << TVE_SLCFG2_VBLANKL_BIT;\
9027} while(0)
9028/* n = 0 ~ 1023 */
9029#define __tve_set_sync_level(n) \
9030do {\
9031 REG_TVE_SLCFG3 &= ~TVE_SLCFG3_SYNCL_MASK;\
9032 REG_TVE_SLCFG3 |= (n) << TVE_SLCFG3_SYNCL_BIT;\
9033} while(0)
9034
9035/* TV Encoder Signal Level Configure register ops */
9036/* n = 0 ~ 31 */
9037#define __tve_set_front_porch(n) \
9038do {\
9039 REG_TVE_LTCFG1 &= ~TVE_LTCFG1_FRONTP_MASK;\
9040 REG_TVE_LTCFG1 |= (n) << TVE_LTCFG1_FRONTP_BIT; \
9041} while(0)
9042/* n = 0 ~ 127 */
9043#define __tve_set_hsync_width(n) \
9044do {\
9045 REG_TVE_LTCFG1 &= ~TVE_LTCFG1_HSYNCW_MASK;\
9046 REG_TVE_LTCFG1 |= (n) << TVE_LTCFG1_HSYNCW_BIT; \
9047} while(0)
9048/* n = 0 ~ 127 */
9049#define __tve_set_back_porch(n) \
9050do {\
9051 REG_TVE_LTCFG1 &= ~TVE_LTCFG1_BACKP_MASK;\
9052 REG_TVE_LTCFG1 |= (n) << TVE_LTCFG1_BACKP_BIT; \
9053} while(0)
9054/* n = 0 ~ 2047 */
9055#define __tve_set_active_linec(n) \
9056do {\
9057 REG_TVE_LTCFG2 &= ~TVE_LTCFG2_ACTLIN_MASK;\
9058 REG_TVE_LTCFG2 |= (n) << TVE_LTCFG2_ACTLIN_BIT; \
9059} while(0)
9060/* n = 0 ~ 31 */
9061#define __tve_set_breezy_way(n) \
9062do {\
9063 REG_TVE_LTCFG2 &= ~TVE_LTCFG2_PREBW_MASK;\
9064 REG_TVE_LTCFG2 |= (n) << TVE_LTCFG2_PREBW_BIT; \
9065} while(0)
9066
9067/* n = 0 ~ 127 */
9068#define __tve_set_burst_width(n) \
9069do {\
9070 REG_TVE_LTCFG2 &= ~TVE_LTCFG2_BURSTW_MASK;\
9071 REG_TVE_LTCFG2 |= (n) << TVE_LTCFG2_BURSTW_BIT; \
9072} while(0)
9073
9074/* TV Encoder Chrominance filter and Modulation register ops */
9075/* n = 0 ~ (2^32-1) */
9076#define __tve_set_c_sub_carrier_freq(n) REG_TVE_CFREQ = (n)
9077/* n = 0 ~ 255 */
9078#define __tve_set_c_sub_carrier_init_phase(n) \
9079do { \
9080 REG_TVE_CPHASE &= ~TVE_CPHASE_INITPH_MASK; \
9081 REG_TVE_CPHASE |= (n) << TVE_CPHASE_INITPH_BIT; \
9082} while(0)
9083/* n = 0 ~ 255 */
9084#define __tve_set_c_sub_carrier_act_phase(n) \
9085do { \
9086 REG_TVE_CPHASE &= ~TVE_CPHASE_ACTPH_MASK; \
9087 REG_TVE_CPHASE |= (n) << TVE_CPHASE_ACTPH_BIT; \
9088} while(0)
9089/* n = 0 ~ 255 */
9090#define __tve_set_c_phase_rst_period(n) \
9091do { \
9092 REG_TVE_CPHASE &= ~TVE_CPHASE_CCRSTP_MASK; \
9093 REG_TVE_CPHASE |= (n) << TVE_CPHASE_CCRSTP_BIT; \
9094} while(0)
9095/* n = 0 ~ 255 */
9096#define __tve_set_cb_burst_amp(n) \
9097do { \
9098 REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CBBA_MASK; \
9099 REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CBBA_BIT; \
9100} while(0)
9101/* n = 0 ~ 255 */
9102#define __tve_set_cr_burst_amp(n) \
9103do { \
9104 REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CRBA_MASK; \
9105 REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CRBA_BIT; \
9106} while(0)
9107/* n = 0 ~ 255 */
9108#define __tve_set_cb_gain_amp(n) \
9109do { \
9110 REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CBGAIN_MASK; \
9111 REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CBGAIN_BIT; \
9112} while(0)
9113/* n = 0 ~ 255 */
9114#define __tve_set_cr_gain_amp(n) \
9115do { \
9116 REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CRGAIN_MASK; \
9117 REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CRGAIN_BIT; \
9118} while(0)
9119
9120/* TV Encoder Wide Screen Signal Control register ops */
9121/* n = 0 ~ 7 */
9122#define __tve_set_notch_freq(n) \
9123do { \
9124 REG_TVE_WSSCR &= ~TVE_WSSCR_NCHFREQ_MASK; \
9125 REG_TVE_WSSCR |= (n) << TVE_WSSCR_NCHFREQ_BIT; \
9126} while(0)
9127/* n = 0 ~ 7 */
9128#define __tve_set_notch_width() (REG_TVE_WSSCR |= TVE_WSSCR_NCHW_BIT)
9129#define __tve_clear_notch_width() (REG_TVE_WSSCR &= ~TVE_WSSCR_NCHW_BIT)
9130#define __tve_enable_notch() (REG_TVE_WSSCR |= TVE_WSSCR_ENCH_BIT)
9131#define __tve_disable_notch() (REG_TVE_WSSCR &= ~TVE_WSSCR_ENCH_BIT)
9132/* n = 0 ~ 7 */
9133#define __tve_set_wss_edge(n) \
9134do { \
9135 REG_TVE_WSSCR &= ~TVE_WSSCR_WSSEDGE_MASK; \
9136 REG_TVE_WSSCR |= (n) << TVE_WSSCR_WSSEDGE_BIT; \
9137} while(0)
9138#define __tve_set_wss_clkbyp() (REG_TVE_WSSCR |= TVE_WSSCR_WSSCKBP_BIT)
9139#define __tve_set_wss_type() (REG_TVE_WSSCR |= TVE_WSSCR_WSSTP_BIT)
9140#define __tve_enable_wssf1() (REG_TVE_WSSCR |= TVE_WSSCR_EWSS1_BIT)
9141#define __tve_enable_wssf0() (REG_TVE_WSSCR |= TVE_WSSCR_EWSS0_BIT)
9142
9143/* TV Encoder Wide Screen Signal Configure register 1, 2 and 3 ops */
9144/* n = 0 ~ 1023 */
9145#define __tve_set_wss_level(n) \
9146do { \
9147 REG_TVE_WSSCFG1 &= ~TVE_WSSCFG1_WSSL_MASK; \
9148 REG_TVE_WSSCFG1 |= (n) << TVE_WSSCFG1_WSSL_BIT; \
9149} while(0)
9150/* n = 0 ~ 4095 */
9151#define __tve_set_wss_freq(n) \
9152do { \
9153 REG_TVE_WSSCFG1 &= ~TVE_WSSCFG1_WSSFREQ_MASK; \
9154 REG_TVE_WSSCFG1 |= (n) << TVE_WSSCFG1_WSSFREQ_BIT; \
9155} while(0)
9156/* n = 0, 1; l = 0 ~ 255 */
9157#define __tve_set_wss_line(n,v) \
9158do { \
9159 REG_TVE_WSSCFG##n &= ~TVE_WSSCFG_WSSLINE_MASK; \
9160 REG_TVE_WSSCFG##n |= (v) << TVE_WSSCFG_WSSLINE_BIT; \
9161} while(0)
9162/* n = 0, 1; d = 0 ~ (2^20-1) */
9163#define __tve_set_wss_data(n, v) \
9164do { \
9165 REG_TVE_WSSCFG##n &= ~TVE_WSSCFG_WSSLINE_MASK; \
9166 REG_TVE_WSSCFG##n |= (v) << TVE_WSSCFG_WSSLINE_BIT; \
9167} while(0)
9168
9169#endif /* __MIPS_ASSEMBLER */
9170
9171#define UART0_BASE 0xB0030000
9172#define UART1_BASE 0xB0031000
9173#define UART2_BASE 0xB0032000
9174#define UART3_BASE 0xB0033000
9175
9176/*************************************************************************
9177 * UART
9178 *************************************************************************/
9179
9180#define IRDA_BASE UART0_BASE
9181#define UART_BASE UART0_BASE
9182#define UART_OFF 0x1000
9183
9184/* Register Offset */
9185#define OFF_RDR (0x00) /* R 8b H'xx */
9186#define OFF_TDR (0x00) /* W 8b H'xx */
9187#define OFF_DLLR (0x00) /* RW 8b H'00 */
9188#define OFF_DLHR (0x04) /* RW 8b H'00 */
9189#define OFF_IER (0x04) /* RW 8b H'00 */
9190#define OFF_ISR (0x08) /* R 8b H'01 */
9191#define OFF_FCR (0x08) /* W 8b H'00 */
9192#define OFF_LCR (0x0C) /* RW 8b H'00 */
9193#define OFF_MCR (0x10) /* RW 8b H'00 */
9194#define OFF_LSR (0x14) /* R 8b H'00 */
9195#define OFF_MSR (0x18) /* R 8b H'00 */
9196#define OFF_SPR (0x1C) /* RW 8b H'00 */
9197#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
9198#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
9199#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
9200
9201/* Register Address */
9202#define UART0_RDR (UART0_BASE + OFF_RDR)
9203#define UART0_TDR (UART0_BASE + OFF_TDR)
9204#define UART0_DLLR (UART0_BASE + OFF_DLLR)
9205#define UART0_DLHR (UART0_BASE + OFF_DLHR)
9206#define UART0_IER (UART0_BASE + OFF_IER)
9207#define UART0_ISR (UART0_BASE + OFF_ISR)
9208#define UART0_FCR (UART0_BASE + OFF_FCR)
9209#define UART0_LCR (UART0_BASE + OFF_LCR)
9210#define UART0_MCR (UART0_BASE + OFF_MCR)
9211#define UART0_LSR (UART0_BASE + OFF_LSR)
9212#define UART0_MSR (UART0_BASE + OFF_MSR)
9213#define UART0_SPR (UART0_BASE + OFF_SPR)
9214#define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
9215#define UART0_UMR (UART0_BASE + OFF_UMR)
9216#define UART0_UACR (UART0_BASE + OFF_UACR)
9217
9218#define UART1_RDR (UART1_BASE + OFF_RDR)
9219#define UART1_TDR (UART1_BASE + OFF_TDR)
9220#define UART1_DLLR (UART1_BASE + OFF_DLLR)
9221#define UART1_DLHR (UART1_BASE + OFF_DLHR)
9222#define UART1_IER (UART1_BASE + OFF_IER)
9223#define UART1_ISR (UART1_BASE + OFF_ISR)
9224#define UART1_FCR (UART1_BASE + OFF_FCR)
9225#define UART1_LCR (UART1_BASE + OFF_LCR)
9226#define UART1_MCR (UART1_BASE + OFF_MCR)
9227#define UART1_LSR (UART1_BASE + OFF_LSR)
9228#define UART1_MSR (UART1_BASE + OFF_MSR)
9229#define UART1_SPR (UART1_BASE + OFF_SPR)
9230#define UART1_SIRCR (UART1_BASE + OFF_SIRCR)
9231
9232#define UART2_RDR (UART2_BASE + OFF_RDR)
9233#define UART2_TDR (UART2_BASE + OFF_TDR)
9234#define UART2_DLLR (UART2_BASE + OFF_DLLR)
9235#define UART2_DLHR (UART2_BASE + OFF_DLHR)
9236#define UART2_IER (UART2_BASE + OFF_IER)
9237#define UART2_ISR (UART2_BASE + OFF_ISR)
9238#define UART2_FCR (UART2_BASE + OFF_FCR)
9239#define UART2_LCR (UART2_BASE + OFF_LCR)
9240#define UART2_MCR (UART2_BASE + OFF_MCR)
9241#define UART2_LSR (UART2_BASE + OFF_LSR)
9242#define UART2_MSR (UART2_BASE + OFF_MSR)
9243#define UART2_SPR (UART2_BASE + OFF_SPR)
9244#define UART2_SIRCR (UART2_BASE + OFF_SIRCR)
9245
9246#define UART3_RDR (UART3_BASE + OFF_RDR)
9247#define UART3_TDR (UART3_BASE + OFF_TDR)
9248#define UART3_DLLR (UART3_BASE + OFF_DLLR)
9249#define UART3_DLHR (UART3_BASE + OFF_DLHR)
9250#define UART3_IER (UART3_BASE + OFF_IER)
9251#define UART3_ISR (UART3_BASE + OFF_ISR)
9252#define UART3_FCR (UART3_BASE + OFF_FCR)
9253#define UART3_LCR (UART3_BASE + OFF_LCR)
9254#define UART3_MCR (UART3_BASE + OFF_MCR)
9255#define UART3_LSR (UART3_BASE + OFF_LSR)
9256#define UART3_MSR (UART3_BASE + OFF_MSR)
9257#define UART3_SPR (UART3_BASE + OFF_SPR)
9258#define UART3_SIRCR (UART3_BASE + OFF_SIRCR)
9259
9260/*
9261 * Define macros for UARTIER
9262 * UART Interrupt Enable Register
9263 */
9264#define UARTIER_RIE (1 << 0) /* 0: receive fifo full interrupt disable */
9265#define UARTIER_TIE (1 << 1) /* 0: transmit fifo empty interrupt disable */
9266#define UARTIER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
9267#define UARTIER_MIE (1 << 3) /* 0: modem status interrupt disable */
9268#define UARTIER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
9269
9270/*
9271 * Define macros for UARTISR
9272 * UART Interrupt Status Register
9273 */
9274#define UARTISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
9275#define UARTISR_IID (7 << 1) /* Source of Interrupt */
9276#define UARTISR_IID_MSI (0 << 1) /* Modem status interrupt */
9277#define UARTISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
9278#define UARTISR_IID_RDI (2 << 1) /* Receiver data interrupt */
9279#define UARTISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
9280#define UARTISR_IID_RTO (6 << 1) /* Receive timeout */
9281#define UARTISR_FFMS (3 << 6) /* FIFO mode select, set when UARTFCR.FE is set to 1 */
9282#define UARTISR_FFMS_NO_FIFO (0 << 6)
9283#define UARTISR_FFMS_FIFO_MODE (3 << 6)
9284
9285/*
9286 * Define macros for UARTFCR
9287 * UART FIFO Control Register
9288 */
9289#define UARTFCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
9290#define UARTFCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
9291#define UARTFCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
9292#define UARTFCR_DMS (1 << 3) /* 0: disable DMA mode */
9293#define UARTFCR_UUE (1 << 4) /* 0: disable UART */
9294#define UARTFCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
9295#define UARTFCR_RTRG_1 (0 << 6)
9296#define UARTFCR_RTRG_4 (1 << 6)
9297#define UARTFCR_RTRG_8 (2 << 6)
9298#define UARTFCR_RTRG_15 (3 << 6)
9299
9300/*
9301 * Define macros for UARTLCR
9302 * UART Line Control Register
9303 */
9304#define UARTLCR_WLEN (3 << 0) /* word length */
9305#define UARTLCR_WLEN_5 (0 << 0)
9306#define UARTLCR_WLEN_6 (1 << 0)
9307#define UARTLCR_WLEN_7 (2 << 0)
9308#define UARTLCR_WLEN_8 (3 << 0)
9309#define UARTLCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
9310 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
9311#define UARTLCR_STOP1 (0 << 2)
9312#define UARTLCR_STOP2 (1 << 2)
9313#define UARTLCR_PE (1 << 3) /* 0: parity disable */
9314#define UARTLCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
9315#define UARTLCR_SPAR (1 << 5) /* 0: sticky parity disable */
9316#define UARTLCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
9317#define UARTLCR_DLAB (1 << 7) /* 0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR */
9318
9319/*
9320 * Define macros for UARTLSR
9321 * UART Line Status Register
9322 */
9323#define UARTLSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
9324#define UARTLSR_ORER (1 << 1) /* 0: no overrun error */
9325#define UARTLSR_PER (1 << 2) /* 0: no parity error */
9326#define UARTLSR_FER (1 << 3) /* 0; no framing error */
9327#define UARTLSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
9328#define UARTLSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
9329#define UARTLSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
9330#define UARTLSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
9331
9332/*
9333 * Define macros for UARTMCR
9334 * UART Modem Control Register
9335 */
9336#define UARTMCR_RTS (1 << 1) /* 0: RTS_ output high, 1: RTS_ output low */
9337#define UARTMCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
9338#define UARTMCR_FCM (1 << 6) /* 0: software 1: hardware */
9339#define UARTMCR_MCE (1 << 7) /* 0: modem function is disable */
9340
9341/*
9342 * Define macros for UARTMSR
9343 * UART Modem Status Register
9344 */
9345#define UARTMSR_CCTS (1 << 0) /* 1: a change on CTS_ pin */
9346#define UARTMSR_CTS (1 << 4) /* 0: CTS_ pin is high */
9347
9348/*
9349 * Define macros for SIRCR
9350 * Slow IrDA Control Register
9351 */
9352#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: SIR mode */
9353#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: SIR mode */
9354#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
9355 1: 0 pulse width is 1.6us for 115.2Kbps */
9356#define SIRCR_TDPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
9357#define SIRCR_RDPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
9358
9359#ifndef __MIPS_ASSEMBLER
9360
9361/***************************************************************************
9362 * UART
9363 ***************************************************************************/
9364#define __jtag_as_uart3() \
9365do { \
9366 REG_GPIO_PXSELC(0) = 0x40000000; \
9367 REG_GPIO_PXSELS(0) = 0x80000000; \
9368} while(0)
9369
9370#define __uart_enable(n) \
9371 ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) |= UARTFCR_UUE | UARTFCR_FE )
9372#define __uart_disable(n) \
9373 ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE )
9374
9375#define __uart_enable_transmit_irq(n) \
9376 ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE )
9377#define __uart_disable_transmit_irq(n) \
9378 ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE )
9379
9380#define __uart_enable_receive_irq(n) \
9381 ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
9382#define __uart_disable_receive_irq(n) \
9383 ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
9384
9385#define __uart_enable_loopback(n) \
9386 ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP )
9387#define __uart_disable_loopback(n) \
9388 ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP )
9389
9390#define __uart_set_8n1(n) \
9391 ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 )
9392
9393#define __uart_set_baud(n, devclk, baud) \
9394 do { \
9395 REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB; \
9396 REG8(UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff; \
9397 REG8(UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \
9398 REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB; \
9399 } while (0)
9400
9401#define __uart_parity_error(n) \
9402 ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 )
9403
9404#define __uart_clear_errors(n) \
9405 ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )
9406
9407#define __uart_transmit_fifo_empty(n) \
9408 ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 )
9409
9410#define __uart_transmit_end(n) \
9411 ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 )
9412
9413#define __uart_transmit_char(n, ch) \
9414 REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch)
9415
9416#define __uart_receive_fifo_full(n) \
9417 ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 )
9418
9419#define __uart_receive_ready(n) \
9420 ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 )
9421
9422#define __uart_receive_char(n) \
9423 REG8(UART_BASE + UART_OFF*(n) + OFF_RDR)
9424
9425#define __uart_disable_irda() \
9426 ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
9427#define __uart_enable_irda() \
9428 /* Tx high pulse as 0, Rx low pulse as 0 */ \
9429 ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
9430
9431#endif /* __MIPS_ASSEMBLER */
9432
9433/*
9434 * Watchdog timer module(WDT) address definition
9435 */
9436#define WDT_BASE 0xb0002000
9437
9438/*
9439 * WDT registers offset address definition
9440 */
9441#define WDT_WDR_OFFSET (0x00) /* rw, 16, 0x???? */
9442#define WDT_WCER_OFFSET (0x04) /* rw, 8, 0x00 */
9443#define WDT_WCNT_OFFSET (0x08) /* rw, 16, 0x???? */
9444#define WDT_WCSR_OFFSET (0x0c) /* rw, 16, 0x0000 */
9445
9446/*
9447 * WDT registers address definition
9448 */
9449#define WDT_WDR (WDT_BASE + WDT_WDR_OFFSET)
9450#define WDT_WCER (WDT_BASE + WDT_WCER_OFFSET)
9451#define WDT_WCNT (WDT_BASE + WDT_WCNT_OFFSET)
9452#define WDT_WCSR (WDT_BASE + WDT_WCSR_OFFSET)
9453
9454/*
9455 * WDT registers common define
9456 */
9457
9458/* Watchdog counter enable register(WCER) */
9459#define WCER_TCEN BIT0
9460
9461/* Watchdog control register(WCSR) */
9462#define WCSR_PRESCALE_LSB 3
9463#define WCSR_PRESCALE_MASK BITS_H2L(5, WCSR_PRESCALE_LSB)
9464#define WCSR_PRESCALE1 (0x0 << WCSR_PRESCALE_LSB)
9465#define WCSR_PRESCALE4 (0x1 << WCSR_PRESCALE_LSB)
9466#define WCSR_PRESCALE16 (0x2 << WCSR_PRESCALE_LSB)
9467#define WCSR_PRESCALE64 (0x3 << WCSR_PRESCALE_LSB)
9468#define WCSR_PRESCALE256 (0x4 << WCSR_PRESCALE_LSB)
9469#define WCSR_PRESCALE1024 (0x5 << WCSR_PRESCALE_LSB)
9470
9471#define WCSR_CLKIN_LSB 0
9472#define WCSR_CLKIN_MASK BITS_H2L(2, WCSR_CLKIN_LSB)
9473#define WCSR_CLKIN_PCK (0x1 << WCSR_CLKIN_LSB)
9474#define WCSR_CLKIN_RTC (0x2 << WCSR_CLKIN_LSB)
9475#define WCSR_CLKIN_EXT (0x4 << WCSR_CLKIN_LSB)
9476
9477#ifndef __MIPS_ASSEMBLER
9478
9479#define REG_WDT_WDR REG16(WDT_WDR)
9480#define REG_WDT_WCER REG8(WDT_WCER)
9481#define REG_WDT_WCNT REG16(WDT_WCNT)
9482#define REG_WDT_WCSR REG16(WDT_WCSR)
9483
9484#endif /* __MIPS_ASSEMBLER */
9485
9486/*
9487 * Operating system timer module(OST) address definition
9488 */
9489#define OST_BASE 0xb0002000
9490
9491/*
9492 * OST registers offset address definition
9493 */
9494#define OST_OSTDR_OFFSET (0xe0) /* rw, 32, 0x???????? */
9495#define OST_OSTCNT_OFFSET (0xe4) /* rw, 32, 0x???????? */
9496#define OST_OSTCNTL_OFFSET (0xe4) /* rw, 32, 0x???????? */
9497#define OST_OSTCNTH_OFFSET (0xe8) /* rw, 32, 0x???????? */
9498#define OST_OSTCSR_OFFSET (0xec) /* rw, 16, 0x0000 */
9499#define OST_OSTCNTHBUF_OFFSET (0xfc) /* r, 32, 0x???????? */
9500
9501/*
9502 * OST registers address definition
9503 */
9504#define OST_OSTDR (OST_BASE + OST_OSTDR_OFFSET)
9505#define OST_OSTCNT (OST_BASE + OST_OSTCNT_OFFSET)
9506#define OST_OSTCNTL (OST_BASE + OST_OSTCNTL_OFFSET)
9507#define OST_OSTCNTH (OST_BASE + OST_OSTCNTH_OFFSET)
9508#define OST_OSTCSR (OST_BASE + OST_OSTCSR_OFFSET)
9509#define OST_OSTCNTHBUF (OST_BASE + OST_OSTCNTHBUF_OFFSET)
9510
9511/*
9512 * OST registers common define
9513 */
9514
9515/* Operating system control register(OSTCSR) */
9516#define OSTCSR_CNT_MD BIT15
9517#define OSTCSR_SD BIT9
9518#define OSTCSR_EXT_EN BIT2
9519#define OSTCSR_RTC_EN BIT1
9520#define OSTCSR_PCK_EN BIT0
9521
9522#define OSTCSR_PRESCALE_LSB 3
9523#define OSTCSR_PRESCALE_MASK BITS_H2L(5, OSTCSR_PRESCALE_LSB)
9524#define OSTCSR_PRESCALE1 (0x0 << OSTCSR_PRESCALE_LSB)
9525#define OSTCSR_PRESCALE4 (0x1 << OSTCSR_PRESCALE_LSB)
9526#define OSTCSR_PRESCALE16 (0x2 << OSTCSR_PRESCALE_LSB)
9527#define OSTCSR_PRESCALE64 (0x3 << OSTCSR_PRESCALE_LSB)
9528#define OSTCSR_PRESCALE256 (0x4 << OSTCSR_PRESCALE_LSB)
9529#define OSTCSR_PRESCALE1024 (0x5 << OSTCSR_PRESCALE_LSB)
9530
9531#ifndef __MIPS_ASSEMBLER
9532
9533#define REG_OST_OSTDR REG32(OST_OSTDR)
9534#define REG_OST_OSTCNT REG32(OST_OSTCNT)
9535#define REG_OST_OSTCNTL REG32(OST_OSTCNTL)
9536#define REG_OST_OSTCNTH REG32(OST_OSTCNTH)
9537#define REG_OST_OSTCSR REG16(OST_OSTCSR)
9538#define REG_OST_OSTCNTHBUF REG32(OST_OSTCNTHBUF)
9539
9540#endif /* __MIPS_ASSEMBLER */
9541
9542#define AOSD_BASE 0xB3070000
9543
9544/*************************************************************************
9545 * OSD (On Screen Display)
9546 *************************************************************************/
9547#define AOSD_ADDR0 (AOSD_BASE + 0x00)
9548#define AOSD_ADDR1 (AOSD_BASE + 0x04)
9549#define AOSD_ADDR2 (AOSD_BASE + 0x08)
9550#define AOSD_ADDR3 (AOSD_BASE + 0x0C)
9551#define AOSD_WADDR (AOSD_BASE + 0x10)
9552#define AOSD_ADDRLEN (AOSD_BASE + 0x14)
9553#define AOSD_ALPHA_VALUE (AOSD_BASE + 0x18)
9554#define AOSD_CTRL (AOSD_BASE + 0x1C)
9555#define AOSD_INT (AOSD_BASE + 0x20)
9556
9557#define REG_AOSD_ADDR0 REG32(AOSD_ADDR0)
9558#define REG_AOSD_ADDR1 REG32(AOSD_ADDR1)
9559#define REG_AOSD_ADDR2 REG32(AOSD_ADDR2)
9560#define REG_AOSD_ADDR3 REG32(AOSD_ADDR3)
9561#define REG_AOSD_WADDR REG32(AOSD_WADDR)
9562#define REG_AOSD_ADDRLEN REG32(AOSD_ADDRLEN)
9563#define REG_AOSD_ALPHA_VALUE REG32(AOSD_ALPHA_VALUE)
9564#define REG_AOSD_CTRL REG32(AOSD_CTRL)
9565#define REG_AOSD_INT REG32(AOSD_INT)
9566
9567#define AOSD_CTRL_FRMLV_MASK (0x3 << 18)
9568#define AOSD_CTRL_FRMLV_2 (0x1 << 18)
9569#define AOSD_CTRL_FRMLV_3 (0x2 << 18)
9570#define AOSD_CTRL_FRMLV_4 (0x3 << 18)
9571
9572#define AOSD_CTRL_FRM_END (1 << 17)
9573#define AOSD_CTRL_ALPHA_START (1 << 16)
9574#define AOSD_CTRL_INT_MAKS (1 << 15)
9575#define AOSD_CTRL_CHANNEL_LEVEL_BIT 7
9576#define AOSD_CTRL_CHANNEL_LEVEL_MASK (0xff << AOSD_CTRL_CHANNEL_LEVEL_BIT)
9577#define AOSD_CTRL_ALPHA_MODE_BIT 3
9578#define AOSD_CTRL_ALPHA_MODE_MASK (0xf << AOSD_CTRL_ALPHA_MODE_BIT)
9579#define AOSD_CTRL_ALPHA_PIXEL_MODE 0
9580#define AOSD_CTRL_ALPHA_FRAME_MODE 1
9581
9582#define AOSD_CTRL_FORMAT_MODE_BIT 1
9583#define AOSD_CTRL_FORMAT_MODE_MASK (0x3 << 1)
9584#define AOSD_CTRL_RGB565_FORMAT_MODE (0 << AOSD_CTRL_FORMAT_MODE_BIT)
9585#define AOSD_CTRL_RGB555_FORMAT_MODE (1 << AOSD_CTRL_FORMAT_MODE_BIT)
9586#define AOSD_CTRL_RGB8888_FORMAT_MODE (2 << AOSD_CTRL_FORMAT_MODE_BIT)
9587
9588#define AOSD_ALPHA_ENABLE (1 << 0)
9589
9590#define AOSD_INT_COMPRESS_END (1 << 1)
9591#define AOSD_INT_AOSD_END (1 << 0)
9592
9593#define __osd_enable_alpha() (REG_AOSD_CTRL |= AOSD_ALPHA_ENABLE)
9594#define __osd_alpha_start() (REG_AOSD_CTRL |= AOSD_CTRL_ALPHA_START)
9595
9596/*************************************************************************
9597 * COMPRESS
9598 *************************************************************************/
9599#define COMPRESS_SCR_ADDR (AOSD_BASE + 0x00)
9600#define COMPRESS_DES_ADDR (AOSD_BASE + 0x10)
9601#define COMPRESS_DST_OFFSET (AOSD_BASE + 0x34)
9602#define COMPRESS_FRAME_SIZE (AOSD_BASE + 0x38)
9603#define COMPRESS_CTRL (AOSD_BASE + 0x3C)
9604#define COMPRESS_RATIO (AOSD_BASE + 0x40)
9605#define COMPRESS_SRC_OFFSET (AOSD_BASE + 0x44)
9606
9607#define REG_COMPRESS_SCR_ADDR REG32(COMPRESS_SCR_ADDR)
9608#define REG_COMPRESS_DES_ADDR REG32(COMPRESS_DES_ADDR)
9609#define REG_COMPRESS_DST_OFFSET REG32(COMPRESS_DST_OFFSET)
9610#define REG_COMPRESS_FRAME_SIZE REG32(COMPRESS_FRAME_SIZE)
9611#define REG_COMPRESS_CTRL REG32(COMPRESS_CTRL)
9612#define REG_COMPRESS_RATIO REG32(COMPRESS_RATIO)
9613#define REG_COMPRESS_SRC_OFFSET REG32(COMPRESS_SRC_OFFSET)
9614
9615#define COMPRESS_CTRL_WITHOUT_ALPHA (1 << 4)
9616#define COMPRESS_CTRL_WITH_ALPHA (0 << 4)
9617#define COMPRESS_CTRL_COMP_START (1 << 3)
9618#define COMPRESS_CTRL_COMP_END (1 << 2)
9619#define COMPRESS_CTRL_INT_MASK (1 << 1)
9620#define COMPRESS_CTRL_COMP_ENABLE (1 << 0)
9621
9622#define COMPRESS_RATIO_FRM_BYPASS (1 << 31)
9623#define COMPRESS_BYPASS_ROW (1 << 12)
9624#define COMPRESS_ROW_QUARTER (1 << 0)
9625
9626#define COMPRESS_CTRL_ALIGNED_MODE_BIT (31)
9627#define COMPRESS_CTRL_ALIGNED_16_WORD (0 << COMPRESS_CTRL_ALIGNED_MODE_BIT)
9628#define COMPRESS_CTRL_ALIGNED_64_WORD (1 << COMPRESS_CTRL_ALIGNED_MODE_BIT)
9629
9630#define __compress_enable() (REG_COMPRESS_CTRL |= COMPRESS_INT_AOSD_END)
9631#define __compress_start() (REG_COMPRESS_CTRL |= COMPRESS_CTRL_COMP_START)
9632#define __compress_with_alpha() (REG_COMPRESS_CTRL |= COMPRESS_CTRL_ALPHA_EN)
9633
9634/* Rockbox defines */
9635
9636/* Timer frequency */
9637#define TIMER_FREQ (CFG_EXTAL) /* For full precision! */
9638
9639/* Serial */
9640#define CFG_UART_BASE UART1_BASE /* Base of the UART channel */
9641#define CFG_BAUDRATE 57600
9642
9643#endif /* __JZ4760B_H__ */
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-04 22:03:43 +0000