1 files changed, 30 insertions, 0 deletions

diff --git a/firmware/target/coldfire/pcm-coldfire.c b/firmware/target/coldfire/pcm-coldfire.c
index 0782b116b4..209d227187 100644
--- a/firmware/target/coldfire/pcm-coldfire.c
+++ b/firmware/target/coldfire/pcm-coldfire.c
@@ -55,6 +55,24 @@
 
 #define FPARM_CLOCKSEL       0
 #define FPARM_CLSEL          1
+
+/* SCLK = Fs * bit clocks per word
+ * so SCLK should be Fs * 64
+ *
+ * CLOCKSEL sets SCLK freq based on Audio CLK
+ * 0x0c SCLK = Audio CLK/2   88200 * 64 = 5644800 Hz
+ * 0x06 SCLK = Audio CLK/4   44100 * 64 = 2822400 Hz
+ * 0x04 SCLK = Audio CLK/8   22050 * 64 = 1411200 Hz
+ * 0x02 SCLK = Audio CLK/16  11025 * 64 = 705600 Hz
+ *
+ * CLSEL sets MCLK1/2 DAC freq based on XTAL freq
+ * 0x01 MCLK1/2 = XTAL freq
+ * 0x02 MCLK1/2 = XTAL/2 freq
+ *
+ * Audio CLK can be XTAL freq or XTAL/2 freq  (bit22 in PLLCR)
+ * we always set bit22 so Audio CLK is always XTAL freq
+ */
+
 #if CONFIG_CPU == MCF5249 && defined(HAVE_UDA1380)
 static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
 {
@@ -65,6 +83,16 @@ static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
 };
 #endif
 
+#if CONFIG_CPU == MCF5249 && defined(HAVE_WM8750)
+static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
+{
+    [HW_FREQ_88] = { 0x0c, 0x01 },
+    [HW_FREQ_44] = { 0x06, 0x01 },
+    [HW_FREQ_22] = { 0x04, 0x01 },
+    [HW_FREQ_11] = { 0x02, 0x01 },
+};
+#endif
+
 #if (CONFIG_CPU == MCF5250 || CONFIG_CPU == MCF5249) && defined(HAVE_TLV320)
 static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
 {
@@ -324,6 +352,7 @@ const void * pcm_play_dma_get_peak_buffer(int *count)
     return (void *)((addr + 2) & ~3);
 } /* pcm_play_dma_get_peak_buffer */
 
+#ifdef HAVE_RECORDING
 /****************************************************************************
  ** Recording DMA transfer
  **/
@@ -487,3 +516,4 @@ const void * pcm_rec_dma_get_peak_buffer(int *count)
     *count = (end >> 2) - addr;
     return (void *)(addr << 2);
 } /* pcm_rec_dma_get_peak_buffer */
+#endif