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-rw-r--r--firmware/target/arm/s3c2440/adc-s3c2440.c (renamed from firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c)0
-rw-r--r--firmware/target/arm/s3c2440/gigabeat-fx/wmcodec-meg-fx.c2
-rw-r--r--firmware/target/arm/s3c2440/i2c-s3c2440.c (renamed from firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c)2
-rw-r--r--firmware/target/arm/s3c2440/i2c-s3c2440.h (renamed from firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.h)0
-rw-r--r--firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c292
-rw-r--r--firmware/target/arm/s3c2440/mini2440/powermgmt-mini2440.c69
-rw-r--r--firmware/target/arm/s3c2440/sd-s3c2440.c13
-rw-r--r--firmware/target/arm/s3c2440/system-target.h40
-rw-r--r--firmware/target/arm/s3c2440/uart-s3c2440.c108
-rw-r--r--firmware/target/arm/s3c2440/uart-s3c2440.h24
10 files changed, 481 insertions, 69 deletions
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c b/firmware/target/arm/s3c2440/adc-s3c2440.c
index fd5151a3bf..fd5151a3bf 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c
+++ b/firmware/target/arm/s3c2440/adc-s3c2440.c
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/wmcodec-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/wmcodec-meg-fx.c
index 52c26b898d..01b177da6c 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/wmcodec-meg-fx.c
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/wmcodec-meg-fx.c
@@ -28,7 +28,7 @@
28#include "cpu.h" 28#include "cpu.h"
29#include "kernel.h" 29#include "kernel.h"
30#include "sound.h" 30#include "sound.h"
31#include "i2c-meg-fx.h" 31#include "i2c-s3c2440.h"
32#include "system-target.h" 32#include "system-target.h"
33#include "timer.h" 33#include "timer.h"
34#include "wmcodec.h" 34#include "wmcodec.h"
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c b/firmware/target/arm/s3c2440/i2c-s3c2440.c
index 836dedd462..4669186a4c 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c
+++ b/firmware/target/arm/s3c2440/i2c-s3c2440.c
@@ -19,7 +19,7 @@
19 * 19 *
20 ****************************************************************************/ 20 ****************************************************************************/
21#include "system.h" 21#include "system.h"
22#include "i2c-meg-fx.h" 22#include "i2c-s3c2440.h"
23 23
24static struct wakeup i2c_wake; /* Transfer completion signal */ 24static struct wakeup i2c_wake; /* Transfer completion signal */
25static struct mutex i2c_mtx; /* Mutual exclusion */ 25static struct mutex i2c_mtx; /* Mutual exclusion */
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.h b/firmware/target/arm/s3c2440/i2c-s3c2440.h
index 793ee213fd..793ee213fd 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.h
+++ b/firmware/target/arm/s3c2440/i2c-s3c2440.h
diff --git a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c
new file mode 100644
index 0000000000..237bf264f5
--- /dev/null
+++ b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c
@@ -0,0 +1,292 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2006 by Michael Sevakis
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#include <stdlib.h>
22#include "system.h"
23#include "kernel.h"
24#include "logf.h"
25#include "audio.h"
26#include "sound.h"
27#include "file.h"
28
29/* PCM interrupt routine lockout */
30static struct
31{
32 int locked;
33 unsigned long state;
34} dma_play_lock =
35{
36 .locked = 0,
37 .state = 0,
38};
39
40#define FIFO_COUNT ((IISFCON >> 6) & 0x3F)
41
42/* Setup for the DMA controller */
43#define DMA_CONTROL_SETUP ((1<<31) | (1<<29) | (1<<23) | (1<<22) | (1<<20))
44
45#ifdef HAVE_UDA1341
46/* for PCLK = 50 MHz, frame size = 32 */
47/* [prescaler, master clock rate] */
48static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
49{
50 [HW_FREQ_64] = { 2, IISMOD_MASTER_CLOCK_256FS },
51 [HW_FREQ_44] = { 3, IISMOD_MASTER_CLOCK_384FS },
52 [HW_FREQ_22] = { 8, IISMOD_MASTER_CLOCK_256FS },
53 [HW_FREQ_11] = { 17, IISMOD_MASTER_CLOCK_256FS },
54};
55#endif
56
57/* DMA count has hit zero - no more data */
58/* Get more data from the callback and top off the FIFO */
59void fiq_handler(void) __attribute__((interrupt ("FIQ")));
60
61/* Mask the DMA interrupt */
62void pcm_play_lock(void)
63{
64 if (++dma_play_lock.locked == 1)
65 s3c_regset32(&INTMSK, DMA2_MASK);
66}
67
68/* Unmask the DMA interrupt if enabled */
69void pcm_play_unlock(void)
70{
71 if (--dma_play_lock.locked == 0)
72 s3c_regclr32(&INTMSK, dma_play_lock.state);
73}
74
75void pcm_play_dma_init(void)
76{
77 /* There seem to be problems when changing the IIS interface configuration
78 * when a clock is not present.
79 */
80 s3c_regset32(&CLKCON, 1<<17);
81
82#ifdef HAVE_UDA1341
83 /* master, transmit mode, 16 bit samples, BCLK 32fs, PCLK */
84 IISMOD = IISMOD_MASTER_CLOCK_PCLK | IISMOD_MASTER_MODE | IISMOD_TRANSMIT_MODE
85 | IISMOD_16_BIT | IISMOD_MASTER_CLOCK_256FS | IISMOD_BIT_CLOCK_32FS;
86
87 /* TX idle, enable prescaler */
88 IISCON |= IISCON_TX_IDLE | IISCON_IIS_PRESCALER_ENABLE;
89#else
90 /* slave, transmit mode, 16 bit samples - MCLK 384fs - use 16.9344Mhz -
91 BCLK 32fs */
92 IISMOD = (1<<9) | (1<<8) | (2<<6) | (1<<3) | (1<<2) | (1<<0);
93
94 /* RX,TX off,on */
95 IISCON |= (1<<3) | (1<<2);
96#endif
97
98 s3c_regclr32(&CLKCON, 1<<17);
99
100 audiohw_init();
101
102 /* init GPIO */
103#ifdef GIGABEAT_F
104/* GPCCON = (GPCCON & ~(3<<14)) | (1<<14); */
105 S3C244_GPIO_CONFIG (GPCCON, 7, GPIO_OUTPUT);
106 GPCDAT |= (1<<7);
107#endif
108
109 /* GPE4=I2SDO, GPE3=I2SDI, GPE2=CDCLK, GPE1=I2SSCLK, GPE0=I2SLRCK */
110 GPECON = (GPECON & ~0x3ff) | 0x2aa;
111
112 /* Do not service DMA requests, yet */
113
114 /* clear any pending int and mask it */
115 s3c_regset32(&INTMSK, DMA2_MASK);
116 SRCPND = DMA2_MASK;
117
118 /* connect to FIQ */
119 s3c_regset32(&INTMOD, DMA2_MASK);
120}
121
122void pcm_postinit(void)
123{
124 audiohw_postinit();
125}
126
127void pcm_dma_apply_settings(void)
128{
129#ifdef HAVE_UDA1341
130 /* set prescaler and master clock rate according to freq */
131 IISPSR = (pcm_freq_parms [pcm_fsel][0] * IISPSR_PRESCALER_A) | pcm_freq_parms [pcm_fsel][0];
132 IISMOD |= ~IISMOD_MASTER_CLOCK_384FS | pcm_freq_parms [pcm_fsel][1] ;
133#endif
134
135 audiohw_set_frequency(pcm_fsel);
136}
137
138/* Connect the DMA and start filling the FIFO */
139static void play_start_pcm(void)
140{
141 /* clear pending DMA interrupt */
142 SRCPND = DMA2_MASK;
143
144 /* Flush any pending writes */
145 clean_dcache_range((char*)DISRC2-0x30000000, (DCON2 & 0xFFFFF) * 2);
146
147 /* unmask DMA interrupt when unlocking */
148 dma_play_lock.state = DMA2_MASK;
149
150 /* turn on the request */
151 IISCON |= (1<<5);
152
153 /* Activate the channel */
154 DMASKTRIG2 = 0x2;
155
156 /* turn off the idle */
157 IISCON &= ~(1<<3);
158
159 /* start the IIS */
160 IISCON |= (1<<0);
161}
162
163/* Disconnect the DMA and wait for the FIFO to clear */
164static void play_stop_pcm(void)
165{
166 /* Mask DMA interrupt */
167 s3c_regset32(&INTMSK, DMA2_MASK);
168
169 /* De-Activate the DMA channel */
170 DMASKTRIG2 = 0x4;
171
172 /* are we playing? wait for the chunk to finish */
173 if (dma_play_lock.state != 0)
174 {
175 /* wait for the FIFO to empty and DMA to stop */
176 while ((IISCON & (1<<7)) || (DMASKTRIG2 & 0x2));
177 }
178
179 /* Keep interrupt masked when unlocking */
180 dma_play_lock.state = 0;
181
182 /* turn off the request */
183 IISCON &= ~(1<<5);
184
185 /* turn on the idle */
186 IISCON |= (1<<3);
187
188 /* stop the IIS */
189 IISCON &= ~(1<<0);
190}
191
192void pcm_play_dma_start(const void *addr, size_t size)
193{
194 /* Enable the IIS clock */
195 s3c_regset32(&CLKCON, 1<<17);
196
197 /* stop any DMA in progress - idle IIS */
198 play_stop_pcm();
199
200 /* connect DMA to the FIFO and enable the FIFO */
201 IISFCON = (1<<15) | (1<<13);
202
203 /* set DMA dest */
204 DIDST2 = (unsigned int)&IISFIFO;
205
206 /* IIS is on the APB bus, INT when TC reaches 0, fixed dest addr */
207 DIDSTC2 = 0x03;
208
209 /* set DMA source and options */
210 DISRC2 = (unsigned int)addr + 0x30000000;
211 /* How many transfers to make - we transfer half-word at a time = 2 bytes */
212 /* DMA control: CURR_TC int, single service mode, I2SSDO int, HW trig */
213 /* no auto-reload, half-word (16bit) */
214 DCON2 = DMA_CONTROL_SETUP | (size / 2);
215 DISRCC2 = 0x00; /* memory is on AHB bus, increment addresses */
216
217 play_start_pcm();
218}
219
220/* Promptly stop DMA transfers and stop IIS */
221void pcm_play_dma_stop(void)
222{
223 play_stop_pcm();
224
225 /* Disconnect the IIS clock */
226 s3c_regclr32(&CLKCON, 1<<17);
227}
228
229void pcm_play_dma_pause(bool pause)
230{
231 if (pause)
232 {
233 /* pause playback on current buffer */
234 play_stop_pcm();
235 }
236 else
237 {
238 /* restart playback on current buffer */
239 /* make sure we're aligned on left channel - skip any right
240 channel sample left waiting */
241 DISRC2 = (DCSRC2 + 2) & ~0x3;
242 DCON2 = DMA_CONTROL_SETUP | (DSTAT2 & 0xFFFFE);
243 play_start_pcm();
244 }
245}
246
247void fiq_handler(void)
248{
249 static unsigned char *start;
250 static size_t size;
251 register pcm_more_callback_type get_more; /* No stack for this */
252
253 /* clear any pending interrupt */
254 SRCPND = DMA2_MASK;
255
256 /* Buffer empty. Try to get more. */
257 get_more = pcm_callback_for_more;
258 size = 0;
259
260 if (get_more == NULL || (get_more(&start, &size), size == 0))
261 {
262 /* Callback missing or no more DMA to do */
263 pcm_play_dma_stop();
264 pcm_play_dma_stopped_callback();
265 }
266 else
267 {
268 /* Flush any pending cache writes */
269 clean_dcache_range(start, size);
270
271 /* set the new DMA values */
272 DCON2 = DMA_CONTROL_SETUP | (size >> 1);
273 DISRC2 = (unsigned int)start + 0x30000000;
274
275 /* Re-Activate the channel */
276 DMASKTRIG2 = 0x2;
277 }
278}
279
280size_t pcm_get_bytes_waiting(void)
281{
282 /* lie a little and only return full pairs */
283 return (DSTAT2 & 0xFFFFE) * 2;
284}
285
286const void * pcm_play_dma_get_peak_buffer(int *count)
287{
288 unsigned long addr = DCSRC2;
289 int cnt = DSTAT2;
290 *count = (cnt & 0xFFFFF) >> 1;
291 return (void *)((addr + 2) & ~3);
292}
diff --git a/firmware/target/arm/s3c2440/mini2440/powermgmt-mini2440.c b/firmware/target/arm/s3c2440/mini2440/powermgmt-mini2440.c
new file mode 100644
index 0000000000..5584993040
--- /dev/null
+++ b/firmware/target/arm/s3c2440/mini2440/powermgmt-mini2440.c
@@ -0,0 +1,69 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2009 by Bob Cousins
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#include "config.h"
22#include "system.h"
23#include "adc.h"
24#include "power.h"
25#include "powermgmt.h"
26
27/* The following constants are dummy values since there is no battery */
28const unsigned short battery_level_dangerous[BATTERY_TYPES_COUNT] =
29{
30 3450
31};
32
33const unsigned short battery_level_shutoff[BATTERY_TYPES_COUNT] =
34{
35 3400
36};
37
38/* voltages (millivolt) of 0%, 10%, ... 100% when charging disabled */
39const unsigned short percent_to_volt_discharge[BATTERY_TYPES_COUNT][11] =
40{
41 /* Typical Li Ion 830mAH */
42 { 3480, 3550, 3590, 3610, 3630, 3650, 3700, 3760, 3800, 3910, 3990 },
43};
44
45/* voltages (millivolt) of 0%, 10%, ... 100% when charging enabled */
46const unsigned short percent_to_volt_charge[11] =
47{
48 /* Typical Li Ion 830mAH */
49 3480, 3550, 3590, 3610, 3630, 3650, 3700, 3760, 3800, 3910, 3990
50};
51
52
53/* Returns battery voltage from ADC [millivolts] */
54/* full-scale (2^10) in millivolt */
55unsigned int battery_adc_voltage(void)
56{
57 /* Since we have no battery, return a fully charged value */
58 return 4000 * 1024 / 1000;
59}
60
61unsigned int input_millivolts(void)
62{
63 unsigned int batt_millivolts = battery_voltage();
64
65 /* No battery, return nominal value */
66 return batt_millivolts;
67}
68
69
diff --git a/firmware/target/arm/s3c2440/sd-s3c2440.c b/firmware/target/arm/s3c2440/sd-s3c2440.c
index 78c9e9bf23..9cb9bdfc58 100644
--- a/firmware/target/arm/s3c2440/sd-s3c2440.c
+++ b/firmware/target/arm/s3c2440/sd-s3c2440.c
@@ -126,9 +126,6 @@ static unsigned char * uncached_buffer;
126/***************************************************************************** 126/*****************************************************************************
127 Definitions specific to Mini2440 127 Definitions specific to Mini2440
128 *****************************************************************************/ 128 *****************************************************************************/
129#define FCLK 405000000
130#define HCLK (FCLK/4) /* = 101,250,000 */
131#define PCLK (HCLK/2) /* = 50,625,000 */
132 129
133#define SD_CD (1<<8) /* Port G */ 130#define SD_CD (1<<8) /* Port G */
134#define SD_WP (1<<8) /* Port H */ 131#define SD_WP (1<<8) /* Port H */
@@ -206,8 +203,11 @@ static void debug_r1(int cmd)
206void SDI (void) 203void SDI (void)
207{ 204{
208 int status = SDIDSTA; 205 int status = SDIDSTA;
206#ifndef HAVE_MULTIDRIVE
207 const int curr_card = 0;
208#endif
209 209
210 transfer_error[curr_card] = status 210 transfer_error[curr_card] = status
211#if 0 211#if 0
212 & ( S3C2410_SDIDSTA_CRCFAIL | S3C2410_SDIDSTA_RXCRCFAIL | 212 & ( S3C2410_SDIDSTA_CRCFAIL | S3C2410_SDIDSTA_RXCRCFAIL |
213 S3C2410_SDIDSTA_DATATIMEOUT ) 213 S3C2410_SDIDSTA_DATATIMEOUT )
@@ -619,7 +619,9 @@ static int sd_transfer_sectors(IF_MD2(int card_no,) unsigned long start,
619 sd_enable(true); 619 sd_enable(true);
620 set_leds(SD_ACTIVE_LED); 620 set_leds(SD_ACTIVE_LED);
621 621
622#ifdef HAVE_MULTIDRIVE
622 curr_card = card_no; 623 curr_card = card_no;
624#endif
623 if (card_info[card_no].initialized <= 0) 625 if (card_info[card_no].initialized <= 0)
624 { 626 {
625 ret = sd_init_card(card_no); 627 ret = sd_init_card(card_no);
@@ -814,6 +816,9 @@ int sd_read_sectors(IF_MD2(int card_no,) unsigned long start, int incount,
814int sd_write_sectors(IF_MD2(int card_no,) unsigned long start, int count, 816int sd_write_sectors(IF_MD2(int card_no,) unsigned long start, int count,
815 const void* outbuf) 817 const void* outbuf)
816{ 818{
819#ifndef HAVE_MULTIDRIVE
820 const int card_no = 0;
821#endif
817 dbgprintf ("sd_write %d %x %d\n", card_no, start, count); 822 dbgprintf ("sd_write %d %x %d\n", card_no, start, count);
818 823
819 return sd_transfer_sectors(IF_MD2(card_no,) start, count, outbuf, true); 824 return sd_transfer_sectors(IF_MD2(card_no,) start, count, outbuf, true);
diff --git a/firmware/target/arm/s3c2440/system-target.h b/firmware/target/arm/s3c2440/system-target.h
index 9808d31255..cf3db301eb 100644
--- a/firmware/target/arm/s3c2440/system-target.h
+++ b/firmware/target/arm/s3c2440/system-target.h
@@ -27,30 +27,34 @@
27/* TODO: Needs checking/porting */ 27/* TODO: Needs checking/porting */
28 28
29#ifdef GIGABEAT_F 29#ifdef GIGABEAT_F
30#define CPUFREQ_DEFAULT 98784000 30 #define CPUFREQ_DEFAULT 98784000
31#define CPUFREQ_NORMAL 98784000 31 #define CPUFREQ_NORMAL 98784000
32#define CPUFREQ_MAX 296352000 32 #define CPUFREQ_MAX 296352000
33 33
34#ifdef BOOTLOADER 34 #ifdef BOOTLOADER
35/* All addresses within rockbox are in IRAM in the bootloader so 35 /* All addresses within rockbox are in IRAM in the bootloader so
36 are therefore uncached */ 36 are therefore uncached */
37#define UNCACHED_ADDR(a) (a) 37 #define UNCACHED_ADDR(a) (a)
38#else /* !BOOTLOADER */ 38 #else /* !BOOTLOADER */
39#define UNCACHED_BASE_ADDR 0x30000000 39 #define UNCACHED_BASE_ADDR 0x30000000
40#define UNCACHED_ADDR(a) ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR )) 40 #define UNCACHED_ADDR(a) ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR ))
41#endif /* BOOTLOADER */ 41 #endif /* BOOTLOADER */
42 42
43#elif defined(MINI2440) 43#elif defined(MINI2440)
44 44
45#define CPUFREQ_DEFAULT 101250000 45 #define CPUFREQ_DEFAULT 101250000
46#define CPUFREQ_NORMAL 101250000 46 #define CPUFREQ_NORMAL 101250000
47#define CPUFREQ_MAX 405000000 47 #define CPUFREQ_MAX 405000000
48 48
49#define UNCACHED_BASE_ADDR 0x30000000 49 #define UNCACHED_BASE_ADDR 0x30000000
50#define UNCACHED_ADDR(a) ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR )) 50 #define UNCACHED_ADDR(a) ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR ))
51 51
52 #define FCLK 405000000
53 #define HCLK (FCLK/4) /* = 101,250,000 */
54 #define PCLK (HCLK/2) /* = 50,625,000 */
55
52#else 56#else
53#error Unknown target 57 #error Unknown target
54#endif 58#endif
55 59
56 60
diff --git a/firmware/target/arm/s3c2440/uart-s3c2440.c b/firmware/target/arm/s3c2440/uart-s3c2440.c
index 2a61b61a39..84282f731a 100644
--- a/firmware/target/arm/s3c2440/uart-s3c2440.c
+++ b/firmware/target/arm/s3c2440/uart-s3c2440.c
@@ -30,13 +30,32 @@
30#include "kernel.h" 30#include "kernel.h"
31#include "thread.h" 31#include "thread.h"
32 32
33#include "system-target.h"
33#include "uart-s3c2440.h" 34#include "uart-s3c2440.h"
34 35
35#define FCLK 405000000 36#define MAX_PRINTF_BUF 1024
36#define HCLK (FCLK/4) /* = 101,250,000 */
37#define PCLK (HCLK/2) /* = 50,625,000 */
38 37
39#define MAX_TX_BUF 1024 38/****************************************************************************
39 * serial driver API
40 ****************************************************************************/
41void serial_setup (void)
42{
43 uart_init();
44 uart_init_device(DEBUG_UART_PORT);
45}
46
47int tx_rdy(void)
48{
49 if (uart_tx_ready (DEBUG_UART_PORT))
50 return 1;
51 else
52 return 0;
53}
54
55void tx_writec(unsigned char c)
56{
57 uart_send_byte (DEBUG_UART_PORT, c);
58}
40 59
41 60
42/**************************************************************************** 61/****************************************************************************
@@ -46,10 +65,12 @@
46void uart_printf (const char *format, ...) 65void uart_printf (const char *format, ...)
47{ 66{
48 static bool debug_uart_init = false; 67 static bool debug_uart_init = false;
49 static char tx_buf [MAX_TX_BUF]; 68 static char tx_buf [MAX_PRINTF_BUF];
50 69
51 int len; 70 int len;
52 unsigned char *ptr; 71 unsigned char *ptr;
72 int j;
73
53 va_list ap; 74 va_list ap;
54 va_start(ap, format); 75 va_start(ap, format);
55 76
@@ -59,11 +80,16 @@ void uart_printf (const char *format, ...)
59 80
60 if (!debug_uart_init) 81 if (!debug_uart_init)
61 { 82 {
62 uart_init_device(UART_DEBUG); 83 uart_init_device(DEBUG_UART_PORT);
63 debug_uart_init = true; 84 debug_uart_init = true;
64 } 85 }
65 86
66 uart_send (UART_DEBUG, tx_buf, len); 87 for (j=0; j<len; j++)
88 {
89 uart_send_byte (DEBUG_UART_PORT, tx_buf[j]);
90 if ( tx_buf[j] == '\n')
91 uart_send_byte (DEBUG_UART_PORT, '\r');
92 }
67} 93}
68 94
69/**************************************************************************** 95/****************************************************************************
@@ -142,28 +168,49 @@ bool uart_config (unsigned dev, unsigned speed, unsigned num_bits,
142 return true; 168 return true;
143} 169}
144 170
171/* transmit */
172bool uart_tx_ready (unsigned dev)
173{
174 /* test if transmit buffer empty */
175 switch (dev)
176 {
177 case 0:
178 if (UTRSTAT0 & 0x02)
179 return true;
180 else
181 return false;
182 break;
183 case 1:
184 if (UTRSTAT1 & 0x02)
185 return true;
186 else
187 return false;
188 break;
189 case 2:
190 if (UTRSTAT2 & 0x02)
191 return true;
192 else
193 return false;
194 break;
195 }
196 return false;
197}
198
145bool uart_send_byte (unsigned dev, char ch) 199bool uart_send_byte (unsigned dev, char ch)
146{ 200{
201 /* wait for transmit buffer empty */
202 while (!uart_tx_ready(dev))
203 ;
204
147 switch (dev) 205 switch (dev)
148 { 206 {
149 case 0: 207 case 0:
150 /* wait for transmit buffer empty */
151 while ((UTRSTAT0 & 0x02) == 0)
152 ;
153 UTXH0 = ch; 208 UTXH0 = ch;
154 break; 209 break;
155
156 case 1: 210 case 1:
157 /* wait for transmit buffer empty */
158 while ((UTRSTAT1 & 0x02) == 0)
159 ;
160 UTXH1 = ch; 211 UTXH1 = ch;
161 break; 212 break;
162
163 case 2: 213 case 2:
164 /* wait for transmit buffer empty */
165 while ((UTRSTAT2 & 0x02) == 0)
166 ;
167 UTXH2 = ch; 214 UTXH2 = ch;
168 break; 215 break;
169 } 216 }
@@ -171,26 +218,26 @@ bool uart_send_byte (unsigned dev, char ch)
171 return true; 218 return true;
172} 219}
173 220
174char uart_rx_ready (unsigned dev) 221/* Receive */
222
223bool uart_rx_ready (unsigned dev)
175{ 224{
225 /* test receive buffer data ready */
176 switch (dev) 226 switch (dev)
177 { 227 {
178 case 0: 228 case 0:
179 /* wait for receive buffer data ready */
180 if (UTRSTAT0 & 0x01) 229 if (UTRSTAT0 & 0x01)
181 return true; 230 return true;
182 else 231 else
183 return false; 232 return false;
184 break; 233 break;
185 case 1: 234 case 1:
186 /* wait for receive buffer data ready */
187 if (UTRSTAT1 & 0x01) 235 if (UTRSTAT1 & 0x01)
188 return true; 236 return true;
189 else 237 else
190 return false; 238 return false;
191 break; 239 break;
192 case 2: 240 case 2:
193 /* wait for receive buffer data ready */
194 if (UTRSTAT2 & 0x01) 241 if (UTRSTAT2 & 0x01)
195 return true; 242 return true;
196 else 243 else
@@ -202,43 +249,34 @@ char uart_rx_ready (unsigned dev)
202 249
203char uart_read_byte (unsigned dev) 250char uart_read_byte (unsigned dev)
204{ 251{
252 while (!uart_rx_ready(dev))
253 ;
205 switch (dev) 254 switch (dev)
206 { 255 {
207 case 0: 256 case 0:
208 while (!uart_rx_ready(dev))
209 ;
210 return URXH0; 257 return URXH0;
211 break; 258 break;
212 case 1: 259 case 1:
213 while (!uart_rx_ready(dev))
214 ;
215 return URXH1; 260 return URXH1;
216 break; 261 break;
217 case 2: 262 case 2:
218 while (!uart_rx_ready(dev))
219 ;
220 return URXH2; 263 return URXH2;
221 break; 264 break;
222 } 265 }
223 266
224 return true; 267 return '\0';
225} 268}
226 269
227/**************************************************************************** 270/****************************************************************************
228 * General 271 * General
229 *****************************************************************************/ 272 *****************************************************************************/
230 273
231bool uart_send (unsigned dev, char *buf, unsigned len) 274bool uart_send_buf (unsigned dev, char *buf, unsigned len)
232{ 275{
233 unsigned index=0; 276 unsigned index=0;
234 while (index<len) 277 while (index<len)
235 { 278 {
236 uart_send_byte (dev, buf[index]); 279 uart_send_byte (dev, buf[index]);
237
238 /* hack for ASCII terminals */
239 if (buf[index] == '\n')
240 uart_send_byte (dev, '\r');
241
242 index++; 280 index++;
243 } 281 }
244 return true; 282 return true;
diff --git a/firmware/target/arm/s3c2440/uart-s3c2440.h b/firmware/target/arm/s3c2440/uart-s3c2440.h
index 01a8f67ea1..38790af8e8 100644
--- a/firmware/target/arm/s3c2440/uart-s3c2440.h
+++ b/firmware/target/arm/s3c2440/uart-s3c2440.h
@@ -22,16 +22,17 @@
22#ifndef __UART_S3C2440_H__ 22#ifndef __UART_S3C2440_H__
23#define __UART_S3C2440_H__ 23#define __UART_S3C2440_H__
24 24
25#define UART_DEBUG 0 25/* target specific */
26#define DEBUG_UART_PORT 0
26 27
27#define UART_NO_PARITY 0 28#define UART_NO_PARITY 0
28#define UART_ODD_PARITY 4 29#define UART_ODD_PARITY 4
29#define UART_EVEN_PARITY 5 30#define UART_EVEN_PARITY 5
30#define UART_MARK_PARITY 6 31#define UART_MARK_PARITY 6
31#define UART_SPACE_PARITY 7 32#define UART_SPACE_PARITY 7
32 33
33#define UART_1_STOP_BIT 0 34#define UART_1_STOP_BIT 0
34#define UART_2_STOP_BIT 1 35#define UART_2_STOP_BIT 1
35 36
36bool uart_init (void); 37bool uart_init (void);
37void uart_printf (const char *format, ...); 38void uart_printf (const char *format, ...);
@@ -39,10 +40,13 @@ void uart_printf (const char *format, ...);
39/* low level routines */ 40/* low level routines */
40bool uart_init_device (unsigned dev); 41bool uart_init_device (unsigned dev);
41bool uart_config (unsigned dev, unsigned speed, unsigned num_bits, unsigned parity, unsigned stop_bits); 42bool uart_config (unsigned dev, unsigned speed, unsigned num_bits, unsigned parity, unsigned stop_bits);
42bool uart_send (unsigned dev, char *buf, unsigned len);
43 43
44bool uart_tx_ready (unsigned dev);
45bool uart_send_byte (unsigned dev, char ch);
46bool uart_send_buf (unsigned dev, char *buf, unsigned len);
47
48bool uart_rx_ready (unsigned dev);
44char uart_read_byte (unsigned dev); 49char uart_read_byte (unsigned dev);
45char uart_rx_ready (unsigned dev);
46 50
47 51
48#endif 52#endif