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-rw-r--r--firmware/target/arm/tms320dm320/dsp/Makefile55
-rw-r--r--firmware/target/arm/tms320dm320/dsp/aic23.c58
-rw-r--r--firmware/target/arm/tms320dm320/dsp/arm.c49
-rw-r--r--firmware/target/arm/tms320dm320/dsp/arm.h32
-rw-r--r--firmware/target/arm/tms320dm320/dsp/audio.h26
-rw-r--r--firmware/target/arm/tms320dm320/dsp/dma.c87
-rw-r--r--firmware/target/arm/tms320dm320/dsp/dma.h28
-rw-r--r--firmware/target/arm/tms320dm320/dsp/ipc.h69
-rw-r--r--firmware/target/arm/tms320dm320/dsp/linker.cmd29
-rw-r--r--firmware/target/arm/tms320dm320/dsp/main.c145
-rw-r--r--firmware/target/arm/tms320dm320/dsp/registers.h93
-rw-r--r--firmware/target/arm/tms320dm320/dsp/tsc2100.c40
-rw-r--r--firmware/target/arm/tms320dm320/dsp/vectors.asm143
13 files changed, 854 insertions, 0 deletions
diff --git a/firmware/target/arm/tms320dm320/dsp/Makefile b/firmware/target/arm/tms320dm320/dsp/Makefile
new file mode 100644
index 0000000000..8f016378fd
--- /dev/null
+++ b/firmware/target/arm/tms320dm320/dsp/Makefile
@@ -0,0 +1,55 @@
1# __________ __ ___.
2# Open \______ \ ____ ____ | | _\_ |__ _______ ___
3# Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
4# Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
5# Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
6# \/ \/ \/ \/ \/
7# $Id: Makefile 12058 2007-01-18 00:46:52Z dave $
8#
9
10# http://daniel.haxx.se/blog/2007/11/18/free-to-use-compiler-from-ti/
11CC = cl500
12LD = lnk500
13CFLAGS = $(BUILDDATE)
14# There's more in linker.cmd.
15LDFLAGS = -w
16
17OBJS = arm.obj main.obj vectors.obj dma.obj
18
19ifeq ($(findstring -DCREATIVE_ZV,$(TARGET)), -DCREATIVE_ZV)
20OBJS += aic23.obj
21else
22OBJS += tsc2100.obj
23endif
24
25OBJS := $(patsubst %.obj, $(OBJDIR)/%.obj, $(OBJS))
26
27all: $(BUILDDIR)/dsp-image.h
28
29clean:
30 $(call PRINTS,cleaning DSP firmware)rm -f $(OBJS) $(OBJDIR)/dsp-image.out $(OBJDIR)/dsp-image.xml
31
32$(BUILDDIR)/dsp-image.h: $(OBJS) linker.cmd
33 $(call PRINTS,LNK500 dsp-image.out)lnk500 $(LDFLAGS) -o $(OBJDIR)/dsp-image.out $^
34 $(call PRINTS,OFD500+XML2H $(@F))ofd500 -x -o /dev/stdout $(OBJDIR)/dsp-image.out | python $(TOOLSDIR)/xml2h.py $(OBJDIR)/dsp-image.xml > $@
35
36$(OBJDIR)/%.obj: %.asm
37 $(SILENT)mkdir -p $(dir $@)
38 $(call PRINTS,CL500 $<)$(CC) $(CFLAGS) -fr $(dir $@) $<
39
40$(OBJDIR)/%.obj: %.c
41 $(SILENT)mkdir -p $(dir $@)
42 $(call PRINTS,CL500 $<)$(CC) $(CFLAGS) -fr $(dir $@) $<
43
44$(OBJDIR)/arm.obj: arm.c arm.h registers.h ipc.h
45
46$(OBJDIR)/main.obj: main.c arm.h registers.h ipc.h dma.h audio.h
47
48$(OBJDIR)/aic23.obj: aic23.c audio.h registers.h
49
50$(OBJDIR)/tsc2100.obj: tsc2100.c audio.h registers.h
51
52$(OBJDIR)/dma.obj: dma.c dma.h registers.h ipc.h
53
54# For PRINTS.
55include $(TOOLSDIR)/make.inc
diff --git a/firmware/target/arm/tms320dm320/dsp/aic23.c b/firmware/target/arm/tms320dm320/dsp/aic23.c
new file mode 100644
index 0000000000..e6eb8b4c29
--- /dev/null
+++ b/firmware/target/arm/tms320dm320/dsp/aic23.c
@@ -0,0 +1,58 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Maurus Cuelenaere
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#include "audio.h"
21#include "registers.h"
22
23/* based on http://archopen.svn.sourceforge.net/viewvc/archopen/ArchOpen/trunk/libdsp/aic23.c?revision=213&view=markup */
24void audiohw_init(void)
25{
26 /* port config */
27#if 0
28 SPCR10 = 0; /* DLB = 0 ** RJUST = 0 ** CLKSTP = 0 ** DXENA = 0 ** ABIS = 0 ** RINTM = 0 ** RSYNCER = 0 ** RFULL = 0 ** RRDY = 0 ** RRST = 0 */
29 SPCR20 = (1 << 9); /* FREE = 1 ** SOFT = 0 ** FRST = 0 ** GRST = 0 ** XINTM = 0 ** XSYNCER = 0 ** XEMPTY = 0 ** XRDY = 0 ** XRST = 0 */
30 RCR10 = (1 << 8) | (2 << 5); /* RFRLEN1 = 1 ** RWDLEN1 = 2 */
31 RCR20 = 0; /* RPHASE = 0 ** RFRLEN2 = 0 ** RWDLEN2 = 0 ** RCOMPAND = 0 ** RFIG = 0 ** RDATDLY = 0 */
32 XCR10 = (1 << 8) | (2 << 5); /* XFRLEN1 = 1 ** XWDLEN1 = 2 */
33 XCR20 = 0; /* XPHASE = 0 ** XFRLEN2 = 0 ** XWDLEN2 = 0 ** XCOMPAND = 0 ** XFIG = 0 ** XDATDLY = 0 */
34 SRGR10 = 0; /* FWID = 0 ** CLKGDV = 0 */
35 SRGR20 = 0; /* FREE = 0 ** CLKSP = 0 ** CLKSM = 0 ** FSGM = 0 ** FPER = 0 */
36 PCR0 = (1 << 1) | 1; /* IDLEEN = 0 ** XIOEN = 0 ** RIOEN = 0 ** FSXM = 0 ** FSRM = 0 ** SCLKME = 0 ** CLKSSTAT = 0 ** DXSTAT = 0 ** DRSTAT = 0 ** CLKXM = 0 ** CLKRM = 0 ** FSXP = 0 ** FSRP = 0 ** CLKXP = 1 ** CLKRP = 1 */
37#else
38 SPCR10 = 0;
39 SPCR20 = 0x0200; /* SPCR : free running mode */
40
41 RCR10 = 0x00A0;
42 RCR20 = 0x00A1; /* RCR : 32 bit receive data length */
43
44 XCR10 = 0x00A0;
45 XCR20 = 0x00A0; /* XCR : 32 bit transmit data length */
46
47 SRGR10 = 0;
48 SRGR20 = 0x3000; /* SRGR 1 & 2 */
49
50 PCR0 = 0x000E - 8; /* PCR : FSX, FSR active low, external FS/CLK source */
51#endif
52}
53
54void audiohw_postinit(void)
55{
56 /* Trigger first XEVT0 */
57 SPCR20 |= 1;
58}
diff --git a/firmware/target/arm/tms320dm320/dsp/arm.c b/firmware/target/arm/tms320dm320/dsp/arm.c
new file mode 100644
index 0000000000..eedff7d439
--- /dev/null
+++ b/firmware/target/arm/tms320dm320/dsp/arm.c
@@ -0,0 +1,49 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Catalin Patulea
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#include <stdio.h>
21#include "arm.h"
22#include "registers.h"
23#include "ipc.h"
24
25volatile struct ipc_message status;
26
27volatile int acked;
28interrupt void handle_int0(void) {
29 IFR = 1;
30 acked = 1;
31}
32
33void debugf(const char *fmt, ...) {
34 va_list args;
35 va_start(args, fmt);
36 status.msg = MSG_DEBUGF;
37 vsnprintf((char *)status.payload.debugf.buffer, sizeof(status), fmt, args);
38 va_end(args);
39
40 /* Wait until ARM has picked up data. */
41 acked = 0;
42 int_arm();
43 while (!acked) {
44 /* IDLE alone never seems to wake up :( */
45 asm(" IDLE 1");
46 asm(" NOP");
47 }
48 acked = 2;
49}
diff --git a/firmware/target/arm/tms320dm320/dsp/arm.h b/firmware/target/arm/tms320dm320/dsp/arm.h
new file mode 100644
index 0000000000..515c75ad26
--- /dev/null
+++ b/firmware/target/arm/tms320dm320/dsp/arm.h
@@ -0,0 +1,32 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Catalin Patulea
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#ifndef ARM_H
21#define ARM_H
22#include "registers.h"
23
24extern volatile struct ipc_message status;
25
26void debugf(const char *fmt, ...);
27
28inline void int_arm(void) {
29 CP_INTC = 1 << 3;
30}
31
32#endif
diff --git a/firmware/target/arm/tms320dm320/dsp/audio.h b/firmware/target/arm/tms320dm320/dsp/audio.h
new file mode 100644
index 0000000000..e5bf003301
--- /dev/null
+++ b/firmware/target/arm/tms320dm320/dsp/audio.h
@@ -0,0 +1,26 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Maurus Cuelenaere
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#ifndef AUDIO_H
21#define AUDIO_H
22
23void audiohw_init(void);
24void audiohw_postinit(void);
25
26#endif
diff --git a/firmware/target/arm/tms320dm320/dsp/dma.c b/firmware/target/arm/tms320dm320/dsp/dma.c
new file mode 100644
index 0000000000..fe39dc3b21
--- /dev/null
+++ b/firmware/target/arm/tms320dm320/dsp/dma.c
@@ -0,0 +1,87 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Catalin Patulea
11 * Copyright (C) 2008 by Maurus Cuelenaere
12 *
13 * All files in this archive are subject to the GNU General Public License.
14 * See the file COPYING in the source tree root for full license agreement.
15 *
16 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
17 * KIND, either express or implied.
18 *
19 ****************************************************************************/
20
21#include "registers.h"
22#include "arm.h"
23#include "dma.h"
24
25/* This is placed at the right (aligned) address using linker.cmd. */
26#pragma DATA_SECTION (data, ".dma")
27signed short data[PCM_SIZE / 2];
28
29/* Filled in by loader. */
30unsigned short sdem_addrh;
31unsigned short sdem_addrl;
32
33interrupt void handle_dma0(void) {
34 unsigned long sdem_addr;
35 /* Byte offset to half-buffer locked by DMA0.
36 0 for top, PCM_SIZE/2(0x4000) for bottom */
37 unsigned short dma0_locked;
38 unsigned short dma0_unlocked;
39
40 IFR = 1 << 6;
41
42 /* DMSRC0 is the beginning of the DMA0-locked SARAM half-buffer. */
43 DMSA = 0x00 /* DMSRC0 */;
44 dma0_locked = (DMSDN << 1) & (PCM_SIZE / 2);
45 dma0_unlocked = dma0_locked ^ (PCM_SIZE / 2);
46
47 /* ARM, decode into same half, in SDRAM. */
48 status.msg = MSG_REFILL;
49 status.payload.refill.topbottom = dma0_locked;
50 int_arm();
51
52 /* DMAC, copy opposite halves from SDRAM to SARAM. */
53 sdem_addr = ((unsigned long)sdem_addrh << 16 | sdem_addrl) + dma0_unlocked;
54 SDEM_ADDRL = sdem_addr & 0xffff;
55 SDEM_ADDRH = sdem_addr >> 16;
56 DSP_ADDRL = (unsigned short)data + (dma0_unlocked >> 1);
57 DSP_ADDRH = 0;
58 DMA_SIZE = PCM_SIZE / 2;
59 DMA_CTRL = 0;
60
61 status.payload.refill._DMA_TRG = DMA_TRG;
62 status.payload.refill._SDEM_ADDRH = SDEM_ADDRH;
63 status.payload.refill._SDEM_ADDRL = SDEM_ADDRL;
64 status.payload.refill._DSP_ADDRH = DSP_ADDRH;
65 status.payload.refill._DSP_ADDRL = DSP_ADDRL;
66
67 DMA_TRG = 1;
68}
69
70interrupt void handle_dmac(void) {
71 IFR = 1 << 11;
72}
73
74void dma_init(void) {
75 /* Configure DMA */
76 DMSFC0 = 2 << 12 | 1 << 11; /* Event XEVT0, 32-bit transfers, 0 frame count */
77 DMMCR0 = 1 << 14 | 1 << 13 | /* Interrupts generated, Half and full buffer */
78 1 << 12 | 1 << 8 | 1 << 6 | 1; /* ABU mode,
79 From data space with postincrement,
80 To data space with no mod */
81 DMSRC0 = (unsigned short)&data;
82 DMDST0 = (unsigned short)&DXR20; /* First of two-word register pair */
83 DMCTR0 = sizeof(data);
84
85 /* Run, Rudolf, run! (with DMA0 interrupts) */
86 DMPREC = 2 << 6 | 1;
87}
diff --git a/firmware/target/arm/tms320dm320/dsp/dma.h b/firmware/target/arm/tms320dm320/dsp/dma.h
new file mode 100644
index 0000000000..d776302796
--- /dev/null
+++ b/firmware/target/arm/tms320dm320/dsp/dma.h
@@ -0,0 +1,28 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Maurus Cuelenaere
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#ifndef DMA_H
21#define DMA_H
22
23#include "ipc.h"
24
25extern signed short data[PCM_SIZE / 2];
26void dma_init(void);
27
28#endif
diff --git a/firmware/target/arm/tms320dm320/dsp/ipc.h b/firmware/target/arm/tms320dm320/dsp/ipc.h
new file mode 100644
index 0000000000..ada4f17f61
--- /dev/null
+++ b/firmware/target/arm/tms320dm320/dsp/ipc.h
@@ -0,0 +1,69 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Catalin Patulea
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#ifndef IPC_H
21#define IPC_H
22
23/* Inter-Processor Communication */
24
25/* Meant to be included by both DSP and ARM code. */
26#ifdef __GNUC__
27/* aligned(2) is VERY IMPORTANT. It ensures gcc generates code with "STRH"
28 instead of with "STRB". STRB in the DSP memory range is broken because
29 the HPI is in 16-bit mode. */
30#define PACKED __attribute__((packed)) __attribute__((aligned (2)))
31#else
32#define PACKED
33#endif
34
35#define PCM_SIZE 32768 /* bytes */
36
37struct sdram_buffer {
38 unsigned long addr;
39 unsigned short bytes;
40} PACKED;
41
42#define SDRAM_BUFFERS 4
43
44struct ipc_message {
45 unsigned short msg;
46 union {
47#define MSG_INIT 1
48 struct msg_init {
49 unsigned short sdem_addrl;
50 unsigned short sdem_addrh;
51 } init PACKED;
52#define MSG_DEBUGF 2
53 struct {
54 short buffer[80];
55 } debugf PACKED;
56#define MSG_REFILL 3
57 struct {
58 unsigned short topbottom; /* byte offset to unlocked half-buffer */
59
60 unsigned short _DMA_TRG;
61 unsigned short _SDEM_ADDRH;
62 unsigned short _SDEM_ADDRL;
63 unsigned short _DSP_ADDRH;
64 unsigned short _DSP_ADDRL;
65 unsigned short _DMA_SIZE;
66 } refill PACKED;
67 } payload PACKED;
68} PACKED;
69#endif
diff --git a/firmware/target/arm/tms320dm320/dsp/linker.cmd b/firmware/target/arm/tms320dm320/dsp/linker.cmd
new file mode 100644
index 0000000000..844fe25903
--- /dev/null
+++ b/firmware/target/arm/tms320dm320/dsp/linker.cmd
@@ -0,0 +1,29 @@
1-c
2-x
3-stack 0x1000
4-heap 0x100
5-l rts500.lib
6
7MEMORY
8{
9PAGE 0:
10 DARAM: origin = 80h, length = 7F80h
11 SARAM: origin = 8000h, length = 4000h
12}
13
14SECTIONS
15{
16 .text PAGE 0
17 .cinit PAGE 0
18 .switch PAGE 0
19
20 .bss PAGE 0
21 .const PAGE 0
22 .sysmem PAGE 0
23 .stack PAGE 0
24
25 .vectors : PAGE 0 load = 7F80h
26
27 /* DMA buffers for ABU mode must start on a 2*size boundary. */
28 .dma : PAGE 0 load = 0x8000
29}
diff --git a/firmware/target/arm/tms320dm320/dsp/main.c b/firmware/target/arm/tms320dm320/dsp/main.c
new file mode 100644
index 0000000000..6ba001db2f
--- /dev/null
+++ b/firmware/target/arm/tms320dm320/dsp/main.c
@@ -0,0 +1,145 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Catalin Patulea
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#include "registers.h"
21#include "arm.h"
22#include "ipc.h"
23#include "dma.h"
24#include "audio.h"
25#include <math.h>
26
27void main(void) {
28 register int i;
29 register signed short *p;
30
31 TCR = 1 << 4; /* Stop the timer. */
32 IMR = 0xffff; /* Unmask all interrupts. */
33 IFR = IFR; /* Clear all pending interrupts. */
34 asm(" rsbx INTM"); /* Globally enable interrupts. */
35
36 audiohw_init();
37
38 dma_init();
39
40 audiohw_postinit();
41
42#if 0
43 for (i = 0; i < 32; i++)
44 {
45 double ratio = ((double)i)/32.0;
46 double rad = 3.0*3.141592*ratio;
47 double normal = sin(rad);
48 double scaled = 32767.0*(normal);
49 data[2*i + 0] = -(signed short)scaled;
50 data[2*i + 1] = (signed short)scaled;
51 }
52
53 debugf("starting write");
54
55 i = 0;
56 p = data;
57 SPSA0 = 0x01;
58 for (;;) {
59 while ((SPSD0 & (1 << 1)) == 0);
60 DXR20 = *p++; // left channel
61 DXR10 = *p++; // right channel
62 if (++i == 32)
63 {
64 p = data;
65 i = 0;
66 }
67 }
68#endif
69 debugf("DSP inited...");
70
71 for (;;) {
72 asm(" IDLE 1");
73 asm(" NOP");
74 }
75}
76
77/* Obsoleted/testing snippets: */
78#ifdef REMAP_VECTORS
79 /* Remap vectors to 0x3F80 (set in linker.cmd). */
80 PMST = (PMST & 0x7f) | 0x3F80;
81
82 /* Make sure working interrupts aren't a fluke. */
83 memset((unsigned short *)0x7f80, 0, 0x80);
84#endif
85
86#ifdef DATA_32_SINE
87 for (i = 0; i < 32; i++) {
88 double ratio = ((double)i)/32.0;
89 double rad = 3.0*3.141592*ratio;
90 double normal = sin(rad);
91 double scaled = 32767.0*(normal);
92 data[2*i + 0] = -(signed short)scaled;
93 data[2*i + 1] = (signed short)scaled;
94 }
95#endif
96
97#ifdef MANUAL_TRANSFER
98 register signed short *p;
99
100 debugf("starting write");
101
102 i = 0;
103 p = data;
104 SPSA0 = 0x01;
105 for (;;) {
106 while ((SPSD0 & (1 << 1)) == 0);
107 DXR20 = *p++; // left channel
108 DXR10 = *p++; // right channel
109 if (++i == 32) {
110 p = data;
111 i = 0;
112 }
113 }
114#endif
115
116#ifdef INIT_MSG
117 /* Copy codec init data (before debugf, which clobbers status). */
118 if (status.msg != MSG_INIT) {
119 debugf("No init message (%04x: %04x %04x %04x %04x instead)",
120 (unsigned short)&status,
121 ((unsigned short *)&status)[0],
122 ((unsigned short *)&status)[1],
123 ((unsigned short *)&status)[2],
124 ((unsigned short *)&status)[3]);
125 return;
126 }
127
128 memcpy(&init, (void *)&status.payload.init, sizeof(init));
129#endif
130
131#ifdef IPC_SIZES
132 debugf("sizeof(ipc_message)=%uw offset(ipc_message.payload)=%uw",
133 sizeof(struct ipc_message), (int)&((struct ipc_message*)0)->payload);
134#endif
135
136#ifdef VERBOSE_INIT
137 debugf("codec started with PCM at SDRAM offset %04x:%04x",
138 sdem_addrh, sdem_addrl);
139#endif
140
141#ifdef SPIKE_DATA
142 for (i = 0; i < 0x2000; i++) {
143 data[2*i ] = data[2*i+1] = ((i % 32) == 0) * 32767;
144 }
145#endif
diff --git a/firmware/target/arm/tms320dm320/dsp/registers.h b/firmware/target/arm/tms320dm320/dsp/registers.h
new file mode 100644
index 0000000000..57e32be490
--- /dev/null
+++ b/firmware/target/arm/tms320dm320/dsp/registers.h
@@ -0,0 +1,93 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Catalin Patulea
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#ifndef REGISTERS_H
21#define REGISTERS_H
22
23#define C5409_REG(addr) (*(volatile unsigned short *)(addr))
24
25/* This is NOT good for reading, only for writing. */
26#define BANKED_REG(spsa, spsd, subaddr) spsa = (subaddr), spsd
27
28#define IMR C5409_REG(0x00)
29#define IFR C5409_REG(0x01)
30
31#define PMST C5409_REG(0x1D)
32
33#define TCR C5409_REG(0x26)
34
35/* McBSP 0 (SPRU302 Chapter 2) */
36#define DXR20 C5409_REG(0x22)
37#define DXR10 C5409_REG(0x23)
38#define SPSA0 C5409_REG(0x38)
39#define SPSD0 C5409_REG(0x39)
40#define SPCR10 BANKED_REG(SPSA0, SPSD0, 0x00)
41#define SPCR20 BANKED_REG(SPSA0, SPSD0, 0x01)
42#define RCR10 BANKED_REG(SPSA0, SPSD0, 0x02)
43#define RCR20 BANKED_REG(SPSA0, SPSD0, 0x03)
44#define XCR10 BANKED_REG(SPSA0, SPSD0, 0x04)
45#define XCR20 BANKED_REG(SPSA0, SPSD0, 0x05)
46#define SRGR10 BANKED_REG(SPSA0, SPSD0, 0x06)
47#define SRGR20 BANKED_REG(SPSA0, SPSD0, 0x07)
48#define PCR0 BANKED_REG(SPSA0, SPSD0, 0x0e)
49
50/* McBSP 1 */
51#define DXR21 C5409_REG(0x42)
52#define DXR11 C5409_REG(0x43)
53#define SPSA1 C5409_REG(0x48)
54#define SPSD1 C5409_REG(0x49)
55#define SPCR11 BANKED_REG(SPSA1, SPSD1, 0x00)
56#define SPCR21 BANKED_REG(SPSA1, SPSD1, 0x01)
57#define XCR11 BANKED_REG(SPSA1, SPSD1, 0x04)
58#define XCR21 BANKED_REG(SPSA1, SPSD1, 0x05)
59#define PCR1 BANKED_REG(SPSA1, SPSD1, 0x0e)
60
61/* DMA */
62#define DMPREC C5409_REG(0x54)
63#define DMSA C5409_REG(0x55)
64#define DMSDI C5409_REG(0x56)
65#define DMSDN C5409_REG(0x57)
66#define DMSRC0 BANKED_REG(DMSA, DMSDN, 0x00)
67#define DMDST0 BANKED_REG(DMSA, DMSDN, 0x01)
68#define DMCTR0 BANKED_REG(DMSA, DMSDN, 0x02)
69#define DMSFC0 BANKED_REG(DMSA, DMSDN, 0x03)
70#define DMMCR0 BANKED_REG(DMSA, DMSDN, 0x04)
71
72
73/* DM320 */
74ioport unsigned short port280;
75#define CP_INTC port280
76ioport unsigned short port8000;
77#define SDEM_ADDRL port8000
78ioport unsigned short port8001;
79#define SDEM_ADDRH port8001
80ioport unsigned short port8002;
81#define DSP_ADDRL port8002
82ioport unsigned short port8003;
83#define DSP_ADDRH port8003
84ioport unsigned short port8004;
85#define DMA_SIZE port8004
86ioport unsigned short port8005;
87#define DMA_CTRL port8005
88ioport unsigned short port8006;
89#define DMA_TRG port8006
90ioport unsigned short port8007;
91#define DMA_REST port8007
92
93#endif
diff --git a/firmware/target/arm/tms320dm320/dsp/tsc2100.c b/firmware/target/arm/tms320dm320/dsp/tsc2100.c
new file mode 100644
index 0000000000..f9c7a2d724
--- /dev/null
+++ b/firmware/target/arm/tms320dm320/dsp/tsc2100.c
@@ -0,0 +1,40 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Catalin Patulea
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#include "audio.h"
21#include "registers.h"
22
23void audiohw_init(void)
24{
25 /* Configure McBSP */
26 SPCR10 = 0; /* Receiver reset */
27 SPCR20 = 3 << 4; /* Rate gen disabled, RINT=XSYNCERR, TX disabled for now */
28 PCR0 = 1 << 1; /* Serial port pins, external frame sync, external clock,
29 frame sync FSX is active-high,
30 TX data sampled on falling clock */
31 XCR10 = 0x00a0; /* 1 word per frame, 32 bits per word */
32 XCR20 = 0; /* Single-phase, unexpected frame pulse restarts xfer,
33 0-bit data delay */
34}
35
36void audiohw_postinit(void)
37{
38 /* Trigger first XEVT0 */
39 SPCR20 |= 1;
40}
diff --git a/firmware/target/arm/tms320dm320/dsp/vectors.asm b/firmware/target/arm/tms320dm320/dsp/vectors.asm
new file mode 100644
index 0000000000..1551d996fc
--- /dev/null
+++ b/firmware/target/arm/tms320dm320/dsp/vectors.asm
@@ -0,0 +1,143 @@
1;* Copyright (c) 2007, C.P.R. Baaij
2;* All rights reserved.
3;*
4;* Redistribution and use in source and binary forms, with or without
5;* modification, are permitted provided that the following conditions are met:
6;* * Redistributions of source code must retain the above copyright
7;* notice, this list of conditions and the following disclaimer.
8;* * Redistributions in binary form must reproduce the above copyright
9;* notice, this list of conditions and the following disclaimer in the
10;* documentation and/or other materials provided with the distribution.
11;*
12;* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
13;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
14;* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15;* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17;* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
18;* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
19;* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20;* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21;* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22
23;*-----------------------------------------------------------------------------*
24;* Interrupt Vectors *
25;*-----------------------------------------------------------------------------*
26 .mmregs
27
28 ; External Functions
29 .global _handle_int0
30 .global _c_int00
31 .global _handle_dma0
32 .global _handle_dmac
33
34 .sect ".vectors"
35; Reset Interrupt
36RS_V: BD _c_int00
37 NOP
38 NOP
39
40; Non-Maskable Interrupt
41NMI_V: RETE
42 NOP
43 NOP
44 NOP
45
46; Software Interrupts
47SINt17_V: .space 4*16
48SINt18_V: .space 4*16
49SINt19_V: .space 4*16
50SINt20_V: .space 4*16
51SINt21_V: .space 4*16
52SINt22_V: .space 4*16
53SINt23_V: .space 4*16
54SINt24_V: .space 4*16
55SINt25_V: .space 4*16
56SINt26_V: .space 4*16
57SINt27_V: .space 4*16
58SINt28_V: .space 4*16
59SINt29_V: .space 4*16
60SINt30_V: .space 4*16
61; INT0 - ARM Interrupting DSP via HPIB
62INT0_V: BD _handle_int0
63 NOP
64 NOP
65; INT1 - Interrupt is generated based on the settings of DSP_SYNC_STATE and
66; DSP_SYNC_MASK register of the coprocessor subsystem or when DSPINT1 bit in
67; CP_INTC is set.
68INT1_V: RETE
69 NOP
70 NOP
71 NOP
72; INT2 - Interrupt is generated when DSPINT2 bit in CP_INTC register of the
73; coprocessor subsystem is set.
74INT2_V: RETE
75 NOP
76 NOP
77 NOP
78; Timer Interrupt
79TINT_V: RETE
80 NOP
81 NOP
82 NOP
83; McBSP0 receive interrupt
84BRINT0_V: RETE
85 NOP
86 NOP
87 NOP
88; McBSP0 transmit interrupt
89BXINT0_V: RETE
90 NOP
91 NOP
92 NOP
93; DMA Channel-0 interrupt
94DMAC0_V: BD _handle_dma0
95 NOP
96 NOP
97; DMA Channel-1 interrupt
98DMAC1_V: RETE
99 NOP
100 NOP
101 NOP
102; INT3 - Interrupt is generated when DSPINT3 bit in CP_INTC register of the
103; coprocessor subsystem is set or on write of any value to BRKPT_TRG
104INT3_V: RETE
105 NOP
106 NOP
107 NOP
108; HPIB HINT to DSP
109HINT_V: RETE
110 NOP
111 NOP
112 NOP
113; BRINT1/DMAC2 McBSP1 receive interrupt
114BRINT1_V: RETE
115 NOP
116 NOP
117 NOP
118; BXINT1/DMAC3 McBSP1 transmit interrupt
119BXINT1_V: RETE
120 NOP
121 NOP
122 NOP
123; DMA Channel-4 interrupt
124DMAC4_V: RETE
125 NOP
126 NOP
127 NOP
128; DMA Channel-5 interrupt
129DMAC5_V: RETE
130 NOP
131 NOP
132 NOP
133; HPIB DMAC interrupt
134HPIB_DMA_V: BD _handle_dmac
135 NOP
136 NOP
137
138; EHIF interrupt to DSP
139EHIV_V: RETE
140 NOP
141 NOP
142 NOP
143 .end
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-05 15:01:47 +0000