diff options
Diffstat (limited to 'firmware/target/arm/tms320dm320/dsp/tsc2100.c')
-rw-r--r-- | firmware/target/arm/tms320dm320/dsp/tsc2100.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/firmware/target/arm/tms320dm320/dsp/tsc2100.c b/firmware/target/arm/tms320dm320/dsp/tsc2100.c new file mode 100644 index 0000000000..f9c7a2d724 --- /dev/null +++ b/firmware/target/arm/tms320dm320/dsp/tsc2100.c | |||
@@ -0,0 +1,40 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Catalin Patulea | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | |||
20 | #include "audio.h" | ||
21 | #include "registers.h" | ||
22 | |||
23 | void audiohw_init(void) | ||
24 | { | ||
25 | /* Configure McBSP */ | ||
26 | SPCR10 = 0; /* Receiver reset */ | ||
27 | SPCR20 = 3 << 4; /* Rate gen disabled, RINT=XSYNCERR, TX disabled for now */ | ||
28 | PCR0 = 1 << 1; /* Serial port pins, external frame sync, external clock, | ||
29 | frame sync FSX is active-high, | ||
30 | TX data sampled on falling clock */ | ||
31 | XCR10 = 0x00a0; /* 1 word per frame, 32 bits per word */ | ||
32 | XCR20 = 0; /* Single-phase, unexpected frame pulse restarts xfer, | ||
33 | 0-bit data delay */ | ||
34 | } | ||
35 | |||
36 | void audiohw_postinit(void) | ||
37 | { | ||
38 | /* Trigger first XEVT0 */ | ||
39 | SPCR20 |= 1; | ||
40 | } | ||