diff options
Diffstat (limited to 'firmware/target/arm/tms320dm320/dsp/registers.h')
-rw-r--r-- | firmware/target/arm/tms320dm320/dsp/registers.h | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/firmware/target/arm/tms320dm320/dsp/registers.h b/firmware/target/arm/tms320dm320/dsp/registers.h new file mode 100644 index 0000000000..57e32be490 --- /dev/null +++ b/firmware/target/arm/tms320dm320/dsp/registers.h | |||
@@ -0,0 +1,93 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Catalin Patulea | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | |||
20 | #ifndef REGISTERS_H | ||
21 | #define REGISTERS_H | ||
22 | |||
23 | #define C5409_REG(addr) (*(volatile unsigned short *)(addr)) | ||
24 | |||
25 | /* This is NOT good for reading, only for writing. */ | ||
26 | #define BANKED_REG(spsa, spsd, subaddr) spsa = (subaddr), spsd | ||
27 | |||
28 | #define IMR C5409_REG(0x00) | ||
29 | #define IFR C5409_REG(0x01) | ||
30 | |||
31 | #define PMST C5409_REG(0x1D) | ||
32 | |||
33 | #define TCR C5409_REG(0x26) | ||
34 | |||
35 | /* McBSP 0 (SPRU302 Chapter 2) */ | ||
36 | #define DXR20 C5409_REG(0x22) | ||
37 | #define DXR10 C5409_REG(0x23) | ||
38 | #define SPSA0 C5409_REG(0x38) | ||
39 | #define SPSD0 C5409_REG(0x39) | ||
40 | #define SPCR10 BANKED_REG(SPSA0, SPSD0, 0x00) | ||
41 | #define SPCR20 BANKED_REG(SPSA0, SPSD0, 0x01) | ||
42 | #define RCR10 BANKED_REG(SPSA0, SPSD0, 0x02) | ||
43 | #define RCR20 BANKED_REG(SPSA0, SPSD0, 0x03) | ||
44 | #define XCR10 BANKED_REG(SPSA0, SPSD0, 0x04) | ||
45 | #define XCR20 BANKED_REG(SPSA0, SPSD0, 0x05) | ||
46 | #define SRGR10 BANKED_REG(SPSA0, SPSD0, 0x06) | ||
47 | #define SRGR20 BANKED_REG(SPSA0, SPSD0, 0x07) | ||
48 | #define PCR0 BANKED_REG(SPSA0, SPSD0, 0x0e) | ||
49 | |||
50 | /* McBSP 1 */ | ||
51 | #define DXR21 C5409_REG(0x42) | ||
52 | #define DXR11 C5409_REG(0x43) | ||
53 | #define SPSA1 C5409_REG(0x48) | ||
54 | #define SPSD1 C5409_REG(0x49) | ||
55 | #define SPCR11 BANKED_REG(SPSA1, SPSD1, 0x00) | ||
56 | #define SPCR21 BANKED_REG(SPSA1, SPSD1, 0x01) | ||
57 | #define XCR11 BANKED_REG(SPSA1, SPSD1, 0x04) | ||
58 | #define XCR21 BANKED_REG(SPSA1, SPSD1, 0x05) | ||
59 | #define PCR1 BANKED_REG(SPSA1, SPSD1, 0x0e) | ||
60 | |||
61 | /* DMA */ | ||
62 | #define DMPREC C5409_REG(0x54) | ||
63 | #define DMSA C5409_REG(0x55) | ||
64 | #define DMSDI C5409_REG(0x56) | ||
65 | #define DMSDN C5409_REG(0x57) | ||
66 | #define DMSRC0 BANKED_REG(DMSA, DMSDN, 0x00) | ||
67 | #define DMDST0 BANKED_REG(DMSA, DMSDN, 0x01) | ||
68 | #define DMCTR0 BANKED_REG(DMSA, DMSDN, 0x02) | ||
69 | #define DMSFC0 BANKED_REG(DMSA, DMSDN, 0x03) | ||
70 | #define DMMCR0 BANKED_REG(DMSA, DMSDN, 0x04) | ||
71 | |||
72 | |||
73 | /* DM320 */ | ||
74 | ioport unsigned short port280; | ||
75 | #define CP_INTC port280 | ||
76 | ioport unsigned short port8000; | ||
77 | #define SDEM_ADDRL port8000 | ||
78 | ioport unsigned short port8001; | ||
79 | #define SDEM_ADDRH port8001 | ||
80 | ioport unsigned short port8002; | ||
81 | #define DSP_ADDRL port8002 | ||
82 | ioport unsigned short port8003; | ||
83 | #define DSP_ADDRH port8003 | ||
84 | ioport unsigned short port8004; | ||
85 | #define DMA_SIZE port8004 | ||
86 | ioport unsigned short port8005; | ||
87 | #define DMA_CTRL port8005 | ||
88 | ioport unsigned short port8006; | ||
89 | #define DMA_TRG port8006 | ||
90 | ioport unsigned short port8007; | ||
91 | #define DMA_REST port8007 | ||
92 | |||
93 | #endif | ||