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-rw-r--r--firmware/target/arm/tms320dm320/mrobe-500/usb-mr500.c38
-rw-r--r--firmware/target/arm/tms320dm320/system-dm320.c8
2 files changed, 32 insertions, 14 deletions
diff --git a/firmware/target/arm/tms320dm320/mrobe-500/usb-mr500.c b/firmware/target/arm/tms320dm320/mrobe-500/usb-mr500.c
index 1fbc1ce60f..06a501179d 100644
--- a/firmware/target/arm/tms320dm320/mrobe-500/usb-mr500.c
+++ b/firmware/target/arm/tms320dm320/mrobe-500/usb-mr500.c
@@ -30,32 +30,44 @@
30void usb_init_device(void) { 30void usb_init_device(void) {
31 logf("mxx: SOC Init"); 31 logf("mxx: SOC Init");
32 32
33 /* The EMIF timing that is currently used may not be apropriate when the 33 /* The following EMIF timing values are from the OF:
34 * device is boosted. The following values were used with sucess too:
35 * IO_EMIF_CS4CTRL1 = 0x66AB; 34 * IO_EMIF_CS4CTRL1 = 0x66AB;
36 * IO_EMIF_CS4CTRL2 = 0x4220; 35 * IO_EMIF_CS4CTRL2 = 0x4220;
36 *
37 * These EMIF timing values are more agressive, but appear to work as long
38 * as USB_TRANS_BLOCK is defined in the USB driver:
39 * IO_EMIF_CS4CTRL1 = 0x2245;
40 * IO_EMIF_CS4CTRL2 = 0x4110;
41 *
42 * When USB_TRANS_BLOCK is not defined the USB driver does not work unless
43 * the values from the OF are used.
37 */ 44 */
45
38 IO_EMIF_CS4CTRL1 = 0x2245; 46 IO_EMIF_CS4CTRL1 = 0x2245;
39 IO_EMIF_CS4CTRL2 = 0x4110; 47 IO_EMIF_CS4CTRL2 = 0x4110;
40 48
41 IO_GIO_DIR0 &= ~(1<<2); 49 /* Setup the m66591 reset signal */
42 IO_GIO_INV0 &= ~(1<<2); 50 IO_GIO_DIR0 &= ~(1<<2); /* output */
43 IO_GIO_FSEL0 &= ~(0x03); 51 IO_GIO_INV0 &= ~(1<<2); /* non-inverted */
52 IO_GIO_FSEL0 &= ~(0x03); /* normal pins */
53
54 /* Setup the m66591 interrupt signal */
55 IO_GIO_DIR0 |= 1<<3; /* input */
56 IO_GIO_INV0 &= ~(1<<3); /* non-inverted */
57 IO_GIO_IRQPORT |= 1<<3; /* enable EIRQ */
58
59 udelay(100);
44 60
45 /* Drive the reset pin low */ 61 /* Drive the reset pin low */
46 IO_GIO_BITCLR0 = 1<<2; 62 IO_GIO_BITCLR0 = 1<<2;
47 63
48 /* Wait a bit */ 64 /* Wait a bit */
49 udelay(3); 65 udelay(100);
50 66
51 /* Release the reset (drive it high) */ 67 /* Release the reset (drive it high) */
52 IO_GIO_BITSET0 = 1<<2; 68 IO_GIO_BITSET0 = 1<<2;
53
54 udelay(300);
55 69
56 IO_GIO_DIR0 |= 1<<3; 70 udelay(500);
57 IO_GIO_INV0 &= ~(1<<3);
58 IO_GIO_IRQPORT |= 1<<3;
59 71
60 /* Enable the MXX interrupt */ 72 /* Enable the MXX interrupt */
61 IO_INTC_EINT1 |= (1<<8); /* IRQ_GIO3 */ 73 IO_INTC_EINT1 |= (1<<8); /* IRQ_GIO3 */
diff --git a/firmware/target/arm/tms320dm320/system-dm320.c b/firmware/target/arm/tms320dm320/system-dm320.c
index d1f2ff1684..434b0065a5 100644
--- a/firmware/target/arm/tms320dm320/system-dm320.c
+++ b/firmware/target/arm/tms320dm320/system-dm320.c
@@ -102,7 +102,7 @@ static const unsigned short const irqpriority[] =
102 IRQ_ICE,IRQ_ARMCOM_RX,IRQ_ARMCOM_TX,IRQ_RESERVED 102 IRQ_ICE,IRQ_ARMCOM_RX,IRQ_ARMCOM_TX,IRQ_RESERVED
103}; /* IRQ priorities, ranging from highest to lowest */ 103}; /* IRQ priorities, ranging from highest to lowest */
104 104
105static void (* const irqvector[])(void) = 105static void (* const irqvector[])(void) __attribute__ ((section(".idata"))) =
106{ 106{
107 TIMER0,TIMER1,TIMER2,TIMER3,CCD_VD0,CCD_VD1, 107 TIMER0,TIMER1,TIMER2,TIMER3,CCD_VD0,CCD_VD1,
108 CCD_WEN,VENC,SERIAL0,SERIAL1,EXT_HOST,DSPHINT, 108 CCD_WEN,VENC,SERIAL0,SERIAL1,EXT_HOST,DSPHINT,
@@ -222,11 +222,16 @@ void system_init(void)
222 222
223 /* setup the clocks */ 223 /* setup the clocks */
224 IO_CLK_DIV0=0x0003; 224 IO_CLK_DIV0=0x0003;
225
226 /* SDRAM Divide by 3 */
225 IO_CLK_DIV1=0x0102; 227 IO_CLK_DIV1=0x0102;
226 IO_CLK_DIV2=0x021F; 228 IO_CLK_DIV2=0x021F;
227 IO_CLK_DIV3=0x1FFF; 229 IO_CLK_DIV3=0x1FFF;
228 IO_CLK_DIV4=0x1F00; 230 IO_CLK_DIV4=0x1F00;
229 231
232 /* 27 MHz input clock:
233 * PLLA = 27*11/1
234 */
230 IO_CLK_PLLA=0x80A0; 235 IO_CLK_PLLA=0x80A0;
231 IO_CLK_PLLB=0x80C0; 236 IO_CLK_PLLB=0x80C0;
232 237
@@ -286,6 +291,7 @@ void system_init(void)
286 ttb_init(); 291 ttb_init();
287 /* Make sure everything is mapped on itself */ 292 /* Make sure everything is mapped on itself */
288 map_section(0, 0, 0x1000, CACHE_NONE); 293 map_section(0, 0, 0x1000, CACHE_NONE);
294
289 /* Enable caching for RAM */ 295 /* Enable caching for RAM */
290 map_section(CONFIG_SDRAM_START, CONFIG_SDRAM_START, MEM, CACHE_ALL); 296 map_section(CONFIG_SDRAM_START, CONFIG_SDRAM_START, MEM, CACHE_ALL);
291 /* enable buffered writing for the framebuffer */ 297 /* enable buffered writing for the framebuffer */