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Diffstat (limited to 'firmware/target/arm/tms320dm320/dsp-dm320.c')
-rw-r--r--firmware/target/arm/tms320dm320/dsp-dm320.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/target/arm/tms320dm320/dsp-dm320.c b/firmware/target/arm/tms320dm320/dsp-dm320.c
index be9f8d8bd9..a8610f703a 100644
--- a/firmware/target/arm/tms320dm320/dsp-dm320.c
+++ b/firmware/target/arm/tms320dm320/dsp-dm320.c
@@ -66,7 +66,7 @@ void dsp_reset(void)
66 66
67 bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 8); 67 bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 8);
68 /* HPIB bus cycles will lock up the ARM in here. Don't touch DSP RAM. */ 68 /* HPIB bus cycles will lock up the ARM in here. Don't touch DSP RAM. */
69 nop; nop; 69 udelay(1);
70 bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 8); 70 bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 8);
71 71
72 /* TODO: Timeout. */ 72 /* TODO: Timeout. */
@@ -82,7 +82,7 @@ void dsp_wake(void)
82 /* The first time you INT0 the DSP, the ROM loader will branch to your RST 82 /* The first time you INT0 the DSP, the ROM loader will branch to your RST
83 handler. Subsequent times, your INT0 handler will get executed. */ 83 handler. Subsequent times, your INT0 handler will get executed. */
84 bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 7); 84 bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 7);
85 nop; nop; 85 udelay(1); /* wait atleast two DSP clocks */
86 bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 7); 86 bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 7);
87 87
88 restore_irq(old_level); 88 restore_irq(old_level);