diff options
author | Tomasz Moń <desowin@gmail.com> | 2011-12-26 09:45:18 +0000 |
---|---|---|
committer | Tomasz Moń <desowin@gmail.com> | 2011-12-26 09:45:18 +0000 |
commit | fdcf5e48e1221ca8575170269dcfd31fd6869152 (patch) | |
tree | f597c6b4862465697eb5d8a1274c7c1a48483b2a /firmware/target/arm/tms320dm320/dsp-dm320.c | |
parent | 5dba771d63b26195b24fc5bbd098aff733da2599 (diff) | |
download | rockbox-fdcf5e48e1221ca8575170269dcfd31fd6869152.tar.gz rockbox-fdcf5e48e1221ca8575170269dcfd31fd6869152.zip |
Sansa Connect: Set unknown GIOs to state with lowest power consumption. This slightly improves runtime.
Use proper delay for DSP reset and interrupt.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31438 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/tms320dm320/dsp-dm320.c')
-rw-r--r-- | firmware/target/arm/tms320dm320/dsp-dm320.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/target/arm/tms320dm320/dsp-dm320.c b/firmware/target/arm/tms320dm320/dsp-dm320.c index be9f8d8bd9..a8610f703a 100644 --- a/firmware/target/arm/tms320dm320/dsp-dm320.c +++ b/firmware/target/arm/tms320dm320/dsp-dm320.c | |||
@@ -66,7 +66,7 @@ void dsp_reset(void) | |||
66 | 66 | ||
67 | bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 8); | 67 | bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 8); |
68 | /* HPIB bus cycles will lock up the ARM in here. Don't touch DSP RAM. */ | 68 | /* HPIB bus cycles will lock up the ARM in here. Don't touch DSP RAM. */ |
69 | nop; nop; | 69 | udelay(1); |
70 | bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 8); | 70 | bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 8); |
71 | 71 | ||
72 | /* TODO: Timeout. */ | 72 | /* TODO: Timeout. */ |
@@ -82,7 +82,7 @@ void dsp_wake(void) | |||
82 | /* The first time you INT0 the DSP, the ROM loader will branch to your RST | 82 | /* The first time you INT0 the DSP, the ROM loader will branch to your RST |
83 | handler. Subsequent times, your INT0 handler will get executed. */ | 83 | handler. Subsequent times, your INT0 handler will get executed. */ |
84 | bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 7); | 84 | bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 7); |
85 | nop; nop; | 85 | udelay(1); /* wait atleast two DSP clocks */ |
86 | bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 7); | 86 | bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 7); |
87 | 87 | ||
88 | restore_irq(old_level); | 88 | restore_irq(old_level); |