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-rw-r--r--firmware/target/arm/tms320dm320/dsp-dm320.c4
-rw-r--r--firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S4
-rw-r--r--firmware/target/arm/tms320dm320/system-dm320.c13
3 files changed, 17 insertions, 4 deletions
diff --git a/firmware/target/arm/tms320dm320/dsp-dm320.c b/firmware/target/arm/tms320dm320/dsp-dm320.c
index be9f8d8bd9..a8610f703a 100644
--- a/firmware/target/arm/tms320dm320/dsp-dm320.c
+++ b/firmware/target/arm/tms320dm320/dsp-dm320.c
@@ -66,7 +66,7 @@ void dsp_reset(void)
66 66
67 bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 8); 67 bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 8);
68 /* HPIB bus cycles will lock up the ARM in here. Don't touch DSP RAM. */ 68 /* HPIB bus cycles will lock up the ARM in here. Don't touch DSP RAM. */
69 nop; nop; 69 udelay(1);
70 bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 8); 70 bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 8);
71 71
72 /* TODO: Timeout. */ 72 /* TODO: Timeout. */
@@ -82,7 +82,7 @@ void dsp_wake(void)
82 /* The first time you INT0 the DSP, the ROM loader will branch to your RST 82 /* The first time you INT0 the DSP, the ROM loader will branch to your RST
83 handler. Subsequent times, your INT0 handler will get executed. */ 83 handler. Subsequent times, your INT0 handler will get executed. */
84 bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 7); 84 bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 7);
85 nop; nop; 85 udelay(1); /* wait atleast two DSP clocks */
86 bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 7); 86 bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 7);
87 87
88 restore_irq(old_level); 88 restore_irq(old_level);
diff --git a/firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S b/firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S
index debd2cd2be..a356016fb4 100644
--- a/firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S
+++ b/firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S
@@ -121,7 +121,9 @@ _clock_setup:
121 /* IO_CLK_DIV1: Accelerator, SDRAM */ 121 /* IO_CLK_DIV1: Accelerator, SDRAM */
122 mwh 0x3088C, 0x0102 122 mwh 0x3088C, 0x0102
123 123
124 /* IO_CLK_DIV2: DSP, MS Clock */ 124 /* IO_CLK_DIV2: DSP, MS Clock
125 * OF must be booted with this value
126 */
125 mwhm 0x3088E, 0x0200 127 mwhm 0x3088E, 0x0200
126 128
127 # PLLA &= ~0x1000 (BIC #0x1000) 129 # PLLA &= ~0x1000 (BIC #0x1000)
diff --git a/firmware/target/arm/tms320dm320/system-dm320.c b/firmware/target/arm/tms320dm320/system-dm320.c
index dc9c2060c6..a918d99064 100644
--- a/firmware/target/arm/tms320dm320/system-dm320.c
+++ b/firmware/target/arm/tms320dm320/system-dm320.c
@@ -7,6 +7,7 @@
7 * \/ \/ \/ \/ \/ 7 * \/ \/ \/ \/ \/
8 * $Id$ 8 * $Id$
9 * 9 *
10 * Copyright (C) 2011 by Tomasz Moń
10 * Copyright (C) 2007 by Karl Kurbjun 11 * Copyright (C) 2007 by Karl Kurbjun
11 * 12 *
12 * This program is free software; you can redistribute it and/or 13 * This program is free software; you can redistribute it and/or
@@ -311,7 +312,7 @@ void system_init(void)
311#endif 312#endif
312 { 313 {
313#ifdef SANSA_CONNECT 314#ifdef SANSA_CONNECT
314 /* Setting AHB divisor to 0 causes MMC/SD interface to lock */ 315 /* Setting AHB divisor to 0 increases power consumption */
315 clock_arm_slow = (1 << 8) | 3; 316 clock_arm_slow = (1 << 8) | 3;
316 clock_arm_fast = (1 << 8) | 1; 317 clock_arm_fast = (1 << 8) | 1;
317#else 318#else
@@ -379,6 +380,16 @@ void system_init(void)
379 /* Disable External Memory interface (used for accessing NOR flash) */ 380 /* Disable External Memory interface (used for accessing NOR flash) */
380 bitclr16(&IO_CLK_MOD0, CLK_MOD0_EMIF); 381 bitclr16(&IO_CLK_MOD0, CLK_MOD0_EMIF);
381#endif 382#endif
383
384 /* Unknown GIOs - set them to save power */
385 /* GIO40 - output 0
386 * GIO28 - output 0
387 */
388 IO_GIO_DIR2 &= ~(1 << 8);
389 IO_GIO_BITCLR2 = (1 << 8);
390
391 IO_GIO_DIR1 &= ~(1 << 12);
392 IO_GIO_BITCLR1 = (1 << 12);
382#endif 393#endif
383} 394}
384 395