1 files changed, 48 insertions, 48 deletions
diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S
index fe2a2c1980..bb6d910e22 100644
--- a/firmware/target/arm/s5l8700/crt0.S
+++ b/firmware/target/arm/s5l8700/crt0.S
@@ -260,64 +260,64 @@ start_loc:
 #if defined(MEIZU_M6SP) || defined(MEIZU_M3)
    /* setup SDRAM for Meizu M6SP */
-    ldr r1, =0x38200000
+    ldr r1, =0x38200000
-    // configure SDR drive strength and pad settings
+    // configure SDR drive strength and pad settings
    mov r0, #SDR_DSS_SEL_B
-    str r0, [r1, #0x4C] // MIU_DSS_SEL_B
+    str r0, [r1, #0x4C] // MIU_DSS_SEL_B
    mov r0, #SDR_DSS_SEL_O
-    str r0, [r1, #0x50] // MIU_DSS_SEL_O
+    str r0, [r1, #0x50] // MIU_DSS_SEL_O
    mov r0, #SDR_DSS_SEL_C
-    str r0, [r1, #0x54] // MIU_DSS_SEL_C
+    str r0, [r1, #0x54] // MIU_DSS_SEL_C
-    mov r0, #2
+    mov r0, #2
-    str r0, [r1, #0x60] // SSTL2_PAD_ON
+    str r0, [r1, #0x60] // SSTL2_PAD_ON
-    // select SDR mode
+    // select SDR mode
    ldr r0, [r1, #0x40]
-    mov r2, #0xFFFDFFFF
+    mov r2, #0xFFFDFFFF
-    and r0, r0, r2
+    and r0, r0, r2
-    orr r0, r0, #1
+    orr r0, r0, #1
-    str r0, [r1, #0x40] // MIUORG
+    str r0, [r1, #0x40] // MIUORG
    // set controller configuration
    mov r0, #SDR_CONFIG
    str r0, [r1]        // MIUCON
-    // set SDRAM timing
+    // set SDRAM timing
    ldr r0, =SDR_TIMING
-    str r0, [r1, #0x10] // MIUSDPARA
+    str r0, [r1, #0x10] // MIUSDPARA
-    // set refresh rate
+    // set refresh rate
-    mov r0, #0x1080
+    mov r0, #0x1080
-    str r0, [r1, #0x08] // MIUAREF
+    str r0, [r1, #0x08] // MIUAREF
-    // initialise SDRAM 
+    // initialise SDRAM 
-    mov r0, #0x003
+    mov r0, #0x003
-    str r0, [r1, #0x04] // MIUCOM = nop
+    str r0, [r1, #0x04] // MIUCOM = nop
-    ldr r0, =0x203
+    ldr r0, =0x203
-    str r0, [r1, #0x04] // MIUCOM = precharge all banks
+    str r0, [r1, #0x04] // MIUCOM = precharge all banks
-    nop
+    nop
-    nop
+    nop
-    nop
+    nop
-    ldr r0, =0x303
+    ldr r0, =0x303
-    str r0, [r1, #0x04] // MIUCOM = auto-refresh
+    str r0, [r1, #0x04] // MIUCOM = auto-refresh
-    nop
+    nop
-    nop
+    nop
-    nop
+    nop
-    nop
+    nop
-    str r0, [r1, #0x04] // MIUCOM = auto-refresh
+    str r0, [r1, #0x04] // MIUCOM = auto-refresh
-    nop
+    nop
-    nop
+    nop
-    nop
+    nop
-    nop
+    nop
-    str r0, [r1, #0x04] // MIUCOM = auto-refresh
+    str r0, [r1, #0x04] // MIUCOM = auto-refresh
-    nop
+    nop
-    nop
+    nop
-    nop
+    nop
-    nop
+    nop
-    // set mode register
+    // set mode register
    mov r0, #SDR_MRS
-    str r0, [r1, #0x0C] // MIUMRS
+    str r0, [r1, #0x0C] // MIUMRS
-    ldr r0, =0x103
+    ldr r0, =0x103
-    str r0, [r1, #0x04] // MIUCOM = mode register set
+    str r0, [r1, #0x04] // MIUCOM = mode register set
    ldr r0, =SDR_EMRS
-    str r0, [r1, #0x0C] // MIUMRS
+    str r0, [r1, #0x0C] // MIUMRS
-    ldr r0, =0x103
+    ldr r0, =0x103
-    str r0, [r1, #0x04] // MIUCOM = mode register set
+    str r0, [r1, #0x04] // MIUCOM = mode register set
 #endif /* MEIZU_M6SP */
    mov r1, #0x1

diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S index fe2a2c1980..bb6d910e22 100644 --- a/firmware/target/arm/s5l8700/crt0.S +++ b/firmware/target/arm/s5l8700/crt0.S
@@ -260,64 +260,64 @@ start_loc:
260		260
261	#if defined(MEIZU_M6SP) \|\| defined(MEIZU_M3)	261	#if defined(MEIZU_M6SP) \|\| defined(MEIZU_M3)
262	/* setup SDRAM for Meizu M6SP */	262	/* setup SDRAM for Meizu M6SP */
263	ldr r1, =0x38200000	263	ldr r1, =0x38200000
264	// configure SDR drive strength and pad settings	264	// configure SDR drive strength and pad settings
265	mov r0, #SDR_DSS_SEL_B	265	mov r0, #SDR_DSS_SEL_B
266	str r0, [r1, #0x4C] // MIU_DSS_SEL_B	266	str r0, [r1, #0x4C] // MIU_DSS_SEL_B
267	mov r0, #SDR_DSS_SEL_O	267	mov r0, #SDR_DSS_SEL_O
268	str r0, [r1, #0x50] // MIU_DSS_SEL_O	268	str r0, [r1, #0x50] // MIU_DSS_SEL_O
269	mov r0, #SDR_DSS_SEL_C	269	mov r0, #SDR_DSS_SEL_C
270	str r0, [r1, #0x54] // MIU_DSS_SEL_C	270	str r0, [r1, #0x54] // MIU_DSS_SEL_C
271	mov r0, #2	271	mov r0, #2
272	str r0, [r1, #0x60] // SSTL2_PAD_ON	272	str r0, [r1, #0x60] // SSTL2_PAD_ON
273	// select SDR mode	273	// select SDR mode
274	ldr r0, [r1, #0x40]	274	ldr r0, [r1, #0x40]
275	mov r2, #0xFFFDFFFF	275	mov r2, #0xFFFDFFFF
276	and r0, r0, r2	276	and r0, r0, r2
277	orr r0, r0, #1	277	orr r0, r0, #1
278	str r0, [r1, #0x40] // MIUORG	278	str r0, [r1, #0x40] // MIUORG
279	// set controller configuration	279	// set controller configuration
280	mov r0, #SDR_CONFIG	280	mov r0, #SDR_CONFIG
281	str r0, [r1] // MIUCON	281	str r0, [r1] // MIUCON
282	// set SDRAM timing	282	// set SDRAM timing
283	ldr r0, =SDR_TIMING	283	ldr r0, =SDR_TIMING
284	str r0, [r1, #0x10] // MIUSDPARA	284	str r0, [r1, #0x10] // MIUSDPARA
285	// set refresh rate	285	// set refresh rate
286	mov r0, #0x1080	286	mov r0, #0x1080
287	str r0, [r1, #0x08] // MIUAREF	287	str r0, [r1, #0x08] // MIUAREF
288	// initialise SDRAM	288	// initialise SDRAM
289	mov r0, #0x003	289	mov r0, #0x003
290	str r0, [r1, #0x04] // MIUCOM = nop	290	str r0, [r1, #0x04] // MIUCOM = nop
291	ldr r0, =0x203	291	ldr r0, =0x203
292	str r0, [r1, #0x04] // MIUCOM = precharge all banks	292	str r0, [r1, #0x04] // MIUCOM = precharge all banks
293	nop	293	nop
294	nop	294	nop
295	nop	295	nop
296	ldr r0, =0x303	296	ldr r0, =0x303
297	str r0, [r1, #0x04] // MIUCOM = auto-refresh	297	str r0, [r1, #0x04] // MIUCOM = auto-refresh
298	nop	298	nop
299	nop	299	nop
300	nop	300	nop
301	nop	301	nop
302	str r0, [r1, #0x04] // MIUCOM = auto-refresh	302	str r0, [r1, #0x04] // MIUCOM = auto-refresh
303	nop	303	nop
304	nop	304	nop
305	nop	305	nop
306	nop	306	nop
307	str r0, [r1, #0x04] // MIUCOM = auto-refresh	307	str r0, [r1, #0x04] // MIUCOM = auto-refresh
308	nop	308	nop
309	nop	309	nop
310	nop	310	nop
311	nop	311	nop
312	// set mode register	312	// set mode register
313	mov r0, #SDR_MRS	313	mov r0, #SDR_MRS
314	str r0, [r1, #0x0C] // MIUMRS	314	str r0, [r1, #0x0C] // MIUMRS
315	ldr r0, =0x103	315	ldr r0, =0x103
316	str r0, [r1, #0x04] // MIUCOM = mode register set	316	str r0, [r1, #0x04] // MIUCOM = mode register set
317	ldr r0, =SDR_EMRS	317	ldr r0, =SDR_EMRS
318	str r0, [r1, #0x0C] // MIUMRS	318	str r0, [r1, #0x0C] // MIUMRS
319	ldr r0, =0x103	319	ldr r0, =0x103
320	str r0, [r1, #0x04] // MIUCOM = mode register set	320	str r0, [r1, #0x04] // MIUCOM = mode register set
321	#endif /* MEIZU_M6SP */	321	#endif /* MEIZU_M6SP */
322		322
323	mov r1, #0x1	323	mov r1, #0x1