diff options
Diffstat (limited to 'firmware/target/arm/s3c2440')
-rw-r--r-- | firmware/target/arm/s3c2440/adc-s3c2440.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/dma-s3c2440.c | 4 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c | 18 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/i2c-s3c2440.c | 12 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/kernel-s3c2440.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/lcd-s3c2440.c | 10 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c | 18 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/sd-s3c2440.c | 4 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/system-s3c2440.c | 18 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/system-target.h | 10 |
10 files changed, 35 insertions, 63 deletions
diff --git a/firmware/target/arm/s3c2440/adc-s3c2440.c b/firmware/target/arm/s3c2440/adc-s3c2440.c index f42a3d2b6a..2e0cf8a512 100644 --- a/firmware/target/arm/s3c2440/adc-s3c2440.c +++ b/firmware/target/arm/s3c2440/adc-s3c2440.c | |||
@@ -39,7 +39,7 @@ void adc_init(void) | |||
39 | int i; | 39 | int i; |
40 | 40 | ||
41 | /* Turn on the ADC PCLK */ | 41 | /* Turn on the ADC PCLK */ |
42 | s3c_regset32(&CLKCON, 1<<15); | 42 | bitset32(&CLKCON, 1<<15); |
43 | 43 | ||
44 | /* Set channel 0, normal mode, disable "start by read" */ | 44 | /* Set channel 0, normal mode, disable "start by read" */ |
45 | ADCCON &= ~(0x3F); | 45 | ADCCON &= ~(0x3F); |
diff --git a/firmware/target/arm/s3c2440/dma-s3c2440.c b/firmware/target/arm/s3c2440/dma-s3c2440.c index b83897cb22..c8df4fcc75 100644 --- a/firmware/target/arm/s3c2440/dma-s3c2440.c +++ b/firmware/target/arm/s3c2440/dma-s3c2440.c | |||
@@ -76,8 +76,8 @@ void dma_init(void) | |||
76 | INTPND = DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK; | 76 | INTPND = DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK; |
77 | 77 | ||
78 | /* Enable interrupt in controller */ | 78 | /* Enable interrupt in controller */ |
79 | s3c_regclr32(&INTMOD, DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK); | 79 | bitclr32(&INTMOD, DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK); |
80 | s3c_regclr32(&INTMSK, DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK); | 80 | bitclr32(&INTMSK, DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK); |
81 | } | 81 | } |
82 | 82 | ||
83 | void dma_retain(void) | 83 | void dma_retain(void) |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c index e9f55479c7..c1c9017fbb 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c | |||
@@ -50,14 +50,14 @@ void fiq_handler(void) __attribute__((interrupt ("FIQ"))); | |||
50 | void pcm_play_lock(void) | 50 | void pcm_play_lock(void) |
51 | { | 51 | { |
52 | if (++dma_play_lock.locked == 1) | 52 | if (++dma_play_lock.locked == 1) |
53 | s3c_regset32(&INTMSK, DMA2_MASK); | 53 | bitset32(&INTMSK, DMA2_MASK); |
54 | } | 54 | } |
55 | 55 | ||
56 | /* Unmask the DMA interrupt if enabled */ | 56 | /* Unmask the DMA interrupt if enabled */ |
57 | void pcm_play_unlock(void) | 57 | void pcm_play_unlock(void) |
58 | { | 58 | { |
59 | if (--dma_play_lock.locked == 0) | 59 | if (--dma_play_lock.locked == 0) |
60 | s3c_regclr32(&INTMSK, dma_play_lock.state); | 60 | bitclr32(&INTMSK, dma_play_lock.state); |
61 | } | 61 | } |
62 | 62 | ||
63 | void pcm_play_dma_init(void) | 63 | void pcm_play_dma_init(void) |
@@ -65,7 +65,7 @@ void pcm_play_dma_init(void) | |||
65 | /* There seem to be problems when changing the IIS interface configuration | 65 | /* There seem to be problems when changing the IIS interface configuration |
66 | * when a clock is not present. | 66 | * when a clock is not present. |
67 | */ | 67 | */ |
68 | s3c_regset32(&CLKCON, 1<<17); | 68 | bitset32(&CLKCON, 1<<17); |
69 | /* slave, transmit mode, 16 bit samples - MCLK 384fs - use 16.9344Mhz - | 69 | /* slave, transmit mode, 16 bit samples - MCLK 384fs - use 16.9344Mhz - |
70 | BCLK 32fs */ | 70 | BCLK 32fs */ |
71 | IISMOD = (1<<9) | (1<<8) | (2<<6) | (1<<3) | (1<<2) | (1<<0); | 71 | IISMOD = (1<<9) | (1<<8) | (2<<6) | (1<<3) | (1<<2) | (1<<0); |
@@ -73,7 +73,7 @@ void pcm_play_dma_init(void) | |||
73 | /* RX,TX off,on */ | 73 | /* RX,TX off,on */ |
74 | IISCON |= (1<<3) | (1<<2); | 74 | IISCON |= (1<<3) | (1<<2); |
75 | 75 | ||
76 | s3c_regclr32(&CLKCON, 1<<17); | 76 | bitclr32(&CLKCON, 1<<17); |
77 | 77 | ||
78 | audiohw_init(); | 78 | audiohw_init(); |
79 | 79 | ||
@@ -86,11 +86,11 @@ void pcm_play_dma_init(void) | |||
86 | /* Do not service DMA requests, yet */ | 86 | /* Do not service DMA requests, yet */ |
87 | 87 | ||
88 | /* clear any pending int and mask it */ | 88 | /* clear any pending int and mask it */ |
89 | s3c_regset32(&INTMSK, DMA2_MASK); | 89 | bitset32(&INTMSK, DMA2_MASK); |
90 | SRCPND = DMA2_MASK; | 90 | SRCPND = DMA2_MASK; |
91 | 91 | ||
92 | /* connect to FIQ */ | 92 | /* connect to FIQ */ |
93 | s3c_regset32(&INTMOD, DMA2_MASK); | 93 | bitset32(&INTMOD, DMA2_MASK); |
94 | } | 94 | } |
95 | 95 | ||
96 | void pcm_postinit(void) | 96 | void pcm_postinit(void) |
@@ -132,7 +132,7 @@ static void play_start_pcm(void) | |||
132 | static void play_stop_pcm(void) | 132 | static void play_stop_pcm(void) |
133 | { | 133 | { |
134 | /* Mask DMA interrupt */ | 134 | /* Mask DMA interrupt */ |
135 | s3c_regset32(&INTMSK, DMA2_MASK); | 135 | bitset32(&INTMSK, DMA2_MASK); |
136 | 136 | ||
137 | /* De-Activate the DMA channel */ | 137 | /* De-Activate the DMA channel */ |
138 | DMASKTRIG2 = 0x4; | 138 | DMASKTRIG2 = 0x4; |
@@ -160,7 +160,7 @@ static void play_stop_pcm(void) | |||
160 | void pcm_play_dma_start(const void *addr, size_t size) | 160 | void pcm_play_dma_start(const void *addr, size_t size) |
161 | { | 161 | { |
162 | /* Enable the IIS clock */ | 162 | /* Enable the IIS clock */ |
163 | s3c_regset32(&CLKCON, 1<<17); | 163 | bitset32(&CLKCON, 1<<17); |
164 | 164 | ||
165 | /* stop any DMA in progress - idle IIS */ | 165 | /* stop any DMA in progress - idle IIS */ |
166 | play_stop_pcm(); | 166 | play_stop_pcm(); |
@@ -191,7 +191,7 @@ void pcm_play_dma_stop(void) | |||
191 | play_stop_pcm(); | 191 | play_stop_pcm(); |
192 | 192 | ||
193 | /* Disconnect the IIS clock */ | 193 | /* Disconnect the IIS clock */ |
194 | s3c_regclr32(&CLKCON, 1<<17); | 194 | bitclr32(&CLKCON, 1<<17); |
195 | } | 195 | } |
196 | 196 | ||
197 | void pcm_play_dma_pause(bool pause) | 197 | void pcm_play_dma_pause(bool pause) |
diff --git a/firmware/target/arm/s3c2440/i2c-s3c2440.c b/firmware/target/arm/s3c2440/i2c-s3c2440.c index 4669186a4c..155eb2f956 100644 --- a/firmware/target/arm/s3c2440/i2c-s3c2440.c +++ b/firmware/target/arm/s3c2440/i2c-s3c2440.c | |||
@@ -43,7 +43,7 @@ void i2c_write(int addr, const unsigned char *buf, int count) | |||
43 | mutex_lock(&i2c_mtx); | 43 | mutex_lock(&i2c_mtx); |
44 | 44 | ||
45 | /* Turn on I2C clock */ | 45 | /* Turn on I2C clock */ |
46 | s3c_regset32(&CLKCON, 1 << 16); | 46 | bitset32(&CLKCON, 1 << 16); |
47 | 47 | ||
48 | /* Set mode to master transmitter and enable lines */ | 48 | /* Set mode to master transmitter and enable lines */ |
49 | IICSTAT = I2C_MODE_MASTER | I2C_MODE_TX | I2C_RXTX_ENB; | 49 | IICSTAT = I2C_MODE_MASTER | I2C_MODE_TX | I2C_RXTX_ENB; |
@@ -76,7 +76,7 @@ void i2c_write(int addr, const unsigned char *buf, int count) | |||
76 | IICSTAT = 0; | 76 | IICSTAT = 0; |
77 | 77 | ||
78 | /* Turn off I2C clock */ | 78 | /* Turn off I2C clock */ |
79 | s3c_regclr32(&CLKCON, 1 << 16); | 79 | bitclr32(&CLKCON, 1 << 16); |
80 | 80 | ||
81 | mutex_unlock(&i2c_mtx); | 81 | mutex_unlock(&i2c_mtx); |
82 | } | 82 | } |
@@ -92,11 +92,11 @@ void i2c_init(void) | |||
92 | INTPND = IIC_MASK; | 92 | INTPND = IIC_MASK; |
93 | 93 | ||
94 | /* Enable i2c interrupt in controller */ | 94 | /* Enable i2c interrupt in controller */ |
95 | s3c_regclr32(&INTMOD, IIC_MASK); | 95 | bitclr32(&INTMOD, IIC_MASK); |
96 | s3c_regclr32(&INTMSK, IIC_MASK); | 96 | bitclr32(&INTMSK, IIC_MASK); |
97 | 97 | ||
98 | /* Turn on I2C clock */ | 98 | /* Turn on I2C clock */ |
99 | s3c_regset32(&CLKCON, 1 << 16); | 99 | bitset32(&CLKCON, 1 << 16); |
100 | 100 | ||
101 | /* Set GPE15 (IICSDA) and GPE14 (IICSCL) to IIC */ | 101 | /* Set GPE15 (IICSDA) and GPE14 (IICSCL) to IIC */ |
102 | GPECON = (GPECON & ~((3 << 30) | (3 << 28))) | | 102 | GPECON = (GPECON & ~((3 << 30) | (3 << 28))) | |
@@ -110,7 +110,7 @@ void i2c_init(void) | |||
110 | IICLC = (0 << 0); | 110 | IICLC = (0 << 0); |
111 | 111 | ||
112 | /* Turn off I2C clock */ | 112 | /* Turn off I2C clock */ |
113 | s3c_regclr32(&CLKCON, 1 << 16); | 113 | bitclr32(&CLKCON, 1 << 16); |
114 | } | 114 | } |
115 | 115 | ||
116 | void IIC(void) | 116 | void IIC(void) |
diff --git a/firmware/target/arm/s3c2440/kernel-s3c2440.c b/firmware/target/arm/s3c2440/kernel-s3c2440.c index 6cabc8dc81..892758e147 100644 --- a/firmware/target/arm/s3c2440/kernel-s3c2440.c +++ b/firmware/target/arm/s3c2440/kernel-s3c2440.c | |||
@@ -62,7 +62,7 @@ void tick_start(unsigned int interval_in_ms) | |||
62 | #ifdef BOOTLOADER | 62 | #ifdef BOOTLOADER |
63 | void tick_stop(void) | 63 | void tick_stop(void) |
64 | { | 64 | { |
65 | s3c_regset32(&INTMSK, TIMER4_MASK); | 65 | bitset32(&INTMSK, TIMER4_MASK); |
66 | TCON &= ~(1 << 20); | 66 | TCON &= ~(1 << 20); |
67 | SRCPND = TIMER4_MASK; | 67 | SRCPND = TIMER4_MASK; |
68 | INTPND = TIMER4_MASK; | 68 | INTPND = TIMER4_MASK; |
diff --git a/firmware/target/arm/s3c2440/lcd-s3c2440.c b/firmware/target/arm/s3c2440/lcd-s3c2440.c index b9f7d3ef3d..77be29f556 100644 --- a/firmware/target/arm/s3c2440/lcd-s3c2440.c +++ b/firmware/target/arm/s3c2440/lcd-s3c2440.c | |||
@@ -101,7 +101,7 @@ static void LCD_CTRL_clock(bool onoff) | |||
101 | GPDCON |= 0xAAA0AAA0; | 101 | GPDCON |= 0xAAA0AAA0; |
102 | GPDUP |= 0xFCFC; | 102 | GPDUP |= 0xFCFC; |
103 | 103 | ||
104 | s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */ | 104 | bitset32(&CLKCON, 0x20); /* enable LCD clock */ |
105 | LCDCON1 |= LCD_ENVID; | 105 | LCDCON1 |= LCD_ENVID; |
106 | } | 106 | } |
107 | else | 107 | else |
@@ -113,7 +113,7 @@ static void LCD_CTRL_clock(bool onoff) | |||
113 | GPDUP &= ~0xFCFC; | 113 | GPDUP &= ~0xFCFC; |
114 | 114 | ||
115 | LCDCON1 &= ~LCD_ENVID; /* Must disable first or bus may freeze */ | 115 | LCDCON1 &= ~LCD_ENVID; /* Must disable first or bus may freeze */ |
116 | s3c_regclr32(&CLKCON, 0x20); /* disable LCD clock */ | 116 | bitclr32(&CLKCON, 0x20); /* disable LCD clock */ |
117 | } | 117 | } |
118 | } | 118 | } |
119 | 119 | ||
@@ -165,7 +165,7 @@ static void LCD_SPI_SS(bool select) | |||
165 | 165 | ||
166 | static void LCD_SPI_start(void) | 166 | static void LCD_SPI_start(void) |
167 | { | 167 | { |
168 | s3c_regset32(&CLKCON, 0x40000); /* enable SPI clock */ | 168 | bitset32(&CLKCON, 0x40000); /* enable SPI clock */ |
169 | LCD_SPI_SS(false); | 169 | LCD_SPI_SS(false); |
170 | SPCON0=0x3E; | 170 | SPCON0=0x3E; |
171 | SPPRE0=24; | 171 | SPPRE0=24; |
@@ -179,7 +179,7 @@ static void LCD_SPI_stop(void) | |||
179 | LCD_SPI_SS(false); | 179 | LCD_SPI_SS(false); |
180 | 180 | ||
181 | SPCON0 &= ~0x10; | 181 | SPCON0 &= ~0x10; |
182 | s3c_regclr32(&CLKCON, 0x40000); /* disable SPI clock */ | 182 | bitclr32(&CLKCON, 0x40000); /* disable SPI clock */ |
183 | } | 183 | } |
184 | 184 | ||
185 | static void LCD_SPI_init(void) | 185 | static void LCD_SPI_init(void) |
@@ -253,7 +253,7 @@ void lcd_init_device(void) | |||
253 | GPBUP |= 0x181; | 253 | GPBUP |= 0x181; |
254 | #endif | 254 | #endif |
255 | 255 | ||
256 | s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */ | 256 | bitset32(&CLKCON, 0x20); /* enable LCD clock */ |
257 | 257 | ||
258 | LCD_CTRL_setup(); | 258 | LCD_CTRL_setup(); |
259 | #ifdef GIGABEAT_F | 259 | #ifdef GIGABEAT_F |
diff --git a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c index 30db29c42c..8a6b62f31f 100644 --- a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c +++ b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c | |||
@@ -62,14 +62,14 @@ void fiq_handler(void) __attribute__((interrupt ("FIQ"))); | |||
62 | void pcm_play_lock(void) | 62 | void pcm_play_lock(void) |
63 | { | 63 | { |
64 | if (++dma_play_lock.locked == 1) | 64 | if (++dma_play_lock.locked == 1) |
65 | s3c_regset32(&INTMSK, DMA2_MASK); | 65 | bitset32(&INTMSK, DMA2_MASK); |
66 | } | 66 | } |
67 | 67 | ||
68 | /* Unmask the DMA interrupt if enabled */ | 68 | /* Unmask the DMA interrupt if enabled */ |
69 | void pcm_play_unlock(void) | 69 | void pcm_play_unlock(void) |
70 | { | 70 | { |
71 | if (--dma_play_lock.locked == 0) | 71 | if (--dma_play_lock.locked == 0) |
72 | s3c_regclr32(&INTMSK, dma_play_lock.state); | 72 | bitclr32(&INTMSK, dma_play_lock.state); |
73 | } | 73 | } |
74 | 74 | ||
75 | void pcm_play_dma_init(void) | 75 | void pcm_play_dma_init(void) |
@@ -77,7 +77,7 @@ void pcm_play_dma_init(void) | |||
77 | /* There seem to be problems when changing the IIS interface configuration | 77 | /* There seem to be problems when changing the IIS interface configuration |
78 | * when a clock is not present. | 78 | * when a clock is not present. |
79 | */ | 79 | */ |
80 | s3c_regset32(&CLKCON, 1<<17); | 80 | bitset32(&CLKCON, 1<<17); |
81 | 81 | ||
82 | #ifdef HAVE_UDA1341 | 82 | #ifdef HAVE_UDA1341 |
83 | /* master, transmit mode, 16 bit samples, BCLK 32fs, PCLK */ | 83 | /* master, transmit mode, 16 bit samples, BCLK 32fs, PCLK */ |
@@ -95,7 +95,7 @@ void pcm_play_dma_init(void) | |||
95 | IISCON |= (1<<3) | (1<<2); | 95 | IISCON |= (1<<3) | (1<<2); |
96 | #endif | 96 | #endif |
97 | 97 | ||
98 | s3c_regclr32(&CLKCON, 1<<17); | 98 | bitclr32(&CLKCON, 1<<17); |
99 | 99 | ||
100 | audiohw_init(); | 100 | audiohw_init(); |
101 | 101 | ||
@@ -112,11 +112,11 @@ void pcm_play_dma_init(void) | |||
112 | /* Do not service DMA requests, yet */ | 112 | /* Do not service DMA requests, yet */ |
113 | 113 | ||
114 | /* clear any pending int and mask it */ | 114 | /* clear any pending int and mask it */ |
115 | s3c_regset32(&INTMSK, DMA2_MASK); | 115 | bitset32(&INTMSK, DMA2_MASK); |
116 | SRCPND = DMA2_MASK; | 116 | SRCPND = DMA2_MASK; |
117 | 117 | ||
118 | /* connect to FIQ */ | 118 | /* connect to FIQ */ |
119 | s3c_regset32(&INTMOD, DMA2_MASK); | 119 | bitset32(&INTMOD, DMA2_MASK); |
120 | } | 120 | } |
121 | 121 | ||
122 | void pcm_postinit(void) | 122 | void pcm_postinit(void) |
@@ -172,7 +172,7 @@ static void play_start_pcm(void) | |||
172 | static void play_stop_pcm(void) | 172 | static void play_stop_pcm(void) |
173 | { | 173 | { |
174 | /* Mask DMA interrupt */ | 174 | /* Mask DMA interrupt */ |
175 | s3c_regset32(&INTMSK, DMA2_MASK); | 175 | bitset32(&INTMSK, DMA2_MASK); |
176 | 176 | ||
177 | /* De-Activate the DMA channel */ | 177 | /* De-Activate the DMA channel */ |
178 | DMASKTRIG2 = 0x4; | 178 | DMASKTRIG2 = 0x4; |
@@ -200,7 +200,7 @@ static void play_stop_pcm(void) | |||
200 | void pcm_play_dma_start(const void *addr, size_t size) | 200 | void pcm_play_dma_start(const void *addr, size_t size) |
201 | { | 201 | { |
202 | /* Enable the IIS clock */ | 202 | /* Enable the IIS clock */ |
203 | s3c_regset32(&CLKCON, 1<<17); | 203 | bitset32(&CLKCON, 1<<17); |
204 | 204 | ||
205 | /* stop any DMA in progress - idle IIS */ | 205 | /* stop any DMA in progress - idle IIS */ |
206 | play_stop_pcm(); | 206 | play_stop_pcm(); |
@@ -231,7 +231,7 @@ void pcm_play_dma_stop(void) | |||
231 | play_stop_pcm(); | 231 | play_stop_pcm(); |
232 | 232 | ||
233 | /* Disconnect the IIS clock */ | 233 | /* Disconnect the IIS clock */ |
234 | s3c_regclr32(&CLKCON, 1<<17); | 234 | bitclr32(&CLKCON, 1<<17); |
235 | } | 235 | } |
236 | 236 | ||
237 | void pcm_play_dma_pause(bool pause) | 237 | void pcm_play_dma_pause(bool pause) |
diff --git a/firmware/target/arm/s3c2440/sd-s3c2440.c b/firmware/target/arm/s3c2440/sd-s3c2440.c index f4c8a4f599..d42405db65 100644 --- a/firmware/target/arm/s3c2440/sd-s3c2440.c +++ b/firmware/target/arm/s3c2440/sd-s3c2440.c | |||
@@ -299,8 +299,8 @@ static void init_sdi_controller(const int card_no) | |||
299 | 299 | ||
300 | #if 1 | 300 | #if 1 |
301 | /* Enable interrupt in controller */ | 301 | /* Enable interrupt in controller */ |
302 | s3c_regclr32(&INTMOD, SDI_MASK); | 302 | bitclr32(&INTMOD, SDI_MASK); |
303 | s3c_regclr32(&INTMSK, SDI_MASK); | 303 | bitclr32(&INTMSK, SDI_MASK); |
304 | 304 | ||
305 | SDIIMSK |= S3C2410_SDIIMSK_DATAFINISH | 305 | SDIIMSK |= S3C2410_SDIIMSK_DATAFINISH |
306 | | S3C2410_SDIIMSK_DATATIMEOUT | 306 | | S3C2410_SDIIMSK_DATATIMEOUT |
diff --git a/firmware/target/arm/s3c2440/system-s3c2440.c b/firmware/target/arm/s3c2440/system-s3c2440.c index cb273ad4df..577b46966c 100644 --- a/firmware/target/arm/s3c2440/system-s3c2440.c +++ b/firmware/target/arm/s3c2440/system-s3c2440.c | |||
@@ -136,24 +136,6 @@ void memory_init(void) | |||
136 | enable_mmu(); | 136 | enable_mmu(); |
137 | } | 137 | } |
138 | 138 | ||
139 | void s3c_regmod32(volatile unsigned long *reg, unsigned long bits, | ||
140 | unsigned long mask) | ||
141 | { | ||
142 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); | ||
143 | *reg = (*reg & ~mask) | (bits & mask); | ||
144 | restore_interrupt(oldstatus); | ||
145 | } | ||
146 | |||
147 | void s3c_regset32(volatile unsigned long *reg, unsigned long bits) | ||
148 | { | ||
149 | s3c_regmod32(reg, bits, bits); | ||
150 | } | ||
151 | |||
152 | void s3c_regclr32(volatile unsigned long *reg, unsigned long bits) | ||
153 | { | ||
154 | s3c_regmod32(reg, 0, bits); | ||
155 | } | ||
156 | |||
157 | #ifdef BOOTLOADER | 139 | #ifdef BOOTLOADER |
158 | void system_prepare_fw_start(void) | 140 | void system_prepare_fw_start(void) |
159 | { | 141 | { |
diff --git a/firmware/target/arm/s3c2440/system-target.h b/firmware/target/arm/s3c2440/system-target.h index ad32f89552..c48a62cf47 100644 --- a/firmware/target/arm/s3c2440/system-target.h +++ b/firmware/target/arm/s3c2440/system-target.h | |||
@@ -69,14 +69,4 @@ | |||
69 | void system_prepare_fw_start(void); | 69 | void system_prepare_fw_start(void); |
70 | void tick_stop(void); | 70 | void tick_stop(void); |
71 | 71 | ||
72 | /* Functions to set and clear register bits atomically */ | ||
73 | |||
74 | /* Set and clear register bits */ | ||
75 | void s3c_regmod32(volatile unsigned long *reg, unsigned long bits, | ||
76 | unsigned long mask); | ||
77 | /* Set register bits */ | ||
78 | void s3c_regset32(volatile unsigned long *reg, unsigned long bits); | ||
79 | /* Clear register bits */ | ||
80 | void s3c_regclr32(volatile unsigned long *reg, unsigned long bits); | ||
81 | |||
82 | #endif /* SYSTEM_TARGET_H */ | 72 | #endif /* SYSTEM_TARGET_H */ |