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Diffstat (limited to 'firmware/target/arm/mmu-arm.c')
-rw-r--r--firmware/target/arm/mmu-arm.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/firmware/target/arm/mmu-arm.c b/firmware/target/arm/mmu-arm.c
index d86cd430b5..fae7fd0b8f 100644
--- a/firmware/target/arm/mmu-arm.c
+++ b/firmware/target/arm/mmu-arm.c
@@ -265,6 +265,8 @@ void __attribute__((naked)) clean_dcache(void)
265 /* Clean entire data cache */ 265 /* Clean entire data cache */
266 "mov r0, #0 \n" 266 "mov r0, #0 \n"
267 "mcr p15, 0, r0, c7, c10, 0 \n" 267 "mcr p15, 0, r0, c7, c10, 0 \n"
268 /* Data synchronization barrier */
269 "mcr p15, 0, r0, c7, c10, 4 \n"
268 "bx lr \n" 270 "bx lr \n"
269 ); 271 );
270} 272}
@@ -290,3 +292,31 @@ void clean_dcache(void)
290} 292}
291#endif 293#endif
292 294
295#if CONFIG_CPU == IMX31L
296void invalidate_idcache(void)
297{
298 asm volatile(
299 /* Clean and invalidate entire data cache */
300 "mcr p15, 0, %0, c7, c14, 0 \n"
301 /* Invalidate entire instruction cache
302 * Also flushes the branch target cache */
303 "mcr p15, 0, %0, c7, c5, 0 \n"
304 /* Data synchronization barrier */
305 "mcr p15, 0, %0, c7, c10, 4 \n"
306 /* Flush prefetch buffer */
307 "mcr p15, 0, %0, c7, c5, 4 \n"
308 : : "r"(0)
309 );
310}
311#else
312void invalidate_idcache(void)
313{
314 clean_dcache();
315 asm volatile(
316 "mov r0, #0 \n"
317 "mcr p15, 0, r0, c7, c5, 0 \n"
318 : : : "r0"
319 );
320}
321#endif
322