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author | Michael Sevakis <jethead71@rockbox.org> | 2009-02-11 12:55:51 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2009-02-11 12:55:51 +0000 |
commit | 21f0c9a2829415f52b64cbdf965b01525e78f17a (patch) | |
tree | b5cb8021097722969f75784011c9f64f991c0c3d /firmware/target/arm/mmu-arm.c | |
parent | 4cd7597172d916db9fc99bde4c03b669366f852a (diff) | |
download | rockbox-21f0c9a2829415f52b64cbdf965b01525e78f17a.tar.gz rockbox-21f0c9a2829415f52b64cbdf965b01525e78f17a.zip |
Make basic cache functions into calls, and get rid of CACHE_FUNCTION_WRAPPERS and CACHE_FUNCTIONS_AS_CALL macros. Rename flush/invalidate_icache to cpucache_flush/invalidate. They're inlined only if an implementation isn't provided by defining HAVE_CPUCACHE_FLUSH/INVALIDATE.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19971 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/mmu-arm.c')
-rw-r--r-- | firmware/target/arm/mmu-arm.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/firmware/target/arm/mmu-arm.c b/firmware/target/arm/mmu-arm.c index d86cd430b5..fae7fd0b8f 100644 --- a/firmware/target/arm/mmu-arm.c +++ b/firmware/target/arm/mmu-arm.c | |||
@@ -265,6 +265,8 @@ void __attribute__((naked)) clean_dcache(void) | |||
265 | /* Clean entire data cache */ | 265 | /* Clean entire data cache */ |
266 | "mov r0, #0 \n" | 266 | "mov r0, #0 \n" |
267 | "mcr p15, 0, r0, c7, c10, 0 \n" | 267 | "mcr p15, 0, r0, c7, c10, 0 \n" |
268 | /* Data synchronization barrier */ | ||
269 | "mcr p15, 0, r0, c7, c10, 4 \n" | ||
268 | "bx lr \n" | 270 | "bx lr \n" |
269 | ); | 271 | ); |
270 | } | 272 | } |
@@ -290,3 +292,31 @@ void clean_dcache(void) | |||
290 | } | 292 | } |
291 | #endif | 293 | #endif |
292 | 294 | ||
295 | #if CONFIG_CPU == IMX31L | ||
296 | void invalidate_idcache(void) | ||
297 | { | ||
298 | asm volatile( | ||
299 | /* Clean and invalidate entire data cache */ | ||
300 | "mcr p15, 0, %0, c7, c14, 0 \n" | ||
301 | /* Invalidate entire instruction cache | ||
302 | * Also flushes the branch target cache */ | ||
303 | "mcr p15, 0, %0, c7, c5, 0 \n" | ||
304 | /* Data synchronization barrier */ | ||
305 | "mcr p15, 0, %0, c7, c10, 4 \n" | ||
306 | /* Flush prefetch buffer */ | ||
307 | "mcr p15, 0, %0, c7, c5, 4 \n" | ||
308 | : : "r"(0) | ||
309 | ); | ||
310 | } | ||
311 | #else | ||
312 | void invalidate_idcache(void) | ||
313 | { | ||
314 | clean_dcache(); | ||
315 | asm volatile( | ||
316 | "mov r0, #0 \n" | ||
317 | "mcr p15, 0, r0, c7, c5, 0 \n" | ||
318 | : : : "r0" | ||
319 | ); | ||
320 | } | ||
321 | #endif | ||
322 | |||