6 files changed, 45 insertions, 52 deletions

diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h
index ae50ec4c78..921af0ec8b 100644
--- a/firmware/target/arm/imx31/gigabeat-s/system-target.h
+++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h
@@ -57,34 +57,12 @@ void imx31_regclr32(volatile uint32_t *reg_p, uint32_t mask);
 
 #define KDEV_INIT
 
-#define HAVE_INVALIDATE_ICACHE
-static inline void invalidate_icache(void)
-{
-    asm volatile(
-        /* Clean and invalidate entire data cache */
-        "mcr p15, 0, %0, c7, c14, 0 \n"
-        /* Invalidate entire instruction cache
-         * Also flushes the branch target cache */
-        "mcr p15, 0, %0, c7, c5, 0  \n"
-        /* Data synchronization barrier */
-        "mcr p15, 0, %0, c7, c10, 4 \n"
-        /* Flush prefetch buffer */
-        "mcr p15, 0, %0, c7, c5, 4  \n"
-        : : "r"(0)
-    );
-}
+#define HAVE_CPUCACHE_INVALIDATE
+#define HAVE_CPUCACHE_FLUSH
 
-#define HAVE_FLUSH_ICACHE
-static inline void flush_icache(void)
-{
-    asm volatile (
-        /* Clean entire data cache */
-        "mcr p15, 0, %0, c7, c10, 0 \n"
-        /* Data synchronization barrier */
-        "mcr p15, 0, %0, c7, c10, 4 \n"
-        : : "r"(0)
-    );
-}
+/* Different internal names */
+#define cpucache_flush      clean_dcache
+#define cpucache_invalidate invalidate_idcache
 
 struct ARM_REGS {
         int r0;
diff --git a/firmware/target/arm/mmu-arm.c b/firmware/target/arm/mmu-arm.c
index d86cd430b5..fae7fd0b8f 100644
--- a/firmware/target/arm/mmu-arm.c
+++ b/firmware/target/arm/mmu-arm.c
@@ -265,6 +265,8 @@ void __attribute__((naked)) clean_dcache(void)
         /* Clean entire data cache */
         "mov    r0, #0                 \n"
         "mcr    p15, 0, r0, c7, c10, 0 \n"
+        /* Data synchronization barrier */
+        "mcr    p15, 0, r0, c7, c10, 4 \n"
         "bx     lr                     \n"
     );
 }
@@ -290,3 +292,31 @@ void clean_dcache(void)
 }
 #endif
 
+#if CONFIG_CPU == IMX31L
+void invalidate_idcache(void)
+{
+    asm volatile(
+        /* Clean and invalidate entire data cache */
+        "mcr p15, 0, %0, c7, c14, 0 \n"
+        /* Invalidate entire instruction cache
+         * Also flushes the branch target cache */
+        "mcr p15, 0, %0, c7, c5, 0  \n"
+        /* Data synchronization barrier */
+        "mcr p15, 0, %0, c7, c10, 4 \n"
+        /* Flush prefetch buffer */
+        "mcr p15, 0, %0, c7, c5, 4  \n"
+        : : "r"(0)
+    );
+}
+#else
+void invalidate_idcache(void)
+{
+    clean_dcache();
+    asm volatile(
+        "mov r0, #0 \n"
+        "mcr p15, 0, r0, c7, c5, 0 \n"
+        : : : "r0"
+    );
+}
+#endif
+
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h
index 320c595b99..aa7c0aa50c 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h
@@ -41,15 +41,9 @@ void s3c_regset32(volatile unsigned long *reg, unsigned long bits);
 /* Clear register bits */
 void s3c_regclr32(volatile unsigned long *reg, unsigned long bits);
 
-#define HAVE_INVALIDATE_ICACHE
-static inline void invalidate_icache(void)
-{
-    clean_dcache();
-    asm volatile(
-        "mov r0, #0 \n"
-        "mcr p15, 0, r0, c7, c5, 0 \n"
-        : : : "r0"
-    );
-}
+#define HAVE_CPUCACHE_FLUSH
+#define HAVE_CPUCACHE_INVALIDATE
+#define cpucache_flush      clean_dcache
+#define cpucache_invalidate invalidate_idcache
 
 #endif /* SYSTEM_TARGET_H */
diff --git a/firmware/target/arm/system-pp5002.c b/firmware/target/arm/system-pp5002.c
index a995a5464b..98bf5f21f1 100644
--- a/firmware/target/arm/system-pp5002.c
+++ b/firmware/target/arm/system-pp5002.c
@@ -62,8 +62,7 @@ void __attribute__((interrupt("IRQ"))) irq_handler(void)
    some other CPU frequency scaling. */
 
 #ifndef BOOTLOADER
-void flush_icache(void) ICODE_ATTR;
-void flush_icache(void)
+void ICODE_ATTR cpucache_flush(void)
 {
     intptr_t b, e;
 
@@ -73,8 +72,7 @@ void flush_icache(void)
     }
 }
 
-void invalidate_icache(void) ICODE_ATTR;
-void invalidate_icache(void)
+void ICODE_ATTR cpucache_invalidate(void)
 {
     intptr_t b, e;
 
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c
index b1cef7152a..10a7651f7b 100644
--- a/firmware/target/arm/system-pp502x.c
+++ b/firmware/target/arm/system-pp502x.c
@@ -163,8 +163,7 @@ void __attribute__((interrupt("IRQ"))) irq_handler(void)
    to extend the funtions to do alternate cache configurations. */
 
 #ifndef BOOTLOADER
-void flush_icache(void) ICODE_ATTR;
-void flush_icache(void)
+void ICODE_ATTR cpucache_flush(void)
 {
     if (CACHE_CTL & CACHE_CTL_ENABLE)
     {
@@ -173,8 +172,7 @@ void flush_icache(void)
     }
 }
 
-void invalidate_icache(void) ICODE_ATTR;
-void invalidate_icache(void)
+void ICODE_ATTR cpucache_invalidate(void)
 {
     if (CACHE_CTL & CACHE_CTL_ENABLE)
     {
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h
index 4719b8c971..60844e0b5f 100644
--- a/firmware/target/arm/system-target.h
+++ b/firmware/target/arm/system-target.h
@@ -168,13 +168,8 @@ static inline void wake_core(int core)
 
 /** cache functions **/
 #ifndef BOOTLOADER
-#define CACHE_FUNCTIONS_AS_CALL
-
-#define HAVE_INVALIDATE_ICACHE
-void invalidate_icache(void);
-
-#define HAVE_FLUSH_ICACHE
-void flush_icache(void);
+#define HAVE_CPUCACHE_INVALIDATE
+#define HAVE_CPUCACHE_FLUSH
 #endif
 
 #endif /* CPU_PP */