diff options
-rw-r--r-- | firmware/export/system.h | 12 | ||||
-rw-r--r-- | firmware/target/arm/mmu-arm.S | 107 | ||||
-rw-r--r-- | firmware/target/arm/mmu-arm.h | 52 | ||||
-rw-r--r-- | firmware/target/arm/mmu-armv6.S | 102 | ||||
-rw-r--r-- | firmware/target/arm/system-pp5002.c | 12 | ||||
-rw-r--r-- | firmware/target/arm/system-target.h | 3 | ||||
-rw-r--r-- | firmware/target/coldfire/system-coldfire.c | 4 | ||||
-rw-r--r-- | firmware/target/coldfire/system-target.h | 2 |
8 files changed, 191 insertions, 103 deletions
diff --git a/firmware/export/system.h b/firmware/export/system.h index ce6277ac7a..ed10c84a58 100644 --- a/firmware/export/system.h +++ b/firmware/export/system.h | |||
@@ -282,16 +282,28 @@ static inline uint32_t swap_odd_even32(uint32_t value) | |||
282 | 282 | ||
283 | /* Just define these as empty if not declared */ | 283 | /* Just define these as empty if not declared */ |
284 | #ifdef HAVE_CPUCACHE_INVALIDATE | 284 | #ifdef HAVE_CPUCACHE_INVALIDATE |
285 | void cpucache_commit_discard(void); | ||
286 | /* deprecated alias */ | ||
285 | void cpucache_invalidate(void); | 287 | void cpucache_invalidate(void); |
286 | #else | 288 | #else |
289 | static inline void cpucache_commit_discard(void) | ||
290 | { | ||
291 | } | ||
292 | /* deprecated alias */ | ||
287 | static inline void cpucache_invalidate(void) | 293 | static inline void cpucache_invalidate(void) |
288 | { | 294 | { |
289 | } | 295 | } |
290 | #endif | 296 | #endif |
291 | 297 | ||
292 | #ifdef HAVE_CPUCACHE_FLUSH | 298 | #ifdef HAVE_CPUCACHE_FLUSH |
299 | void cpucache_commit(void); | ||
300 | /* deprecated alias */ | ||
293 | void cpucache_flush(void); | 301 | void cpucache_flush(void); |
294 | #else | 302 | #else |
303 | static inline void cpucache_commit(void) | ||
304 | { | ||
305 | } | ||
306 | /* deprecated alias */ | ||
295 | static inline void cpucache_flush(void) | 307 | static inline void cpucache_flush(void) |
296 | { | 308 | { |
297 | } | 309 | } |
diff --git a/firmware/target/arm/mmu-arm.S b/firmware/target/arm/mmu-arm.S index 02f1454399..5693ca587b 100644 --- a/firmware/target/arm/mmu-arm.S +++ b/firmware/target/arm/mmu-arm.S | |||
@@ -171,15 +171,18 @@ enable_mmu: | |||
171 | /** Cache coherency **/ | 171 | /** Cache coherency **/ |
172 | 172 | ||
173 | /* | 173 | /* |
174 | * Invalidate DCache for this range | 174 | * Write DCache back to RAM for the given range and remove cache lines |
175 | * will do write back | 175 | * from DCache afterwards |
176 | * void invalidate_dcache_range(const void *base, unsigned int size); | 176 | * void commit_discard_dcache_range(const void *base, unsigned int size); |
177 | */ | 177 | */ |
178 | .section .text, "ax", %progbits | 178 | .section .text, "ax", %progbits |
179 | .align 2 | 179 | .align 2 |
180 | .global invalidate_dcache_range | 180 | .global commit_discard_dcache_range |
181 | .type invalidate_dcache_range, %function | 181 | .type commit_discard_dcache_range, %function |
182 | .global invalidate_dcache_range @ Alias, deprecated | ||
183 | |||
182 | @ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ | 184 | @ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ |
185 | commit_discard_dcache_range: | ||
183 | invalidate_dcache_range: | 186 | invalidate_dcache_range: |
184 | add r1, r0, r1 @ size -> end | 187 | add r1, r0, r1 @ size -> end |
185 | cmp r1, r0 @ end <= start? | 188 | cmp r1, r0 @ end <= start? |
@@ -214,18 +217,20 @@ invalidate_dcache_range: | |||
214 | mov r0, #0 @ | 217 | mov r0, #0 @ |
215 | mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer | 218 | mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer |
216 | bx lr @ | 219 | bx lr @ |
217 | .size invalidate_dcache_range, .-invalidate_dcache_range | 220 | .size commit_discard_dcache_range, .-commit_discard_dcache_range |
218 | 221 | ||
219 | /* | 222 | /* |
220 | * clean DCache for this range | 223 | * Write DCache back to RAM for the given range |
221 | * forces DCache writeback for the specified range | 224 | * void commit_dcache_range(const void *base, unsigned int size); |
222 | * void clean_dcache_range(const void *base, unsigned int size); | ||
223 | */ | 225 | */ |
224 | .section .text, "ax", %progbits | 226 | .section .text, "ax", %progbits |
225 | .align 2 | 227 | .align 2 |
226 | .global clean_dcache_range | 228 | .global commit_dcache_range |
227 | .type clean_dcache_range, %function | 229 | .type commit_dcache_range, %function |
230 | .global clean_dcache_range @ Alias, deprecated | ||
231 | |||
228 | @ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ | 232 | @ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ |
233 | commit_dcache_range: | ||
229 | clean_dcache_range: | 234 | clean_dcache_range: |
230 | add r1, r0, r1 @ size -> end | 235 | add r1, r0, r1 @ size -> end |
231 | cmp r1, r0 @ end <= start? | 236 | cmp r1, r0 @ end <= start? |
@@ -260,19 +265,22 @@ clean_dcache_range: | |||
260 | mov r0, #0 @ | 265 | mov r0, #0 @ |
261 | mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer | 266 | mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer |
262 | bx lr @ | 267 | bx lr @ |
263 | .size clean_dcache_range, .-clean_dcache_range | 268 | .size commit_dcache_range, .-commit_dcache_range |
264 | 269 | ||
265 | /* | 270 | /* |
266 | * Dump DCache for this range | 271 | * Remove cache lines for the given range from DCache |
267 | * will *NOT* do write back except for buffer edges not on a line boundary | 272 | * will *NOT* do write back except for buffer edges not on a line boundary |
268 | * void dump_dcache_range(const void *base, unsigned int size); | 273 | * void discard_dcache_range(const void *base, unsigned int size); |
269 | */ | 274 | */ |
270 | .section .text, "ax", %progbits | 275 | .section .text, "ax", %progbits |
271 | .align 2 | 276 | .align 2 |
272 | .global dump_dcache_range | 277 | .global discard_dcache_range |
273 | .type dump_dcache_range, %function | 278 | .type discard_dcache_range, %function |
279 | .global dump_dcache_range @ Alias, deprecated | ||
280 | |||
274 | @ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ | 281 | @ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ |
275 | dump_dcache_range: | 282 | discard_dcache_range: |
283 | dump_dcache_range: | ||
276 | add r1, r0, r1 @ size -> end | 284 | add r1, r0, r1 @ size -> end |
277 | cmp r1, r0 @ end <= start? | 285 | cmp r1, r0 @ end <= start? |
278 | bxls lr @ | 286 | bxls lr @ |
@@ -287,7 +295,7 @@ clean_dcache_range: | |||
287 | mcrne p15, 0, r1, c7, c14, 1 @ Clean and invalidate line by MVA | 295 | mcrne p15, 0, r1, c7, c14, 1 @ Clean and invalidate line by MVA |
288 | @ if not cache aligned | 296 | @ if not cache aligned |
289 | cmp r1, r0 @ end <= start now? | 297 | cmp r1, r0 @ end <= start now? |
290 | 1: @ dump_start @ | 298 | 1: @ discard_start @ |
291 | mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA | 299 | mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA |
292 | addhi r0, r0, #32 @ | 300 | addhi r0, r0, #32 @ |
293 | cmphi r1, r0 @ | 301 | cmphi r1, r0 @ |
@@ -312,30 +320,35 @@ clean_dcache_range: | |||
312 | mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA | 320 | mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA |
313 | addhi r0, r0, #32 @ | 321 | addhi r0, r0, #32 @ |
314 | cmphi r1, r0 @ | 322 | cmphi r1, r0 @ |
315 | bhi 1b @ dump_start @ | 323 | bhi 1b @ discard_start @ |
316 | mov r0, #0 @ | 324 | mov r0, #0 @ |
317 | mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer | 325 | mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer |
318 | bx lr @ | 326 | bx lr @ |
319 | .size dump_dcache_range, .-dump_dcache_range | 327 | .size discard_dcache_range, .-discard_dcache_range |
320 | 328 | ||
321 | /* | 329 | /* |
322 | * Cleans entire DCache | 330 | * Write entire DCache back to RAM |
323 | * void clean_dcache(void); | 331 | * void commit_dcache(void); |
324 | */ | 332 | */ |
325 | .section .text, "ax", %progbits | 333 | .section .text, "ax", %progbits |
326 | .align 2 | 334 | .align 2 |
327 | .global clean_dcache | 335 | .global commit_dcache |
328 | .type clean_dcache, %function | 336 | .type commit_dcache, %function |
329 | .global cpucache_flush @ Alias | 337 | .global cpucache_commit @ Alias |
338 | .global clean_dcache @ Alias, deprecated | ||
339 | .global cpucache_flush @ Alias, deprecated | ||
340 | |||
341 | commit_dcache: | ||
342 | cpucache_commit: | ||
330 | clean_dcache: | 343 | clean_dcache: |
331 | cpucache_flush: | 344 | cpucache_flush: |
332 | #ifdef HAVE_TEST_AND_CLEAN_CACHE | 345 | #ifdef HAVE_TEST_AND_CLEAN_CACHE |
333 | mrc p15, 0, r15, c7, c10, 3 @ test and clean dcache | 346 | mrc p15, 0, r15, c7, c10, 3 @ test and clean dcache |
334 | bne clean_dcache | 347 | bne commit_dcache |
335 | mov r1, #0 | 348 | mov r1, #0 |
336 | #else | 349 | #else |
337 | mov r1, #0x00000000 @ | 350 | mov r1, #0x00000000 @ |
338 | 1: @ clean_start @ | 351 | 1: @ commit_start @ |
339 | mcr p15, 0, r1, c7, c10, 2 @ Clean entry by index | 352 | mcr p15, 0, r1, c7, c10, 2 @ Clean entry by index |
340 | add r0, r1, #(1<<CACHEALIGN_BITS) | 353 | add r0, r1, #(1<<CACHEALIGN_BITS) |
341 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index | 354 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index |
@@ -344,25 +357,27 @@ cpucache_flush: | |||
344 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index | 357 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index |
345 | .endr | 358 | .endr |
346 | adds r1, r1, #0x04000000 @ will wrap to zero at loop end | 359 | adds r1, r1, #0x04000000 @ will wrap to zero at loop end |
347 | bne 1b @ clean_start @ | 360 | bne 1b @ commit_start @ |
348 | #endif /* HAVE_TEST_AND_CLEAN_CACHE */ | 361 | #endif /* HAVE_TEST_AND_CLEAN_CACHE */ |
349 | mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer | 362 | mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer |
350 | bx lr @ | 363 | bx lr @ |
351 | .size clean_dcache, .-clean_dcache | 364 | .size commit_dcache, .-commit_dcache |
352 | 365 | ||
353 | /* | 366 | /* |
354 | * Invalidate entire DCache | 367 | * Commit and discard entire DCache, will do writeback |
355 | * will do writeback | 368 | * void commit_discard_dcache(void); |
356 | * void invalidate_dcache(void); | ||
357 | */ | 369 | */ |
358 | .section .icode, "ax", %progbits | 370 | .section .icode, "ax", %progbits |
359 | .align 2 | 371 | .align 2 |
360 | .global invalidate_dcache | 372 | .global commit_discard_dcache |
361 | .type invalidate_dcache, %function | 373 | .type commit_discard_dcache, %function |
374 | .global invalidate_dcache @ Alias, deprecated | ||
375 | |||
376 | commit_discard_dcache: | ||
362 | invalidate_dcache: | 377 | invalidate_dcache: |
363 | #ifdef HAVE_TEST_AND_CLEAN_CACHE | 378 | #ifdef HAVE_TEST_AND_CLEAN_CACHE |
364 | mrc p15, 0, r15, c7, c14, 3 @ test, clean and invalidate dcache | 379 | mrc p15, 0, r15, c7, c14, 3 @ test, clean and invalidate dcache |
365 | bne invalidate_dcache | 380 | bne commit_discard_dcache |
366 | mov r1, #0 | 381 | mov r1, #0 |
367 | #else | 382 | #else |
368 | mov r1, #0x00000000 @ | 383 | mov r1, #0x00000000 @ |
@@ -379,22 +394,26 @@ invalidate_dcache: | |||
379 | #endif /* HAVE_TEST_AND_CLEAN_CACHE */ | 394 | #endif /* HAVE_TEST_AND_CLEAN_CACHE */ |
380 | mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer | 395 | mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer |
381 | bx lr @ | 396 | bx lr @ |
382 | .size invalidate_dcache, .-invalidate_dcache | 397 | .size commit_discard_dcache, .-commit_discard_dcache |
383 | 398 | ||
384 | /* | 399 | /* |
385 | * Invalidate entire ICache and DCache | 400 | * Discards the entire ICache, and commit+discards the entire DCache |
386 | * will do writeback | 401 | * void commit_discard_idcache(void); |
387 | * void invalidate_idcache(void); | ||
388 | */ | 402 | */ |
389 | .section .icode, "ax", %progbits | 403 | .section .icode, "ax", %progbits |
390 | .align 2 | 404 | .align 2 |
391 | .global invalidate_idcache | 405 | .global commit_discard_idcache |
392 | .type invalidate_idcache, %function | 406 | .type commit_discard_idcache, %function |
393 | .global cpucache_invalidate @ Alias | 407 | .global cpucache_commit_discard @ Alias |
408 | .global invalidate_idcache @ Alias, deprecated | ||
409 | .global cpucache_invalidate @ Alias, deprecated | ||
410 | |||
411 | commit_discard_idcache: | ||
412 | cpucache_commit_discard: | ||
394 | invalidate_idcache: | 413 | invalidate_idcache: |
395 | cpucache_invalidate: | 414 | cpucache_invalidate: |
396 | mov r2, lr @ save lr to r1, call uses r0 only | 415 | mov r2, lr @ save lr to r1, call uses r0 only |
397 | bl invalidate_dcache @ Clean and invalidate entire DCache | 416 | bl commit_discard_dcache @ commit and discard entire DCache |
398 | mcr p15, 0, r1, c7, c5, 0 @ Invalidate ICache (r1=0 from call) | 417 | mcr p15, 0, r1, c7, c5, 0 @ Invalidate ICache (r1=0 from call) |
399 | bx r2 | 418 | bx r2 |
400 | .size invalidate_idcache, .-invalidate_idcache | 419 | .size commit_discard_idcache, .-commit_discard_idcache |
diff --git a/firmware/target/arm/mmu-arm.h b/firmware/target/arm/mmu-arm.h index 1cf1f68d00..92a81c0c34 100644 --- a/firmware/target/arm/mmu-arm.h +++ b/firmware/target/arm/mmu-arm.h | |||
@@ -35,29 +35,59 @@ void ttb_init(void); | |||
35 | void enable_mmu(void); | 35 | void enable_mmu(void); |
36 | void map_section(unsigned int pa, unsigned int va, int mb, int flags); | 36 | void map_section(unsigned int pa, unsigned int va, int mb, int flags); |
37 | 37 | ||
38 | /* Cleans entire DCache */ | 38 | /* Note for the function names |
39 | * | ||
40 | * ARM refers to the cache coherency functions as (in the CPU manuals): | ||
41 | * clean (write-back) | ||
42 | * clean and invalidate (write-back and removing the line from cache) | ||
43 | * invalidate (removing from cache without write-back) | ||
44 | * | ||
45 | * The deprecated functions below don't follow the above (which is why | ||
46 | * they're deprecated). | ||
47 | * | ||
48 | * This names have been proven to cause confusion, therefore we use: | ||
49 | * commit | ||
50 | * commit and discard | ||
51 | * discard | ||
52 | */ | ||
53 | |||
54 | /* Commits entire DCache */ | ||
55 | void commit_dcache(void); | ||
56 | /* deprecated alias */ | ||
39 | void clean_dcache(void); | 57 | void clean_dcache(void); |
40 | 58 | ||
41 | /* Invalidate entire DCache */ | 59 | /* Commit and discard entire DCache, will do writeback */ |
42 | /* will do writeback */ | 60 | void commit_discard_dcache(void); |
61 | /* deprecated alias */ | ||
43 | void invalidate_dcache(void); | 62 | void invalidate_dcache(void); |
44 | 63 | ||
45 | /* Invalidate DCache for this range */ | 64 | /* Write DCache back to RAM for the given range and remove cache lines |
46 | /* will do writeback */ | 65 | * from DCache afterwards */ |
66 | void commit_discard_dcache_range(const void *base, unsigned int size); | ||
67 | /* deprecated alias */ | ||
47 | void invalidate_dcache_range(const void *base, unsigned int size); | 68 | void invalidate_dcache_range(const void *base, unsigned int size); |
48 | 69 | ||
49 | /* clean DCache for this range */ | 70 | /* Write DCache back to RAM for the given range */ |
50 | /* forces DCache writeback for the specified range */ | 71 | void commit_dcache_range(const void *base, unsigned int size); |
72 | /* deprecated alias */ | ||
51 | void clean_dcache_range(const void *base, unsigned int size); | 73 | void clean_dcache_range(const void *base, unsigned int size); |
52 | 74 | ||
53 | /* Dump DCache for this range */ | 75 | /* |
54 | /* Will *NOT* do write back except for buffer ends not on a line boundary */ | 76 | * Remove cache lines for the given range from DCache |
77 | * will *NOT* do write back except for buffer edges not on a line boundary | ||
78 | */ | ||
79 | void discard_dcache_range(const void *base, unsigned int size); | ||
80 | /* deprecated alias */ | ||
55 | void dump_dcache_range(const void *base, unsigned int size); | 81 | void dump_dcache_range(const void *base, unsigned int size); |
56 | 82 | ||
57 | /* Invalidate entire ICache and DCache */ | 83 | /* Discards the entire ICache, and commit+discards the entire DCache */ |
58 | /* will do writeback */ | 84 | void commit_discard_idcache(void); |
85 | /* deprecated alias */ | ||
59 | void invalidate_idcache(void); | 86 | void invalidate_idcache(void); |
60 | 87 | ||
88 | #define HAVE_CPUCACHE_COMMIT_DISCARD | ||
89 | #define HAVE_CPUCACHE_COMMIT | ||
90 | /* deprecated alias */ | ||
61 | #define HAVE_CPUCACHE_INVALIDATE | 91 | #define HAVE_CPUCACHE_INVALIDATE |
62 | #define HAVE_CPUCACHE_FLUSH | 92 | #define HAVE_CPUCACHE_FLUSH |
63 | 93 | ||
diff --git a/firmware/target/arm/mmu-armv6.S b/firmware/target/arm/mmu-armv6.S index 58e03d6614..38eefece81 100644 --- a/firmware/target/arm/mmu-armv6.S +++ b/firmware/target/arm/mmu-armv6.S | |||
@@ -28,15 +28,18 @@ | |||
28 | #if 0 /* unused */ | 28 | #if 0 /* unused */ |
29 | 29 | ||
30 | /* | 30 | /* |
31 | * Invalidate DCache for this range | 31 | * Write DCache back to RAM for the given range and remove cache lines |
32 | * will do write back | 32 | * from DCache afterwards |
33 | * void invalidate_dcache_range(const void *base, unsigned int size) | 33 | * void commit_discard_dcache_range(const void *base, unsigned int size); |
34 | */ | 34 | */ |
35 | .section .text, "ax", %progbits | 35 | .section .text, "ax", %progbits |
36 | .align 2 | 36 | .align 2 |
37 | .global invalidate_dcache_range | 37 | .global commit_discard_dcache_range |
38 | .type invalidate_dcache_range, %function | 38 | .type commit_discard_dcache_range, %function |
39 | @ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored | 39 | .global invalidate_dcache_range @ Alias, deprecated |
40 | |||
41 | @ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ | ||
42 | commit_discard_dcache_range: | ||
40 | invalidate_dcache_range: | 43 | invalidate_dcache_range: |
41 | add r1, r0, r1 @ size -> end | 44 | add r1, r0, r1 @ size -> end |
42 | cmp r1, r0 @ end <= start? | 45 | cmp r1, r0 @ end <= start? |
@@ -45,20 +48,22 @@ invalidate_dcache_range: | |||
45 | mcrrhi p15, 0, r1, r0, c14 @ Clean and invalidate DCache range | 48 | mcrrhi p15, 0, r1, r0, c14 @ Clean and invalidate DCache range |
46 | mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier | 49 | mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier |
47 | bx lr @ | 50 | bx lr @ |
48 | .size invalidate_dcache_range, .-invalidate_dcache_range | 51 | .size commit_discard_dcache_range, .-commit_discard_dcache_range |
49 | 52 | ||
50 | #endif /* unused function */ | 53 | #endif /* unused function */ |
51 | 54 | ||
52 | /* | 55 | /* |
53 | * clean DCache for this range | 56 | * Write DCache back to RAM for the given range |
54 | * forces DCache writeback for the specified range | 57 | * void commit_dcache_range(const void *base, unsigned int size); |
55 | * void clean_dcache_range(const void *base, unsigned int size); | ||
56 | */ | 58 | */ |
57 | .section .text, "ax", %progbits | 59 | .section .text, "ax", %progbits |
58 | .align 2 | 60 | .align 2 |
59 | .global clean_dcache_range | 61 | .global commit_dcache_range |
60 | .type clean_dcache_range, %function | 62 | .type commit_dcache_range, %function |
61 | @ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored | 63 | .global clean_dcache_range @ Alias, deprecated |
64 | |||
65 | @ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ | ||
66 | commit_dcache_range: | ||
62 | clean_dcache_range: | 67 | clean_dcache_range: |
63 | add r1, r0, r1 @ size -> end | 68 | add r1, r0, r1 @ size -> end |
64 | cmp r1, r0 @ end <= start? | 69 | cmp r1, r0 @ end <= start? |
@@ -67,20 +72,22 @@ clean_dcache_range: | |||
67 | mcrrhi p15, 0, r1, r0, c12 @ Clean DCache range | 72 | mcrrhi p15, 0, r1, r0, c12 @ Clean DCache range |
68 | mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier | 73 | mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier |
69 | bx lr @ | 74 | bx lr @ |
70 | .size clean_dcache_range, .-clean_dcache_range | 75 | .size commit_dcache_range, .-commit_dcache_range |
71 | 76 | ||
72 | /* | 77 | /* |
73 | * Dump DCache for this range | 78 | * Remove cache lines for the given range from DCache |
74 | * will *NOT* do write back except for buffer edges not on a line boundary | 79 | * will *NOT* do write back except for buffer edges not on a line boundary |
75 | * void dump_dcache_range(const void *base, unsigned int size); | 80 | * void discard_dcache_range(const void *base, unsigned int size); |
76 | */ | 81 | */ |
77 | .section .text, "ax", %progbits | 82 | .section .text, "ax", %progbits |
78 | .align 2 | 83 | .align 2 |
79 | .global dump_dcache_range | 84 | .global discard_dcache_range |
80 | .type dump_dcache_range, %function | 85 | .type discard_dcache_range, %function |
81 | @ MVA format (mcr): 31:5 = Modified virtual address, 4:0 = SBZ | 86 | .global dump_dcache_range @ Alias, deprecated |
82 | @ MVA format (mcrr): 31:5 = Modified virtual address, 4:0 = Ignored | 87 | |
83 | dump_dcache_range: | 88 | @ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ |
89 | discard_dcache_range: | ||
90 | dump_dcache_range: | ||
84 | add r1, r0, r1 @ size -> end | 91 | add r1, r0, r1 @ size -> end |
85 | cmp r1, r0 @ end <= start? | 92 | cmp r1, r0 @ end <= start? |
86 | bxls lr @ | 93 | bxls lr @ |
@@ -100,52 +107,63 @@ clean_dcache_range: | |||
100 | mov r0, #0 @ | 107 | mov r0, #0 @ |
101 | mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier | 108 | mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier |
102 | bx lr @ | 109 | bx lr @ |
103 | .size dump_dcache_range, .-dump_dcache_range | 110 | .size discard_dcache_range, .-discard_dcache_range |
104 | 111 | ||
105 | 112 | ||
106 | /* | 113 | /* |
107 | * Cleans entire DCache | 114 | * Write entire DCache back to RAM |
108 | * void clean_dcache(void); | 115 | * void commit_dcache(void); |
109 | */ | 116 | */ |
110 | .section .text, "ax", %progbits | 117 | .section .text, "ax", %progbits |
111 | .align 2 | 118 | .align 2 |
112 | .global clean_dcache | 119 | .global commit_dcache |
113 | .type clean_dcache, %function | 120 | .type commit_dcache, %function |
114 | .global cpucache_flush @ Alias | 121 | .global cpucache_commit @ Alias |
122 | .global clean_dcache @ Alias, deprecated | ||
123 | .global cpucache_flush @ Alias, deprecated | ||
124 | |||
125 | commit_dcache: | ||
126 | cpucache_commit: | ||
115 | clean_dcache: | 127 | clean_dcache: |
116 | cpucache_flush: | 128 | cpucache_flush: |
117 | mov r0, #0 @ | 129 | mov r0, #0 @ |
118 | mcr p15, 0, r0, c7, c10, 0 @ Clean entire DCache | 130 | mcr p15, 0, r0, c7, c10, 0 @ Clean entire DCache |
119 | mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier | 131 | mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier |
120 | bx lr @ | 132 | bx lr @ |
121 | .size clean_dcache, .-clean_dcache | 133 | .size commit_dcache, .-commit_dcache |
122 | 134 | ||
123 | /* | 135 | /* |
124 | * Invalidate entire DCache | 136 | * Clean and invalidate entire DCache, will do writeback |
125 | * will do writeback | 137 | * void commit_discard_dcache(void); |
126 | * void invalidate_dcache(void); | ||
127 | */ | 138 | */ |
128 | .section .text, "ax", %progbits | 139 | .section .icode, "ax", %progbits |
129 | .align 2 | 140 | .align 2 |
130 | .global invalidate_dcache | 141 | .global commit_discard_dcache |
131 | .type invalidate_dcache, %function | 142 | .type commit_discard_dcache, %function |
143 | .global invalidate_dcache @ Alias, deprecated | ||
144 | |||
145 | commit_discard_dcache: | ||
132 | invalidate_dcache: | 146 | invalidate_dcache: |
133 | mov r0, #0 @ | 147 | mov r0, #0 @ |
134 | mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache | 148 | mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache |
135 | mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier | 149 | mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier |
136 | bx lr @ | 150 | bx lr @ |
137 | .size invalidate_dcache, .-invalidate_dcache | 151 | .size commit_discard_dcache, .-commit_discard_dcache |
138 | 152 | ||
153 | |||
139 | /* | 154 | /* |
140 | * Invalidate entire ICache and DCache | 155 | * Discards the entire ICache, and commit+discards the entire DCache |
141 | * will do writeback | 156 | * void commit_discard_idcache(void); |
142 | * void invalidate_idcache(void); | ||
143 | */ | 157 | */ |
144 | .section .icode, "ax", %progbits | 158 | .section .icode, "ax", %progbits |
145 | .align 2 | 159 | .align 2 |
146 | .global invalidate_idcache | 160 | .global commit_discard_idcache |
147 | .type invalidate_idcache, %function | 161 | .type commit_discard_idcache, %function |
148 | .global cpucache_invalidate @ Alias | 162 | .global cpucache_commit_discard @ Alias |
163 | .global invalidate_idcache @ Alias, deprecated | ||
164 | .global cpucache_invalidate @ Alias, deprecated | ||
165 | |||
166 | commit_discard_idcache: | ||
149 | invalidate_idcache: | 167 | invalidate_idcache: |
150 | cpucache_invalidate: | 168 | cpucache_invalidate: |
151 | mov r0, #0 @ | 169 | mov r0, #0 @ |
@@ -155,4 +173,4 @@ cpucache_invalidate: | |||
155 | mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier | 173 | mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier |
156 | mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer (IMB) | 174 | mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer (IMB) |
157 | bx lr @ | 175 | bx lr @ |
158 | .size invalidate_idcache, .-invalidate_idcache | 176 | .size commit_discard_idcache, .-commit_discard_idcache |
diff --git a/firmware/target/arm/system-pp5002.c b/firmware/target/arm/system-pp5002.c index 746441113e..04e052fa83 100644 --- a/firmware/target/arm/system-pp5002.c +++ b/firmware/target/arm/system-pp5002.c | |||
@@ -62,7 +62,7 @@ void __attribute__((interrupt("IRQ"))) irq_handler(void) | |||
62 | some other CPU frequency scaling. */ | 62 | some other CPU frequency scaling. */ |
63 | 63 | ||
64 | #ifndef BOOTLOADER | 64 | #ifndef BOOTLOADER |
65 | void ICODE_ATTR __attribute__((naked)) cpucache_flush(void) | 65 | void ICODE_ATTR __attribute__((naked)) cpucache_commit(void) |
66 | { | 66 | { |
67 | asm volatile( | 67 | asm volatile( |
68 | "mov r0, #0xf0000000 \n" | 68 | "mov r0, #0xf0000000 \n" |
@@ -70,14 +70,15 @@ void ICODE_ATTR __attribute__((naked)) cpucache_flush(void) | |||
70 | "add r1, r0, #0x2000 \n" /* r1 = CACHE_FLUSH_BASE + CACHE_SIZE */ | 70 | "add r1, r0, #0x2000 \n" /* r1 = CACHE_FLUSH_BASE + CACHE_SIZE */ |
71 | "mov r2, #0 \n" | 71 | "mov r2, #0 \n" |
72 | "1: \n" | 72 | "1: \n" |
73 | "str r2, [r0], #16 \n" /* Flush */ | 73 | "str r2, [r0], #16 \n" /* Commit */ |
74 | "cmp r0, r1 \n" | 74 | "cmp r0, r1 \n" |
75 | "blo 1b \n" | 75 | "blo 1b \n" |
76 | "bx lr \n" | 76 | "bx lr \n" |
77 | ); | 77 | ); |
78 | } | 78 | } |
79 | void cpucache_flush(void) __attribute__((alias("cpucache_commit"))); | ||
79 | 80 | ||
80 | void ICODE_ATTR __attribute__((naked)) cpucache_invalidate(void) | 81 | void ICODE_ATTR __attribute__((naked)) cpucache_commit_discard(void) |
81 | { | 82 | { |
82 | asm volatile( | 83 | asm volatile( |
83 | "mov r0, #0xf0000000 \n" | 84 | "mov r0, #0xf0000000 \n" |
@@ -86,13 +87,14 @@ void ICODE_ATTR __attribute__((naked)) cpucache_invalidate(void) | |||
86 | "add r1, r0, #0x2000 \n" /* r2 = CACHE_FLUSH_BASE + CACHE_SIZE */ | 87 | "add r1, r0, #0x2000 \n" /* r2 = CACHE_FLUSH_BASE + CACHE_SIZE */ |
87 | "mov r3, #0 \n" | 88 | "mov r3, #0 \n" |
88 | "1: \n" | 89 | "1: \n" |
89 | "str r3, [r0], #16 \n" /* Flush */ | 90 | "str r3, [r0], #16 \n" /* Commit */ |
90 | "str r3, [r2], #16 \n" /* Invalidate */ | 91 | "str r3, [r2], #16 \n" /* Discard */ |
91 | "cmp r0, r1 \n" | 92 | "cmp r0, r1 \n" |
92 | "blo 1b \n" | 93 | "blo 1b \n" |
93 | "bx lr \n" | 94 | "bx lr \n" |
94 | ); | 95 | ); |
95 | } | 96 | } |
97 | void cpucache_invalidate(void) __attribute__((alias("cpucache_commit_discard"))); | ||
96 | 98 | ||
97 | static void ipod_init_cache(void) | 99 | static void ipod_init_cache(void) |
98 | { | 100 | { |
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index c7503d7bcb..1e573be291 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h | |||
@@ -168,6 +168,9 @@ static inline void wake_core(int core) | |||
168 | 168 | ||
169 | /** cache functions **/ | 169 | /** cache functions **/ |
170 | #ifndef BOOTLOADER | 170 | #ifndef BOOTLOADER |
171 | #define HAVE_CPUCACHE_COMMIT_DISCARD | ||
172 | #define HAVE_CPUCACHE_COMMIT | ||
173 | /* deprecated alias */ | ||
171 | #define HAVE_CPUCACHE_INVALIDATE | 174 | #define HAVE_CPUCACHE_INVALIDATE |
172 | #define HAVE_CPUCACHE_FLUSH | 175 | #define HAVE_CPUCACHE_FLUSH |
173 | #endif | 176 | #endif |
diff --git a/firmware/target/coldfire/system-coldfire.c b/firmware/target/coldfire/system-coldfire.c index 75440a23bf..57d729f7e8 100644 --- a/firmware/target/coldfire/system-coldfire.c +++ b/firmware/target/coldfire/system-coldfire.c | |||
@@ -369,10 +369,12 @@ void coldfire_set_dataincontrol(unsigned long value) | |||
369 | restore_irq(level); | 369 | restore_irq(level); |
370 | } | 370 | } |
371 | 371 | ||
372 | void cpucache_invalidate(void) | 372 | void cpucache_commit_discard(void) |
373 | { | 373 | { |
374 | asm volatile ("move.l #0x01000000,%d0\n" | 374 | asm volatile ("move.l #0x01000000,%d0\n" |
375 | "movec.l %d0,%cacr\n" | 375 | "movec.l %d0,%cacr\n" |
376 | "move.l #0x80000000,%d0\n" | 376 | "move.l #0x80000000,%d0\n" |
377 | "movec.l %d0,%cacr"); | 377 | "movec.l %d0,%cacr"); |
378 | } | 378 | } |
379 | |||
380 | void cpucache_invalidate(void) __attribute__((alias("cpucache_commit_discard"))); | ||
diff --git a/firmware/target/coldfire/system-target.h b/firmware/target/coldfire/system-target.h index 347d8e13dc..2de8fd06c2 100644 --- a/firmware/target/coldfire/system-target.h +++ b/firmware/target/coldfire/system-target.h | |||
@@ -194,6 +194,8 @@ static inline uint32_t swap_odd_even32(uint32_t value) | |||
194 | return value; | 194 | return value; |
195 | } | 195 | } |
196 | 196 | ||
197 | #define HAVE_CPUCACHE_COMMIT_DISCARD | ||
198 | /* deprecated alias */ | ||
197 | #define HAVE_CPUCACHE_INVALIDATE | 199 | #define HAVE_CPUCACHE_INVALIDATE |
198 | 200 | ||
199 | #define DEFAULT_PLLCR_AUDIO_BITS 0x10400000 | 201 | #define DEFAULT_PLLCR_AUDIO_BITS 0x10400000 |