1 files changed, 60 insertions, 42 deletions
diff --git a/firmware/target/arm/mmu-armv6.S b/firmware/target/arm/mmu-armv6.S
index 58e03d6614..38eefece81 100644
--- a/firmware/target/arm/mmu-armv6.S
+++ b/firmware/target/arm/mmu-armv6.S
@@ -28,15 +28,18 @@
 #if 0 /* unused */
 /*
- * Invalidate DCache for this range
+ * Write DCache back to RAM for the given range and remove cache lines
- * will do write back
+ * from DCache afterwards
- * void invalidate_dcache_range(const void *base, unsigned int size)
+ * void commit_discard_dcache_range(const void *base, unsigned int size);
 */
    .section   .text, "ax", %progbits
    .align      2
-    .global     invalidate_dcache_range
+    .global     commit_discard_dcache_range
-    .type       invalidate_dcache_range, %function
+    .type       commit_discard_dcache_range, %function
-    @ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored
+    .global     invalidate_dcache_range @ Alias, deprecated
+    @ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ
+commit_discard_dcache_range:
 invalidate_dcache_range:
    add     r1, r0, r1              @ size -> end
    cmp     r1, r0                  @ end <= start?
@@ -45,20 +48,22 @@ invalidate_dcache_range:
    mcrrhi  p15, 0, r1, r0, c14     @ Clean and invalidate DCache range
    mcrhi   p15, 0, r2, c7, c10, 4  @ Data synchronization barrier
    bx      lr                      @
-    .size   invalidate_dcache_range, .-invalidate_dcache_range
+    .size   commit_discard_dcache_range, .-commit_discard_dcache_range
 #endif /* unused function */
 /*
- * clean DCache for this range
+ * Write DCache back to RAM for the given range
- * forces DCache writeback for the specified range
+ * void commit_dcache_range(const void *base, unsigned int size);
- * void clean_dcache_range(const void *base, unsigned int size);
 */
    .section   .text, "ax", %progbits
    .align      2
-    .global     clean_dcache_range
+    .global     commit_dcache_range
-    .type       clean_dcache_range, %function
+    .type       commit_dcache_range, %function
-    @ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored
+    .global     clean_dcache_range  @ Alias, deprecated
+    @ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ
+commit_dcache_range:
 clean_dcache_range:
    add     r1, r0, r1              @ size -> end
    cmp     r1, r0                  @ end <= start?
@@ -67,20 +72,22 @@ clean_dcache_range:
    mcrrhi  p15, 0, r1, r0, c12     @ Clean DCache range
    mcrhi   p15, 0, r2, c7, c10, 4  @ Data synchronization barrier
    bx      lr                      @
-    .size   clean_dcache_range, .-clean_dcache_range
+    .size   commit_dcache_range, .-commit_dcache_range
 /*
- * Dump DCache for this range
+ * Remove cache lines for the given range from DCache
 * will *NOT* do write back except for buffer edges not on a line boundary
- * void dump_dcache_range(const void *base, unsigned int size);
+ * void discard_dcache_range(const void *base, unsigned int size);
 */
    .section   .text, "ax", %progbits
    .align      2
-    .global     dump_dcache_range
+    .global     discard_dcache_range
-    .type       dump_dcache_range, %function
+    .type       discard_dcache_range, %function
-    @ MVA format (mcr):  31:5 = Modified virtual address, 4:0 = SBZ
+    .global     dump_dcache_range   @ Alias, deprecated
-    @ MVA format (mcrr): 31:5 = Modified virtual address, 4:0 = Ignored
- dump_dcache_range:
+    @ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ
+discard_dcache_range:
+dump_dcache_range:
    add     r1, r0, r1              @ size -> end
    cmp     r1, r0                  @ end <= start?
    bxls    lr                      @ 
@@ -100,52 +107,63 @@ clean_dcache_range:
    mov     r0, #0                  @
    mcr     p15, 0, r0, c7, c10, 4  @ Data synchronization barrier
    bx      lr                      @
-    .size   dump_dcache_range, .-dump_dcache_range
+    .size   discard_dcache_range, .-discard_dcache_range
 /*
- * Cleans entire DCache
+ * Write entire DCache back to RAM
- * void clean_dcache(void);
+ * void commit_dcache(void);
 */
    .section   .text, "ax", %progbits
    .align      2
-    .global     clean_dcache
+    .global     commit_dcache
-    .type       clean_dcache, %function
+    .type       commit_dcache, %function
-    .global     cpucache_flush      @ Alias
+    .global     cpucache_commit     @ Alias
+    .global     clean_dcache        @ Alias, deprecated
+    .global     cpucache_flush      @ Alias, deprecated
+commit_dcache:
+cpucache_commit:
 clean_dcache:
 cpucache_flush:
    mov     r0, #0                  @
    mcr     p15, 0, r0, c7, c10, 0  @ Clean entire DCache
    mcr     p15, 0, r0, c7, c10, 4  @ Data synchronization barrier
    bx      lr                      @
-    .size   clean_dcache, .-clean_dcache
+    .size   commit_dcache, .-commit_dcache
 /*
- * Invalidate entire DCache
+ * Clean and invalidate entire DCache, will do writeback
- * will do writeback
+ * void commit_discard_dcache(void);
- * void invalidate_dcache(void);
 */
-    .section   .text, "ax", %progbits
+    .section   .icode, "ax", %progbits
    .align      2
-    .global     invalidate_dcache
+    .global     commit_discard_dcache
-    .type       invalidate_dcache, %function
+    .type       commit_discard_dcache, %function
+    .global     invalidate_dcache   @ Alias, deprecated
+commit_discard_dcache:
 invalidate_dcache:
    mov     r0, #0                  @
    mcr     p15, 0, r0, c7, c14, 0  @ Clean and invalidate entire DCache
    mcr     p15, 0, r0, c7, c10, 4  @ Data synchronization barrier
    bx      lr                      @
-    .size   invalidate_dcache, .-invalidate_dcache
+    .size   commit_discard_dcache, .-commit_discard_dcache
    
 /*
- * Invalidate entire ICache and DCache
+ * Discards the entire ICache, and commit+discards the entire DCache
- * will do writeback
+ * void commit_discard_idcache(void);
- * void invalidate_idcache(void);
 */
    .section   .icode, "ax", %progbits
    .align      2
-    .global     invalidate_idcache
+    .global     commit_discard_idcache
-    .type       invalidate_idcache, %function
+    .type       commit_discard_idcache, %function
-    .global     cpucache_invalidate @ Alias
+    .global     cpucache_commit_discard @ Alias
+    .global     invalidate_idcache      @ Alias, deprecated
+    .global     cpucache_invalidate     @ Alias, deprecated
+commit_discard_idcache:
 invalidate_idcache:
 cpucache_invalidate:
    mov     r0, #0                  @
@@ -155,4 +173,4 @@ cpucache_invalidate:
    mcr     p15, 0, r0, c7, c10, 4  @ Data synchronization barrier
    mcr     p15, 0, r0, c7, c5, 4   @ Flush prefetch buffer (IMB)
    bx      lr                      @
-    .size   invalidate_idcache, .-invalidate_idcache
+    .size   commit_discard_idcache, .-commit_discard_idcache

diff --git a/firmware/target/arm/mmu-armv6.S b/firmware/target/arm/mmu-armv6.S index 58e03d6614..38eefece81 100644 --- a/firmware/target/arm/mmu-armv6.S +++ b/firmware/target/arm/mmu-armv6.S
@@ -28,15 +28,18 @@
28	#if 0 /* unused */	28	#if 0 /* unused */
29		29
30	/*	30	/*
31	* Invalidate DCache for this range	31	* Write DCache back to RAM for the given range and remove cache lines
32	* will do write back	32	* from DCache afterwards
33	* void invalidate_dcache_range(const void *base, unsigned int size)	33	* void commit_discard_dcache_range(const void *base, unsigned int size);
34	*/	34	*/
35	.section .text, "ax", %progbits	35	.section .text, "ax", %progbits
36	.align 2	36	.align 2
37	.global invalidate_dcache_range	37	.global commit_discard_dcache_range
38	.type invalidate_dcache_range, %function	38	.type commit_discard_dcache_range, %function
39	@ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored	39	.global invalidate_dcache_range @ Alias, deprecated
		40
		41	@ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ
		42	commit_discard_dcache_range:
40	invalidate_dcache_range:	43	invalidate_dcache_range:
41	add r1, r0, r1 @ size -> end	44	add r1, r0, r1 @ size -> end
42	cmp r1, r0 @ end <= start?	45	cmp r1, r0 @ end <= start?
@@ -45,20 +48,22 @@ invalidate_dcache_range:
45	mcrrhi p15, 0, r1, r0, c14 @ Clean and invalidate DCache range	48	mcrrhi p15, 0, r1, r0, c14 @ Clean and invalidate DCache range
46	mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier	49	mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier
47	bx lr @	50	bx lr @
48	.size invalidate_dcache_range, .-invalidate_dcache_range	51	.size commit_discard_dcache_range, .-commit_discard_dcache_range
49		52
50	#endif /* unused function */	53	#endif /* unused function */
51		54
52	/*	55	/*
53	* clean DCache for this range	56	* Write DCache back to RAM for the given range
54	* forces DCache writeback for the specified range	57	* void commit_dcache_range(const void *base, unsigned int size);
55	* void clean_dcache_range(const void *base, unsigned int size);
56	*/	58	*/
57	.section .text, "ax", %progbits	59	.section .text, "ax", %progbits
58	.align 2	60	.align 2
59	.global clean_dcache_range	61	.global commit_dcache_range
60	.type clean_dcache_range, %function	62	.type commit_dcache_range, %function
61	@ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored	63	.global clean_dcache_range @ Alias, deprecated
		64
		65	@ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ
		66	commit_dcache_range:
62	clean_dcache_range:	67	clean_dcache_range:
63	add r1, r0, r1 @ size -> end	68	add r1, r0, r1 @ size -> end
64	cmp r1, r0 @ end <= start?	69	cmp r1, r0 @ end <= start?
@@ -67,20 +72,22 @@ clean_dcache_range:
67	mcrrhi p15, 0, r1, r0, c12 @ Clean DCache range	72	mcrrhi p15, 0, r1, r0, c12 @ Clean DCache range
68	mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier	73	mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier
69	bx lr @	74	bx lr @
70	.size clean_dcache_range, .-clean_dcache_range	75	.size commit_dcache_range, .-commit_dcache_range
71		76
72	/*	77	/*
73	* Dump DCache for this range	78	* Remove cache lines for the given range from DCache
74	* will NOT do write back except for buffer edges not on a line boundary	79	* will NOT do write back except for buffer edges not on a line boundary
75	* void dump_dcache_range(const void *base, unsigned int size);	80	* void discard_dcache_range(const void *base, unsigned int size);
76	*/	81	*/
77	.section .text, "ax", %progbits	82	.section .text, "ax", %progbits
78	.align 2	83	.align 2
79	.global dump_dcache_range	84	.global discard_dcache_range
80	.type dump_dcache_range, %function	85	.type discard_dcache_range, %function
81	@ MVA format (mcr): 31:5 = Modified virtual address, 4:0 = SBZ	86	.global dump_dcache_range @ Alias, deprecated
82	@ MVA format (mcrr): 31:5 = Modified virtual address, 4:0 = Ignored	87
83	dump_dcache_range:	88	@ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ
		89	discard_dcache_range:
		90	dump_dcache_range:
84	add r1, r0, r1 @ size -> end	91	add r1, r0, r1 @ size -> end
85	cmp r1, r0 @ end <= start?	92	cmp r1, r0 @ end <= start?
86	bxls lr @	93	bxls lr @
@@ -100,52 +107,63 @@ clean_dcache_range:
100	mov r0, #0 @	107	mov r0, #0 @
101	mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier	108	mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
102	bx lr @	109	bx lr @
103	.size dump_dcache_range, .-dump_dcache_range	110	.size discard_dcache_range, .-discard_dcache_range
104		111
105		112
106	/*	113	/*
107	* Cleans entire DCache	114	* Write entire DCache back to RAM
108	* void clean_dcache(void);	115	* void commit_dcache(void);
109	*/	116	*/
110	.section .text, "ax", %progbits	117	.section .text, "ax", %progbits
111	.align 2	118	.align 2
112	.global clean_dcache	119	.global commit_dcache
113	.type clean_dcache, %function	120	.type commit_dcache, %function
114	.global cpucache_flush @ Alias	121	.global cpucache_commit @ Alias
		122	.global clean_dcache @ Alias, deprecated
		123	.global cpucache_flush @ Alias, deprecated
		124
		125	commit_dcache:
		126	cpucache_commit:
115	clean_dcache:	127	clean_dcache:
116	cpucache_flush:	128	cpucache_flush:
117	mov r0, #0 @	129	mov r0, #0 @
118	mcr p15, 0, r0, c7, c10, 0 @ Clean entire DCache	130	mcr p15, 0, r0, c7, c10, 0 @ Clean entire DCache
119	mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier	131	mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
120	bx lr @	132	bx lr @
121	.size clean_dcache, .-clean_dcache	133	.size commit_dcache, .-commit_dcache
122		134
123	/*	135	/*
124	* Invalidate entire DCache	136	* Clean and invalidate entire DCache, will do writeback
125	* will do writeback	137	* void commit_discard_dcache(void);
126	* void invalidate_dcache(void);
127	*/	138	*/
128	.section .text, "ax", %progbits	139	.section .icode, "ax", %progbits
129	.align 2	140	.align 2
130	.global invalidate_dcache	141	.global commit_discard_dcache
131	.type invalidate_dcache, %function	142	.type commit_discard_dcache, %function
		143	.global invalidate_dcache @ Alias, deprecated
		144
		145	commit_discard_dcache:
132	invalidate_dcache:	146	invalidate_dcache:
133	mov r0, #0 @	147	mov r0, #0 @
134	mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache	148	mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache
135	mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier	149	mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
136	bx lr @	150	bx lr @
137	.size invalidate_dcache, .-invalidate_dcache	151	.size commit_discard_dcache, .-commit_discard_dcache
138		152
		153
139	/*	154	/*
140	* Invalidate entire ICache and DCache	155	* Discards the entire ICache, and commit+discards the entire DCache
141	* will do writeback	156	* void commit_discard_idcache(void);
142	* void invalidate_idcache(void);
143	*/	157	*/
144	.section .icode, "ax", %progbits	158	.section .icode, "ax", %progbits
145	.align 2	159	.align 2
146	.global invalidate_idcache	160	.global commit_discard_idcache
147	.type invalidate_idcache, %function	161	.type commit_discard_idcache, %function
148	.global cpucache_invalidate @ Alias	162	.global cpucache_commit_discard @ Alias
		163	.global invalidate_idcache @ Alias, deprecated
		164	.global cpucache_invalidate @ Alias, deprecated
		165
		166	commit_discard_idcache:
149	invalidate_idcache:	167	invalidate_idcache:
150	cpucache_invalidate:	168	cpucache_invalidate:
151	mov r0, #0 @	169	mov r0, #0 @
@@ -155,4 +173,4 @@ cpucache_invalidate:
155	mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier	173	mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
156	mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer (IMB)	174	mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer (IMB)
157	bx lr @	175	bx lr @
158	.size invalidate_idcache, .-invalidate_idcache	176	.size commit_discard_idcache, .-commit_discard_idcache