diff options
-rw-r--r-- | firmware/export/ltv350qv.h | 113 | ||||
-rw-r--r-- | firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c | 106 |
2 files changed, 165 insertions, 54 deletions
diff --git a/firmware/export/ltv350qv.h b/firmware/export/ltv350qv.h new file mode 100644 index 0000000000..e557fc71e1 --- /dev/null +++ b/firmware/export/ltv350qv.h | |||
@@ -0,0 +1,113 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | /* | ||
20 | * Register definitions for Samsung LTV350QV Quarter VGA LCD Panel | ||
21 | * | ||
22 | * Copyright (C) 2006, 2007 Atmel Corporation | ||
23 | * | ||
24 | * This program is free software; you can redistribute it and/or modify | ||
25 | * it under the terms of the GNU General Public License version 2 as | ||
26 | * published by the Free Software Foundation. | ||
27 | */ | ||
28 | #ifndef __LTV350QV_H | ||
29 | #define __LTV350QV_H | ||
30 | |||
31 | #define LTV_OPC_INDEX 0x74 | ||
32 | #define LTV_OPC_DATA 0x76 | ||
33 | |||
34 | #define LTV_ID 0x00 /* ID Read */ | ||
35 | #define LTV_IFCTL 0x01 /* Display Interface Control */ | ||
36 | #define LTV_DATACTL 0x02 /* Display Data Control */ | ||
37 | #define LTV_ENTRY_MODE 0x03 /* Entry Mode */ | ||
38 | #define LTV_GATECTL1 0x04 /* Gate Control 1 */ | ||
39 | #define LTV_GATECTL2 0x05 /* Gate Control 2 */ | ||
40 | #define LTV_VBP 0x06 /* Vertical Back Porch */ | ||
41 | #define LTV_HBP 0x07 /* Horizontal Back Porch */ | ||
42 | #define LTV_SOTCTL 0x08 /* Source Output Timing Control */ | ||
43 | #define LTV_PWRCTL1 0x09 /* Power Control 1 */ | ||
44 | #define LTV_PWRCTL2 0x0a /* Power Control 2 */ | ||
45 | #define LTV_GAMMA(x) (0x10 + (x))/* Gamma control */ | ||
46 | |||
47 | /* Bit definitions for LTV_IFCTL */ | ||
48 | #define LTV_IM (1 << 15) | ||
49 | #define LTV_NMD (1 << 14) | ||
50 | #define LTV_SSMD (1 << 13) | ||
51 | #define LTV_REV (1 << 7) | ||
52 | #define LTV_NL(x) (((x) & 0x001f) << 0) | ||
53 | |||
54 | /* Bit definitions for LTV_DATACTL */ | ||
55 | #define LTV_DS_SAME (0 << 12) | ||
56 | #define LTV_DS_D_TO_S (1 << 12) | ||
57 | #define LTV_DS_S_TO_D (2 << 12) | ||
58 | #define LTV_CHS_384 (0 << 9) | ||
59 | #define LTV_CHS_480 (1 << 9) | ||
60 | #define LTV_CHS_492 (2 << 9) | ||
61 | #define LTV_DF_RGB (0 << 6) | ||
62 | #define LTV_DF_RGBX (1 << 6) | ||
63 | #define LTV_DF_XRGB (2 << 6) | ||
64 | #define LTV_RGB_RGB (0 << 2) | ||
65 | #define LTV_RGB_BGR (1 << 2) | ||
66 | #define LTV_RGB_GRB (2 << 2) | ||
67 | #define LTV_RGB_RBG (3 << 2) | ||
68 | |||
69 | /* Bit definitions for LTV_ENTRY_MODE */ | ||
70 | #define LTV_VSPL_ACTIVE_LOW (0 << 15) | ||
71 | #define LTV_VSPL_ACTIVE_HIGH (1 << 15) | ||
72 | #define LTV_HSPL_ACTIVE_LOW (0 << 14) | ||
73 | #define LTV_HSPL_ACTIVE_HIGH (1 << 14) | ||
74 | #define LTV_DPL_SAMPLE_RISING (0 << 13) | ||
75 | #define LTV_DPL_SAMPLE_FALLING (1 << 13) | ||
76 | #define LTV_EPL_ACTIVE_LOW (0 << 12) | ||
77 | #define LTV_EPL_ACTIVE_HIGH (1 << 12) | ||
78 | #define LTV_SS_LEFT_TO_RIGHT (0 << 8) | ||
79 | #define LTV_SS_RIGHT_TO_LEFT (1 << 8) | ||
80 | #define LTV_STB (1 << 1) | ||
81 | |||
82 | /* Bit definitions for LTV_GATECTL1 */ | ||
83 | #define LTV_CLW(x) (((x) & 0x0007) << 12) | ||
84 | #define LTV_GAON (1 << 5) | ||
85 | #define LTV_SDR (1 << 3) | ||
86 | |||
87 | /* Bit definitions for LTV_GATECTL2 */ | ||
88 | #define LTV_NW_INV_FRAME (0 << 14) | ||
89 | #define LTV_NW_INV_1LINE (1 << 14) | ||
90 | #define LTV_NW_INV_2LINE (2 << 14) | ||
91 | #define LTV_DSC (1 << 12) | ||
92 | #define LTV_GIF (1 << 8) | ||
93 | #define LTV_FHN (1 << 7) | ||
94 | #define LTV_FTI(x) (((x) & 0x0003) << 4) | ||
95 | #define LTV_FWI(x) (((x) & 0x0003) << 0) | ||
96 | |||
97 | /* Bit definitions for LTV_SOTCTL */ | ||
98 | #define LTV_SDT(x) (((x) & 0x0007) << 10) | ||
99 | #define LTV_EQ(x) (((x) & 0x0007) << 2) | ||
100 | |||
101 | /* Bit definitions for LTV_PWRCTL1 */ | ||
102 | #define LTV_VCOM_DISABLE (1 << 14) | ||
103 | #define LTV_VCOMOUT_ENABLE (1 << 11) | ||
104 | #define LTV_POWER_ON (1 << 9) | ||
105 | #define LTV_DRIVE_CURRENT(x) (((x) & 0x0007) << 4) /* 0=off, 5=max */ | ||
106 | #define LTV_SUPPLY_CURRENT(x) (((x) & 0x0007) << 0) /* 0=off, 5=max */ | ||
107 | |||
108 | /* Bit definitions for LTV_PWRCTL2 */ | ||
109 | #define LTV_VCOML_ENABLE (1 << 13) | ||
110 | #define LTV_VCOML_VOLTAGE(x) (((x) & 0x001f) << 8) /* 0=1V, 31=-1V */ | ||
111 | #define LTV_VCOMH_VOLTAGE(x) (((x) & 0x001f) << 0) /* 0=3V, 31=4.5V */ | ||
112 | |||
113 | #endif /* __LTV350QV_H */ | ||
diff --git a/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c b/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c index 2d75b1ffa6..a2634f0de7 100644 --- a/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c +++ b/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include "spi.h" | 27 | #include "spi.h" |
28 | #include "spi-target.h" | 28 | #include "spi-target.h" |
29 | #include "lcd-target.h" | 29 | #include "lcd-target.h" |
30 | #include "ltv350qv.h" | ||
30 | 31 | ||
31 | /* Power and display status */ | 32 | /* Power and display status */ |
32 | static bool display_on = false; /* Is the display turned on? */ | 33 | static bool display_on = false; /* Is the display turned on? */ |
@@ -85,13 +86,10 @@ static void enable_venc(bool enable) | |||
85 | /* LTV250QV panel functions */ | 86 | /* LTV250QV panel functions */ |
86 | static void lcd_write_reg(unsigned char reg, unsigned short val) | 87 | static void lcd_write_reg(unsigned char reg, unsigned short val) |
87 | { | 88 | { |
88 | unsigned char block[3]; | 89 | unsigned char block[3] = {LTV_OPC_INDEX, 0, reg | 0xFF}; |
89 | block[0] = 0x74; | ||
90 | block[1] = 0; | ||
91 | block[2] = reg | 0xFF; | ||
92 | spi_block_transfer(SPI_target_LTV250QV, block, sizeof(block), NULL, 0); | 90 | spi_block_transfer(SPI_target_LTV250QV, block, sizeof(block), NULL, 0); |
93 | block[0] = 0x76; | 91 | block[0] = LTV_OPC_DATA; |
94 | block[1] = (val >> 8) & 0xFF; | 92 | block[1] = val >> 8; |
95 | block[2] = val & 0xFF; | 93 | block[2] = val & 0xFF; |
96 | spi_block_transfer(SPI_target_LTV250QV, block, sizeof(block), NULL, 0); | 94 | spi_block_transfer(SPI_target_LTV250QV, block, sizeof(block), NULL, 0); |
97 | } | 95 | } |
@@ -128,57 +126,57 @@ static void lcd_display_on(bool reset) | |||
128 | IO_GIO_BITSET2 = (1 << 8); | 126 | IO_GIO_BITSET2 = (1 << 8); |
129 | sleep_ms(1); | 127 | sleep_ms(1); |
130 | 128 | ||
131 | lcd_write_reg(1, 0x1D); | 129 | lcd_write_reg(LTV_IFCTL, LTV_NL(29)); |
132 | lcd_write_reg(2, 0x0); | 130 | lcd_write_reg(LTV_DATACTL, 0); |
133 | lcd_write_reg(3, 0x0); | 131 | lcd_write_reg(LTV_ENTRY_MODE,0); |
134 | lcd_write_reg(4, 0x0); | 132 | lcd_write_reg(LTV_GATECTL1, 0); |
135 | lcd_write_reg(5, 0x40A3); | 133 | lcd_write_reg(LTV_GATECTL2, (LTV_NW_INV_1LINE | LTV_FHN | LTV_FTI(2) | LTV_FWI(3))); |
136 | lcd_write_reg(6, 0x0); | 134 | lcd_write_reg(LTV_VBP, 0); |
137 | lcd_write_reg(7, 0x0); | 135 | lcd_write_reg(LTV_HBP, 0); |
138 | lcd_write_reg(8, 0x0); | 136 | lcd_write_reg(LTV_SOTCTL, 0); |
139 | lcd_write_reg(9, 0x0); | 137 | lcd_write_reg(LTV_PWRCTL1, 0); |
140 | lcd_write_reg(10, 0x0); | 138 | lcd_write_reg(LTV_PWRCTL2, 0); |
141 | lcd_write_reg(16, 0x0); | 139 | lcd_write_reg(LTV_GAMMA(0), 0); |
142 | lcd_write_reg(17, 0x0); | 140 | lcd_write_reg(LTV_GAMMA(1), 0); |
143 | lcd_write_reg(18, 0x0); | 141 | lcd_write_reg(LTV_GAMMA(2), 0); |
144 | lcd_write_reg(19, 0x0); | 142 | lcd_write_reg(LTV_GAMMA(3), 0); |
145 | lcd_write_reg(20, 0x0); | 143 | lcd_write_reg(LTV_GAMMA(4), 0); |
146 | lcd_write_reg(21, 0x0); | 144 | lcd_write_reg(LTV_GAMMA(5), 0); |
147 | lcd_write_reg(22, 0x0); | 145 | lcd_write_reg(LTV_GAMMA(6), 0); |
148 | lcd_write_reg(23, 0x0); | 146 | lcd_write_reg(LTV_GAMMA(7), 0); |
149 | lcd_write_reg(24, 0x0); | 147 | lcd_write_reg(LTV_GAMMA(8), 0); |
150 | lcd_write_reg(25, 0x0); | 148 | lcd_write_reg(LTV_GAMMA(9), 0); |
151 | sleep_ms(10); | 149 | sleep_ms(10); |
152 | 150 | ||
153 | lcd_write_reg(9, 0x4055); | 151 | lcd_write_reg(LTV_PWRCTL1, (LTV_VCOM_DISABLE | LTV_DRIVE_CURRENT(5) | LTV_SUPPLY_CURRENT(5))); |
154 | lcd_write_reg(10, 0x0); | 152 | lcd_write_reg(LTV_PWRCTL2, 0); |
155 | sleep_ms(40); | 153 | sleep_ms(40); |
156 | 154 | ||
157 | lcd_write_reg(10, 0x2000); | 155 | lcd_write_reg(LTV_PWRCTL2, LTV_VCOML_ENABLE); |
158 | sleep_ms(40); | 156 | sleep_ms(40); |
159 | 157 | ||
160 | lcd_write_reg(1, 0x401D); | 158 | lcd_write_reg(LTV_IFCTL, (LTV_NMD | LTV_NL(29))); |
161 | lcd_write_reg(2, 0x204); | 159 | lcd_write_reg(LTV_DATACTL, (LTV_DS_SAME | LTV_CHS_480 | LTV_DF_RGB | LTV_RGB_BGR)); |
162 | lcd_write_reg(3, 0x100); | 160 | lcd_write_reg(LTV_ENTRY_MODE,(LTV_VSPL_ACTIVE_LOW | LTV_HSPL_ACTIVE_LOW | LTV_DPL_SAMPLE_RISING | LTV_EPL_ACTIVE_LOW | LTV_SS_RIGHT_TO_LEFT)); |
163 | lcd_write_reg(4, 0x1000); | 161 | lcd_write_reg(LTV_GATECTL1, LTV_CLW(1)); |
164 | lcd_write_reg(5, 0x5033); | 162 | lcd_write_reg(LTV_GATECTL2, (LTV_NW_INV_1LINE | LTV_DSC | LTV_FTI(3) | LTV_FWI(3))); |
165 | lcd_write_reg(6, 0x5); | 163 | lcd_write_reg(LTV_VBP, 0x5); |
166 | lcd_write_reg(7, 0x1B); | 164 | lcd_write_reg(LTV_HBP, 0x1B); |
167 | lcd_write_reg(8, 0x800); | 165 | lcd_write_reg(LTV_SOTCTL, LTV_SDT(2)); |
168 | lcd_write_reg(16, 0x203); | 166 | lcd_write_reg(LTV_GAMMA(0), 0x203); |
169 | lcd_write_reg(17, 0x302); | 167 | lcd_write_reg(LTV_GAMMA(1), 0x302); |
170 | lcd_write_reg(18, 0xC08); | 168 | lcd_write_reg(LTV_GAMMA(2), 0xC08); |
171 | lcd_write_reg(19, 0xC08); | 169 | lcd_write_reg(LTV_GAMMA(3), 0xC08); |
172 | lcd_write_reg(20, 0x707); | 170 | lcd_write_reg(LTV_GAMMA(4), 0x707); |
173 | lcd_write_reg(21, 0x707); | 171 | lcd_write_reg(LTV_GAMMA(5), 0x707); |
174 | lcd_write_reg(22, 0x104); | 172 | lcd_write_reg(LTV_GAMMA(6), 0x104); |
175 | lcd_write_reg(23, 0x306); | 173 | lcd_write_reg(LTV_GAMMA(7), 0x306); |
176 | lcd_write_reg(24, 0x0); | 174 | lcd_write_reg(LTV_GAMMA(8), 0); |
177 | lcd_write_reg(25, 0x0); | 175 | lcd_write_reg(LTV_GAMMA(9), 0); |
178 | sleep_ms(60); | 176 | sleep_ms(60); |
179 | 177 | ||
180 | lcd_write_reg(9, 0xA55); | 178 | lcd_write_reg(LTV_PWRCTL1, (LTV_VCOMOUT_ENABLE | LTV_POWER_ON | LTV_DRIVE_CURRENT(5) | LTV_SUPPLY_CURRENT(5))); |
181 | lcd_write_reg(10, 0x111A); | 179 | lcd_write_reg(LTV_PWRCTL2, (LTV_VCOML_VOLTAGE(17) | LTV_VCOMH_VOLTAGE(26))); /* VCOML=0,0625V VCOMH=1,21875V */ |
182 | sleep_ms(10); | 180 | sleep_ms(10); |
183 | 181 | ||
184 | if(!reset) | 182 | if(!reset) |
@@ -194,15 +192,15 @@ static void lcd_display_on(bool reset) | |||
194 | static void lcd_display_off(void) | 192 | static void lcd_display_off(void) |
195 | { | 193 | { |
196 | /* LQV shutdown sequence */ | 194 | /* LQV shutdown sequence */ |
197 | lcd_write_reg(9, 0x855); | 195 | lcd_write_reg(LTV_PWRCTL1, (LTV_VCOMOUT_ENABLE | LTV_DRIVE_CURRENT(5) | LTV_SUPPLY_CURRENT(5))); |
198 | sleep_ms(20); | 196 | sleep_ms(20); |
199 | 197 | ||
200 | lcd_write_reg(9, 0x55); | 198 | lcd_write_reg(LTV_PWRCTL1, (LTV_DRIVE_CURRENT(5) | LTV_SUPPLY_CURRENT(5))); |
201 | lcd_write_reg(5, 0x4033); | 199 | lcd_write_reg(LTV_GATECTL2, (LTV_NW_INV_1LINE | LTV_FTI(3) | LTV_FWI(3))); |
202 | lcd_write_reg(10, 0x0); | 200 | lcd_write_reg(LTV_PWRCTL2, 0); |
203 | sleep_ms(20); | 201 | sleep_ms(20); |
204 | 202 | ||
205 | lcd_write_reg(9, 0x0); | 203 | lcd_write_reg(LTV_PWRCTL1, 0); |
206 | sleep_ms(10); | 204 | sleep_ms(10); |
207 | unsigned char temp[1]; | 205 | unsigned char temp[1]; |
208 | temp[0] = 0; | 206 | temp[0] = 0; |