Use LTV350QV register definitions

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17452 a1c6a512-1295-4272-9138-f99709370657

2 files changed, 165 insertions, 54 deletions

diff --git a/firmware/export/ltv350qv.h b/firmware/export/ltv350qv.h
new file mode 100644
index 0000000000..e557fc71e1
--- /dev/null
+++ b/firmware/export/ltv350qv.h
@@ -0,0 +1,113 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2008 by Maurus Cuelenaere
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+/*
+ * Register definitions for Samsung LTV350QV Quarter VGA LCD Panel
+ *
+ * Copyright (C) 2006, 2007 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LTV350QV_H
+#define __LTV350QV_H
+
+#define LTV_OPC_INDEX          0x74
+#define LTV_OPC_DATA           0x76
+
+#define LTV_ID                 0x00        /* ID Read */
+#define LTV_IFCTL              0x01        /* Display Interface Control */
+#define LTV_DATACTL            0x02        /* Display Data Control */
+#define LTV_ENTRY_MODE         0x03        /* Entry Mode */
+#define LTV_GATECTL1           0x04        /* Gate Control 1 */
+#define LTV_GATECTL2           0x05        /* Gate Control 2 */
+#define LTV_VBP                0x06        /* Vertical Back Porch */
+#define LTV_HBP                0x07        /* Horizontal Back Porch */
+#define LTV_SOTCTL             0x08        /* Source Output Timing Control */
+#define LTV_PWRCTL1            0x09        /* Power Control 1 */
+#define LTV_PWRCTL2            0x0a        /* Power Control 2 */
+#define LTV_GAMMA(x)           (0x10 + (x))/* Gamma control */
+
+/* Bit definitions for LTV_IFCTL */
+#define LTV_IM                 (1 << 15)
+#define LTV_NMD                (1 << 14)
+#define LTV_SSMD               (1 << 13)
+#define LTV_REV                (1 <<  7)
+#define LTV_NL(x)              (((x) & 0x001f) << 0)
+
+/* Bit definitions for LTV_DATACTL */
+#define LTV_DS_SAME            (0 << 12)
+#define LTV_DS_D_TO_S          (1 << 12)
+#define LTV_DS_S_TO_D          (2 << 12)
+#define LTV_CHS_384            (0 <<  9)
+#define LTV_CHS_480            (1 <<  9)
+#define LTV_CHS_492            (2 <<  9)
+#define LTV_DF_RGB             (0 <<  6)
+#define LTV_DF_RGBX            (1 <<  6)
+#define LTV_DF_XRGB            (2 <<  6)
+#define LTV_RGB_RGB            (0 <<  2)
+#define LTV_RGB_BGR            (1 <<  2)
+#define LTV_RGB_GRB            (2 <<  2)
+#define LTV_RGB_RBG            (3 <<  2)
+
+/* Bit definitions for LTV_ENTRY_MODE */
+#define LTV_VSPL_ACTIVE_LOW    (0 << 15)
+#define LTV_VSPL_ACTIVE_HIGH   (1 << 15)
+#define LTV_HSPL_ACTIVE_LOW    (0 << 14)
+#define LTV_HSPL_ACTIVE_HIGH   (1 << 14)
+#define LTV_DPL_SAMPLE_RISING  (0 << 13)
+#define LTV_DPL_SAMPLE_FALLING (1 << 13)
+#define LTV_EPL_ACTIVE_LOW     (0 << 12)
+#define LTV_EPL_ACTIVE_HIGH    (1 << 12)
+#define LTV_SS_LEFT_TO_RIGHT   (0 <<  8)
+#define LTV_SS_RIGHT_TO_LEFT   (1 <<  8)
+#define LTV_STB                (1 <<  1)
+
+/* Bit definitions for LTV_GATECTL1 */
+#define LTV_CLW(x)             (((x) & 0x0007) << 12)
+#define LTV_GAON               (1 <<  5)
+#define LTV_SDR                (1 <<  3)
+
+/* Bit definitions for LTV_GATECTL2 */
+#define LTV_NW_INV_FRAME       (0 << 14)
+#define LTV_NW_INV_1LINE       (1 << 14)
+#define LTV_NW_INV_2LINE       (2 << 14)
+#define LTV_DSC                (1 << 12)
+#define LTV_GIF                (1 <<  8)
+#define LTV_FHN                (1 <<  7)
+#define LTV_FTI(x)             (((x) & 0x0003) << 4)
+#define LTV_FWI(x)             (((x) & 0x0003) << 0)
+
+/* Bit definitions for LTV_SOTCTL */
+#define LTV_SDT(x)             (((x) & 0x0007) << 10)
+#define LTV_EQ(x)              (((x) & 0x0007) <<  2)
+
+/* Bit definitions for LTV_PWRCTL1 */
+#define LTV_VCOM_DISABLE       (1 << 14)
+#define LTV_VCOMOUT_ENABLE     (1 << 11)
+#define LTV_POWER_ON           (1 <<  9)
+#define LTV_DRIVE_CURRENT(x)   (((x) & 0x0007) << 4)    /* 0=off, 5=max */
+#define LTV_SUPPLY_CURRENT(x)  (((x) & 0x0007) << 0)    /* 0=off, 5=max */
+
+/* Bit definitions for LTV_PWRCTL2 */
+#define LTV_VCOML_ENABLE       (1 << 13)
+#define LTV_VCOML_VOLTAGE(x)   (((x) & 0x001f) << 8)    /* 0=1V, 31=-1V */
+#define LTV_VCOMH_VOLTAGE(x)   (((x) & 0x001f) << 0)    /* 0=3V, 31=4.5V */
+
+#endif /* __LTV350QV_H */
diff --git a/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c b/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c
index 2d75b1ffa6..a2634f0de7 100644
--- a/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c
+++ b/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c
@@ -27,6 +27,7 @@
 #include "spi.h"
 #include "spi-target.h"
 #include "lcd-target.h"
+#include "ltv350qv.h"
 
 /* Power and display status */
 static bool display_on = false; /* Is the display turned on? */
@@ -85,13 +86,10 @@ static void enable_venc(bool enable)
 /* LTV250QV panel functions */
 static void lcd_write_reg(unsigned char reg, unsigned short val)
 {
-    unsigned char block[3];
-    block[0] = 0x74;
-    block[1] = 0;
-    block[2] = reg | 0xFF;
+    unsigned char block[3] = {LTV_OPC_INDEX, 0, reg | 0xFF};
     spi_block_transfer(SPI_target_LTV250QV, block, sizeof(block), NULL, 0);
-    block[0] = 0x76;
-    block[1] = (val >> 8) & 0xFF;
+    block[0] = LTV_OPC_DATA;
+    block[1] = val >> 8;
     block[2] = val & 0xFF;
     spi_block_transfer(SPI_target_LTV250QV, block, sizeof(block), NULL, 0);
 }
@@ -128,57 +126,57 @@ static void lcd_display_on(bool reset)
     IO_GIO_BITSET2 = (1 << 8);
     sleep_ms(1);
     
-    lcd_write_reg(1,  0x1D);
-    lcd_write_reg(2,  0x0);
-    lcd_write_reg(3,  0x0);
-    lcd_write_reg(4,  0x0);
-    lcd_write_reg(5,  0x40A3);
-    lcd_write_reg(6,  0x0);
-    lcd_write_reg(7,  0x0);
-    lcd_write_reg(8,  0x0);
-    lcd_write_reg(9,  0x0);
-    lcd_write_reg(10, 0x0);
-    lcd_write_reg(16, 0x0);
-    lcd_write_reg(17, 0x0);
-    lcd_write_reg(18, 0x0);
-    lcd_write_reg(19, 0x0);
-    lcd_write_reg(20, 0x0);
-    lcd_write_reg(21, 0x0);
-    lcd_write_reg(22, 0x0);
-    lcd_write_reg(23, 0x0);
-    lcd_write_reg(24, 0x0);
-    lcd_write_reg(25, 0x0);
+    lcd_write_reg(LTV_IFCTL,     LTV_NL(29));
+    lcd_write_reg(LTV_DATACTL,   0);
+    lcd_write_reg(LTV_ENTRY_MODE,0);
+    lcd_write_reg(LTV_GATECTL1,  0);
+    lcd_write_reg(LTV_GATECTL2,  (LTV_NW_INV_1LINE | LTV_FHN | LTV_FTI(2) | LTV_FWI(3)));
+    lcd_write_reg(LTV_VBP,       0);
+    lcd_write_reg(LTV_HBP,       0);
+    lcd_write_reg(LTV_SOTCTL,    0);
+    lcd_write_reg(LTV_PWRCTL1,   0);
+    lcd_write_reg(LTV_PWRCTL2,   0);
+    lcd_write_reg(LTV_GAMMA(0),  0);
+    lcd_write_reg(LTV_GAMMA(1),  0);
+    lcd_write_reg(LTV_GAMMA(2),  0);
+    lcd_write_reg(LTV_GAMMA(3),  0);
+    lcd_write_reg(LTV_GAMMA(4),  0);
+    lcd_write_reg(LTV_GAMMA(5),  0);
+    lcd_write_reg(LTV_GAMMA(6),  0);
+    lcd_write_reg(LTV_GAMMA(7),  0);
+    lcd_write_reg(LTV_GAMMA(8),  0);
+    lcd_write_reg(LTV_GAMMA(9),  0);
     sleep_ms(10);
     
-    lcd_write_reg(9,  0x4055);
-    lcd_write_reg(10, 0x0);
+    lcd_write_reg(LTV_PWRCTL1,   (LTV_VCOM_DISABLE | LTV_DRIVE_CURRENT(5) | LTV_SUPPLY_CURRENT(5)));
+    lcd_write_reg(LTV_PWRCTL2,   0);
     sleep_ms(40);
     
-    lcd_write_reg(10, 0x2000);
+    lcd_write_reg(LTV_PWRCTL2,   LTV_VCOML_ENABLE);
     sleep_ms(40);
     
-    lcd_write_reg(1,  0x401D);
-    lcd_write_reg(2,  0x204);
-    lcd_write_reg(3,  0x100);
-    lcd_write_reg(4,  0x1000);
-    lcd_write_reg(5,  0x5033);
-    lcd_write_reg(6,  0x5);
-    lcd_write_reg(7,  0x1B);
-    lcd_write_reg(8,  0x800);
-    lcd_write_reg(16, 0x203);
-    lcd_write_reg(17, 0x302);
-    lcd_write_reg(18, 0xC08);
-    lcd_write_reg(19, 0xC08);
-    lcd_write_reg(20, 0x707);
-    lcd_write_reg(21, 0x707);
-    lcd_write_reg(22, 0x104);
-    lcd_write_reg(23, 0x306);
-    lcd_write_reg(24, 0x0);
-    lcd_write_reg(25, 0x0);
+    lcd_write_reg(LTV_IFCTL,     (LTV_NMD | LTV_NL(29)));
+    lcd_write_reg(LTV_DATACTL,   (LTV_DS_SAME | LTV_CHS_480 | LTV_DF_RGB | LTV_RGB_BGR));
+    lcd_write_reg(LTV_ENTRY_MODE,(LTV_VSPL_ACTIVE_LOW | LTV_HSPL_ACTIVE_LOW | LTV_DPL_SAMPLE_RISING | LTV_EPL_ACTIVE_LOW | LTV_SS_RIGHT_TO_LEFT));
+    lcd_write_reg(LTV_GATECTL1,  LTV_CLW(1));
+    lcd_write_reg(LTV_GATECTL2,  (LTV_NW_INV_1LINE | LTV_DSC | LTV_FTI(3) | LTV_FWI(3)));
+    lcd_write_reg(LTV_VBP,       0x5);
+    lcd_write_reg(LTV_HBP,       0x1B);
+    lcd_write_reg(LTV_SOTCTL,    LTV_SDT(2));
+    lcd_write_reg(LTV_GAMMA(0),  0x203);
+    lcd_write_reg(LTV_GAMMA(1),  0x302);
+    lcd_write_reg(LTV_GAMMA(2),  0xC08);
+    lcd_write_reg(LTV_GAMMA(3),  0xC08);
+    lcd_write_reg(LTV_GAMMA(4),  0x707);
+    lcd_write_reg(LTV_GAMMA(5),  0x707);
+    lcd_write_reg(LTV_GAMMA(6),  0x104);
+    lcd_write_reg(LTV_GAMMA(7),  0x306);
+    lcd_write_reg(LTV_GAMMA(8),  0);
+    lcd_write_reg(LTV_GAMMA(9),  0);
     sleep_ms(60);
     
-    lcd_write_reg(9,  0xA55);
-    lcd_write_reg(10, 0x111A);
+    lcd_write_reg(LTV_PWRCTL1,   (LTV_VCOMOUT_ENABLE | LTV_POWER_ON | LTV_DRIVE_CURRENT(5) | LTV_SUPPLY_CURRENT(5)));
+    lcd_write_reg(LTV_PWRCTL2,   (LTV_VCOML_VOLTAGE(17) | LTV_VCOMH_VOLTAGE(26))); /* VCOML=0,0625V VCOMH=1,21875V */
     sleep_ms(10);
 
     if(!reset)
@@ -194,15 +192,15 @@ static void lcd_display_on(bool reset)
 static void lcd_display_off(void)
 {
     /* LQV shutdown sequence */
-    lcd_write_reg(9,  0x855);
+    lcd_write_reg(LTV_PWRCTL1,  (LTV_VCOMOUT_ENABLE | LTV_DRIVE_CURRENT(5) | LTV_SUPPLY_CURRENT(5)));
     sleep_ms(20);
     
-    lcd_write_reg(9,  0x55);
-    lcd_write_reg(5,  0x4033);
-    lcd_write_reg(10, 0x0);
+    lcd_write_reg(LTV_PWRCTL1,  (LTV_DRIVE_CURRENT(5) | LTV_SUPPLY_CURRENT(5)));
+    lcd_write_reg(LTV_GATECTL2, (LTV_NW_INV_1LINE | LTV_FTI(3) | LTV_FWI(3)));
+    lcd_write_reg(LTV_PWRCTL2,  0);
     sleep_ms(20);
     
-    lcd_write_reg(9, 0x0);
+    lcd_write_reg(LTV_PWRCTL1,  0);
     sleep_ms(10);
     unsigned char temp[1];
     temp[0] = 0;