diff options
Diffstat (limited to 'firmware/export/imx31l.h')
| -rwxr-xr-x | firmware/export/imx31l.h | 493 |
1 files changed, 209 insertions, 284 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index ea2187e0c2..2c1e93e528 100755 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
| @@ -247,10 +247,10 @@ | |||
| 247 | #define SW_MUX_CTL_SIG3 (0x7f << 16) | 247 | #define SW_MUX_CTL_SIG3 (0x7f << 16) |
| 248 | #define SW_MUX_CTL_SIG4 (0x7f << 24) | 248 | #define SW_MUX_CTL_SIG4 (0x7f << 24) |
| 249 | /* Shift above flags into one of the four fields in each register */ | 249 | /* Shift above flags into one of the four fields in each register */ |
| 250 | #define SW_MUX_CTL_SIG1w(x) (((x) << 0) & SW_MUX_CTL_SIG1) | 250 | #define SW_MUX_CTL_SIG1_POS (0) |
| 251 | #define SW_MUX_CTL_SIG2w(x) (((x) << 8) & SW_MUX_CTL_SIG2) | 251 | #define SW_MUX_CTL_SIG2_POS (8) |
| 252 | #define SW_MUX_CTL_SIG3w(x) (((x) << 16) & SW_MUX_CTL_SIG3) | 252 | #define SW_MUX_CTL_SIG3_POS (16) |
| 253 | #define SW_MUX_CTL_SIG4w(x) (((x) << 24) & SW_MUX_CTL_SIG4) | 253 | #define SW_MUX_CTL_SIG4_POS (24) |
| 254 | 254 | ||
| 255 | /* SW_PAD_CTL */ | 255 | /* SW_PAD_CTL */ |
| 256 | #define SW_PAD_CTL_TTM_PAD__X__X IOMUXC_(0x154) | 256 | #define SW_PAD_CTL_TTM_PAD__X__X IOMUXC_(0x154) |
| @@ -395,9 +395,9 @@ | |||
| 395 | #define SW_PAD_CTL_IO3 (0x3ff << 20) | 395 | #define SW_PAD_CTL_IO3 (0x3ff << 20) |
| 396 | 396 | ||
| 397 | /* Shift above flags into one of the three fields in each register */ | 397 | /* Shift above flags into one of the three fields in each register */ |
| 398 | #define SW_PAD_CTL_IO1w(x) (((x) << 0) & SW_PAD_CTL_IO1) | 398 | #define SW_PAD_CTL_IO1_POS (0) |
| 399 | #define SW_PAD_CTL_IO2w(x) (((x) << 10) & SW_PAD_CTL_IO2) | 399 | #define SW_PAD_CTL_IO2_POS (10) |
| 400 | #define SW_PAD_CTL_IO3w(x) (((x) << 20) & SW_PAD_CTL_IO3) | 400 | #define SW_PAD_CTL_IO3_POS (20) |
| 401 | 401 | ||
| 402 | /* RNGA */ | 402 | /* RNGA */ |
| 403 | #define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00)) | 403 | #define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00)) |
| @@ -530,7 +530,8 @@ | |||
| 530 | #define EPITCR_DBGEN (1 << 18) | 530 | #define EPITCR_DBGEN (1 << 18) |
| 531 | #define EPITCR_IOVW (1 << 17) | 531 | #define EPITCR_IOVW (1 << 17) |
| 532 | #define EPITCR_SWR (1 << 16) | 532 | #define EPITCR_SWR (1 << 16) |
| 533 | #define EPITCR_PRESCALER(n) ((n) << 4) /* Divide by n+1 */ | 533 | #define EPITCR_PRESCALER (0xfff << 4) /* Divide by n+1 */ |
| 534 | #define EPITCR_PRESCALER_POS (4) | ||
| 534 | #define EPITCR_RLD (1 << 3) | 535 | #define EPITCR_RLD (1 << 3) |
| 535 | #define EPITCR_OCIEN (1 << 2) | 536 | #define EPITCR_OCIEN (1 << 2) |
| 536 | #define EPITCR_ENMOD (1 << 1) | 537 | #define EPITCR_ENMOD (1 << 1) |
| @@ -933,10 +934,10 @@ | |||
| 933 | #define AUDMUX_CNMCR_CLKPOL (1 << 16) | 934 | #define AUDMUX_CNMCR_CLKPOL (1 << 16) |
| 934 | 935 | ||
| 935 | #define AUDMUX_CNMCR_CNTHI (0xff << 8) | 936 | #define AUDMUX_CNMCR_CNTHI (0xff << 8) |
| 936 | #define AUDMUX_CNMCR_CNTHIw(x) (((x) << 8) & AUDMUX_CNMCR_CNTHI) | 937 | #define AUDMUX_CNMCR_CNTHI_POS (8) |
| 937 | 938 | ||
| 938 | #define AUDMUX_CNMCR_CNTLOW (0xff << 0) | 939 | #define AUDMUX_CNMCR_CNTLOW (0xff << 0) |
| 939 | #define AUDMUX_CNMCR_CNTLOWw(x) (((x) << 0) & AUDMUX_CNMCR_CNTLOW) | 940 | #define AUDMUX_CNMCR_CNTLOW_POS (0) |
| 940 | 941 | ||
| 941 | /* SSI */ | 942 | /* SSI */ |
| 942 | #define SSI_STX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x00)) | 943 | #define SSI_STX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x00)) |
| @@ -1080,57 +1081,39 @@ | |||
| 1080 | #define SSI_STRCCR_WL24 (0xb << 13) | 1081 | #define SSI_STRCCR_WL24 (0xb << 13) |
| 1081 | 1082 | ||
| 1082 | #define SSI_STRCCR_DC (0x1f << 8) | 1083 | #define SSI_STRCCR_DC (0x1f << 8) |
| 1083 | #define SSI_STRCCR_DCw(x) (((x) << 8) & SSI_STRCCR_DC) | 1084 | #define SSI_STRCCR_DC_POS (8) |
| 1084 | #define SSI_STRCCR_DCr(x) (((x) & SSI_SRCCR_DC) >> 8) | ||
| 1085 | 1085 | ||
| 1086 | #define SSI_STRCCR_PM (0xf << 0) | 1086 | #define SSI_STRCCR_PM (0xf << 0) |
| 1087 | #define SSI_STRCCR_PMw(x) (((x) << 0) & SSI_STRCCR_PM) | 1087 | #define SSI_STRCCR_PM_POS (0) |
| 1088 | #define SSI_STRCCR_PMr(x) (((x) & SSI_SRCCR_PM) >> 0) | ||
| 1089 | 1088 | ||
| 1090 | /* SSI SFCSR */ | 1089 | /* SSI SFCSR */ |
| 1091 | #define SSI_SFCSR_RFCNT1 (0xf << 28) | 1090 | #define SSI_SFCSR_RFCNT1 (0xf << 28) |
| 1092 | #define SSI_SFCSR_RFCNT1w(x) (((x) << 28) & SSI_SFCSR_RFCNT1) | 1091 | #define SSI_SFCSR_RFCNT1_POS (28) |
| 1093 | #define SSI_SFCSR_RFCNT1r(x) (((x) & SSI_SFCSR_RFCNT1) >> 28) | ||
| 1094 | 1092 | ||
| 1095 | #define SSI_SFCSR_TFCNT1 (0xf << 24) | 1093 | #define SSI_SFCSR_TFCNT1 (0xf << 24) |
| 1096 | #define SSI_SFCSR_TFCNT1w(x) (((x) << 24) & SSI_SFCSR_TFCNT1) | 1094 | #define SSI_SFCSR_TFCNN1_POS (24) |
| 1097 | #define SSI_SFCSR_TFCNT1r(x) (((x) & SSI_SFCSR_TFCNT1) >> 24) | ||
| 1098 | 1095 | ||
| 1099 | #define SSI_SFCSR_RFWM1 (0xf << 20) | 1096 | #define SSI_SFCSR_RFWM1 (0xf << 20) |
| 1100 | #define SSI_SFCSR_RFWM1w(x) (((x) << 20) & SSI_SFCSR_RFWM1) | 1097 | #define SSI_SFCSR_RFWM1_POS (20) |
| 1101 | #define SSI_SFCSR_RFWM1r(x) (((x) & SSI_SFCSR_RFWM1) >> 20) | ||
| 1102 | #define SSI_SFCSR_RFWM1_1 (0x1 << 20) | ||
| 1103 | #define SSI_SFCSR_RFWM1_2 (0x2 << 20) | ||
| 1104 | #define SSI_SFCSR_RFWM1_3 (0x3 << 20) | ||
| 1105 | #define SSI_SFCSR_RFWM1_4 (0x4 << 20) | ||
| 1106 | #define SSI_SFCSR_RFWM1_5 (0x5 << 20) | ||
| 1107 | #define SSI_SFCSR_RFWM1_6 (0x6 << 20) | ||
| 1108 | #define SSI_SFCSR_RFWM1_7 (0x7 << 20) | ||
| 1109 | 1098 | ||
| 1110 | #define SSI_SFCSR_TFWM1 (0xf << 16) | 1099 | #define SSI_SFCSR_TFWM1 (0xf << 16) |
| 1111 | #define SSI_SFCSR_TFWM1w(x) (((x) << 16) & SSI_SFCSR_TFWM1) | 1100 | #define SSI_SFCSR_TFWM1_POS (16) |
| 1112 | #define SSI_SFCSR_TFWM1r(x) (((x) & SSI_SFCSR_TFWM1) >> 16) | ||
| 1113 | 1101 | ||
| 1114 | #define SSI_SFCSR_RFCNT0 (0xf << 12) | 1102 | #define SSI_SFCSR_RFCNT0 (0xf << 12) |
| 1115 | #define SSI_SFCSR_RFCNT0w(x) (((x) << 12) & SSI_SFCSR_RFCNT0) | 1103 | #define SSI_SFCSR_RFCNT0_POS (12) |
| 1116 | #define SSI_SFCSR_RFCNT0r(x) (((x) & SSI_SFCSR_RFCNT0) >> 12) | ||
| 1117 | 1104 | ||
| 1118 | #define SSI_SFCSR_TFCNT0 (0xf << 8) | 1105 | #define SSI_SFCSR_TFCNT0 (0xf << 8) |
| 1119 | #define SSI_SFCSR_TFCNT0w(x) (((x) << 8) & SSI_SFCSR_TFCNT0) | 1106 | #define SSI_SFCSR_TFCNT0_POS (8) |
| 1120 | #define SSI_SFCSR_TFCNT0r(x) (((x) & SSI_SFCSR_TFCNT0) >> 8) | ||
| 1121 | 1107 | ||
| 1122 | #define SSI_SFCSR_RFWM0 (0xf << 4) | 1108 | #define SSI_SFCSR_RFWM0 (0xf << 4) |
| 1123 | #define SSI_SFCSR_RFWM0w(x) (((x) << 4) & SSI_SFCSR_RFWM0) | 1109 | #define SSI_SFCSR_RFWM0_POS (4) |
| 1124 | #define SSI_SFCSR_RFWM0r(x) (((x) & SSI_SFCSR_RFWM0) >> 4) | ||
| 1125 | 1110 | ||
| 1126 | #define SSI_SFCSR_TFWM0 (0xf << 0) | 1111 | #define SSI_SFCSR_TFWM0 (0xf << 0) |
| 1127 | #define SSI_SFCSR_TFWM0w(x) (((x) << 0) & SSI_SFCSR_TFWM0) | 1112 | #define SSI_SFCSR_TFWM0_POS (0) |
| 1128 | #define SSI_SFCSR_TFWM0r(x) (((x) & SSI_SFCSR_TFWM0) >> 0) | ||
| 1129 | 1113 | ||
| 1130 | /* SACNT */ | 1114 | /* SACNT */ |
| 1131 | #define SSI_SACNT_FRDIV (0x3f << 5) | 1115 | #define SSI_SACNT_FRDIV (0x3f << 5) |
| 1132 | #define SSI_SACNT_FRDIVw(x) (((x) << 5) & SSI_SACNT_FRDIV) | 1116 | #define SSI_SACNT_FRDIV_POS (5) |
| 1133 | #define SSI_SACNT_FRDIVr(x) (((x) & SSI_SACNT_FRDIV) >> 5) | ||
| 1134 | 1117 | ||
| 1135 | #define SSI_SACNT_WR (0x1 << 4) | 1118 | #define SSI_SACNT_WR (0x1 << 4) |
| 1136 | #define SSI_SACNT_RD (0x1 << 3) | 1119 | #define SSI_SACNT_RD (0x1 << 3) |
| @@ -1156,8 +1139,7 @@ | |||
| 1156 | #define WDOG_WRSR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x04)) | 1139 | #define WDOG_WRSR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x04)) |
| 1157 | 1140 | ||
| 1158 | #define WDOG_WCR_WT (0xff << 8) | 1141 | #define WDOG_WCR_WT (0xff << 8) |
| 1159 | #define WDOG_WCR_WTw(x) (((x) << 8) & WDOG_WCR_WT) | 1142 | #define WDOG_WCR_WT_POS (8) |
| 1160 | #define WDOG_WCR_WTr(x) (((x) & WDOG_WCR_WT) >> 8) | ||
| 1161 | 1143 | ||
| 1162 | #define WDOG_WCR_WOE (0x1 << 6) | 1144 | #define WDOG_WCR_WOE (0x1 << 6) |
| 1163 | #define WDOG_WCR_WDA (0x1 << 5) | 1145 | #define WDOG_WCR_WDA (0x1 << 5) |
| @@ -1245,45 +1227,45 @@ | |||
| 1245 | /* | 1227 | /* |
| 1246 | * IRQ Controller Register Definitions. | 1228 | * IRQ Controller Register Definitions. |
| 1247 | */ | 1229 | */ |
| 1248 | #define AVIC_BASE_ADDR 0x68000000 | 1230 | #define AVIC_BASE_ADDR 0x68000000 |
| 1249 | #define INTCNTL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00)) | 1231 | #define AVIC_INTCNTL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00)) |
| 1250 | #define NIMASK (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04)) | 1232 | #define AVIC_NIMASK (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04)) |
| 1251 | #define INTENNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08)) | 1233 | #define AVIC_INTENNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08)) |
| 1252 | #define INTDISNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C)) | 1234 | #define AVIC_INTDISNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C)) |
| 1253 | #define INTENABLEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10)) | 1235 | #define AVIC_INTENABLEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10)) |
| 1254 | #define INTENABLEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14)) | 1236 | #define AVIC_INTENABLEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14)) |
| 1255 | #define INTTYPEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18)) | 1237 | #define AVIC_INTTYPEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18)) |
| 1256 | #define INTTYPEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C)) | 1238 | #define AVIC_INTTYPEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C)) |
| 1257 | #define NIPRIORITY(n) (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n]) | 1239 | #define AVIC_NIPRIORITY(n) (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n]) |
| 1258 | #define NIPRIORITY7 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20)) | 1240 | #define AVIC_NIPRIORITY7 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20)) |
| 1259 | #define NIPRIORITY6 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24)) | 1241 | #define AVIC_NIPRIORITY6 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24)) |
| 1260 | #define NIPRIORITY5 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28)) | 1242 | #define AVIC_NIPRIORITY5 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28)) |
| 1261 | #define NIPRIORITY4 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C)) | 1243 | #define AVIC_NIPRIORITY4 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C)) |
| 1262 | #define NIPRIORITY3 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30)) | 1244 | #define AVIC_NIPRIORITY3 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30)) |
| 1263 | #define NIPRIORITY2 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34)) | 1245 | #define AVIC_NIPRIORITY2 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34)) |
| 1264 | #define NIPRIORITY1 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38)) | 1246 | #define AVIC_NIPRIORITY1 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38)) |
| 1265 | #define NIPRIORITY0 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C)) | 1247 | #define AVIC_NIPRIORITY0 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C)) |
| 1266 | #define NIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40)) | 1248 | #define AVIC_NIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40)) |
| 1267 | #define FIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44)) | 1249 | #define AVIC_FIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44)) |
| 1268 | #define INTSRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48)) | 1250 | #define AVIC_INTSRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48)) |
| 1269 | #define INTSRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C)) | 1251 | #define AVIC_INTSRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C)) |
| 1270 | #define INTFRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50)) | 1252 | #define AVIC_INTFRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50)) |
| 1271 | #define INTFRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54)) | 1253 | #define AVIC_INTFRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54)) |
| 1272 | #define NIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58)) | 1254 | #define AVIC_NIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58)) |
| 1273 | #define NIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C)) | 1255 | #define AVIC_NIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C)) |
| 1274 | #define FIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60)) | 1256 | #define AVIC_FIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60)) |
| 1275 | #define FIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64)) | 1257 | #define AVIC_FIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64)) |
| 1276 | #define VECTOR_BASE_ADDR (AVIC_BASE_ADDR+0x100) | 1258 | #define AVIC_VECTOR_BASE_ADDR (AVIC_BASE_ADDR+0x100) |
| 1277 | #define VECTOR(n) (((REG32_PTR_T)VECTOR_BASE_ADDR)[n]) | 1259 | #define AVIC_VECTOR(n) (((REG32_PTR_T)VECTOR_BASE_ADDR)[n]) |
| 1278 | 1260 | ||
| 1279 | /* The vectors go all the way up to 63. 4 bytes for each */ | 1261 | /* The vectors go all the way up to 63. 4 bytes for each */ |
| 1280 | #define INTCNTL_ABFLAG (1 << 25) | 1262 | #define AVIC_INTCNTL_ABFLAG (1 << 25) |
| 1281 | #define INTCNTL_ABFEN (1 << 24) | 1263 | #define AVIC_INTCNTL_ABFEN (1 << 24) |
| 1282 | #define INTCNTL_NIDIS (1 << 22) | 1264 | #define AVIC_INTCNTL_NIDIS (1 << 22) |
| 1283 | #define INTCNTL_FIDIS (1 << 21) | 1265 | #define AVIC_INTCNTL_FIDIS (1 << 21) |
| 1284 | #define INTCNTL_NIAD (1 << 20) | 1266 | #define AVIC_INTCNTL_NIAD (1 << 20) |
| 1285 | #define INTCNTL_FIAD (1 << 19) | 1267 | #define AVIC_INTCNTL_FIAD (1 << 19) |
| 1286 | #define INTCNTL_NM (1 << 18) | 1268 | #define AVIC_INTCNTL_NM (1 << 18) |
| 1287 | 1269 | ||
| 1288 | /* L210 */ | 1270 | /* L210 */ |
| 1289 | #define L2CC_BASE_ADDR 0x30000000 | 1271 | #define L2CC_BASE_ADDR 0x30000000 |
| @@ -1299,224 +1281,167 @@ | |||
| 1299 | #define L2CC_CACHE_SYNC (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG)) | 1281 | #define L2CC_CACHE_SYNC (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG)) |
| 1300 | 1282 | ||
| 1301 | /* CCM */ | 1283 | /* CCM */ |
| 1302 | #define CLKCTL_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00)) | 1284 | #define CCM_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00)) |
| 1303 | #define CLKCTL_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04)) | 1285 | #define CCM_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04)) |
| 1304 | #define CLKCTL_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08)) | 1286 | #define CCM_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08)) |
| 1305 | #define CLKCTL_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C)) | 1287 | #define CCM_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C)) |
| 1306 | #define CLKCTL_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10)) | 1288 | #define CCM_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10)) |
| 1307 | #define CLKCTL_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14)) | 1289 | #define CCM_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14)) |
| 1308 | #define CLKCTL_SPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18)) | 1290 | #define CCM_SPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18)) |
| 1309 | #define CLKCTL_COSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C)) | 1291 | #define CCM_COSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C)) |
| 1310 | #define CLKCTL_CGR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20)) | 1292 | #define CCM_CGR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20)) |
| 1311 | #define CLKCTL_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24)) | 1293 | #define CCM_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24)) |
| 1312 | #define CLKCTL_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28)) | 1294 | #define CCM_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28)) |
| 1313 | #define CLKCTL_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C)) | 1295 | #define CCM_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C)) |
| 1314 | #define CLKCTL_LDC (*(REG32_PTR_T)(CCM_BASE_ADDR+0x30)) | 1296 | #define CCM_LDC (*(REG32_PTR_T)(CCM_BASE_ADDR+0x30)) |
| 1315 | #define CLKCTL_DCVR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x34)) | 1297 | #define CCM_DCVR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x34)) |
| 1316 | #define CLKCTL_DCVR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x38)) | 1298 | #define CCM_DCVR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x38)) |
| 1317 | #define CLKCTL_DCVR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x3C)) | 1299 | #define CCM_DCVR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x3C)) |
| 1318 | #define CLKCTL_DCVR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x40)) | 1300 | #define CCM_DCVR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x40)) |
| 1319 | #define CLKCTL_LTR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x44)) | 1301 | #define CCM_LTR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x44)) |
| 1320 | #define CLKCTL_LTR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x48)) | 1302 | #define CCM_LTR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x48)) |
| 1321 | #define CLKCTL_LTR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x4C)) | 1303 | #define CCM_LTR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x4C)) |
| 1322 | #define CLKCTL_LTR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x50)) | 1304 | #define CCM_LTR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x50)) |
| 1323 | #define CLKCTL_LTBR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x54)) | 1305 | #define CCM_LTBR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x54)) |
| 1324 | #define CLKCTL_LTBR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x58)) | 1306 | #define CCM_LTBR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x58)) |
| 1325 | #define CLKCTL_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C)) | 1307 | #define CCM_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C)) |
| 1326 | #define CLKCTL_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60)) | 1308 | #define CCM_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60)) |
| 1327 | #define CLKCTL_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64)) | 1309 | #define CCM_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64)) |
| 1328 | 1310 | ||
| 1329 | /* CCMR */ | 1311 | /* CCMR */ |
| 1330 | #define CCMR_L2PG (0x1 << 29) | 1312 | #define CCM_CCMR_L2PG (0x1 << 29) |
| 1331 | #define CCMR_VSTBY (0x1 << 28) | 1313 | #define CCM_CCMR_VSTBY (0x1 << 28) |
| 1332 | #define CCMR_WBEN (0x1 << 27) | 1314 | #define CCM_CCMR_WBEN (0x1 << 27) |
| 1333 | #define CCMR_FPMF (0x1 << 26) | 1315 | #define CCM_CCMR_FPMF (0x1 << 26) |
| 1334 | #define CCMR_CSCS (0x1 << 25) | 1316 | #define CCM_CCMR_CSCS (0x1 << 25) |
| 1335 | #define CCMR_PERCS (0x1 << 24) | 1317 | #define CCM_CCMR_PERCS (0x1 << 24) |
| 1336 | 1318 | ||
| 1337 | #define CCMR_SSI2S (0x3 << 21) | 1319 | #define CCM_CCMR_SSI2S (0x3 << 21) |
| 1338 | #define CCMR_SSI2S_MCU_CLK (0x0 << 21) | 1320 | #define CCM_CCMR_SSI2S_MCU_CLK (0x0 << 21) |
| 1339 | #define CCMR_SSI2S_USB_CLK (0x1 << 21) | 1321 | #define CCM_CCMR_SSI2S_USB_CLK (0x1 << 21) |
| 1340 | #define CCMR_SSI2S_SERIAL_CLK (0x2 << 21) /* default */ | 1322 | #define CCM_CCMR_SSI2S_SERIAL_CLK (0x2 << 21) /* default */ |
| 1341 | 1323 | ||
| 1342 | #define CCMR_SSI1S (0x3 << 18) | 1324 | #define CCM_CCMR_SSI1S (0x3 << 18) |
| 1343 | #define CCMR_SSI1S_MCU_CLK (0x0 << 18) | 1325 | #define CCM_CCMR_SSI1S_MCU_CLK (0x0 << 18) |
| 1344 | #define CCMR_SSI1S_USB_CLK (0x1 << 18) | 1326 | #define CCM_CCMR_SSI1S_USB_CLK (0x1 << 18) |
| 1345 | #define CCMR_SSI1S_SERIAL_CLK (0x2 << 18) /* default */ | 1327 | #define CCM_CCMR_SSI1S_SERIAL_CLK (0x2 << 18) /* default */ |
| 1346 | 1328 | ||
| 1347 | #define CCMR_RAMW (0x3 << 16) | 1329 | #define CCM_CCMR_RAMW (0x3 << 16) |
| 1348 | #define CCMR_RAMW_0ARM_0ALTMS (0x0 << 16) | 1330 | #define CCM_CCMR_RAMW_0ARM_0ALTMS (0x0 << 16) |
| 1349 | #define CCMR_RAMW_0ARM_1ALTMS (0x1 << 16) /* Not recommended */ | 1331 | #define CCM_CCMR_RAMW_0ARM_1ALTMS (0x1 << 16) /* Not recommended */ |
| 1350 | #define CCMR_RAMW_1ARM_0ALTMS (0x2 << 16) /* Not recommended */ | 1332 | #define CCM_CCMR_RAMW_1ARM_0ALTMS (0x2 << 16) /* Not recommended */ |
| 1351 | #define CCMR_RAMW_1ARM_1ALTMS (0x3 << 16) | 1333 | #define CCM_CCMR_RAMW_1ARM_1ALTMS (0x3 << 16) |
| 1352 | 1334 | ||
| 1353 | #define CCMR_LPM (0x3 << 14) | 1335 | #define CCM_CCMR_LPM (0x3 << 14) |
| 1354 | #define CCMR_LPM_WAIT_MODE (0x0 << 14) | 1336 | #define CCM_CCMR_LPM_WAIT_MODE (0x0 << 14) |
| 1355 | #define CCMR_LPM_DOZE_MODE (0x1 << 14) | 1337 | #define CCM_CCMR_LPM_DOZE_MODE (0x1 << 14) |
| 1356 | #define CCMR_LPM_SRM (0x2 << 14) /* State retention mode */ | 1338 | #define CCM_CCMR_LPM_SRM (0x2 << 14) /* State retention mode */ |
| 1357 | #define CCMR_LPM_DSM (0x3 << 14) /* Deep sleep mode */ | 1339 | #define CCM_CCMR_LPM_DSM (0x3 << 14) /* Deep sleep mode */ |
| 1358 | 1340 | ||
| 1359 | #define CCMR_FIRS (0x3 << 11) | 1341 | #define CCM_CCMR_FIRS (0x3 << 11) |
| 1360 | #define CCMR_FIRS_MCU_CLK (0x0 << 11) | 1342 | #define CCM_CCMR_FIRS_MCU_CLK (0x0 << 11) |
| 1361 | #define CCMR_FIRS_USB_CLK (0x1 << 11) | 1343 | #define CCM_CCMR_FIRS_USB_CLK (0x1 << 11) |
| 1362 | #define CCMR_FIRS_SERIAL_CLK (0x2 << 11) | 1344 | #define CCM_CCMR_FIRS_SERIAL_CLK (0x2 << 11) |
| 1363 | 1345 | ||
| 1364 | #define CCMR_WAMO (0x1 << 10) | 1346 | #define CCM_CCMR_WAMO (0x1 << 10) |
| 1365 | #define CCMR_UPE (0x1 << 9) | 1347 | #define CCM_CCMR_UPE (0x1 << 9) |
| 1366 | #define CCMR_SPE (0x1 << 8) | 1348 | #define CCM_CCMR_SPE (0x1 << 8) |
| 1367 | #define CCMR_MDS (0x1 << 7) | 1349 | #define CCM_CCMR_MDS (0x1 << 7) |
| 1368 | 1350 | ||
| 1369 | #define CCMR_ROMW (0x3 << 5) | 1351 | #define CCM_CCMR_ROMW (0x3 << 5) |
| 1370 | #define CCMR_ROMW_0ARM_0ALTMS (0x0 << 5) | 1352 | #define CCM_CCMR_ROMW_0ARM_0ALTMS (0x0 << 5) |
| 1371 | #define CCMR_ROMW_0ARM_1ALTMS (0x1 << 5) /* Not recommended */ | 1353 | #define CCM_CCMR_ROMW_0ARM_1ALTMS (0x1 << 5) /* Not recommended */ |
| 1372 | #define CCMR_ROMW_1ARM_0ALTMS (0x2 << 5) /* Not recommended */ | 1354 | #define CCM_CCMR_ROMW_1ARM_0ALTMS (0x2 << 5) /* Not recommended */ |
| 1373 | #define CCMR_ROMW_1ARM_1ALTMS (0x3 << 5) | 1355 | #define CCM_CCMR_ROMW_1ARM_1ALTMS (0x3 << 5) |
| 1374 | 1356 | ||
| 1375 | #define CCMR_SBYCS (0x1 << 4) | 1357 | #define CCM_CCMR_SBYCS (0x1 << 4) |
| 1376 | #define CCMR_MPE (0x1 << 3) | 1358 | #define CCM_CCMR_MPE (0x1 << 3) |
| 1377 | 1359 | ||
| 1378 | #define CCMR_PRCS (0x3 << 1) | 1360 | #define CCM_CCMR_PRCS (0x3 << 1) |
| 1379 | #define CCMR_PRCS_FPM (0x1 << 1) | 1361 | #define CCM_CCMR_PRCS_FPM (0x1 << 1) |
| 1380 | #define CCMR_PRCS_CKIH (0x2 << 1) | 1362 | #define CCM_CCMR_PRCS_CKIH (0x2 << 1) |
| 1381 | 1363 | ||
| 1382 | #define CCMR_FPME (0x1 << 0) | 1364 | #define CCM_CCMR_FPME (0x1 << 0) |
| 1383 | 1365 | ||
| 1384 | /* PDR0 */ | 1366 | /* PDR0 */ |
| 1385 | #define PDR0_CSI_PODF (0x1ff << 23) | 1367 | #define CCM_PDR0_CSI_PODF (0x1ff << 23) |
| 1386 | #define PDR0_CSI_PODFw(x) (((x) << 23) & PDR0_CSI_PODF) | 1368 | #define CCM_PDR0_CSI_PODF_POS (23) |
| 1387 | #define PDR0_CSI_PODFr(x) (((x) & PDR0_CSI_PODF) >> 23) | ||
| 1388 | 1369 | ||
| 1389 | #define PDR0_PER_PODF (0x1f << 16) | 1370 | #define CCM_PDR0_PER_PODF (0x1f << 16) |
| 1390 | #define PDR0_PER_PODFw(x) (((x) << 16) & PDR0_PER_PODF) | 1371 | #define CCM_PDR0_PER_PODF_POS (16) |
| 1391 | #define PDR0_PER_PODFr(x) (((x) & PDR0_PER_PODF) >> 16) | ||
| 1392 | 1372 | ||
| 1393 | #define PDR0_HSP_PODF (0x7 << 11) | 1373 | #define CCM_PDR0_HSP_PODF (0x7 << 11) |
| 1394 | #define PDR0_HSP_PODFw(x) (((x) << 11) & PDR0_HSP_PODF) | 1374 | #define CCM_PDR0_HSP_PODF_POS (11) |
| 1395 | #define PDR0_HSP_PODFr(x) (((x) & PDR0_HSP_PODF) >> 11) | ||
| 1396 | 1375 | ||
| 1397 | #define PDR0_NFC_PODF (0x7 << 8) | 1376 | #define CCM_PDR0_NFC_PODF (0x7 << 8) |
| 1398 | #define PDR0_NFC_PODFw(x) (((x) << 8) & PDR0_NFC_PODF) | 1377 | #define CCM_PDR0_NFC_PODF_POS (8) |
| 1399 | #define PDR0_NFC_PODFr(x) (((x) & PDR0_NFC_PODF) >> 8) | ||
| 1400 | 1378 | ||
| 1401 | #define PDR0_IPG_PODF (0x3 << 6) | 1379 | #define CCM_PDR0_IPG_PODF (0x3 << 6) |
| 1402 | #define PDR0_IPG_PODFw(x) (((x) << 6) & PDR0_IPG_PODF) | 1380 | #define CCM_PDR0_IPG_PODF_POS (6) |
| 1403 | #define PDR0_IPG_PODFr(x) (((x) & PDR0_IPG_PODF) >> 6) | ||
| 1404 | 1381 | ||
| 1405 | #define PDR0_MAX_PODF (0x7 << 3) | 1382 | #define CCM_PDR0_MAX_PODF (0x7 << 3) |
| 1406 | #define PDR0_MAX_PODFw(x) (((x) << 3) & PDR0_MAX_PODF) | 1383 | #define CCM_PDR0_MAX_PODF_POS (3) |
| 1407 | #define PDR0_MAX_PODFr(x) (((x) & PDR0_MAX_PODF) >> 3) | ||
| 1408 | 1384 | ||
| 1409 | #define PDR0_MCU_PODF (0x7 << 0) | 1385 | #define CCM_PDR0_MCU_PODF (0x7 << 0) |
| 1410 | #define PDR0_MCU_PODFw(x) (((x) << 0) & PDR0_MCU_PODF) | 1386 | #define CCM_PDR0_MCU_PODF_POS (0) |
| 1411 | #define PDR0_MCU_PODFr(x) (((x) & PDR0_MCU_PODF) >> 0) | ||
| 1412 | 1387 | ||
| 1413 | /* PDR1 */ | 1388 | /* PDR1 */ |
| 1414 | #define PDR1_USB_PRDF (0x3 << 30) | 1389 | #define CCM_PDR1_USB_PRDF (0x3 << 30) |
| 1415 | #define PDR1_USB_PRDFw(x) (((x) << 30) & PDR1_USB_PRDF) | 1390 | #define CCM_PDR1_USB_PRDF_POS (30) |
| 1416 | #define PDR1_USB_PRDFr(x) (((x) & PDR1_USB_PRDF) >> 30) | 1391 | |
| 1417 | 1392 | #define CCM_PDR1_USB_PODF (0x7 << 27) | |
| 1418 | #define PDR1_USB_PODF (0x7 << 27) | 1393 | #define CCM_PDR1_USB_PODF_POS (27) |
| 1419 | #define PDR1_USB_PODFw(x) (((x) << 27) & PDR1_USB_PODF) | 1394 | |
| 1420 | #define PDR1_USB_PODFr(x) (((x) & PDR1_USB_PODF) >> 27) | 1395 | #define CCM_PDR1_FIRI_PRE_PODF (0x7 << 24) |
| 1421 | 1396 | #define CCM_PDR1_FIRI_PRE_PODF_POS (24) | |
| 1422 | #define PDR1_FIRI_PRE_PODF (0x7 << 24) | 1397 | |
| 1423 | #define PDR1_FIRI_PRE_PODFw(x) (((x) << 24) & PDR1_FIRI_PRE_PODF) | 1398 | #define CCM_PDR1_FIRI_PODF (0x3f << 18) |
| 1424 | #define PDR1_FIRI_PRE_PODFr(x) (((x) & PDR1_FIRI_PRE_PODF) >> 24) | 1399 | #define CCM_PDR1_FIRI_PODF_POS (18) |
| 1425 | 1400 | ||
| 1426 | #define PDR1_FIRI_PODF (0x3f << 18) | 1401 | #define CCM_PDR1_SSI2_PRE_PODF (0x7 << 15) |
| 1427 | #define PDR1_FIRI_PODFw(x) (((x) << 18) & PDR1_FIRI_PODF) | 1402 | #define CCM_PDR1_SSI2_PRE_PODF_POS (15) |
| 1428 | #define PDR1_FIRI_PODFr(x) (((x) & PDR1_FIRI_PODF) >> 18) | 1403 | |
| 1429 | 1404 | #define CCM_PDR1_SSI2_PODF (0x3f << 9) | |
| 1430 | #define PDR1_SSI2_PRE_PODF (0x7 << 15) | 1405 | #define CCM_PDR1_SSI2_PODF_POS (9) |
| 1431 | #define PDR1_SSI2_PRE_PODFw(x) (((x) << 15) & PDR1_SSI2_PRE_PODF) | 1406 | |
| 1432 | #define PDR1_SSI2_PRE_PODFr(x) (((x) & PDR1_SSI2_PRE_PODF) >> 15) | 1407 | #define CCM_PDR1_SSI1_PRE_PODF (0x7 << 6) |
| 1433 | 1408 | #define CCM_PDR1_SSI1_PRE_PODF_POS (6) | |
| 1434 | #define PDR1_SSI2_PODF (0x3f << 9) | 1409 | |
| 1435 | #define PDR1_SSI2_PODFw(x) (((x) << 9) & PDR1_SSI2_PODF) | 1410 | #define CCM_PDR1_SSI1_PODF (0x3f << 0) |
| 1436 | #define PDR1_SSI2_PODFr(x) (((x) & PDR1_SSI2_PODF) >> 9) | 1411 | #define CCM_PDR1_SSI1_PODF_POS (0) |
| 1437 | 1412 | ||
| 1438 | #define PDR1_SSI1_PRE_PODF (0x7 << 6) | 1413 | #define CCM_WIMR0_GPIO3 (1 << 0) |
| 1439 | #define PDR1_SSI1_PRE_PODFw(x) (((x) << 6) & PDR1_SSI1_PRE_PODF) | 1414 | #define CCM_WIMR0_GPIO2 (1 << 1) |
| 1440 | #define PDR1_SSI1_PRE_PODFr(x) (((x) & PDR1_SSI1_PRE_PODF) >> 6) | 1415 | #define CCM_WIMR0_GPIO1 (1 << 2) |
| 1441 | 1416 | #define CCM_WIMR0_PCMCIA (1 << 3) | |
| 1442 | #define PDR1_SSI1_PODF (0x3f << 0) | 1417 | #define CCM_WIMR0_WDT (1 << 4) |
| 1443 | #define PDR1_SSI1_PODFw(x) (((x) << 0) & PDR1_SSI1_PODF) | 1418 | #define CCM_WIMR0_USB_OTG (1 << 5) |
| 1444 | #define PDR1_SSI1_PODFr(x) (((x) & PDR1_SSI1_PODF) >> 0) | 1419 | #define CCM_WIMR0_IPI_INT_UH2 (1 << 6) |
| 1445 | 1420 | #define CCM_WIMR0_IPI_INT_UH1 (1 << 7) | |
| 1446 | #define CGR0_SD_MMC1(cg) ((cg) << 0*2) | 1421 | #define CCM_WIMR0_IPI_INT_UART5_ANDED (1 << 8) |
| 1447 | #define CGR0_SD_MMC2(cg) ((cg) << 1*2) | 1422 | #define CCM_WIMR0_IPI_INT_UART4_ANDED (1 << 9) |
| 1448 | #define CGR0_GPT(cg) ((cg) << 2*2) | 1423 | #define CCM_WIMR0_IPI_INT_UART3_ANDED (1 << 10) |
| 1449 | #define CGR0_EPIT1(cg) ((cg) << 3*2) | 1424 | #define CCM_WIMR0_IPI_INT_UART2_ANDED (1 << 11) |
| 1450 | #define CGR0_EPIT2(cg) ((cg) << 4*2) | 1425 | #define CCM_WIMR0_IPI_INT_UART1_ANDED (1 << 12) |
| 1451 | #define CGR0_IIM(cg) ((cg) << 5*2) | 1426 | #define CCM_WIMR0_IPI_INT_SIM_DATA_IRQ (1 << 13) |
| 1452 | #define CGR0_ATA(cg) ((cg) << 6*2) | 1427 | #define CCM_WIMR0_IPI_INT_SDHC2 (1 << 14) |
| 1453 | #define CGR0_SDMA(cg) ((cg) << 7*2) | 1428 | #define CCM_WIMR0_IPI_INT_SDHC1 (1 << 15) |
| 1454 | #define CGR0_CSPI3(cg) ((cg) << 8*2) | 1429 | #define CCM_WIMR0_IPI_INT_RTC (1 << 16) |
| 1455 | #define CGR0_RNG(cg) ((cg) << 9*2) | 1430 | #define CCM_WIMR0_IPI_INT_PWM (1 << 17) |
| 1456 | #define CGR0_UART1(cg) ((cg) << 10*2) | 1431 | #define CCM_WIMR0_IPI_INT_KPP (1 << 18) |
| 1457 | #define CGR0_UART2(cg) ((cg) << 11*2) | 1432 | #define CCM_WIMR0_IPI_INT_IIM (1 << 19) |
| 1458 | #define CGR0_SSI1(cg) ((cg) << 12*2) | 1433 | #define CCM_WIMR0_IPI_INT_GPT (1 << 20) |
| 1459 | #define CGR0_I2C1(cg) ((cg) << 13*2) | 1434 | #define CCM_WIMR0_IPI_INT_FIR (1 << 21) |
| 1460 | #define CGR0_I2C2(cg) ((cg) << 14*2) | 1435 | #define CCM_WIMR0_IPI_INT_EPIT2 (1 << 22) |
| 1461 | #define CGR0_I2C3(cg) ((cg) << 15*2) | 1436 | #define CCM_WIMR0_IPI_INT_EPIT1 (1 << 23) |
| 1462 | 1437 | #define CCM_WIMR0_IPI_INT_CSPI2 (1 << 24) | |
| 1463 | #define CGR1_HANTRO(cg) ((cg) << 0*2) | 1438 | #define CCM_WIMR0_IPI_INT_CSPI1 (1 << 25) |
| 1464 | #define CGR1_MEMSTICK1(cg) ((cg) << 1*2) | 1439 | #define CCM_WIMR0_IPI_INT_POWER_FAIL (1 << 26) |
| 1465 | #define CGR1_MEMSTICK2(cg) ((cg) << 2*2) | 1440 | #define CCM_WIMR0_IPI_INT_CSPI3 (1 << 27) |
| 1466 | #define CGR1_CSI(cg) ((cg) << 3*2) | 1441 | #define CCM_WIMR0_RESERVED28 (1 << 28) |
| 1467 | #define CGR1_RTC(cg) ((cg) << 4*2) | 1442 | #define CCM_WIMR0_RESERVED29 (1 << 29) |
| 1468 | #define CGR1_WDOG(cg) ((cg) << 5*2) | 1443 | #define CCM_WIMR0_RESERVED30 (1 << 30) |
| 1469 | #define CGR1_PWM(cg) ((cg) << 6*2) | 1444 | #define CCM_WIMR0_RESERVED31 (1 << 31) |
| 1470 | #define CGR1_SIM(cg) ((cg) << 7*2) | ||
| 1471 | #define CGR1_ECT(cg) ((cg) << 8*2) | ||
| 1472 | #define CGR1_USBOTG(cg) ((cg) << 9*2) | ||
| 1473 | #define CGR1_KPP(cg) ((cg) << 10*2) | ||
| 1474 | #define CGR1_IPU(cg) ((cg) << 11*2) | ||
| 1475 | #define CGR1_UART3(cg) ((cg) << 12*2) | ||
| 1476 | #define CGR1_UART4(cg) ((cg) << 13*2) | ||
| 1477 | #define CGR1_UART5(cg) ((cg) << 14*2) | ||
| 1478 | #define CGR1_1_WIRE(cg) ((cg) << 15*2) | ||
| 1479 | |||
| 1480 | #define CGR2_SSI2(cg) ((cg) << 0*2) | ||
| 1481 | #define CGR2_CSPI1(cg) ((cg) << 1*2) | ||
| 1482 | #define CGR2_CSPI2(cg) ((cg) << 2*2) | ||
| 1483 | #define CGR2_GACC(cg) ((cg) << 3*2) | ||
| 1484 | #define CGR2_EMI(cg) ((cg) << 4*2) | ||
| 1485 | #define CGR2_RTIC(cg) ((cg) << 5*2) | ||
| 1486 | #define CGR2_FIR(cg) ((cg) << 6*2) | ||
| 1487 | |||
| 1488 | #define WIM_GPIO3 (1 << 0) | ||
| 1489 | #define WIM_GPIO2 (1 << 1) | ||
| 1490 | #define WIM_GPIO1 (1 << 2) | ||
| 1491 | #define WIM_PCMCIA (1 << 3) | ||
| 1492 | #define WIM_WDT (1 << 4) | ||
| 1493 | #define WIM_USB_OTG (1 << 5) | ||
| 1494 | #define WIM_IPI_INT_UH2 (1 << 6) | ||
| 1495 | #define WIM_IPI_INT_UH1 (1 << 7) | ||
| 1496 | #define WIM_IPI_INT_UART5_ANDED (1 << 8) | ||
| 1497 | #define WIM_IPI_INT_UART4_ANDED (1 << 9) | ||
| 1498 | #define WIM_IPI_INT_UART3_ANDED (1 << 10) | ||
| 1499 | #define WIM_IPI_INT_UART2_ANDED (1 << 11) | ||
| 1500 | #define WIM_IPI_INT_UART1_ANDED (1 << 12) | ||
| 1501 | #define WIM_IPI_INT_SIM_DATA_IRQ (1 << 13) | ||
| 1502 | #define WIM_IPI_INT_SDHC2 (1 << 14) | ||
| 1503 | #define WIM_IPI_INT_SDHC1 (1 << 15) | ||
| 1504 | #define WIM_IPI_INT_RTC (1 << 16) | ||
| 1505 | #define WIM_IPI_INT_PWM (1 << 17) | ||
| 1506 | #define WIM_IPI_INT_KPP (1 << 18) | ||
| 1507 | #define WIM_IPI_INT_IIM (1 << 19) | ||
| 1508 | #define WIM_IPI_INT_GPT (1 << 20) | ||
| 1509 | #define WIM_IPI_INT_FIR (1 << 21) | ||
| 1510 | #define WIM_IPI_INT_EPIT2 (1 << 22) | ||
| 1511 | #define WIM_IPI_INT_EPIT1 (1 << 23) | ||
| 1512 | #define WIM_IPI_INT_CSPI2 (1 << 24) | ||
| 1513 | #define WIM_IPI_INT_CSPI1 (1 << 25) | ||
| 1514 | #define WIM_IPI_INT_POWER_FAIL (1 << 26) | ||
| 1515 | #define WIM_IPI_INT_CSPI3 (1 << 27) | ||
| 1516 | #define WIM_RESERVED28 (1 << 28) | ||
| 1517 | #define WIM_RESERVED29 (1 << 29) | ||
| 1518 | #define WIM_RESERVED30 (1 << 30) | ||
| 1519 | #define WIM_RESERVED31 (1 << 31) | ||
| 1520 | 1445 | ||
| 1521 | /* WEIM - CS0 */ | 1446 | /* WEIM - CS0 */ |
| 1522 | #define CSCRU 0x00 | 1447 | #define CSCRU 0x00 |