Third try fixing MIPS cache code

Changing this to be a pure discard operation after discussion on IRC

Change-Id: I62955ae7975fdbbfd9eef376476042a36fe3d95a

1 files changed, 1 insertions, 14 deletions

diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c
index 46094bf6b6..35c47207dd 100644
--- a/firmware/target/mips/mmu-mips.c
+++ b/firmware/target/mips/mmu-mips.c
@@ -222,20 +222,7 @@ void discard_dcache_range(const void *base, unsigned int size)
     char *ptr = CACHEALIGN_DOWN((char*)base);
     char *end = CACHEALIGN_UP((char*)base + size);
 
-    if(ptr != base) {
-        /* Start of region not cache aligned */
-        __CACHE_OP(DCHitWBInv, ptr);
-        ptr += CACHEALIGN_SIZE;
-    }
-
-    if(base+size != end) {
-        /* End of region not cache aligned */
-        end -= CACHEALIGN_SIZE;
-        __CACHE_OP(DCHitWBInv, end);
-    }
-
-    /* Interior of region is safe to discard */
-    for(; ptr <= end; ptr += CACHEALIGN_SIZE)
+    for(; ptr != end; ptr += CACHEALIGN_SIZE)
         __CACHE_OP(DCHitInv, ptr);
 
     SYNC_WB();