From de53965e3f83d5741f96a389b039b046f2f01aac Mon Sep 17 00:00:00 2001 From: Aidan MacDonald Date: Thu, 4 Mar 2021 00:53:16 +0000 Subject: Third try fixing MIPS cache code Changing this to be a pure discard operation after discussion on IRC Change-Id: I62955ae7975fdbbfd9eef376476042a36fe3d95a --- firmware/target/mips/mmu-mips.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) (limited to 'firmware/target/mips') diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c index 46094bf6b6..35c47207dd 100644 --- a/firmware/target/mips/mmu-mips.c +++ b/firmware/target/mips/mmu-mips.c @@ -222,20 +222,7 @@ void discard_dcache_range(const void *base, unsigned int size) char *ptr = CACHEALIGN_DOWN((char*)base); char *end = CACHEALIGN_UP((char*)base + size); - if(ptr != base) { - /* Start of region not cache aligned */ - __CACHE_OP(DCHitWBInv, ptr); - ptr += CACHEALIGN_SIZE; - } - - if(base+size != end) { - /* End of region not cache aligned */ - end -= CACHEALIGN_SIZE; - __CACHE_OP(DCHitWBInv, end); - } - - /* Interior of region is safe to discard */ - for(; ptr <= end; ptr += CACHEALIGN_SIZE) + for(; ptr != end; ptr += CACHEALIGN_SIZE) __CACHE_OP(DCHitInv, ptr); SYNC_WB(); -- cgit v1.2.3