diff options
author | Aidan MacDonald <amachronic@protonmail.com> | 2021-03-04 00:53:16 +0000 |
---|---|---|
committer | Solomon Peachy <pizza@shaftnet.org> | 2021-03-04 02:47:13 +0000 |
commit | de53965e3f83d5741f96a389b039b046f2f01aac (patch) | |
tree | e9f30ce0fd96aa4f89145b941b8c54399f543978 | |
parent | b82298ae2c3ba62dbb4347054fe478992df4021c (diff) | |
download | rockbox-de53965e3f83d5741f96a389b039b046f2f01aac.tar.gz rockbox-de53965e3f83d5741f96a389b039b046f2f01aac.zip |
Third try fixing MIPS cache code
Changing this to be a pure discard operation after discussion on IRC
Change-Id: I62955ae7975fdbbfd9eef376476042a36fe3d95a
-rw-r--r-- | firmware/target/mips/mmu-mips.c | 15 |
1 files changed, 1 insertions, 14 deletions
diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c index 46094bf6b6..35c47207dd 100644 --- a/firmware/target/mips/mmu-mips.c +++ b/firmware/target/mips/mmu-mips.c | |||
@@ -222,20 +222,7 @@ void discard_dcache_range(const void *base, unsigned int size) | |||
222 | char *ptr = CACHEALIGN_DOWN((char*)base); | 222 | char *ptr = CACHEALIGN_DOWN((char*)base); |
223 | char *end = CACHEALIGN_UP((char*)base + size); | 223 | char *end = CACHEALIGN_UP((char*)base + size); |
224 | 224 | ||
225 | if(ptr != base) { | 225 | for(; ptr != end; ptr += CACHEALIGN_SIZE) |
226 | /* Start of region not cache aligned */ | ||
227 | __CACHE_OP(DCHitWBInv, ptr); | ||
228 | ptr += CACHEALIGN_SIZE; | ||
229 | } | ||
230 | |||
231 | if(base+size != end) { | ||
232 | /* End of region not cache aligned */ | ||
233 | end -= CACHEALIGN_SIZE; | ||
234 | __CACHE_OP(DCHitWBInv, end); | ||
235 | } | ||
236 | |||
237 | /* Interior of region is safe to discard */ | ||
238 | for(; ptr <= end; ptr += CACHEALIGN_SIZE) | ||
239 | __CACHE_OP(DCHitInv, ptr); | 226 | __CACHE_OP(DCHitInv, ptr); |
240 | 227 | ||
241 | SYNC_WB(); | 228 | SYNC_WB(); |