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author | Solomon Peachy <pizza@shaftnet.org> | 2020-09-04 23:50:38 -0400 |
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committer | Solomon Peachy <pizza@shaftnet.org> | 2020-09-05 22:18:26 +0000 |
commit | d015165bc546e80b1c033c23c68a0ba307b7a39f (patch) | |
tree | 3618d4af6740d353d22f2e48a3729775968176c9 /firmware/target/mips/mmu-mips.c | |
parent | 8188588f14849fbc80254caf073fc7c790596c0a (diff) | |
download | rockbox-d015165bc546e80b1c033c23c68a0ba307b7a39f.tar.gz rockbox-d015165bc546e80b1c033c23c68a0ba307b7a39f.zip |
mips: Convert 'nop' to 'ssnop' -- for future-proofing
Change-Id: I17625f4d56a1f5205887cb47668a2dcb628053f4
Diffstat (limited to 'firmware/target/mips/mmu-mips.c')
-rw-r--r-- | firmware/target/mips/mmu-mips.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c index 14a013211d..eb7004952e 100644 --- a/firmware/target/mips/mmu-mips.c +++ b/firmware/target/mips/mmu-mips.c | |||
@@ -36,12 +36,12 @@ | |||
36 | __asm__ __volatile__( \ | 36 | __asm__ __volatile__( \ |
37 | " .set push \n" \ | 37 | " .set push \n" \ |
38 | " .set noreorder \n" \ | 38 | " .set noreorder \n" \ |
39 | " nop \n" \ | 39 | " ssnop \n" \ |
40 | " nop \n" \ | 40 | " ssnop \n" \ |
41 | " nop \n" \ | 41 | " ssnop \n" \ |
42 | " nop \n" \ | 42 | " ssnop \n" \ |
43 | " nop \n" \ | 43 | " ssnop \n" \ |
44 | " nop \n" \ | 44 | " ssnop \n" \ |
45 | " .set pop \n"); | 45 | " .set pop \n"); |
46 | 46 | ||
47 | #define DEFAULT_PAGE_SHIFT PL_4K | 47 | #define DEFAULT_PAGE_SHIFT PL_4K |
@@ -137,16 +137,16 @@ void mmu_init(void) | |||
137 | #if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B | 137 | #if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B |
138 | #define INVALIDATE_BTB() \ | 138 | #define INVALIDATE_BTB() \ |
139 | do { \ | 139 | do { \ |
140 | unsigned long tmp; \ | 140 | register unsigned long tmp; \ |
141 | __asm__ __volatile__( \ | 141 | __asm__ __volatile__( \ |
142 | " .set push \n" \ | 142 | " .set push \n" \ |
143 | " .set noreorder \n" \ | 143 | " .set noreorder \n" \ |
144 | " .set mips32 \n" \ | 144 | " .set mips32 \n" \ |
145 | " mfc0 %0, $16, 7 \n" \ | 145 | " mfc0 %0, $16, 7 \n" \ |
146 | " nop \n" \ | 146 | " ssnop \n" \ |
147 | " ori %0, 2 \n" \ | 147 | " ori %0, 2 \n" \ |
148 | " mtc0 %0, $16, 7 \n" \ | 148 | " mtc0 %0, $16, 7 \n" \ |
149 | " nop \n" \ | 149 | " ssnop \n" \ |
150 | " .set pop \n" \ | 150 | " .set pop \n" \ |
151 | : "=&r"(tmp)); \ | 151 | : "=&r"(tmp)); \ |
152 | } while (0) | 152 | } while (0) |
@@ -178,7 +178,7 @@ void commit_dcache(void) __attribute__((alias("commit_discard_dcache"))); | |||
178 | /* Writeback whole D-cache and invalidate D-cache lines */ | 178 | /* Writeback whole D-cache and invalidate D-cache lines */ |
179 | void commit_discard_dcache(void) | 179 | void commit_discard_dcache(void) |
180 | { | 180 | { |
181 | unsigned int i; | 181 | register unsigned int i; |
182 | 182 | ||
183 | /* Use index type operation and iterate whole cache */ | 183 | /* Use index type operation and iterate whole cache */ |
184 | for (i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHEALIGN_SIZE) | 184 | for (i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHEALIGN_SIZE) |
@@ -192,7 +192,7 @@ void commit_discard_dcache(void) | |||
192 | */ | 192 | */ |
193 | void commit_discard_dcache_range(const void *base, unsigned int size) | 193 | void commit_discard_dcache_range(const void *base, unsigned int size) |
194 | { | 194 | { |
195 | char *s; | 195 | register char *s; |
196 | 196 | ||
197 | for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE) | 197 | for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE) |
198 | __CACHE_OP(DCHitWBInv, s); | 198 | __CACHE_OP(DCHitWBInv, s); |
@@ -204,7 +204,7 @@ void commit_discard_dcache_range(const void *base, unsigned int size) | |||
204 | */ | 204 | */ |
205 | void commit_dcache_range(const void *base, unsigned int size) | 205 | void commit_dcache_range(const void *base, unsigned int size) |
206 | { | 206 | { |
207 | char *s; | 207 | register char *s; |
208 | 208 | ||
209 | for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE) | 209 | for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE) |
210 | __CACHE_OP(DCHitWB, s); | 210 | __CACHE_OP(DCHitWB, s); |
@@ -217,7 +217,7 @@ void commit_dcache_range(const void *base, unsigned int size) | |||
217 | */ | 217 | */ |
218 | void discard_dcache_range(const void *base, unsigned int size) | 218 | void discard_dcache_range(const void *base, unsigned int size) |
219 | { | 219 | { |
220 | char *s; | 220 | register char *s; |
221 | 221 | ||
222 | if (((int)base & CACHEALIGN_SIZE - 1) || | 222 | if (((int)base & CACHEALIGN_SIZE - 1) || |
223 | (((int)base + size) & CACHEALIGN_SIZE - 1)) { | 223 | (((int)base + size) & CACHEALIGN_SIZE - 1)) { |
@@ -235,7 +235,7 @@ void discard_dcache_range(const void *base, unsigned int size) | |||
235 | /* Invalidate whole I-cache */ | 235 | /* Invalidate whole I-cache */ |
236 | static void discard_icache(void) | 236 | static void discard_icache(void) |
237 | { | 237 | { |
238 | unsigned int i; | 238 | register unsigned int i; |
239 | 239 | ||
240 | asm volatile (".set push \n" | 240 | asm volatile (".set push \n" |
241 | ".set noreorder \n" | 241 | ".set noreorder \n" |