mips: Convert 'nop' to 'ssnop' -- for future-proofing

Change-Id: I17625f4d56a1f5205887cb47668a2dcb628053f4

6 files changed, 77 insertions, 77 deletions

diff --git a/firmware/target/mips/ingenic_jz47xx/crt0.S b/firmware/target/mips/ingenic_jz47xx/crt0.S
index ce74b78e81..258a5c02fc 100644
--- a/firmware/target/mips/ingenic_jz47xx/crt0.S
+++ b/firmware/target/mips/ingenic_jz47xx/crt0.S
@@ -108,7 +108,7 @@ _cache_loop:
     cache   0x9, 0(t0)       # index store dcache tag
     addiu   t0, t0, 0x20     # 32 bytes per cache line
     bne     t0, t1, _cache_loop
-    nop
+    ssnop
 
     /*
       ----------------------------------------------------
@@ -116,10 +116,10 @@ _cache_loop:
       ----------------------------------------------------
     */
     mfc0    t0, C0_CONFIG
-    nop
+    ssnop
     ori     t0, 2
     mtc0    t0, C0_CONFIG
-    nop
+    ssnop
 
     /*
       ----------------------------------------------------
@@ -183,9 +183,9 @@ _irq_stack_loop:
       ----------------------------------------------------
     */
     jal     system_main  /* Init clocks etc first */
-    nop
+    ssnop
     j       main
-    nop
+    ssnop
 
 
     /*
@@ -197,19 +197,19 @@ _irq_stack_loop:
 
     .section .vectors.1, "ax", %progbits
     j      tlb_refill_handler
-    nop
+    ssnop
 
     .section .vectors.2, "ax", %progbits
     j      real_exception_handler
-    nop
+    ssnop
 
     .section .vectors.3, "ax", %progbits
     j      real_exception_handler
-    nop
+    ssnop
 
     .section .vectors.4, "ax", %progbits
     j      real_exception_handler
-    nop
+    ssnop
 
     .section .vectors, "ax", %progbits
 real_exception_handler:
@@ -253,47 +253,47 @@ real_exception_handler:
     sw      v0, 0x68(sp)
     sw      $1, 0x6C(sp)
     mflo    k0
-    nop
+    ssnop
     sw      k0, 0x70(sp)
     mfhi    k0
-    nop
+    ssnop
     sw      k0, 0x74(sp)
     mfc0    k0, C0_STATUS
-    nop
-    nop
-    nop
+    ssnop
+    ssnop
+    ssnop
     sw      k0, 0x78(sp)
     mfc0    k0, C0_EPC
-    nop
-    nop
-    nop
+    ssnop
+    ssnop
+    ssnop
     sw      k0, 0x7C(sp)
 
     li      k1, M_CauseExcCode
     mfc0    k0, C0_CAUSE
     and     k0, k1
     beq     zero, k0, _int
-    nop
+    ssnop
     j       _exception
-    nop
+    ssnop
 
 _int:
     jal     intr_handler
-    nop
+    ssnop
     j       _exception_return
 
 _exception:
     move    a0, sp
     mfc0    a1, C0_CAUSE
-    nop
-    nop
-    nop
+    ssnop
+    ssnop
+    ssnop
     mfc0    a2, C0_EPC
-    nop
-    nop
-    nop
+    ssnop
+    ssnop
+    ssnop
     jal     exception_handler
-    nop
+    ssnop
 
 _exception_return:
     lw      ra,    0(sp)
@@ -326,23 +326,23 @@ _exception_return:
     lw      $1, 0x6C(sp)
     lw      k0, 0x70(sp)
     mtlo    k0
-    nop
+    ssnop
     lw      k0, 0x74(sp)
     mthi    k0
-    nop
+    ssnop
     lw      k0, 0x78(sp)
     mtc0    k0, C0_STATUS
-    nop
-    nop
-    nop
+    ssnop
+    ssnop
+    ssnop
     lw      k0, 0x7C(sp)
     mtc0    k0, C0_EPC
-    nop
-    nop
-    nop
+    ssnop
+    ssnop
+    ssnop
     /* Restore previous stack pointer */
     lw      sp, 0x80(sp)
     eret
-    nop
+    ssnop
     .set reorder
     .set at
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
index 7fe3f819b3..22a6709166 100644
--- a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
@@ -18,7 +18,7 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
- 
+
 #include "config.h"
 #include "jz4740.h"
 #include "r61509.h"
@@ -36,7 +36,7 @@ do {                                    \
     REG_GPIO_PXPES(2)  = 0x001cffff;    \
 } while (0)
 
-#define SLEEP(x) { register int __i; for(__i=0; __i<x; __i++) asm volatile("nop\n nop\n"); }
+#define SLEEP(x) { register int __i; for(__i=0; __i<x; __i++) asm volatile("ssnop\n ssnop\n"); }
 #define DELAY    SLEEP(700000);
 
 #if ((defined(ONDA_VX777) || defined(ONDA_VX747P)) && !defined(BOOTLOADER)) \
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx767/lcd-onda_vx767.c b/firmware/target/mips/ingenic_jz47xx/onda_vx767/lcd-onda_vx767.c
index caee8982f6..a32fe45608 100644
--- a/firmware/target/mips/ingenic_jz47xx/onda_vx767/lcd-onda_vx767.c
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx767/lcd-onda_vx767.c
@@ -18,7 +18,7 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
- 
+
 #include "config.h"
 #include "jz4740.h"
 #include "lcd.h"
@@ -37,7 +37,7 @@ do {                                       \
 } while (0)
 
 
-#define SLEEP(x) for(i=0; i<x; i++) asm volatile("nop\n nop\n");
+#define SLEEP(x) for(i=0; i<x; i++) asm volatile("ssnop\n ssnop\n");
 #define DELAY    SLEEP(700000);
 static void _display_pin_init(void)
 {
@@ -48,10 +48,10 @@ static void _display_pin_init(void)
     __gpio_as_output(PIN_CS_N);
     __gpio_as_output(PIN_RESET_N);
     DELAY; /* delay_ms(10); */
-    
+
     __gpio_clear_pin(PIN_CS_N);
     DELAY; /* delay_ms(10); */
-    
+
     __gpio_set_pin(PIN_RESET_N);
     DELAY; /* delay_ms(10); */
     __gpio_clear_pin(PIN_RESET_N);
@@ -80,13 +80,13 @@ static void _display_pin_init(void)
 static void _display_init(void)
 {
     int i;
-    
+
     SLCD_SEND_COMMAND(0xE3, 0x8);
     SLCD_SEND_COMMAND(0xE4, 0x1411);
     SLCD_SEND_COMMAND(0xE5, 0x8000);
     SLCD_SEND_COMMAND(0x0, 0x1);
     DELAY; /* delay_ms(10); */
-    
+
     SLCD_SEND_COMMAND(0x1, 0x100);
     SLCD_SEND_COMMAND(0x2, 0x400);
     SLCD_SEND_COMMAND(0x3, 0x1028);
@@ -139,7 +139,7 @@ static void _display_init(void)
     SLCD_SEND_COMMAND(0x97, 0);
     SLCD_SEND_COMMAND(0x98, 0);
     SLCD_SEND_COMMAND(0x7, 0x173);
-    
+
     __gpio_clear_pin(PIN_UNK_N);
     SLCD_SET_COMMAND(0x22);
     WAIT_ON_SLCD;
@@ -158,7 +158,7 @@ static void _set_lcd_bus(void)
 {
     REG_LCD_CFG &= ~LCD_CFG_LCDPIN_MASK;
     REG_LCD_CFG |= LCD_CFG_LCDPIN_SLCD;
-    
+
     REG_SLCD_CFG = (SLCD_CFG_BURST_4_WORD | SLCD_CFG_DWIDTH_18 | SLCD_CFG_CWIDTH_18BIT
                    | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING
                    | SLCD_CFG_TYPE_PARALLEL);
@@ -167,15 +167,15 @@ static void _set_lcd_bus(void)
 static void _set_lcd_clock(void)
 {
     unsigned int val;
-    
+
     __cpm_stop_lcd();
-    
+
     val = __cpm_get_pllout2() / LCD_PCLK;
     val--;
     if ( val > 0x1ff )
         val = 0x1ff; /* CPM_LPCDR is too large, set it to 0x1ff */
     __cpm_set_pixdiv(val);
-    
+
     __cpm_start_lcd();
 }
 
@@ -196,7 +196,7 @@ void lcd_set_target(int x, int y, int width, int height)
     SLCD_SEND_COMMAND(0x52, x);
     SLCD_SEND_COMMAND(0x53, x+width-1);
     /* TODO */
-    
+
     __gpio_clear_pin(PIN_UNK_N);
     SLCD_SET_COMMAND(0x22);
     WAIT_ON_SLCD;
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
index d3a753a58e..fdc335ad21 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
@@ -18,7 +18,7 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
- 
+
 #include "config.h"
 #include "jz4740.h"
 #include "mips.h"
@@ -165,9 +165,9 @@ static int get_irq_number(void)
 {
     static unsigned long ipl;
     register int irq;
-    
+
     ipl |= REG_INTC_IPR;
-    
+
     if (UNLIKELY(ipl == 0))
         return -1;
 
@@ -180,7 +180,7 @@ static int get_irq_number(void)
                          : "r" (ipl)
                          : "t0"
                         );
-    
+
     if (UNLIKELY(irq < 0))
         return -1;
 
@@ -213,7 +213,7 @@ void intr_handler(void)
     register int irq = get_irq_number();
     if(UNLIKELY(irq < 0))
         return;
-    
+
     ack_irq(irq);
     if(LIKELY(irq > 0))
         irqvector[irq-1]();
@@ -320,14 +320,14 @@ void dma_enable(void)
     if(++dma_count == 1)
     {
         __cpm_start_dmac();
-        
+
         REG_DMAC_DCCSR(0) = 0;
         REG_DMAC_DCCSR(1) = 0;
         REG_DMAC_DCCSR(2) = 0;
         REG_DMAC_DCCSR(3) = 0;
         REG_DMAC_DCCSR(4) = 0;
         REG_DMAC_DCCSR(5) = 0;
-        
+
         REG_DMAC_DMACR = (DMAC_DMACR_PR_RR | DMAC_DMACR_DMAE);
     }
 }
@@ -377,7 +377,7 @@ static void pll_init(void)
         (0 << CPM_CPPCR_PLLN_BIT) |     /* RD=0, NR=2 */
         (0 << CPM_CPPCR_PLLOD_BIT) |    /* OD=0, NO=1 */
         (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
-        CPM_CPPCR_PLLEN;                /* enable PLL */          
+        CPM_CPPCR_PLLEN;                /* enable PLL */
 
     /* init PLL */
     REG_CPM_CPCCR = cfcr;
@@ -539,7 +539,7 @@ void system_reboot(void)
     REG_WDT_TDR = JZ_EXTAL/1000;   /* reset after 4ms */
     REG_TCU_TSCR = TCU_TSSR_WDTSC; /* enable wdt clock */
     REG_WDT_TCER = WDT_TCER_TCEN;  /* wdt start */
-    
+
     while (1);
 }
 
@@ -550,7 +550,7 @@ void system_exception_wait(void)
     {
         if( (~REG_GPIO_PXPIN(3)) & (1 << 29) )
             return;
-        asm volatile("nop");
+        asm volatile("ssnop");
     }
 }
 
@@ -558,7 +558,7 @@ void power_off(void)
 {
     /* Enable RTC clock */
     __cpm_start_rtc();
-    
+
     /* Put system into hibernate mode */
     __rtc_clear_alarm_flag();
     __rtc_clear_hib_stat_all();
@@ -567,7 +567,7 @@ void power_off(void)
     __rtc_set_hrcr_val(0xFE0);
     __rtc_set_hwfcr_val(0xFFFF << 4);
     __rtc_power_down();
-    
+
     while(1);
 }
 
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
index eee767c5ca..19fe0ba661 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
+++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
@@ -737,7 +737,7 @@ void system_exception_wait(void)
     {
         if( (~REG_GPIO_PXPIN(0)) & (1 << 30) )
             return;
-        asm volatile("nop");
+        asm volatile("ssnop");
     }
 }
 
diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c
index 14a013211d..eb7004952e 100644
--- a/firmware/target/mips/mmu-mips.c
+++ b/firmware/target/mips/mmu-mips.c
@@ -36,12 +36,12 @@
     __asm__ __volatile__(                  \
     "    .set    push               \n"    \
     "    .set    noreorder          \n"    \
-    "    nop                        \n"    \
-    "    nop                        \n"    \
-    "    nop                        \n"    \
-    "    nop                        \n"    \
-    "    nop                        \n"    \
-    "    nop                        \n"    \
+    "    ssnop                      \n"    \
+    "    ssnop                      \n"    \
+    "    ssnop                      \n"    \
+    "    ssnop                      \n"    \
+    "    ssnop                      \n"    \
+    "    ssnop                      \n"    \
     "    .set    pop                \n");
 
 #define DEFAULT_PAGE_SHIFT       PL_4K
@@ -137,16 +137,16 @@ void mmu_init(void)
 #if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B
 #define INVALIDATE_BTB()                     \
 do {                                         \
-        unsigned long tmp;                   \
+        register unsigned long tmp;          \
         __asm__ __volatile__(                \
         "    .set push            \n"        \
         "    .set noreorder       \n"        \
         "    .set mips32          \n"        \
         "    mfc0 %0, $16, 7      \n"        \
-        "    nop                  \n"        \
+        "    ssnop                \n"        \
         "    ori  %0, 2           \n"        \
         "    mtc0 %0, $16, 7      \n"        \
-        "    nop                  \n"        \
+        "    ssnop                \n"        \
         "    .set pop             \n"        \
         : "=&r"(tmp));                       \
     } while (0)
@@ -178,7 +178,7 @@ void commit_dcache(void) __attribute__((alias("commit_discard_dcache")));
 /* Writeback whole D-cache and invalidate D-cache lines */
 void commit_discard_dcache(void)
 {
-    unsigned int i;
+    register unsigned int i;
 
     /* Use index type operation and iterate whole cache */
     for (i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHEALIGN_SIZE)
@@ -192,7 +192,7 @@ void commit_discard_dcache(void)
  */
 void commit_discard_dcache_range(const void *base, unsigned int size)
 {
-    char *s;
+    register char *s;
 
     for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE)
         __CACHE_OP(DCHitWBInv, s);
@@ -204,7 +204,7 @@ void commit_discard_dcache_range(const void *base, unsigned int size)
  */
 void commit_dcache_range(const void *base, unsigned int size)
 {
-    char *s;
+    register char *s;
 
     for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE)
         __CACHE_OP(DCHitWB, s);
@@ -217,7 +217,7 @@ void commit_dcache_range(const void *base, unsigned int size)
  */
 void discard_dcache_range(const void *base, unsigned int size)
 {
-    char *s;
+    register char *s;
 
     if (((int)base & CACHEALIGN_SIZE - 1) ||
         (((int)base + size) & CACHEALIGN_SIZE - 1)) {
@@ -235,7 +235,7 @@ void discard_dcache_range(const void *base, unsigned int size)
 /* Invalidate whole I-cache */
 static void discard_icache(void)
 {
-    unsigned int i;
+    register unsigned int i;
 
     asm volatile (".set   push       \n"
                   ".set   noreorder  \n"