diff options
author | Solomon Peachy <pizza@shaftnet.org> | 2020-09-04 23:50:38 -0400 |
---|---|---|
committer | Solomon Peachy <pizza@shaftnet.org> | 2020-09-05 22:18:26 +0000 |
commit | d015165bc546e80b1c033c23c68a0ba307b7a39f (patch) | |
tree | 3618d4af6740d353d22f2e48a3729775968176c9 | |
parent | 8188588f14849fbc80254caf073fc7c790596c0a (diff) | |
download | rockbox-d015165bc546e80b1c033c23c68a0ba307b7a39f.tar.gz rockbox-d015165bc546e80b1c033c23c68a0ba307b7a39f.zip |
mips: Convert 'nop' to 'ssnop' -- for future-proofing
Change-Id: I17625f4d56a1f5205887cb47668a2dcb628053f4
6 files changed, 77 insertions, 77 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/crt0.S b/firmware/target/mips/ingenic_jz47xx/crt0.S index ce74b78e81..258a5c02fc 100644 --- a/firmware/target/mips/ingenic_jz47xx/crt0.S +++ b/firmware/target/mips/ingenic_jz47xx/crt0.S | |||
@@ -108,7 +108,7 @@ _cache_loop: | |||
108 | cache 0x9, 0(t0) # index store dcache tag | 108 | cache 0x9, 0(t0) # index store dcache tag |
109 | addiu t0, t0, 0x20 # 32 bytes per cache line | 109 | addiu t0, t0, 0x20 # 32 bytes per cache line |
110 | bne t0, t1, _cache_loop | 110 | bne t0, t1, _cache_loop |
111 | nop | 111 | ssnop |
112 | 112 | ||
113 | /* | 113 | /* |
114 | ---------------------------------------------------- | 114 | ---------------------------------------------------- |
@@ -116,10 +116,10 @@ _cache_loop: | |||
116 | ---------------------------------------------------- | 116 | ---------------------------------------------------- |
117 | */ | 117 | */ |
118 | mfc0 t0, C0_CONFIG | 118 | mfc0 t0, C0_CONFIG |
119 | nop | 119 | ssnop |
120 | ori t0, 2 | 120 | ori t0, 2 |
121 | mtc0 t0, C0_CONFIG | 121 | mtc0 t0, C0_CONFIG |
122 | nop | 122 | ssnop |
123 | 123 | ||
124 | /* | 124 | /* |
125 | ---------------------------------------------------- | 125 | ---------------------------------------------------- |
@@ -183,9 +183,9 @@ _irq_stack_loop: | |||
183 | ---------------------------------------------------- | 183 | ---------------------------------------------------- |
184 | */ | 184 | */ |
185 | jal system_main /* Init clocks etc first */ | 185 | jal system_main /* Init clocks etc first */ |
186 | nop | 186 | ssnop |
187 | j main | 187 | j main |
188 | nop | 188 | ssnop |
189 | 189 | ||
190 | 190 | ||
191 | /* | 191 | /* |
@@ -197,19 +197,19 @@ _irq_stack_loop: | |||
197 | 197 | ||
198 | .section .vectors.1, "ax", %progbits | 198 | .section .vectors.1, "ax", %progbits |
199 | j tlb_refill_handler | 199 | j tlb_refill_handler |
200 | nop | 200 | ssnop |
201 | 201 | ||
202 | .section .vectors.2, "ax", %progbits | 202 | .section .vectors.2, "ax", %progbits |
203 | j real_exception_handler | 203 | j real_exception_handler |
204 | nop | 204 | ssnop |
205 | 205 | ||
206 | .section .vectors.3, "ax", %progbits | 206 | .section .vectors.3, "ax", %progbits |
207 | j real_exception_handler | 207 | j real_exception_handler |
208 | nop | 208 | ssnop |
209 | 209 | ||
210 | .section .vectors.4, "ax", %progbits | 210 | .section .vectors.4, "ax", %progbits |
211 | j real_exception_handler | 211 | j real_exception_handler |
212 | nop | 212 | ssnop |
213 | 213 | ||
214 | .section .vectors, "ax", %progbits | 214 | .section .vectors, "ax", %progbits |
215 | real_exception_handler: | 215 | real_exception_handler: |
@@ -253,47 +253,47 @@ real_exception_handler: | |||
253 | sw v0, 0x68(sp) | 253 | sw v0, 0x68(sp) |
254 | sw $1, 0x6C(sp) | 254 | sw $1, 0x6C(sp) |
255 | mflo k0 | 255 | mflo k0 |
256 | nop | 256 | ssnop |
257 | sw k0, 0x70(sp) | 257 | sw k0, 0x70(sp) |
258 | mfhi k0 | 258 | mfhi k0 |
259 | nop | 259 | ssnop |
260 | sw k0, 0x74(sp) | 260 | sw k0, 0x74(sp) |
261 | mfc0 k0, C0_STATUS | 261 | mfc0 k0, C0_STATUS |
262 | nop | 262 | ssnop |
263 | nop | 263 | ssnop |
264 | nop | 264 | ssnop |
265 | sw k0, 0x78(sp) | 265 | sw k0, 0x78(sp) |
266 | mfc0 k0, C0_EPC | 266 | mfc0 k0, C0_EPC |
267 | nop | 267 | ssnop |
268 | nop | 268 | ssnop |
269 | nop | 269 | ssnop |
270 | sw k0, 0x7C(sp) | 270 | sw k0, 0x7C(sp) |
271 | 271 | ||
272 | li k1, M_CauseExcCode | 272 | li k1, M_CauseExcCode |
273 | mfc0 k0, C0_CAUSE | 273 | mfc0 k0, C0_CAUSE |
274 | and k0, k1 | 274 | and k0, k1 |
275 | beq zero, k0, _int | 275 | beq zero, k0, _int |
276 | nop | 276 | ssnop |
277 | j _exception | 277 | j _exception |
278 | nop | 278 | ssnop |
279 | 279 | ||
280 | _int: | 280 | _int: |
281 | jal intr_handler | 281 | jal intr_handler |
282 | nop | 282 | ssnop |
283 | j _exception_return | 283 | j _exception_return |
284 | 284 | ||
285 | _exception: | 285 | _exception: |
286 | move a0, sp | 286 | move a0, sp |
287 | mfc0 a1, C0_CAUSE | 287 | mfc0 a1, C0_CAUSE |
288 | nop | 288 | ssnop |
289 | nop | 289 | ssnop |
290 | nop | 290 | ssnop |
291 | mfc0 a2, C0_EPC | 291 | mfc0 a2, C0_EPC |
292 | nop | 292 | ssnop |
293 | nop | 293 | ssnop |
294 | nop | 294 | ssnop |
295 | jal exception_handler | 295 | jal exception_handler |
296 | nop | 296 | ssnop |
297 | 297 | ||
298 | _exception_return: | 298 | _exception_return: |
299 | lw ra, 0(sp) | 299 | lw ra, 0(sp) |
@@ -326,23 +326,23 @@ _exception_return: | |||
326 | lw $1, 0x6C(sp) | 326 | lw $1, 0x6C(sp) |
327 | lw k0, 0x70(sp) | 327 | lw k0, 0x70(sp) |
328 | mtlo k0 | 328 | mtlo k0 |
329 | nop | 329 | ssnop |
330 | lw k0, 0x74(sp) | 330 | lw k0, 0x74(sp) |
331 | mthi k0 | 331 | mthi k0 |
332 | nop | 332 | ssnop |
333 | lw k0, 0x78(sp) | 333 | lw k0, 0x78(sp) |
334 | mtc0 k0, C0_STATUS | 334 | mtc0 k0, C0_STATUS |
335 | nop | 335 | ssnop |
336 | nop | 336 | ssnop |
337 | nop | 337 | ssnop |
338 | lw k0, 0x7C(sp) | 338 | lw k0, 0x7C(sp) |
339 | mtc0 k0, C0_EPC | 339 | mtc0 k0, C0_EPC |
340 | nop | 340 | ssnop |
341 | nop | 341 | ssnop |
342 | nop | 342 | ssnop |
343 | /* Restore previous stack pointer */ | 343 | /* Restore previous stack pointer */ |
344 | lw sp, 0x80(sp) | 344 | lw sp, 0x80(sp) |
345 | eret | 345 | eret |
346 | nop | 346 | ssnop |
347 | .set reorder | 347 | .set reorder |
348 | .set at | 348 | .set at |
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c index 7fe3f819b3..22a6709166 100644 --- a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c | |||
@@ -18,7 +18,7 @@ | |||
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #include "config.h" | 22 | #include "config.h" |
23 | #include "jz4740.h" | 23 | #include "jz4740.h" |
24 | #include "r61509.h" | 24 | #include "r61509.h" |
@@ -36,7 +36,7 @@ do { \ | |||
36 | REG_GPIO_PXPES(2) = 0x001cffff; \ | 36 | REG_GPIO_PXPES(2) = 0x001cffff; \ |
37 | } while (0) | 37 | } while (0) |
38 | 38 | ||
39 | #define SLEEP(x) { register int __i; for(__i=0; __i<x; __i++) asm volatile("nop\n nop\n"); } | 39 | #define SLEEP(x) { register int __i; for(__i=0; __i<x; __i++) asm volatile("ssnop\n ssnop\n"); } |
40 | #define DELAY SLEEP(700000); | 40 | #define DELAY SLEEP(700000); |
41 | 41 | ||
42 | #if ((defined(ONDA_VX777) || defined(ONDA_VX747P)) && !defined(BOOTLOADER)) \ | 42 | #if ((defined(ONDA_VX777) || defined(ONDA_VX747P)) && !defined(BOOTLOADER)) \ |
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx767/lcd-onda_vx767.c b/firmware/target/mips/ingenic_jz47xx/onda_vx767/lcd-onda_vx767.c index caee8982f6..a32fe45608 100644 --- a/firmware/target/mips/ingenic_jz47xx/onda_vx767/lcd-onda_vx767.c +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx767/lcd-onda_vx767.c | |||
@@ -18,7 +18,7 @@ | |||
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #include "config.h" | 22 | #include "config.h" |
23 | #include "jz4740.h" | 23 | #include "jz4740.h" |
24 | #include "lcd.h" | 24 | #include "lcd.h" |
@@ -37,7 +37,7 @@ do { \ | |||
37 | } while (0) | 37 | } while (0) |
38 | 38 | ||
39 | 39 | ||
40 | #define SLEEP(x) for(i=0; i<x; i++) asm volatile("nop\n nop\n"); | 40 | #define SLEEP(x) for(i=0; i<x; i++) asm volatile("ssnop\n ssnop\n"); |
41 | #define DELAY SLEEP(700000); | 41 | #define DELAY SLEEP(700000); |
42 | static void _display_pin_init(void) | 42 | static void _display_pin_init(void) |
43 | { | 43 | { |
@@ -48,10 +48,10 @@ static void _display_pin_init(void) | |||
48 | __gpio_as_output(PIN_CS_N); | 48 | __gpio_as_output(PIN_CS_N); |
49 | __gpio_as_output(PIN_RESET_N); | 49 | __gpio_as_output(PIN_RESET_N); |
50 | DELAY; /* delay_ms(10); */ | 50 | DELAY; /* delay_ms(10); */ |
51 | 51 | ||
52 | __gpio_clear_pin(PIN_CS_N); | 52 | __gpio_clear_pin(PIN_CS_N); |
53 | DELAY; /* delay_ms(10); */ | 53 | DELAY; /* delay_ms(10); */ |
54 | 54 | ||
55 | __gpio_set_pin(PIN_RESET_N); | 55 | __gpio_set_pin(PIN_RESET_N); |
56 | DELAY; /* delay_ms(10); */ | 56 | DELAY; /* delay_ms(10); */ |
57 | __gpio_clear_pin(PIN_RESET_N); | 57 | __gpio_clear_pin(PIN_RESET_N); |
@@ -80,13 +80,13 @@ static void _display_pin_init(void) | |||
80 | static void _display_init(void) | 80 | static void _display_init(void) |
81 | { | 81 | { |
82 | int i; | 82 | int i; |
83 | 83 | ||
84 | SLCD_SEND_COMMAND(0xE3, 0x8); | 84 | SLCD_SEND_COMMAND(0xE3, 0x8); |
85 | SLCD_SEND_COMMAND(0xE4, 0x1411); | 85 | SLCD_SEND_COMMAND(0xE4, 0x1411); |
86 | SLCD_SEND_COMMAND(0xE5, 0x8000); | 86 | SLCD_SEND_COMMAND(0xE5, 0x8000); |
87 | SLCD_SEND_COMMAND(0x0, 0x1); | 87 | SLCD_SEND_COMMAND(0x0, 0x1); |
88 | DELAY; /* delay_ms(10); */ | 88 | DELAY; /* delay_ms(10); */ |
89 | 89 | ||
90 | SLCD_SEND_COMMAND(0x1, 0x100); | 90 | SLCD_SEND_COMMAND(0x1, 0x100); |
91 | SLCD_SEND_COMMAND(0x2, 0x400); | 91 | SLCD_SEND_COMMAND(0x2, 0x400); |
92 | SLCD_SEND_COMMAND(0x3, 0x1028); | 92 | SLCD_SEND_COMMAND(0x3, 0x1028); |
@@ -139,7 +139,7 @@ static void _display_init(void) | |||
139 | SLCD_SEND_COMMAND(0x97, 0); | 139 | SLCD_SEND_COMMAND(0x97, 0); |
140 | SLCD_SEND_COMMAND(0x98, 0); | 140 | SLCD_SEND_COMMAND(0x98, 0); |
141 | SLCD_SEND_COMMAND(0x7, 0x173); | 141 | SLCD_SEND_COMMAND(0x7, 0x173); |
142 | 142 | ||
143 | __gpio_clear_pin(PIN_UNK_N); | 143 | __gpio_clear_pin(PIN_UNK_N); |
144 | SLCD_SET_COMMAND(0x22); | 144 | SLCD_SET_COMMAND(0x22); |
145 | WAIT_ON_SLCD; | 145 | WAIT_ON_SLCD; |
@@ -158,7 +158,7 @@ static void _set_lcd_bus(void) | |||
158 | { | 158 | { |
159 | REG_LCD_CFG &= ~LCD_CFG_LCDPIN_MASK; | 159 | REG_LCD_CFG &= ~LCD_CFG_LCDPIN_MASK; |
160 | REG_LCD_CFG |= LCD_CFG_LCDPIN_SLCD; | 160 | REG_LCD_CFG |= LCD_CFG_LCDPIN_SLCD; |
161 | 161 | ||
162 | REG_SLCD_CFG = (SLCD_CFG_BURST_4_WORD | SLCD_CFG_DWIDTH_18 | SLCD_CFG_CWIDTH_18BIT | 162 | REG_SLCD_CFG = (SLCD_CFG_BURST_4_WORD | SLCD_CFG_DWIDTH_18 | SLCD_CFG_CWIDTH_18BIT |
163 | | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING | 163 | | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING |
164 | | SLCD_CFG_TYPE_PARALLEL); | 164 | | SLCD_CFG_TYPE_PARALLEL); |
@@ -167,15 +167,15 @@ static void _set_lcd_bus(void) | |||
167 | static void _set_lcd_clock(void) | 167 | static void _set_lcd_clock(void) |
168 | { | 168 | { |
169 | unsigned int val; | 169 | unsigned int val; |
170 | 170 | ||
171 | __cpm_stop_lcd(); | 171 | __cpm_stop_lcd(); |
172 | 172 | ||
173 | val = __cpm_get_pllout2() / LCD_PCLK; | 173 | val = __cpm_get_pllout2() / LCD_PCLK; |
174 | val--; | 174 | val--; |
175 | if ( val > 0x1ff ) | 175 | if ( val > 0x1ff ) |
176 | val = 0x1ff; /* CPM_LPCDR is too large, set it to 0x1ff */ | 176 | val = 0x1ff; /* CPM_LPCDR is too large, set it to 0x1ff */ |
177 | __cpm_set_pixdiv(val); | 177 | __cpm_set_pixdiv(val); |
178 | 178 | ||
179 | __cpm_start_lcd(); | 179 | __cpm_start_lcd(); |
180 | } | 180 | } |
181 | 181 | ||
@@ -196,7 +196,7 @@ void lcd_set_target(int x, int y, int width, int height) | |||
196 | SLCD_SEND_COMMAND(0x52, x); | 196 | SLCD_SEND_COMMAND(0x52, x); |
197 | SLCD_SEND_COMMAND(0x53, x+width-1); | 197 | SLCD_SEND_COMMAND(0x53, x+width-1); |
198 | /* TODO */ | 198 | /* TODO */ |
199 | 199 | ||
200 | __gpio_clear_pin(PIN_UNK_N); | 200 | __gpio_clear_pin(PIN_UNK_N); |
201 | SLCD_SET_COMMAND(0x22); | 201 | SLCD_SET_COMMAND(0x22); |
202 | WAIT_ON_SLCD; | 202 | WAIT_ON_SLCD; |
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c index d3a753a58e..fdc335ad21 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c | |||
@@ -18,7 +18,7 @@ | |||
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #include "config.h" | 22 | #include "config.h" |
23 | #include "jz4740.h" | 23 | #include "jz4740.h" |
24 | #include "mips.h" | 24 | #include "mips.h" |
@@ -165,9 +165,9 @@ static int get_irq_number(void) | |||
165 | { | 165 | { |
166 | static unsigned long ipl; | 166 | static unsigned long ipl; |
167 | register int irq; | 167 | register int irq; |
168 | 168 | ||
169 | ipl |= REG_INTC_IPR; | 169 | ipl |= REG_INTC_IPR; |
170 | 170 | ||
171 | if (UNLIKELY(ipl == 0)) | 171 | if (UNLIKELY(ipl == 0)) |
172 | return -1; | 172 | return -1; |
173 | 173 | ||
@@ -180,7 +180,7 @@ static int get_irq_number(void) | |||
180 | : "r" (ipl) | 180 | : "r" (ipl) |
181 | : "t0" | 181 | : "t0" |
182 | ); | 182 | ); |
183 | 183 | ||
184 | if (UNLIKELY(irq < 0)) | 184 | if (UNLIKELY(irq < 0)) |
185 | return -1; | 185 | return -1; |
186 | 186 | ||
@@ -213,7 +213,7 @@ void intr_handler(void) | |||
213 | register int irq = get_irq_number(); | 213 | register int irq = get_irq_number(); |
214 | if(UNLIKELY(irq < 0)) | 214 | if(UNLIKELY(irq < 0)) |
215 | return; | 215 | return; |
216 | 216 | ||
217 | ack_irq(irq); | 217 | ack_irq(irq); |
218 | if(LIKELY(irq > 0)) | 218 | if(LIKELY(irq > 0)) |
219 | irqvector[irq-1](); | 219 | irqvector[irq-1](); |
@@ -320,14 +320,14 @@ void dma_enable(void) | |||
320 | if(++dma_count == 1) | 320 | if(++dma_count == 1) |
321 | { | 321 | { |
322 | __cpm_start_dmac(); | 322 | __cpm_start_dmac(); |
323 | 323 | ||
324 | REG_DMAC_DCCSR(0) = 0; | 324 | REG_DMAC_DCCSR(0) = 0; |
325 | REG_DMAC_DCCSR(1) = 0; | 325 | REG_DMAC_DCCSR(1) = 0; |
326 | REG_DMAC_DCCSR(2) = 0; | 326 | REG_DMAC_DCCSR(2) = 0; |
327 | REG_DMAC_DCCSR(3) = 0; | 327 | REG_DMAC_DCCSR(3) = 0; |
328 | REG_DMAC_DCCSR(4) = 0; | 328 | REG_DMAC_DCCSR(4) = 0; |
329 | REG_DMAC_DCCSR(5) = 0; | 329 | REG_DMAC_DCCSR(5) = 0; |
330 | 330 | ||
331 | REG_DMAC_DMACR = (DMAC_DMACR_PR_RR | DMAC_DMACR_DMAE); | 331 | REG_DMAC_DMACR = (DMAC_DMACR_PR_RR | DMAC_DMACR_DMAE); |
332 | } | 332 | } |
333 | } | 333 | } |
@@ -377,7 +377,7 @@ static void pll_init(void) | |||
377 | (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ | 377 | (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ |
378 | (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ | 378 | (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ |
379 | (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ | 379 | (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ |
380 | CPM_CPPCR_PLLEN; /* enable PLL */ | 380 | CPM_CPPCR_PLLEN; /* enable PLL */ |
381 | 381 | ||
382 | /* init PLL */ | 382 | /* init PLL */ |
383 | REG_CPM_CPCCR = cfcr; | 383 | REG_CPM_CPCCR = cfcr; |
@@ -539,7 +539,7 @@ void system_reboot(void) | |||
539 | REG_WDT_TDR = JZ_EXTAL/1000; /* reset after 4ms */ | 539 | REG_WDT_TDR = JZ_EXTAL/1000; /* reset after 4ms */ |
540 | REG_TCU_TSCR = TCU_TSSR_WDTSC; /* enable wdt clock */ | 540 | REG_TCU_TSCR = TCU_TSSR_WDTSC; /* enable wdt clock */ |
541 | REG_WDT_TCER = WDT_TCER_TCEN; /* wdt start */ | 541 | REG_WDT_TCER = WDT_TCER_TCEN; /* wdt start */ |
542 | 542 | ||
543 | while (1); | 543 | while (1); |
544 | } | 544 | } |
545 | 545 | ||
@@ -550,7 +550,7 @@ void system_exception_wait(void) | |||
550 | { | 550 | { |
551 | if( (~REG_GPIO_PXPIN(3)) & (1 << 29) ) | 551 | if( (~REG_GPIO_PXPIN(3)) & (1 << 29) ) |
552 | return; | 552 | return; |
553 | asm volatile("nop"); | 553 | asm volatile("ssnop"); |
554 | } | 554 | } |
555 | } | 555 | } |
556 | 556 | ||
@@ -558,7 +558,7 @@ void power_off(void) | |||
558 | { | 558 | { |
559 | /* Enable RTC clock */ | 559 | /* Enable RTC clock */ |
560 | __cpm_start_rtc(); | 560 | __cpm_start_rtc(); |
561 | 561 | ||
562 | /* Put system into hibernate mode */ | 562 | /* Put system into hibernate mode */ |
563 | __rtc_clear_alarm_flag(); | 563 | __rtc_clear_alarm_flag(); |
564 | __rtc_clear_hib_stat_all(); | 564 | __rtc_clear_hib_stat_all(); |
@@ -567,7 +567,7 @@ void power_off(void) | |||
567 | __rtc_set_hrcr_val(0xFE0); | 567 | __rtc_set_hrcr_val(0xFE0); |
568 | __rtc_set_hwfcr_val(0xFFFF << 4); | 568 | __rtc_set_hwfcr_val(0xFFFF << 4); |
569 | __rtc_power_down(); | 569 | __rtc_power_down(); |
570 | 570 | ||
571 | while(1); | 571 | while(1); |
572 | } | 572 | } |
573 | 573 | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c index eee767c5ca..19fe0ba661 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c | |||
@@ -737,7 +737,7 @@ void system_exception_wait(void) | |||
737 | { | 737 | { |
738 | if( (~REG_GPIO_PXPIN(0)) & (1 << 30) ) | 738 | if( (~REG_GPIO_PXPIN(0)) & (1 << 30) ) |
739 | return; | 739 | return; |
740 | asm volatile("nop"); | 740 | asm volatile("ssnop"); |
741 | } | 741 | } |
742 | } | 742 | } |
743 | 743 | ||
diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c index 14a013211d..eb7004952e 100644 --- a/firmware/target/mips/mmu-mips.c +++ b/firmware/target/mips/mmu-mips.c | |||
@@ -36,12 +36,12 @@ | |||
36 | __asm__ __volatile__( \ | 36 | __asm__ __volatile__( \ |
37 | " .set push \n" \ | 37 | " .set push \n" \ |
38 | " .set noreorder \n" \ | 38 | " .set noreorder \n" \ |
39 | " nop \n" \ | 39 | " ssnop \n" \ |
40 | " nop \n" \ | 40 | " ssnop \n" \ |
41 | " nop \n" \ | 41 | " ssnop \n" \ |
42 | " nop \n" \ | 42 | " ssnop \n" \ |
43 | " nop \n" \ | 43 | " ssnop \n" \ |
44 | " nop \n" \ | 44 | " ssnop \n" \ |
45 | " .set pop \n"); | 45 | " .set pop \n"); |
46 | 46 | ||
47 | #define DEFAULT_PAGE_SHIFT PL_4K | 47 | #define DEFAULT_PAGE_SHIFT PL_4K |
@@ -137,16 +137,16 @@ void mmu_init(void) | |||
137 | #if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B | 137 | #if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B |
138 | #define INVALIDATE_BTB() \ | 138 | #define INVALIDATE_BTB() \ |
139 | do { \ | 139 | do { \ |
140 | unsigned long tmp; \ | 140 | register unsigned long tmp; \ |
141 | __asm__ __volatile__( \ | 141 | __asm__ __volatile__( \ |
142 | " .set push \n" \ | 142 | " .set push \n" \ |
143 | " .set noreorder \n" \ | 143 | " .set noreorder \n" \ |
144 | " .set mips32 \n" \ | 144 | " .set mips32 \n" \ |
145 | " mfc0 %0, $16, 7 \n" \ | 145 | " mfc0 %0, $16, 7 \n" \ |
146 | " nop \n" \ | 146 | " ssnop \n" \ |
147 | " ori %0, 2 \n" \ | 147 | " ori %0, 2 \n" \ |
148 | " mtc0 %0, $16, 7 \n" \ | 148 | " mtc0 %0, $16, 7 \n" \ |
149 | " nop \n" \ | 149 | " ssnop \n" \ |
150 | " .set pop \n" \ | 150 | " .set pop \n" \ |
151 | : "=&r"(tmp)); \ | 151 | : "=&r"(tmp)); \ |
152 | } while (0) | 152 | } while (0) |
@@ -178,7 +178,7 @@ void commit_dcache(void) __attribute__((alias("commit_discard_dcache"))); | |||
178 | /* Writeback whole D-cache and invalidate D-cache lines */ | 178 | /* Writeback whole D-cache and invalidate D-cache lines */ |
179 | void commit_discard_dcache(void) | 179 | void commit_discard_dcache(void) |
180 | { | 180 | { |
181 | unsigned int i; | 181 | register unsigned int i; |
182 | 182 | ||
183 | /* Use index type operation and iterate whole cache */ | 183 | /* Use index type operation and iterate whole cache */ |
184 | for (i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHEALIGN_SIZE) | 184 | for (i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHEALIGN_SIZE) |
@@ -192,7 +192,7 @@ void commit_discard_dcache(void) | |||
192 | */ | 192 | */ |
193 | void commit_discard_dcache_range(const void *base, unsigned int size) | 193 | void commit_discard_dcache_range(const void *base, unsigned int size) |
194 | { | 194 | { |
195 | char *s; | 195 | register char *s; |
196 | 196 | ||
197 | for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE) | 197 | for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE) |
198 | __CACHE_OP(DCHitWBInv, s); | 198 | __CACHE_OP(DCHitWBInv, s); |
@@ -204,7 +204,7 @@ void commit_discard_dcache_range(const void *base, unsigned int size) | |||
204 | */ | 204 | */ |
205 | void commit_dcache_range(const void *base, unsigned int size) | 205 | void commit_dcache_range(const void *base, unsigned int size) |
206 | { | 206 | { |
207 | char *s; | 207 | register char *s; |
208 | 208 | ||
209 | for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE) | 209 | for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE) |
210 | __CACHE_OP(DCHitWB, s); | 210 | __CACHE_OP(DCHitWB, s); |
@@ -217,7 +217,7 @@ void commit_dcache_range(const void *base, unsigned int size) | |||
217 | */ | 217 | */ |
218 | void discard_dcache_range(const void *base, unsigned int size) | 218 | void discard_dcache_range(const void *base, unsigned int size) |
219 | { | 219 | { |
220 | char *s; | 220 | register char *s; |
221 | 221 | ||
222 | if (((int)base & CACHEALIGN_SIZE - 1) || | 222 | if (((int)base & CACHEALIGN_SIZE - 1) || |
223 | (((int)base + size) & CACHEALIGN_SIZE - 1)) { | 223 | (((int)base + size) & CACHEALIGN_SIZE - 1)) { |
@@ -235,7 +235,7 @@ void discard_dcache_range(const void *base, unsigned int size) | |||
235 | /* Invalidate whole I-cache */ | 235 | /* Invalidate whole I-cache */ |
236 | static void discard_icache(void) | 236 | static void discard_icache(void) |
237 | { | 237 | { |
238 | unsigned int i; | 238 | register unsigned int i; |
239 | 239 | ||
240 | asm volatile (".set push \n" | 240 | asm volatile (".set push \n" |
241 | ".set noreorder \n" | 241 | ".set noreorder \n" |