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| author | Solomon Peachy <pizza@shaftnet.org> | 2020-08-28 21:45:58 -0400 |
|---|---|---|
| committer | Solomon Peachy <pizza@shaftnet.org> | 2020-09-03 15:34:28 -0400 |
| commit | 0cb162a76b16d58250a33e817af6a763e89a770a (patch) | |
| tree | af5ac50c1ec59f665e0a4845672a16d758b44953 /firmware/target/mips/ingenic_jz47xx/system-jz4760.c | |
| parent | 1ae8213a64c23ac86173b8139e01c7cad350ec6b (diff) | |
| download | rockbox-0cb162a76b16d58250a33e817af6a763e89a770a.tar.gz rockbox-0cb162a76b16d58250a33e817af6a763e89a770a.zip | |
mips: Heavily rework DMA & caching code
Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527)
but rebased and heavily updated.
Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/system-jz4760.c')
| -rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4760.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c index ff87e5ad9e..eee767c5ca 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c | |||
| @@ -673,8 +673,7 @@ void ICODE_ATTR system_main(void) | |||
| 673 | { | 673 | { |
| 674 | int i; | 674 | int i; |
| 675 | 675 | ||
| 676 | __dcache_writeback_all(); | 676 | commit_discard_idcache(); |
| 677 | __icache_invalidate_all(); | ||
| 678 | 677 | ||
| 679 | write_c0_status(1 << 28 | 1 << 10 ); /* Enable CP | Mask interrupt 2 */ | 678 | write_c0_status(1 << 28 | 1 << 10 ); /* Enable CP | Mask interrupt 2 */ |
| 680 | 679 | ||