From 0cb162a76b16d58250a33e817af6a763e89a770a Mon Sep 17 00:00:00 2001 From: Solomon Peachy Date: Fri, 28 Aug 2020 21:45:58 -0400 Subject: mips: Heavily rework DMA & caching code Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527) but rebased and heavily updated. Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70 --- firmware/target/mips/ingenic_jz47xx/system-jz4760.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'firmware/target/mips/ingenic_jz47xx/system-jz4760.c') diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c index ff87e5ad9e..eee767c5ca 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c @@ -673,8 +673,7 @@ void ICODE_ATTR system_main(void) { int i; - __dcache_writeback_all(); - __icache_invalidate_all(); + commit_discard_idcache(); write_c0_status(1 << 28 | 1 << 10 ); /* Enable CP | Mask interrupt 2 */ -- cgit v1.2.3