diff options
author | Solomon Peachy <pizza@shaftnet.org> | 2020-09-04 23:50:38 -0400 |
---|---|---|
committer | Solomon Peachy <pizza@shaftnet.org> | 2020-09-05 22:18:26 +0000 |
commit | d015165bc546e80b1c033c23c68a0ba307b7a39f (patch) | |
tree | 3618d4af6740d353d22f2e48a3729775968176c9 /firmware/target/mips/ingenic_jz47xx/system-jz4740.c | |
parent | 8188588f14849fbc80254caf073fc7c790596c0a (diff) | |
download | rockbox-d015165bc546e80b1c033c23c68a0ba307b7a39f.tar.gz rockbox-d015165bc546e80b1c033c23c68a0ba307b7a39f.zip |
mips: Convert 'nop' to 'ssnop' -- for future-proofing
Change-Id: I17625f4d56a1f5205887cb47668a2dcb628053f4
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/system-jz4740.c')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4740.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c index d3a753a58e..fdc335ad21 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c | |||
@@ -18,7 +18,7 @@ | |||
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #include "config.h" | 22 | #include "config.h" |
23 | #include "jz4740.h" | 23 | #include "jz4740.h" |
24 | #include "mips.h" | 24 | #include "mips.h" |
@@ -165,9 +165,9 @@ static int get_irq_number(void) | |||
165 | { | 165 | { |
166 | static unsigned long ipl; | 166 | static unsigned long ipl; |
167 | register int irq; | 167 | register int irq; |
168 | 168 | ||
169 | ipl |= REG_INTC_IPR; | 169 | ipl |= REG_INTC_IPR; |
170 | 170 | ||
171 | if (UNLIKELY(ipl == 0)) | 171 | if (UNLIKELY(ipl == 0)) |
172 | return -1; | 172 | return -1; |
173 | 173 | ||
@@ -180,7 +180,7 @@ static int get_irq_number(void) | |||
180 | : "r" (ipl) | 180 | : "r" (ipl) |
181 | : "t0" | 181 | : "t0" |
182 | ); | 182 | ); |
183 | 183 | ||
184 | if (UNLIKELY(irq < 0)) | 184 | if (UNLIKELY(irq < 0)) |
185 | return -1; | 185 | return -1; |
186 | 186 | ||
@@ -213,7 +213,7 @@ void intr_handler(void) | |||
213 | register int irq = get_irq_number(); | 213 | register int irq = get_irq_number(); |
214 | if(UNLIKELY(irq < 0)) | 214 | if(UNLIKELY(irq < 0)) |
215 | return; | 215 | return; |
216 | 216 | ||
217 | ack_irq(irq); | 217 | ack_irq(irq); |
218 | if(LIKELY(irq > 0)) | 218 | if(LIKELY(irq > 0)) |
219 | irqvector[irq-1](); | 219 | irqvector[irq-1](); |
@@ -320,14 +320,14 @@ void dma_enable(void) | |||
320 | if(++dma_count == 1) | 320 | if(++dma_count == 1) |
321 | { | 321 | { |
322 | __cpm_start_dmac(); | 322 | __cpm_start_dmac(); |
323 | 323 | ||
324 | REG_DMAC_DCCSR(0) = 0; | 324 | REG_DMAC_DCCSR(0) = 0; |
325 | REG_DMAC_DCCSR(1) = 0; | 325 | REG_DMAC_DCCSR(1) = 0; |
326 | REG_DMAC_DCCSR(2) = 0; | 326 | REG_DMAC_DCCSR(2) = 0; |
327 | REG_DMAC_DCCSR(3) = 0; | 327 | REG_DMAC_DCCSR(3) = 0; |
328 | REG_DMAC_DCCSR(4) = 0; | 328 | REG_DMAC_DCCSR(4) = 0; |
329 | REG_DMAC_DCCSR(5) = 0; | 329 | REG_DMAC_DCCSR(5) = 0; |
330 | 330 | ||
331 | REG_DMAC_DMACR = (DMAC_DMACR_PR_RR | DMAC_DMACR_DMAE); | 331 | REG_DMAC_DMACR = (DMAC_DMACR_PR_RR | DMAC_DMACR_DMAE); |
332 | } | 332 | } |
333 | } | 333 | } |
@@ -377,7 +377,7 @@ static void pll_init(void) | |||
377 | (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ | 377 | (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ |
378 | (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ | 378 | (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ |
379 | (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ | 379 | (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ |
380 | CPM_CPPCR_PLLEN; /* enable PLL */ | 380 | CPM_CPPCR_PLLEN; /* enable PLL */ |
381 | 381 | ||
382 | /* init PLL */ | 382 | /* init PLL */ |
383 | REG_CPM_CPCCR = cfcr; | 383 | REG_CPM_CPCCR = cfcr; |
@@ -539,7 +539,7 @@ void system_reboot(void) | |||
539 | REG_WDT_TDR = JZ_EXTAL/1000; /* reset after 4ms */ | 539 | REG_WDT_TDR = JZ_EXTAL/1000; /* reset after 4ms */ |
540 | REG_TCU_TSCR = TCU_TSSR_WDTSC; /* enable wdt clock */ | 540 | REG_TCU_TSCR = TCU_TSSR_WDTSC; /* enable wdt clock */ |
541 | REG_WDT_TCER = WDT_TCER_TCEN; /* wdt start */ | 541 | REG_WDT_TCER = WDT_TCER_TCEN; /* wdt start */ |
542 | 542 | ||
543 | while (1); | 543 | while (1); |
544 | } | 544 | } |
545 | 545 | ||
@@ -550,7 +550,7 @@ void system_exception_wait(void) | |||
550 | { | 550 | { |
551 | if( (~REG_GPIO_PXPIN(3)) & (1 << 29) ) | 551 | if( (~REG_GPIO_PXPIN(3)) & (1 << 29) ) |
552 | return; | 552 | return; |
553 | asm volatile("nop"); | 553 | asm volatile("ssnop"); |
554 | } | 554 | } |
555 | } | 555 | } |
556 | 556 | ||
@@ -558,7 +558,7 @@ void power_off(void) | |||
558 | { | 558 | { |
559 | /* Enable RTC clock */ | 559 | /* Enable RTC clock */ |
560 | __cpm_start_rtc(); | 560 | __cpm_start_rtc(); |
561 | 561 | ||
562 | /* Put system into hibernate mode */ | 562 | /* Put system into hibernate mode */ |
563 | __rtc_clear_alarm_flag(); | 563 | __rtc_clear_alarm_flag(); |
564 | __rtc_clear_hib_stat_all(); | 564 | __rtc_clear_hib_stat_all(); |
@@ -567,7 +567,7 @@ void power_off(void) | |||
567 | __rtc_set_hrcr_val(0xFE0); | 567 | __rtc_set_hrcr_val(0xFE0); |
568 | __rtc_set_hwfcr_val(0xFFFF << 4); | 568 | __rtc_set_hwfcr_val(0xFFFF << 4); |
569 | __rtc_power_down(); | 569 | __rtc_power_down(); |
570 | 570 | ||
571 | while(1); | 571 | while(1); |
572 | } | 572 | } |
573 | 573 | ||