Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27188 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 0 insertions, 18 deletions

diff --git a/firmware/target/arm/s3c2440/system-s3c2440.c b/firmware/target/arm/s3c2440/system-s3c2440.c
index cb273ad4df..577b46966c 100644
--- a/firmware/target/arm/s3c2440/system-s3c2440.c
+++ b/firmware/target/arm/s3c2440/system-s3c2440.c
@@ -136,24 +136,6 @@ void memory_init(void)
     enable_mmu();
 }
 
-void s3c_regmod32(volatile unsigned long *reg, unsigned long bits,
-                  unsigned long mask)
-{
-    int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
-    *reg = (*reg & ~mask) | (bits & mask);
-    restore_interrupt(oldstatus);
-}
-
-void s3c_regset32(volatile unsigned long *reg, unsigned long bits)
-{
-    s3c_regmod32(reg, bits, bits);
-}
-
-void s3c_regclr32(volatile unsigned long *reg, unsigned long bits)
-{
-    s3c_regmod32(reg, 0, bits);
-}
-
 #ifdef BOOTLOADER
 void system_prepare_fw_start(void)
 {