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author | Michael Sevakis <jethead71@rockbox.org> | 2010-06-30 02:02:46 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2010-06-30 02:02:46 +0000 |
commit | e286b0bbc04a34c181978efce19c6d0814e228c0 (patch) | |
tree | 841288761e20dc9a7a25e5ba83306adf52547d65 /firmware/target/arm/s3c2440/i2c-s3c2440.c | |
parent | f4a00174b50c209f2a23b7a73fe7cb544ef59d02 (diff) | |
download | rockbox-e286b0bbc04a34c181978efce19c6d0814e228c0.tar.gz rockbox-e286b0bbc04a34c181978efce19c6d0814e228c0.zip |
Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27188 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/s3c2440/i2c-s3c2440.c')
-rw-r--r-- | firmware/target/arm/s3c2440/i2c-s3c2440.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/firmware/target/arm/s3c2440/i2c-s3c2440.c b/firmware/target/arm/s3c2440/i2c-s3c2440.c index 4669186a4c..155eb2f956 100644 --- a/firmware/target/arm/s3c2440/i2c-s3c2440.c +++ b/firmware/target/arm/s3c2440/i2c-s3c2440.c | |||
@@ -43,7 +43,7 @@ void i2c_write(int addr, const unsigned char *buf, int count) | |||
43 | mutex_lock(&i2c_mtx); | 43 | mutex_lock(&i2c_mtx); |
44 | 44 | ||
45 | /* Turn on I2C clock */ | 45 | /* Turn on I2C clock */ |
46 | s3c_regset32(&CLKCON, 1 << 16); | 46 | bitset32(&CLKCON, 1 << 16); |
47 | 47 | ||
48 | /* Set mode to master transmitter and enable lines */ | 48 | /* Set mode to master transmitter and enable lines */ |
49 | IICSTAT = I2C_MODE_MASTER | I2C_MODE_TX | I2C_RXTX_ENB; | 49 | IICSTAT = I2C_MODE_MASTER | I2C_MODE_TX | I2C_RXTX_ENB; |
@@ -76,7 +76,7 @@ void i2c_write(int addr, const unsigned char *buf, int count) | |||
76 | IICSTAT = 0; | 76 | IICSTAT = 0; |
77 | 77 | ||
78 | /* Turn off I2C clock */ | 78 | /* Turn off I2C clock */ |
79 | s3c_regclr32(&CLKCON, 1 << 16); | 79 | bitclr32(&CLKCON, 1 << 16); |
80 | 80 | ||
81 | mutex_unlock(&i2c_mtx); | 81 | mutex_unlock(&i2c_mtx); |
82 | } | 82 | } |
@@ -92,11 +92,11 @@ void i2c_init(void) | |||
92 | INTPND = IIC_MASK; | 92 | INTPND = IIC_MASK; |
93 | 93 | ||
94 | /* Enable i2c interrupt in controller */ | 94 | /* Enable i2c interrupt in controller */ |
95 | s3c_regclr32(&INTMOD, IIC_MASK); | 95 | bitclr32(&INTMOD, IIC_MASK); |
96 | s3c_regclr32(&INTMSK, IIC_MASK); | 96 | bitclr32(&INTMSK, IIC_MASK); |
97 | 97 | ||
98 | /* Turn on I2C clock */ | 98 | /* Turn on I2C clock */ |
99 | s3c_regset32(&CLKCON, 1 << 16); | 99 | bitset32(&CLKCON, 1 << 16); |
100 | 100 | ||
101 | /* Set GPE15 (IICSDA) and GPE14 (IICSCL) to IIC */ | 101 | /* Set GPE15 (IICSDA) and GPE14 (IICSCL) to IIC */ |
102 | GPECON = (GPECON & ~((3 << 30) | (3 << 28))) | | 102 | GPECON = (GPECON & ~((3 << 30) | (3 << 28))) | |
@@ -110,7 +110,7 @@ void i2c_init(void) | |||
110 | IICLC = (0 << 0); | 110 | IICLC = (0 << 0); |
111 | 111 | ||
112 | /* Turn off I2C clock */ | 112 | /* Turn off I2C clock */ |
113 | s3c_regclr32(&CLKCON, 1 << 16); | 113 | bitclr32(&CLKCON, 1 << 16); |
114 | } | 114 | } |
115 | 115 | ||
116 | void IIC(void) | 116 | void IIC(void) |