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author | Michael Sevakis <jethead71@rockbox.org> | 2008-12-04 15:06:48 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2008-12-04 15:06:48 +0000 |
commit | a1ab7a55ffc768da55e4cb30a87cfb85b1231902 (patch) | |
tree | c64c6bdaa07fb7dd522ae96aa8c3543758dd68d1 /firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c | |
parent | 7bc50d1aa545bfed89e1e8f4f0446f9b9da65a3a (diff) | |
download | rockbox-a1ab7a55ffc768da55e4cb30a87cfb85b1231902.tar.gz rockbox-a1ab7a55ffc768da55e4cb30a87cfb85b1231902.zip |
Meg-FX: s3c register definitions really should be unsigned. Switch from 'int' to 'unsigned long' like other targets.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19325 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c')
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c index ac8dc380e2..f3461cfe91 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c | |||
@@ -103,7 +103,7 @@ static void LCD_CTRL_clock(bool onoff) | |||
103 | GPDCON |= 0xAAA0AAA0; | 103 | GPDCON |= 0xAAA0AAA0; |
104 | GPDUP |= 0xFCFC; | 104 | GPDUP |= 0xFCFC; |
105 | 105 | ||
106 | s3c_regset(&CLKCON, 0x20); /* enable LCD clock */ | 106 | s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */ |
107 | LCDCON1 |=0x01; | 107 | LCDCON1 |=0x01; |
108 | } | 108 | } |
109 | else | 109 | else |
@@ -115,7 +115,7 @@ static void LCD_CTRL_clock(bool onoff) | |||
115 | GPDUP &= ~0xFCFC; | 115 | GPDUP &= ~0xFCFC; |
116 | 116 | ||
117 | LCDCON1 &= ~1; /* Must diable first or bus may freeze */ | 117 | LCDCON1 &= ~1; /* Must diable first or bus may freeze */ |
118 | s3c_regclr(&CLKCON, 0x20); /* disable LCD clock */ | 118 | s3c_regclr32(&CLKCON, 0x20); /* disable LCD clock */ |
119 | } | 119 | } |
120 | } | 120 | } |
121 | 121 | ||
@@ -162,7 +162,7 @@ static void LCD_SPI_SS(bool select) | |||
162 | 162 | ||
163 | static void LCD_SPI_start(void) | 163 | static void LCD_SPI_start(void) |
164 | { | 164 | { |
165 | s3c_regset(&CLKCON, 0x40000); /* enable SPI clock */ | 165 | s3c_regset32(&CLKCON, 0x40000); /* enable SPI clock */ |
166 | LCD_SPI_SS(false); | 166 | LCD_SPI_SS(false); |
167 | SPCON0=0x3E; | 167 | SPCON0=0x3E; |
168 | SPPRE0=24; | 168 | SPPRE0=24; |
@@ -176,7 +176,7 @@ static void LCD_SPI_stop(void) | |||
176 | LCD_SPI_SS(false); | 176 | LCD_SPI_SS(false); |
177 | 177 | ||
178 | SPCON0 &= ~0x10; | 178 | SPCON0 &= ~0x10; |
179 | s3c_regclr(&CLKCON, 0x40000); /* disable SPI clock */ | 179 | s3c_regclr32(&CLKCON, 0x40000); /* disable SPI clock */ |
180 | } | 180 | } |
181 | 181 | ||
182 | static void LCD_SPI_powerdown(void) | 182 | static void LCD_SPI_powerdown(void) |
@@ -271,7 +271,7 @@ void lcd_init_device(void) | |||
271 | 271 | ||
272 | GPBUP |= 0x181; | 272 | GPBUP |= 0x181; |
273 | 273 | ||
274 | s3c_regset(&CLKCON, 0x20); /* enable LCD clock */ | 274 | s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */ |
275 | 275 | ||
276 | LCD_CTRL_setup(); | 276 | LCD_CTRL_setup(); |
277 | LCD_SPI_init(); | 277 | LCD_SPI_init(); |