diff options
author | Michael Sevakis <jethead71@rockbox.org> | 2008-12-04 15:06:48 +0000 |
---|---|---|
committer | Michael Sevakis <jethead71@rockbox.org> | 2008-12-04 15:06:48 +0000 |
commit | a1ab7a55ffc768da55e4cb30a87cfb85b1231902 (patch) | |
tree | c64c6bdaa07fb7dd522ae96aa8c3543758dd68d1 | |
parent | 7bc50d1aa545bfed89e1e8f4f0446f9b9da65a3a (diff) | |
download | rockbox-a1ab7a55ffc768da55e4cb30a87cfb85b1231902.tar.gz rockbox-a1ab7a55ffc768da55e4cb30a87cfb85b1231902.zip |
Meg-FX: s3c register definitions really should be unsigned. Switch from 'int' to 'unsigned long' like other targets.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19325 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/export/s3c2440.h | 730 | ||||
-rw-r--r-- | firmware/target/arm/mmu-arm.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/debug-s3c2440.c | 51 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c | 12 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c | 10 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c | 18 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c | 19 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/system-target.h | 7 |
9 files changed, 427 insertions, 424 deletions
diff --git a/firmware/export/s3c2440.h b/firmware/export/s3c2440.h index fe45a1c1ce..f1d41dbae3 100644 --- a/firmware/export/s3c2440.h +++ b/firmware/export/s3c2440.h | |||
@@ -24,65 +24,65 @@ | |||
24 | #define LCD_BUFFER_SIZE (320*240*2) | 24 | #define LCD_BUFFER_SIZE (320*240*2) |
25 | #define TTB_SIZE (0x4000) | 25 | #define TTB_SIZE (0x4000) |
26 | /* must be 16Kb (0x4000) aligned */ | 26 | /* must be 16Kb (0x4000) aligned */ |
27 | #define TTB_BASE ((unsigned int *)(0x30000000 + (32*1024*1024) - TTB_SIZE)) /* End of memory */ | 27 | #define TTB_BASE ((unsigned long *)(0x30000000 + (32*1024*1024) - TTB_SIZE)) /* End of memory */ |
28 | #define FRAME ((short *) ((char *)TTB_BASE - LCD_BUFFER_SIZE)) /* Right before TTB */ | 28 | #define FRAME ((unsigned short *)((unsigned char *)TTB_BASE - LCD_BUFFER_SIZE)) /* Right before TTB */ |
29 | 29 | ||
30 | /* Memory Controllers */ | 30 | /* Memory Controllers */ |
31 | 31 | ||
32 | #define BWSCON (*(volatile int *)0x48000000) /* Bus width & wait status control */ | 32 | #define BWSCON (*(volatile unsigned long *)0x48000000) /* Bus width & wait status control */ |
33 | #define BANKCON0 (*(volatile int *)0x48000004) /* Boot ROM control */ | 33 | #define BANKCON0 (*(volatile unsigned long *)0x48000004) /* Boot ROM control */ |
34 | #define BANKCON1 (*(volatile int *)0x48000008) /* BANK1 control */ | 34 | #define BANKCON1 (*(volatile unsigned long *)0x48000008) /* BANK1 control */ |
35 | #define BANKCON2 (*(volatile int *)0x4800000C) /* BANK2 control */ | 35 | #define BANKCON2 (*(volatile unsigned long *)0x4800000C) /* BANK2 control */ |
36 | #define BANKCON3 (*(volatile int *)0x48000010) /* BANK3 control */ | 36 | #define BANKCON3 (*(volatile unsigned long *)0x48000010) /* BANK3 control */ |
37 | #define BANKCON4 (*(volatile int *)0x48000014) /* BANK4 control */ | 37 | #define BANKCON4 (*(volatile unsigned long *)0x48000014) /* BANK4 control */ |
38 | #define BANKCON5 (*(volatile int *)0x48000018) /* BANK5 control */ | 38 | #define BANKCON5 (*(volatile unsigned long *)0x48000018) /* BANK5 control */ |
39 | #define BANKCON6 (*(volatile int *)0x4800001C) /* BANK6 control */ | 39 | #define BANKCON6 (*(volatile unsigned long *)0x4800001C) /* BANK6 control */ |
40 | #define BANKCON7 (*(volatile int *)0x48000020) /* BANK7 control */ | 40 | #define BANKCON7 (*(volatile unsigned long *)0x48000020) /* BANK7 control */ |
41 | #define REFRESH (*(volatile int *)0x48000024) /* DRAM/SDRAM refresh control */ | 41 | #define REFRESH (*(volatile unsigned long *)0x48000024) /* DRAM/SDRAM refresh control */ |
42 | #define BANKSIZE (*(volatile int *)0x48000028) /* Flexible bank size */ | 42 | #define BANKSIZE (*(volatile unsigned long *)0x48000028) /* Flexible bank size */ |
43 | #define MRSRB6 (*(volatile int *)0x4800002C) /* Mode register set for SDRAM BANK6 */ | 43 | #define MRSRB6 (*(volatile unsigned long *)0x4800002C) /* Mode register set for SDRAM BANK6 */ |
44 | #define MRSRB7 (*(volatile int *)0x48000030) /* Mode register set for SDRAM BANK7 */ | 44 | #define MRSRB7 (*(volatile unsigned long *)0x48000030) /* Mode register set for SDRAM BANK7 */ |
45 | 45 | ||
46 | /* USB Host Controller */ | 46 | /* USB Host Controller */ |
47 | 47 | ||
48 | /* Control and status group */ | 48 | /* Control and status group */ |
49 | #define HcRevision (*(volatile int *)0x49000000) | 49 | #define HcRevision (*(volatile unsigned long *)0x49000000) |
50 | #define HcControl (*(volatile int *)0x49000004) | 50 | #define HcControl (*(volatile unsigned long *)0x49000004) |
51 | #define HcCommonStatus (*(volatile int *)0x49000008) | 51 | #define HcCommonStatus (*(volatile unsigned long *)0x49000008) |
52 | #define HcInterruptStatus (*(volatile int *)0x4900000C) | 52 | #define HcInterruptStatus (*(volatile unsigned long *)0x4900000C) |
53 | #define HcInterruptEnable (*(volatile int *)0x49000010) | 53 | #define HcInterruptEnable (*(volatile unsigned long *)0x49000010) |
54 | #define HcInterruptDisable (*(volatile int *)0x49000014) | 54 | #define HcInterruptDisable (*(volatile unsigned long *)0x49000014) |
55 | /* Memory pointer group */ | 55 | /* Memory pointer group */ |
56 | #define HcHCCA (*(volatile int *)0x49000018) | 56 | #define HcHCCA (*(volatile unsigned long *)0x49000018) |
57 | #define HcPeriodCuttentED (*(volatile int *)0x4900001C) | 57 | #define HcPeriodCuttentED (*(volatile unsigned long *)0x4900001C) |
58 | #define HcControlHeadED (*(volatile int *)0x49000020) | 58 | #define HcControlHeadED (*(volatile unsigned long *)0x49000020) |
59 | #define HcControlCurrentED (*(volatile int *)0x49000024) | 59 | #define HcControlCurrentED (*(volatile unsigned long *)0x49000024) |
60 | #define HcBulkHeadED (*(volatile int *)0x49000028) | 60 | #define HcBulkHeadED (*(volatile unsigned long *)0x49000028) |
61 | #define HcBulkCurrentED (*(volatile int *)0x4900002C) | 61 | #define HcBulkCurrentED (*(volatile unsigned long *)0x4900002C) |
62 | /* Frame counter group */ | 62 | /* Frame counter group */ |
63 | #define HcDoneHead (*(volatile int *)0x49000030) | 63 | #define HcDoneHead (*(volatile unsigned long *)0x49000030) |
64 | #define HcRmInterval (*(volatile int *)0x49000034) | 64 | #define HcRmInterval (*(volatile unsigned long *)0x49000034) |
65 | #define HcFmRemaining (*(volatile int *)0x49000038) | 65 | #define HcFmRemaining (*(volatile unsigned long *)0x49000038) |
66 | #define HcFmNumber (*(volatile int *)0x4900003C) | 66 | #define HcFmNumber (*(volatile unsigned long *)0x4900003C) |
67 | #define HcPeriodicStart (*(volatile int *)0x49000040) | 67 | #define HcPeriodicStart (*(volatile unsigned long *)0x49000040) |
68 | #define HcLSThreshold (*(volatile int *)0x49000044) | 68 | #define HcLSThreshold (*(volatile unsigned long *)0x49000044) |
69 | /* Root hub group */ | 69 | /* Root hub group */ |
70 | #define HcRhDescriptorA (*(volatile int *)0x49000048) | 70 | #define HcRhDescriptorA (*(volatile unsigned long *)0x49000048) |
71 | #define HcRhDescriptorB (*(volatile int *)0x4900004C) | 71 | #define HcRhDescriptorB (*(volatile unsigned long *)0x4900004C) |
72 | #define HcRhStatus (*(volatile int *)0x49000050) | 72 | #define HcRhStatus (*(volatile unsigned long *)0x49000050) |
73 | #define HcRhPortStatus1 (*(volatile int *)0x49000054) | 73 | #define HcRhPortStatus1 (*(volatile unsigned long *)0x49000054) |
74 | #define HcRhPortStatus2 (*(volatile int *)0x49000058) | 74 | #define HcRhPortStatus2 (*(volatile unsigned long *)0x49000058) |
75 | 75 | ||
76 | /* Interrupt Controller */ | 76 | /* Interrupt Controller */ |
77 | 77 | ||
78 | #define SRCPND (*(volatile int *)0x4A000000) /* Interrupt request status */ | 78 | #define SRCPND (*(volatile unsigned long *)0x4A000000) /* Interrupt request status */ |
79 | #define INTMOD (*(volatile int *)0x4A000004) /* Interrupt mode control */ | 79 | #define INTMOD (*(volatile unsigned long *)0x4A000004) /* Interrupt mode control */ |
80 | #define INTMSK (*(volatile int *)0x4A000008) /* Interrupt mask control */ | 80 | #define INTMSK (*(volatile unsigned long *)0x4A000008) /* Interrupt mask control */ |
81 | #define PRIORITY (*(volatile int *)0x4A00000C) /* IRQ priority control */ | 81 | #define PRIORITY (*(volatile unsigned long *)0x4A00000C) /* IRQ priority control */ |
82 | #define INTPND (*(volatile int *)0x4A000010) /* Interrupt request status */ | 82 | #define INTPND (*(volatile unsigned long *)0x4A000010) /* Interrupt request status */ |
83 | #define INTOFFSET (*(volatile int *)0x4A000014) /* Interrupt request source offset */ | 83 | #define INTOFFSET (*(volatile unsigned long *)0x4A000014) /* Interrupt request source offset */ |
84 | #define SUBSRCPND (*(volatile int *)0x4A000018) /* Sub source pending */ | 84 | #define SUBSRCPND (*(volatile unsigned long *)0x4A000018) /* Sub source pending */ |
85 | #define INTSUBMSK (*(volatile int *)0x4A00001C) /* Interrupt sub mask */ | 85 | #define INTSUBMSK (*(volatile unsigned long *)0x4A00001C) /* Interrupt sub mask */ |
86 | 86 | ||
87 | /* Interrupt indexes - INTOFFSET - IRQ mode only */ | 87 | /* Interrupt indexes - INTOFFSET - IRQ mode only */ |
88 | /* Arbiter 5 => Arbiter 6 Req 5 */ | 88 | /* Arbiter 5 => Arbiter 6 Req 5 */ |
@@ -166,376 +166,376 @@ | |||
166 | 166 | ||
167 | /* DMA */ | 167 | /* DMA */ |
168 | 168 | ||
169 | #define DISRC0 (*(volatile int *)0x4B000000) /* DMA 0 initial source */ | 169 | #define DISRC0 (*(volatile unsigned long *)0x4B000000) /* DMA 0 initial source */ |
170 | #define DISRCC0 (*(volatile int *)0x4B000004) /* DMA 0 initial source control */ | 170 | #define DISRCC0 (*(volatile unsigned long *)0x4B000004) /* DMA 0 initial source control */ |
171 | #define DIDST0 (*(volatile int *)0x4B000008) /* DMA 0 initial destination */ | 171 | #define DIDST0 (*(volatile unsigned long *)0x4B000008) /* DMA 0 initial destination */ |
172 | #define DIDSTC0 (*(volatile int *)0x4B00000C) /* DMA 0 initial destination control */ | 172 | #define DIDSTC0 (*(volatile unsigned long *)0x4B00000C) /* DMA 0 initial destination control */ |
173 | #define DCON0 (*(volatile int *)0x4B000010) /* DMA 0 control */ | 173 | #define DCON0 (*(volatile unsigned long *)0x4B000010) /* DMA 0 control */ |
174 | #define DSTAT0 (*(volatile int *)0x4B000014) /* DMA 0 count */ | 174 | #define DSTAT0 (*(volatile unsigned long *)0x4B000014) /* DMA 0 count */ |
175 | #define DCSRC0 (*(volatile int *)0x4B000018) /* DMA 0 current source */ | 175 | #define DCSRC0 (*(volatile unsigned long *)0x4B000018) /* DMA 0 current source */ |
176 | #define DCDST0 (*(volatile int *)0x4B00001C) /* DMA 0 current destination */ | 176 | #define DCDST0 (*(volatile unsigned long *)0x4B00001C) /* DMA 0 current destination */ |
177 | #define DMASKTRIG0 (*(volatile int *)0x4B000020) /* DMA 0 mask trigger */ | 177 | #define DMASKTRIG0 (*(volatile unsigned long *)0x4B000020) /* DMA 0 mask trigger */ |
178 | #define DISRC1 (*(volatile int *)0x4B000040) /* DMA 1 initial source */ | 178 | #define DISRC1 (*(volatile unsigned long *)0x4B000040) /* DMA 1 initial source */ |
179 | #define DISRCC1 (*(volatile int *)0x4B000044) /* DMA 1 initial source control */ | 179 | #define DISRCC1 (*(volatile unsigned long *)0x4B000044) /* DMA 1 initial source control */ |
180 | #define DIDST1 (*(volatile int *)0x4B000048) /* DMA 1 initial destination */ | 180 | #define DIDST1 (*(volatile unsigned long *)0x4B000048) /* DMA 1 initial destination */ |
181 | #define DIDSTC1 (*(volatile int *)0x4B00004C) /* DMA 1 initial destination control */ | 181 | #define DIDSTC1 (*(volatile unsigned long *)0x4B00004C) /* DMA 1 initial destination control */ |
182 | #define DCON1 (*(volatile int *)0x4B000050) /* DMA 1 control */ | 182 | #define DCON1 (*(volatile unsigned long *)0x4B000050) /* DMA 1 control */ |
183 | #define DSTAT1 (*(volatile int *)0x4B000054) /* DMA 1 count */ | 183 | #define DSTAT1 (*(volatile unsigned long *)0x4B000054) /* DMA 1 count */ |
184 | #define DCSRC1 (*(volatile int *)0x4B000058) /* DMA 1 current source */ | 184 | #define DCSRC1 (*(volatile unsigned long *)0x4B000058) /* DMA 1 current source */ |
185 | #define DCDST1 (*(volatile int *)0x4B00005C) /* DMA 1 current destination */ | 185 | #define DCDST1 (*(volatile unsigned long *)0x4B00005C) /* DMA 1 current destination */ |
186 | #define DMASKTRIG1 (*(volatile int *)0x4B000060) /* DMA 1 mask trigger */ | 186 | #define DMASKTRIG1 (*(volatile unsigned long *)0x4B000060) /* DMA 1 mask trigger */ |
187 | #define DISRC2 (*(volatile int *)0x4B000080) /* DMA 2 initial source */ | 187 | #define DISRC2 (*(volatile unsigned long *)0x4B000080) /* DMA 2 initial source */ |
188 | #define DISRCC2 (*(volatile int *)0x4B000084) /* DMA 2 initial source control */ | 188 | #define DISRCC2 (*(volatile unsigned long *)0x4B000084) /* DMA 2 initial source control */ |
189 | #define DIDST2 (*(volatile int *)0x4B000088) /* DMA 2 initial destination */ | 189 | #define DIDST2 (*(volatile unsigned long *)0x4B000088) /* DMA 2 initial destination */ |
190 | #define DIDSTC2 (*(volatile int *)0x4B00008C) /* DMA 2 initial destination control */ | 190 | #define DIDSTC2 (*(volatile unsigned long *)0x4B00008C) /* DMA 2 initial destination control */ |
191 | #define DCON2 (*(volatile int *)0x4B000090) /* DMA 2 control */ | 191 | #define DCON2 (*(volatile unsigned long *)0x4B000090) /* DMA 2 control */ |
192 | #define DSTAT2 (*(volatile int *)0x4B000094) /* DMA 2 count */ | 192 | #define DSTAT2 (*(volatile unsigned long *)0x4B000094) /* DMA 2 count */ |
193 | #define DCSRC2 (*(volatile int *)0x4B000098) /* DMA 2 current source */ | 193 | #define DCSRC2 (*(volatile unsigned long *)0x4B000098) /* DMA 2 current source */ |
194 | #define DCDST2 (*(volatile int *)0x4B00009C) /* DMA 2 current destination */ | 194 | #define DCDST2 (*(volatile unsigned long *)0x4B00009C) /* DMA 2 current destination */ |
195 | #define DMASKTRIG2 (*(volatile int *)0x4B0000A0) /* DMA 2 mask trigger */ | 195 | #define DMASKTRIG2 (*(volatile unsigned long *)0x4B0000A0) /* DMA 2 mask trigger */ |
196 | #define DISRC3 (*(volatile int *)0x4B0000C0) /* DMA 3 initial source */ | 196 | #define DISRC3 (*(volatile unsigned long *)0x4B0000C0) /* DMA 3 initial source */ |
197 | #define DISRCC3 (*(volatile int *)0x4B0000C4) /* DMA 3 initial source control */ | 197 | #define DISRCC3 (*(volatile unsigned long *)0x4B0000C4) /* DMA 3 initial source control */ |
198 | #define DIDST3 (*(volatile int *)0x4B0000C8) /* DMA 3 initial destination */ | 198 | #define DIDST3 (*(volatile unsigned long *)0x4B0000C8) /* DMA 3 initial destination */ |
199 | #define DIDSTC3 (*(volatile int *)0x4B0000CC) /* DMA 3 initial destination control */ | 199 | #define DIDSTC3 (*(volatile unsigned long *)0x4B0000CC) /* DMA 3 initial destination control */ |
200 | #define DCON3 (*(volatile int *)0x4B0000D0) /* DMA 3 control */ | 200 | #define DCON3 (*(volatile unsigned long *)0x4B0000D0) /* DMA 3 control */ |
201 | #define DSTAT3 (*(volatile int *)0x4B0000D4) /* DMA 3 count */ | 201 | #define DSTAT3 (*(volatile unsigned long *)0x4B0000D4) /* DMA 3 count */ |
202 | #define DCSRC3 (*(volatile int *)0x4B0000D8) /* DMA 3 current source */ | 202 | #define DCSRC3 (*(volatile unsigned long *)0x4B0000D8) /* DMA 3 current source */ |
203 | #define DCDST3 (*(volatile int *)0x4B0000DC) /* DMA 3 current destination */ | 203 | #define DCDST3 (*(volatile unsigned long *)0x4B0000DC) /* DMA 3 current destination */ |
204 | #define DMASKTRIG3 (*(volatile int *)0x4B0000E0) /* DMA 3 mask trigger */ | 204 | #define DMASKTRIG3 (*(volatile unsigned long *)0x4B0000E0) /* DMA 3 mask trigger */ |
205 | 205 | ||
206 | /* Clock & Power Management */ | 206 | /* Clock & Power Management */ |
207 | 207 | ||
208 | #define LOCKTIME (*(volatile int *)0x4C000000) /* PLL lock time counter */ | 208 | #define LOCKTIME (*(volatile unsigned long *)0x4C000000) /* PLL lock time counter */ |
209 | #define MPLLCON (*(volatile int *)0x4C000004) /* MPLL control */ | 209 | #define MPLLCON (*(volatile unsigned long *)0x4C000004) /* MPLL control */ |
210 | #define UPLLCON (*(volatile int *)0x4C000008) /* UPLL control */ | 210 | #define UPLLCON (*(volatile unsigned long *)0x4C000008) /* UPLL control */ |
211 | #define CLKCON (*(volatile int *)0x4C00000C) /* Clock generator control */ | 211 | #define CLKCON (*(volatile unsigned long *)0x4C00000C) /* Clock generator control */ |
212 | #define CLKSLOW (*(volatile int *)0x4C000010) /* Slow clock control */ | 212 | #define CLKSLOW (*(volatile unsigned long *)0x4C000010) /* Slow clock control */ |
213 | #define CLKDIVN (*(volatile int *)0x4C000014) /* Clock divider control */ | 213 | #define CLKDIVN (*(volatile unsigned long *)0x4C000014) /* Clock divider control */ |
214 | #define CAMDIVN (*(volatile int *)0x4C000018) /* Camera clock divider control */ | 214 | #define CAMDIVN (*(volatile unsigned long *)0x4C000018) /* Camera clock divider control */ |
215 | 215 | ||
216 | /* LCD Controller */ | 216 | /* LCD Controller */ |
217 | 217 | ||
218 | #define LCDCON1 (*(volatile int *)0x4D000000) /* LCD control 1 */ | 218 | #define LCDCON1 (*(volatile unsigned long *)0x4D000000) /* LCD control 1 */ |
219 | #define LCDCON2 (*(volatile int *)0x4D000004) /* LCD control 2 */ | 219 | #define LCDCON2 (*(volatile unsigned long *)0x4D000004) /* LCD control 2 */ |
220 | #define LCDCON3 (*(volatile int *)0x4D000008) /* LCD control 3 */ | 220 | #define LCDCON3 (*(volatile unsigned long *)0x4D000008) /* LCD control 3 */ |
221 | #define LCDCON4 (*(volatile int *)0x4D00000C) /* LCD control 4 */ | 221 | #define LCDCON4 (*(volatile unsigned long *)0x4D00000C) /* LCD control 4 */ |
222 | #define LCDCON5 (*(volatile int *)0x4D000010) /* LCD control 5 */ | 222 | #define LCDCON5 (*(volatile unsigned long *)0x4D000010) /* LCD control 5 */ |
223 | #define LCDSADDR1 (*(volatile int *)0x4D000014) /* STN/TFT: frame buffer start address 1 */ | 223 | #define LCDSADDR1 (*(volatile unsigned long *)0x4D000014) /* STN/TFT: frame buffer start address 1 */ |
224 | #define LCDSADDR2 (*(volatile int *)0x4D000018) /* STN/TFT: frame buffer start address 2 */ | 224 | #define LCDSADDR2 (*(volatile unsigned long *)0x4D000018) /* STN/TFT: frame buffer start address 2 */ |
225 | #define LCDSADDR3 (*(volatile int *)0x4D00001C) /* STN/TFT: virtual screen address set */ | 225 | #define LCDSADDR3 (*(volatile unsigned long *)0x4D00001C) /* STN/TFT: virtual screen address set */ |
226 | #define REDLUT (*(volatile int *)0x4D000020) /* STN: red lookup table */ | 226 | #define REDLUT (*(volatile unsigned long *)0x4D000020) /* STN: red lookup table */ |
227 | #define GREENLUT (*(volatile int *)0x4D000024) /* STN: green lookup table */ | 227 | #define GREENLUT (*(volatile unsigned long *)0x4D000024) /* STN: green lookup table */ |
228 | #define BLUELUT (*(volatile int *)0x4D000028) /* STN: blue lookup table */ | 228 | #define BLUELUT (*(volatile unsigned long *)0x4D000028) /* STN: blue lookup table */ |
229 | #define DITHMODE (*(volatile int *)0x4D00004C) /* STN: dithering mode */ | 229 | #define DITHMODE (*(volatile unsigned long *)0x4D00004C) /* STN: dithering mode */ |
230 | #define TPAL (*(volatile int *)0x4D000050) /* TFT: temporary palette */ | 230 | #define TPAL (*(volatile unsigned long *)0x4D000050) /* TFT: temporary palette */ |
231 | #define LCDINTPND (*(volatile int *)0x4D000054) /* LCD interrupt pending */ | 231 | #define LCDINTPND (*(volatile unsigned long *)0x4D000054) /* LCD interrupt pending */ |
232 | #define LCDSRCPND (*(volatile int *)0x4D000058) /* LCD interrupt source */ | 232 | #define LCDSRCPND (*(volatile unsigned long *)0x4D000058) /* LCD interrupt source */ |
233 | #define LCDINTMSK (*(volatile int *)0x4D00005C) /* LCD interrupt mask */ | 233 | #define LCDINTMSK (*(volatile unsigned long *)0x4D00005C) /* LCD interrupt mask */ |
234 | #define TCONSEL (*(volatile int *)0x4D000060) /* TCON(LPC3600/LCC3600) control */ | 234 | #define TCONSEL (*(volatile unsigned long *)0x4D000060) /* TCON(LPC3600/LCC3600) control */ |
235 | 235 | ||
236 | /* NAND Flash */ | 236 | /* NAND Flash */ |
237 | 237 | ||
238 | #define NFCONF (*(volatile int *)0x4E000000) /* NAND flash configuration */ | 238 | #define NFCONF (*(volatile unsigned long *)0x4E000000) /* NAND flash configuration */ |
239 | #define NFCONT (*(volatile int *)0x4E000004) /* NAND flash control */ | 239 | #define NFCONT (*(volatile unsigned long *)0x4E000004) /* NAND flash control */ |
240 | #define NFCMD (*(volatile int *)0x4E000008) /* NAND flash command */ | 240 | #define NFCMD (*(volatile unsigned long *)0x4E000008) /* NAND flash command */ |
241 | #define NFADDR (*(volatile int *)0x4E00000C) /* NAND flash address */ | 241 | #define NFADDR (*(volatile unsigned long *)0x4E00000C) /* NAND flash address */ |
242 | #define NFDATA (*(volatile int *)0x4E000010) /* NAND flash data */ | 242 | #define NFDATA (*(volatile unsigned long *)0x4E000010) /* NAND flash data */ |
243 | #define NFMECC0 (*(volatile int *)0x4E000014) /* NAND flash main area ECC0/1 */ | 243 | #define NFMECC0 (*(volatile unsigned long *)0x4E000014) /* NAND flash main area ECC0/1 */ |
244 | #define NFMECC1 (*(volatile int *)0x4E000018) /* NAND flash main area ECC2/3 */ | 244 | #define NFMECC1 (*(volatile unsigned long *)0x4E000018) /* NAND flash main area ECC2/3 */ |
245 | #define NFSECC (*(volatile int *)0x4E00001C) /* NAND flash spare area ECC */ | 245 | #define NFSECC (*(volatile unsigned long *)0x4E00001C) /* NAND flash spare area ECC */ |
246 | #define NFSTAT (*(volatile int *)0x4E000020) /* NAND flash operation status */ | 246 | #define NFSTAT (*(volatile unsigned long *)0x4E000020) /* NAND flash operation status */ |
247 | #define NFESTAT0 (*(volatile int *)0x4E000024) /* NAND flash ECC status for I/O[7:0] */ | 247 | #define NFESTAT0 (*(volatile unsigned long *)0x4E000024) /* NAND flash ECC status for I/O[7:0] */ |
248 | #define NFESTAT1 (*(volatile int *)0x4E000028) /* NAND flash ECC status for I/O[15:8] */ | 248 | #define NFESTAT1 (*(volatile unsigned long *)0x4E000028) /* NAND flash ECC status for I/O[15:8] */ |
249 | #define NFMECCSTAT0 (*(volatile int *)0x4E00002C) /* NAND flash main area ECC0 status */ | 249 | #define NFMECCSTAT0 (*(volatile unsigned long *)0x4E00002C) /* NAND flash main area ECC0 status */ |
250 | #define NFMECCSTAT1 (*(volatile int *)0x4E000030) /* NAND flash main area ECC1 status */ | 250 | #define NFMECCSTAT1 (*(volatile unsigned long *)0x4E000030) /* NAND flash main area ECC1 status */ |
251 | #define NFSECCSTAT (*(volatile int *)0x4E000034) /* NAND flash spare area ECC status */ | 251 | #define NFSECCSTAT (*(volatile unsigned long *)0x4E000034) /* NAND flash spare area ECC status */ |
252 | #define NFSBLK (*(volatile int *)0x4E000038) /* NAND flash start block address */ | 252 | #define NFSBLK (*(volatile unsigned long *)0x4E000038) /* NAND flash start block address */ |
253 | #define NFEBLK (*(volatile int *)0x4E00003C) /* NAND flash end block address */ | 253 | #define NFEBLK (*(volatile unsigned long *)0x4E00003C) /* NAND flash end block address */ |
254 | 254 | ||
255 | /* Camera Interface */ | 255 | /* Camera Interface */ |
256 | 256 | ||
257 | #define CISRCFMT (*(volatile int *)0x4F000000) /* Input source format */ | 257 | #define CISRCFMT (*(volatile unsigned long *)0x4F000000) /* Input source format */ |
258 | #define CIWDOFST (*(volatile int *)0x4F000004) /* Window offset register */ | 258 | #define CIWDOFST (*(volatile unsigned long *)0x4F000004) /* Window offset register */ |
259 | #define CIGCTRL (*(volatile int *)0x4F000008) /* Global control register */ | 259 | #define CIGCTRL (*(volatile unsigned long *)0x4F000008) /* Global control register */ |
260 | #define CICOYSA1 (*(volatile int *)0x4F000018) /* Y 1st frame start address for codec DMA */ | 260 | #define CICOYSA1 (*(volatile unsigned long *)0x4F000018) /* Y 1st frame start address for codec DMA */ |
261 | #define CICOYSA2 (*(volatile int *)0x4F00001C) /* Y 2nd frame start address for codec DMA */ | 261 | #define CICOYSA2 (*(volatile unsigned long *)0x4F00001C) /* Y 2nd frame start address for codec DMA */ |
262 | #define CICOYSA3 (*(volatile int *)0x4F000020) /* Y 3nd frame start address for codec DMA */ | 262 | #define CICOYSA3 (*(volatile unsigned long *)0x4F000020) /* Y 3nd frame start address for codec DMA */ |
263 | #define CICOYSA4 (*(volatile int *)0x4F000024) /* Y 4th frame start address for codec DMA */ | 263 | #define CICOYSA4 (*(volatile unsigned long *)0x4F000024) /* Y 4th frame start address for codec DMA */ |
264 | #define CICOCBSA1 (*(volatile int *)0x4F000028) /* Cb 1st frame start address for codec DMA */ | 264 | #define CICOCBSA1 (*(volatile unsigned long *)0x4F000028) /* Cb 1st frame start address for codec DMA */ |
265 | #define CICOCBSA2 (*(volatile int *)0x4F00002C) /* Cb 2nd frame start address for codec DMA */ | 265 | #define CICOCBSA2 (*(volatile unsigned long *)0x4F00002C) /* Cb 2nd frame start address for codec DMA */ |
266 | #define CICOCBSA3 (*(volatile int *)0x4F000030) /* Cb 3nd frame start address for codec DMA */ | 266 | #define CICOCBSA3 (*(volatile unsigned long *)0x4F000030) /* Cb 3nd frame start address for codec DMA */ |
267 | #define CICOCBSA4 (*(volatile int *)0x4F000034) /* Cb 4th frame start address for codec DMA */ | 267 | #define CICOCBSA4 (*(volatile unsigned long *)0x4F000034) /* Cb 4th frame start address for codec DMA */ |
268 | #define CICOCRSA1 (*(volatile int *)0x4F000038) /* Cr 1st frame start address for codec DMA */ | 268 | #define CICOCRSA1 (*(volatile unsigned long *)0x4F000038) /* Cr 1st frame start address for codec DMA */ |
269 | #define CICOCRSA2 (*(volatile int *)0x4F00003C) /* Cr 2nd frame start address for codec DMA */ | 269 | #define CICOCRSA2 (*(volatile unsigned long *)0x4F00003C) /* Cr 2nd frame start address for codec DMA */ |
270 | #define CICOCRSA3 (*(volatile int *)0x4F000040) /* Cr 3nd frame start address for codec DMA */ | 270 | #define CICOCRSA3 (*(volatile unsigned long *)0x4F000040) /* Cr 3nd frame start address for codec DMA */ |
271 | #define CICOCRSA4 (*(volatile int *)0x4F000044) /* Cr 4th frame start address for codec DMA */ | 271 | #define CICOCRSA4 (*(volatile unsigned long *)0x4F000044) /* Cr 4th frame start address for codec DMA */ |
272 | #define CICOTRGFMT (*(volatile int *)0x4F000048) /* Target image format of codec DMA */ | 272 | #define CICOTRGFMT (*(volatile unsigned long *)0x4F000048) /* Target image format of codec DMA */ |
273 | #define CICOCTRL (*(volatile int *)0x4F00004C | 273 | #define CICOCTRL (*(volatile unsigned long *)0x4F00004C) |
274 | 274 | ||
275 | /* Codec DMA control related */ | 275 | /* Codec DMA control related */ |
276 | 276 | ||
277 | #define CICOSCPRERATIO (*(volatile int *)0x4F000050) /* Codec pre-scaler ratio control */ | 277 | #define CICOSCPRERATIO (*(volatile unsigned long *)0x4F000050) /* Codec pre-scaler ratio control */ |
278 | #define CICOSCPREDST (*(volatile int *)0x4F000054) /* Codec pre-scaler destination format */ | 278 | #define CICOSCPREDST (*(volatile unsigned long *)0x4F000054) /* Codec pre-scaler destination format */ |
279 | #define CICOSCCTRL (*(volatile int *)0x4F000058) /* Codec main-scaler control */ | 279 | #define CICOSCCTRL (*(volatile unsigned long *)0x4F000058) /* Codec main-scaler control */ |
280 | #define CICOTAREA (*(volatile int *)0x4F00005C) /* Codec scaler target area */ | 280 | #define CICOTAREA (*(volatile unsigned long *)0x4F00005C) /* Codec scaler target area */ |
281 | #define CICOSTATUS (*(volatile int *)0x4F000064) /* Codec path status */ | 281 | #define CICOSTATUS (*(volatile unsigned long *)0x4F000064) /* Codec path status */ |
282 | #define CIPRCLRSA1 (*(volatile int *)0x4F00006C) /* RGB 1st frame start address for preview DMA */ | 282 | #define CIPRCLRSA1 (*(volatile unsigned long *)0x4F00006C) /* RGB 1st frame start address for preview DMA */ |
283 | #define CIPRCLRSA2 (*(volatile int *)0x4F000070) /* RGB 2nd frame start address for preview DMA */ | 283 | #define CIPRCLRSA2 (*(volatile unsigned long *)0x4F000070) /* RGB 2nd frame start address for preview DMA */ |
284 | #define CIPRCLRSA3 (*(volatile int *)0x4F000074) /* RGB 3nd frame start address for preview DMA */ | 284 | #define CIPRCLRSA3 (*(volatile unsigned long *)0x4F000074) /* RGB 3nd frame start address for preview DMA */ |
285 | #define CIPRCLRSA4 (*(volatile int *)0x4F000078) /* RGB 4th frame start address for preview DMA */ | 285 | #define CIPRCLRSA4 (*(volatile unsigned long *)0x4F000078) /* RGB 4th frame start address for preview DMA */ |
286 | #define CIPRTRGFMT (*(volatile int *)0x4F00007C) /* Target image format of preview DMA */ | 286 | #define CIPRTRGFMT (*(volatile unsigned long *)0x4F00007C) /* Target image format of preview DMA */ |
287 | #define CIPRCTRL (*(volatile int *)0x4F000080) /* Preview DMA control related */ | 287 | #define CIPRCTRL (*(volatile unsigned long *)0x4F000080) /* Preview DMA control related */ |
288 | #define CIPRSCPRERATIO (*(volatile int *)0x4F000084) /* Preview pre-scaler ratio control */ | 288 | #define CIPRSCPRERATIO (*(volatile unsigned long *)0x4F000084) /* Preview pre-scaler ratio control */ |
289 | #define CIPRSCPREDST (*(volatile int *)0x4F000088) /* Preview pre-scaler destination format */ | 289 | #define CIPRSCPREDST (*(volatile unsigned long *)0x4F000088) /* Preview pre-scaler destination format */ |
290 | #define CIPRSCCTRL (*(volatile int *)0x4F00008C) /* Preview main-scaler control */ | 290 | #define CIPRSCCTRL (*(volatile unsigned long *)0x4F00008C) /* Preview main-scaler control */ |
291 | #define CIPRTAREA (*(volatile int *)0x4F000090) /* Preview scaler target area */ | 291 | #define CIPRTAREA (*(volatile unsigned long *)0x4F000090) /* Preview scaler target area */ |
292 | #define CIPRSTATUS (*(volatile int *)0x4F000098) /* Preview path status */ | 292 | #define CIPRSTATUS (*(volatile unsigned long *)0x4F000098) /* Preview path status */ |
293 | #define CIIMGCPT (*(volatile int *)0x4F0000A0) /* Image capture enable command */ | 293 | #define CIIMGCPT (*(volatile unsigned long *)0x4F0000A0) /* Image capture enable command */ |
294 | 294 | ||
295 | /* UART */ | 295 | /* UART */ |
296 | 296 | ||
297 | #define ULCON0 (*(volatile int *)0x50000000) /* UART 0 line control */ | 297 | #define ULCON0 (*(volatile unsigned long *)0x50000000) /* UART 0 line control */ |
298 | #define UCON0 (*(volatile int *)0x50000004) /* UART 0 control */ | 298 | #define UCON0 (*(volatile unsigned long *)0x50000004) /* UART 0 control */ |
299 | #define UFCON0 (*(volatile int *)0x50000008) /* UART 0 FIFO control */ | 299 | #define UFCON0 (*(volatile unsigned long *)0x50000008) /* UART 0 FIFO control */ |
300 | #define UMCON0 (*(volatile int *)0x5000000C) /* UART 0 modem control */ | 300 | #define UMCON0 (*(volatile unsigned long *)0x5000000C) /* UART 0 modem control */ |
301 | #define UTRSTAT0 (*(volatile int *)0x50000010) /* UART 0 Tx/Rx status */ | 301 | #define UTRSTAT0 (*(volatile unsigned long *)0x50000010) /* UART 0 Tx/Rx status */ |
302 | #define UERSTAT0 (*(volatile int *)0x50000014) /* UART 0 Rx error status */ | 302 | #define UERSTAT0 (*(volatile unsigned long *)0x50000014) /* UART 0 Rx error status */ |
303 | #define UFSTAT0 (*(volatile int *)0x50000018) /* UART 0 FIFO status */ | 303 | #define UFSTAT0 (*(volatile unsigned long *)0x50000018) /* UART 0 FIFO status */ |
304 | #define UMSTAT0 (*(volatile int *)0x5000001C) /* UART 0 modem status */ | 304 | #define UMSTAT0 (*(volatile unsigned long *)0x5000001C) /* UART 0 modem status */ |
305 | #define UTXH0 (*(volatile char *)0x50000020) /* UART 0 transmission hold */ | 305 | #define UTXH0 (*(volatile unsigned char *)0x50000020) /* UART 0 transmission hold */ |
306 | #define URXH0 (*(volatile char *)0x50000024) /* UART 0 receive buffer */ | 306 | #define URXH0 (*(volatile unsigned char *)0x50000024) /* UART 0 receive buffer */ |
307 | #define UBRDIV0 (*(volatile int *)0x50000028) /* UART 0 baud rate divisor */ | 307 | #define UBRDIV0 (*(volatile unsigned long *)0x50000028) /* UART 0 baud rate divisor */ |
308 | #define ULCON1 (*(volatile int *)0x50004000) /* UART 1 line control */ | 308 | #define ULCON1 (*(volatile unsigned long *)0x50004000) /* UART 1 line control */ |
309 | #define UCON1 (*(volatile int *)0x50004004) /* UART 1 control */ | 309 | #define UCON1 (*(volatile unsigned long *)0x50004004) /* UART 1 control */ |
310 | #define UFCON1 (*(volatile int *)0x50004008) /* UART 1 FIFO control */ | 310 | #define UFCON1 (*(volatile unsigned long *)0x50004008) /* UART 1 FIFO control */ |
311 | #define UMCON1 (*(volatile int *)0x5000400C) /* UART 1 modem control */ | 311 | #define UMCON1 (*(volatile unsigned long *)0x5000400C) /* UART 1 modem control */ |
312 | #define UTRSTAT1 (*(volatile int *)0x50004010) /* UART 1 Tx/Rx status */ | 312 | #define UTRSTAT1 (*(volatile unsigned long *)0x50004010) /* UART 1 Tx/Rx status */ |
313 | #define UERSTAT1 (*(volatile int *)0x50004014) /* UART 1 Rx error status */ | 313 | #define UERSTAT1 (*(volatile unsigned long *)0x50004014) /* UART 1 Rx error status */ |
314 | #define UFSTAT1 (*(volatile int *)0x50004018) /* UART 1 FIFO status */ | 314 | #define UFSTAT1 (*(volatile unsigned long *)0x50004018) /* UART 1 FIFO status */ |
315 | #define UMSTAT1 (*(volatile int *)0x5000401C) /* UART 1 modem status */ | 315 | #define UMSTAT1 (*(volatile unsigned long *)0x5000401C) /* UART 1 modem status */ |
316 | #define UTXH1 (*(volatile char*)0x50004020) /* UART 1 transmission hold */ | 316 | #define UTXH1 (*(volatile unsigned char*)0x50004020) /* UART 1 transmission hold */ |
317 | #define URXH1 (*(volatile char*)0x50004024) /* UART 1 receive buffer */ | 317 | #define URXH1 (*(volatile unsigned char*)0x50004024) /* UART 1 receive buffer */ |
318 | #define UBRDIV1 (*(volatile int *)0x50004028) /* UART 1 baud rate divisor */ | 318 | #define UBRDIV1 (*(volatile unsigned long *)0x50004028) /* UART 1 baud rate divisor */ |
319 | #define ULCON2 (*(volatile int *)0x50008000) /* UART 2 line control */ | 319 | #define ULCON2 (*(volatile unsigned long *)0x50008000) /* UART 2 line control */ |
320 | #define UCON2 (*(volatile int *)0x50008004) /* UART 2 control */ | 320 | #define UCON2 (*(volatile unsigned long *)0x50008004) /* UART 2 control */ |
321 | #define UFCON2 (*(volatile int *)0x50008008) /* UART 2 FIFO control */ | 321 | #define UFCON2 (*(volatile unsigned long *)0x50008008) /* UART 2 FIFO control */ |
322 | #define UTRSTAT2 (*(volatile int *)0x50008010) /* UART 2 Tx/Rx status */ | 322 | #define UTRSTAT2 (*(volatile unsigned long *)0x50008010) /* UART 2 Tx/Rx status */ |
323 | #define UERSTAT2 (*(volatile int *)0x50008014) /* UART 2 Rx error status */ | 323 | #define UERSTAT2 (*(volatile unsigned long *)0x50008014) /* UART 2 Rx error status */ |
324 | #define UFSTAT2 (*(volatile int *)0x50008018) /* UART 2 FIFO status */ | 324 | #define UFSTAT2 (*(volatile unsigned long *)0x50008018) /* UART 2 FIFO status */ |
325 | #define UTXH2 (*(volatile char*)0x50008020) /* UART 2 transmission hold */ | 325 | #define UTXH2 (*(volatile unsigned char*)0x50008020) /* UART 2 transmission hold */ |
326 | #define URXH2 (*(volatile char*)0x50008024) /* UART 2 receive buffer */ | 326 | #define URXH2 (*(volatile unsigned char*)0x50008024) /* UART 2 receive buffer */ |
327 | #define UBRDIV2 (*(volatile int *)0x50008028) /* UART 2 baud rate divisor */ | 327 | #define UBRDIV2 (*(volatile unsigned long *)0x50008028) /* UART 2 baud rate divisor */ |
328 | 328 | ||
329 | /* PWM Timer */ | 329 | /* PWM Timer */ |
330 | 330 | ||
331 | #define TCFG0 (*(volatile int *)0x51000000) /* Timer configuration */ | 331 | #define TCFG0 (*(volatile unsigned long *)0x51000000) /* Timer configuration */ |
332 | #define TCFG1 (*(volatile int *)0x51000004) /* Timer configuration */ | 332 | #define TCFG1 (*(volatile unsigned long *)0x51000004) /* Timer configuration */ |
333 | #define TCON (*(volatile int *)0x51000008) /* Timer control */ | 333 | #define TCON (*(volatile unsigned long *)0x51000008) /* Timer control */ |
334 | #define TCNTB0 (*(volatile int *)0x5100000C) /* Timer count buffer 0 */ | 334 | #define TCNTB0 (*(volatile unsigned long *)0x5100000C) /* Timer count buffer 0 */ |
335 | #define TCMPB0 (*(volatile int *)0x51000010) /* Timer compare buffer 0 */ | 335 | #define TCMPB0 (*(volatile unsigned long *)0x51000010) /* Timer compare buffer 0 */ |
336 | #define TCNTO0 (*(volatile int *)0x51000014) /* Timer count observation 0 */ | 336 | #define TCNTO0 (*(volatile unsigned long *)0x51000014) /* Timer count observation 0 */ |
337 | #define TCNTB1 (*(volatile int *)0x51000018) /* Timer count buffer 1 */ | 337 | #define TCNTB1 (*(volatile unsigned long *)0x51000018) /* Timer count buffer 1 */ |
338 | #define TCMPB1 (*(volatile int *)0x5100001C) /* Timer compare buffer 1 */ | 338 | #define TCMPB1 (*(volatile unsigned long *)0x5100001C) /* Timer compare buffer 1 */ |
339 | #define TCNTO1 (*(volatile int *)0x51000020) /* Timer count observation 1 */ | 339 | #define TCNTO1 (*(volatile unsigned long *)0x51000020) /* Timer count observation 1 */ |
340 | #define TCNTB2 (*(volatile int *)0x51000024) /* Timer count buffer 2 */ | 340 | #define TCNTB2 (*(volatile unsigned long *)0x51000024) /* Timer count buffer 2 */ |
341 | #define TCMPB2 (*(volatile int *)0x51000028) /* Timer compare buffer 2 */ | 341 | #define TCMPB2 (*(volatile unsigned long *)0x51000028) /* Timer compare buffer 2 */ |
342 | #define TCNTO2 (*(volatile int *)0x5100002C) /* Timer count observation 2 */ | 342 | #define TCNTO2 (*(volatile unsigned long *)0x5100002C) /* Timer count observation 2 */ |
343 | #define TCNTB3 (*(volatile int *)0x51000030) /* Timer count buffer 3 */ | 343 | #define TCNTB3 (*(volatile unsigned long *)0x51000030) /* Timer count buffer 3 */ |
344 | #define TCMPB3 (*(volatile int *)0x51000034) /* Timer compare buffer 3 */ | 344 | #define TCMPB3 (*(volatile unsigned long *)0x51000034) /* Timer compare buffer 3 */ |
345 | #define TCNTO3 (*(volatile int *)0x51000038) /* Timer count observation 3 */ | 345 | #define TCNTO3 (*(volatile unsigned long *)0x51000038) /* Timer count observation 3 */ |
346 | #define TCNTB4 (*(volatile int *)0x5100003C) /* Timer count buffer 4 */ | 346 | #define TCNTB4 (*(volatile unsigned long *)0x5100003C) /* Timer count buffer 4 */ |
347 | #define TCNTO4 (*(volatile int *)0x51000040) /* Timer count observation 4 */ | 347 | #define TCNTO4 (*(volatile unsigned long *)0x51000040) /* Timer count observation 4 */ |
348 | 348 | ||
349 | /* USB Device */ | 349 | /* USB Device */ |
350 | 350 | ||
351 | #define FUNC_ADDR_REG (*(volatile char *)0x52000140) /* Function address */ | 351 | #define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) /* Function address */ |
352 | #define PWR_REG (*(volatile char *)0x52000144) /* Power management */ | 352 | #define PWR_REG (*(volatile unsigned char *)0x52000144) /* Power management */ |
353 | #define EP_INT_REG (*(volatile char *)0x52000148) /* EP interrupt pending and clear */ | 353 | #define EP_INT_REG (*(volatile unsigned char *)0x52000148) /* EP interrupt pending and clear */ |
354 | #define USB_INT_REG (*(volatile char *)0x52000158) /* USB interrupt pending and clear */ | 354 | #define USB_INT_REG (*(volatile unsigned char *)0x52000158) /* USB interrupt pending and clear */ |
355 | #define EP_INT_EN_REG (*(volatile char *)0x5200015C) /* Interrupt enable */ | 355 | #define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015C) /* Interrupt enable */ |
356 | #define USB_INT_EN_REG (*(volatile char *)0x5200016C) /* Interrupt enable */ | 356 | #define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016C) /* Interrupt enable */ |
357 | #define FRAME_NUM1_REG (*(volatile char *)0x52000170) /* Frame number lower byte */ | 357 | #define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) /* Frame number lower byte */ |
358 | #define FRAME_NUM2_REG (*(volatile char *)0x52000174) /* Frame number higher byte */ | 358 | #define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) /* Frame number higher byte */ |
359 | #define INDEX_REG (*(volatile char *)0x52000178) /* Register index */ | 359 | #define INDEX_REG (*(volatile unsigned char *)0x52000178) /* Register index */ |
360 | #define EP0_CSR (*(volatile char *)0x52000184) /* Endpoint 0 status */ | 360 | #define EP0_CSR (*(volatile unsigned char *)0x52000184) /* Endpoint 0 status */ |
361 | #define IN_CSR1_REG (*(volatile char *)0x52000184) /* In endpoint control status */ | 361 | #define IN_CSR1_REG (*(volatile unsigned char *)0x52000184) /* In endpoint control status */ |
362 | #define IN_CSR2_REG (*(volatile char *)0x52000188) /* In endpoint control status */ | 362 | #define IN_CSR2_REG (*(volatile unsigned char *)0x52000188) /* In endpoint control status */ |
363 | #define MAXP_REG (*(volatile char *)0x52000180) /* Endpoint max packet */ | 363 | #define MAXP_REG (*(volatile unsigned char *)0x52000180) /* Endpoint max packet */ |
364 | #define OUT_CSR1_REG (*(volatile char *)0x52000190) /* Out endpoint control status */ | 364 | #define OUT_CSR1_REG (*(volatile unsigned char *)0x52000190) /* Out endpoint control status */ |
365 | #define OUT_CSR2_REG (*(volatile char *)0x52000194) /* Out endpoint control status */ | 365 | #define OUT_CSR2_REG (*(volatile unsigned char *)0x52000194) /* Out endpoint control status */ |
366 | #define OUT_FIFO_CNT1_REG (*(volatile char *)0x52000198) /* Endpoint out write count */ | 366 | #define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) /* Endpoint out write count */ |
367 | #define OUT_FIFO_CNT2_REG (*(volatile char *)0x5200019C) /* Endpoint out write count */ | 367 | #define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019C) /* Endpoint out write count */ |
368 | #define EP0_FIFO (*(volatile char *)0x520001C0) /* Endpoint 0 FIFO */ | 368 | #define EP0_FIFO (*(volatile unsigned char *)0x520001C0) /* Endpoint 0 FIFO */ |
369 | #define EP1_FIFO (*(volatile char *)0x520001C4) /* Endpoint 1 FIFO */ | 369 | #define EP1_FIFO (*(volatile unsigned char *)0x520001C4) /* Endpoint 1 FIFO */ |
370 | #define EP2_FIFO (*(volatile char *)0x520001C8) /* Endpoint 2 FIFO */ | 370 | #define EP2_FIFO (*(volatile unsigned char *)0x520001C8) /* Endpoint 2 FIFO */ |
371 | #define EP3_FIFO (*(volatile char *)0x520001CC) /* Endpoint 3 FIFO */ | 371 | #define EP3_FIFO (*(volatile unsigned char *)0x520001CC) /* Endpoint 3 FIFO */ |
372 | #define EP4_FIFO (*(volatile char *)0x520001D0) /* Endpoint 4 FIFO */ | 372 | #define EP4_FIFO (*(volatile unsigned char *)0x520001D0) /* Endpoint 4 FIFO */ |
373 | #define EP1_DMA_CON (*(volatile char *)0x52000200) /* EP1 DMA Interface control */ | 373 | #define EP1_DMA_CON (*(volatile unsigned char *)0x52000200) /* EP1 DMA Interface control */ |
374 | #define EP1_DMA_UNIT (*(volatile char *)0x52000204) /* EP1 DMA Tx unit counter */ | 374 | #define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) /* EP1 DMA Tx unit counter */ |
375 | #define EP1_DMA_FIFO (*(volatile char *)0x52000208) /* EP1 DMA Tx FIFO counter */ | 375 | #define EP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) /* EP1 DMA Tx FIFO counter */ |
376 | #define EP1_DMA_TTC_L (*(volatile char *)0x5200020C) /* EP1 DMA Total Tx counter */ | 376 | #define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020C) /* EP1 DMA Total Tx counter */ |
377 | #define EP1_DMA_TTC_M (*(volatile char *)0x52000210) /* EP1 DMA Total Tx counter */ | 377 | #define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210) /* EP1 DMA Total Tx counter */ |
378 | #define EP1_DMA_TTC_H (*(volatile char *)0x52000214) /* EP1 DMA Total Tx counter */ | 378 | #define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214) /* EP1 DMA Total Tx counter */ |
379 | #define EP2_DMA_CON (*(volatile char *)0x52000218) /* EP2 DMA interface control */ | 379 | #define EP2_DMA_CON (*(volatile unsigned char *)0x52000218) /* EP2 DMA interface control */ |
380 | #define EP2_DMA_UNIT (*(volatile char *)0x5200021C) /* EP2 DMA Tx Unit counter */ | 380 | #define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021C) /* EP2 DMA Tx Unit counter */ |
381 | #define EP2_DMA_FIFO (*(volatile char *)0x52000220) /* EP2 DMA Tx FIFO counter */ | 381 | #define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) /* EP2 DMA Tx FIFO counter */ |
382 | #define EP2_DMA_TTC_L (*(volatile char *)0x52000224) /* EP2 DMA total Tx counter */ | 382 | #define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) /* EP2 DMA total Tx counter */ |
383 | #define EP2_DMA_TTC_M (*(volatile char *)0x52000228) /* EP2 DMA total Tx counter */ | 383 | #define EP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228) /* EP2 DMA total Tx counter */ |
384 | #define EP2_DMA_TTC_H (*(volatile char *)0x5200022C) /* EP2 DMA Total Tx counter */ | 384 | #define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022C) /* EP2 DMA Total Tx counter */ |
385 | #define EP3_DMA_CON (*(volatile char *)0x52000240) /* EP3 DMA Interface control */ | 385 | #define EP3_DMA_CON (*(volatile unsigned char *)0x52000240) /* EP3 DMA Interface control */ |
386 | #define EP3_DMA_UNIT (*(volatile char *)0x52000244) /* EP3 DMA Tx Unit counter */ | 386 | #define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) /* EP3 DMA Tx Unit counter */ |
387 | #define EP3_DMA_FIFO (*(volatile char *)0x52000248) /* EP3 DMA Tx FIFO counter */ | 387 | #define EP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) /* EP3 DMA Tx FIFO counter */ |
388 | #define EP3_DMA_TTC_L (*(volatile char *)0x5200024C) /* EP3 DMA Total Tx counter */ | 388 | #define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024C) /* EP3 DMA Total Tx counter */ |
389 | #define EP3_DMA_TTC_M (*(volatile char *)0x52000250) /* EP3 DMA Total Tx counter */ | 389 | #define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250) /* EP3 DMA Total Tx counter */ |
390 | #define EP3_DMA_TTC_H (*(volatile char *)0x52000254) /* EP3 DMA Total Tx counter */ | 390 | #define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254) /* EP3 DMA Total Tx counter */ |
391 | #define EP4_DMA_CON (*(volatile char *)0x52000258) /* EP4 DMA Interface control */ | 391 | #define EP4_DMA_CON (*(volatile unsigned char *)0x52000258) /* EP4 DMA Interface control */ |
392 | #define EP4_DMA_UNIT (*(volatile char *)0x5200025C) /* EP4 DMA Tx Unit counter */ | 392 | #define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025C) /* EP4 DMA Tx Unit counter */ |
393 | #define EP4_DMA_FIFO (*(volatile char *)0x52000260) /* EP4 DMA Tx FIFO counter */ | 393 | #define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) /* EP4 DMA Tx FIFO counter */ |
394 | #define EP4_DMA_TTC_L (*(volatile char *)0x52000264) /* EP4 DMA Total Tx counter */ | 394 | #define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) /* EP4 DMA Total Tx counter */ |
395 | #define EP4_DMA_TTC_M (*(volatile char *)0x52000268) /* EP4 DMA Total Tx counter */ | 395 | #define EP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268) /* EP4 DMA Total Tx counter */ |
396 | #define EP4_DMA_TTC_H (*(volatile char *)0x5200026C) /* EP4 DMA Total Tx counter */ | 396 | #define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026C) /* EP4 DMA Total Tx counter */ |
397 | 397 | ||
398 | /* Watchdog Timer */ | 398 | /* Watchdog Timer */ |
399 | 399 | ||
400 | #define WTCON (*(volatile int *)0x53000000) /* Watchdog timer mode */ | 400 | #define WTCON (*(volatile unsigned long *)0x53000000) /* Watchdog timer mode */ |
401 | #define WTDAT (*(volatile int *)0x53000004) /* Watchdog timer data */ | 401 | #define WTDAT (*(volatile unsigned long *)0x53000004) /* Watchdog timer data */ |
402 | #define WTCNT (*(volatile int *)0x53000008) /* Watchdog timer count */ | 402 | #define WTCNT (*(volatile unsigned long *)0x53000008) /* Watchdog timer count */ |
403 | 403 | ||
404 | /* IIC */ | 404 | /* IIC */ |
405 | 405 | ||
406 | #define IICCON (*(volatile int *)0x54000000) /* IIC control */ | 406 | #define IICCON (*(volatile unsigned long *)0x54000000) /* IIC control */ |
407 | #define IICSTAT (*(volatile int *)0x54000004) /* IIC status */ | 407 | #define IICSTAT (*(volatile unsigned long *)0x54000004) /* IIC status */ |
408 | #define IICADD (*(volatile int *)0x54000008) /* IIC address */ | 408 | #define IICADD (*(volatile unsigned long *)0x54000008) /* IIC address */ |
409 | #define IICDS (*(volatile int *)0x5400000C) /* IIC data shift */ | 409 | #define IICDS (*(volatile unsigned long *)0x5400000C) /* IIC data shift */ |
410 | #define IICLC (*(volatile int *)0x54000010) /* IIC multi-master line control */ | 410 | #define IICLC (*(volatile unsigned long *)0x54000010) /* IIC multi-master line control */ |
411 | 411 | ||
412 | /* IIS */ | 412 | /* IIS */ |
413 | 413 | ||
414 | #define IISCON (*(volatile int *)0x55000000) /* IIS control */ | 414 | #define IISCON (*(volatile unsigned long *)0x55000000) /* IIS control */ |
415 | #define IISMOD (*(volatile int *)0x55000004) /* IIS mode */ | 415 | #define IISMOD (*(volatile unsigned long *)0x55000004) /* IIS mode */ |
416 | #define IISPSR (*(volatile int *)0x55000008) /* IIS prescaler */ | 416 | #define IISPSR (*(volatile unsigned long *)0x55000008) /* IIS prescaler */ |
417 | #define IISFCON (*(volatile int *)0x5500000C) /* IIS FIFO control */ | 417 | #define IISFCON (*(volatile unsigned long *)0x5500000C) /* IIS FIFO control */ |
418 | #define IISFIFO (*(volatile short *)0x55000010) /* IIS FIFO entry */ | 418 | #define IISFIFO (*(volatile unsigned short *)0x55000010) /* IIS FIFO entry */ |
419 | 419 | ||
420 | /* I/O port */ | 420 | /* I/O port */ |
421 | 421 | ||
422 | #define GPACON (*(volatile int *)0x56000000) /* Port A control */ | 422 | #define GPACON (*(volatile unsigned long *)0x56000000) /* Port A control */ |
423 | #define GPADAT (*(volatile int *)0x56000004) /* Port A data */ | 423 | #define GPADAT (*(volatile unsigned long *)0x56000004) /* Port A data */ |
424 | #define GPBCON (*(volatile int *)0x56000010) /* Port B control */ | 424 | #define GPBCON (*(volatile unsigned long *)0x56000010) /* Port B control */ |
425 | #define GPBDAT (*(volatile int *)0x56000014) /* Port B data */ | 425 | #define GPBDAT (*(volatile unsigned long *)0x56000014) /* Port B data */ |
426 | #define GPBUP (*(volatile int *)0x56000018) /* Pull-up control B */ | 426 | #define GPBUP (*(volatile unsigned long *)0x56000018) /* Pull-up control B */ |
427 | #define GPCCON (*(volatile int *)0x56000020) /* Port C control */ | 427 | #define GPCCON (*(volatile unsigned long *)0x56000020) /* Port C control */ |
428 | #define GPCDAT (*(volatile int *)0x56000024) /* Port C data */ | 428 | #define GPCDAT (*(volatile unsigned long *)0x56000024) /* Port C data */ |
429 | #define GPCUP (*(volatile int *)0x56000028) /* Pull-up control C */ | 429 | #define GPCUP (*(volatile unsigned long *)0x56000028) /* Pull-up control C */ |
430 | #define GPDCON (*(volatile int *)0x56000030) /* Port D control */ | 430 | #define GPDCON (*(volatile unsigned long *)0x56000030) /* Port D control */ |
431 | #define GPDDAT (*(volatile int *)0x56000034) /* Port D data */ | 431 | #define GPDDAT (*(volatile unsigned long *)0x56000034) /* Port D data */ |
432 | #define GPDUP (*(volatile int *)0x56000038) /* Pull-up control D */ | 432 | #define GPDUP (*(volatile unsigned long *)0x56000038) /* Pull-up control D */ |
433 | #define GPECON (*(volatile int *)0x56000040) /* Port E control */ | 433 | #define GPECON (*(volatile unsigned long *)0x56000040) /* Port E control */ |
434 | #define GPEDAT (*(volatile int *)0x56000044) /* Port E data */ | 434 | #define GPEDAT (*(volatile unsigned long *)0x56000044) /* Port E data */ |
435 | #define GPEUP (*(volatile int *)0x56000048) /* Pull-up control E */ | 435 | #define GPEUP (*(volatile unsigned long *)0x56000048) /* Pull-up control E */ |
436 | #define GPFCON (*(volatile int *)0x56000050) /* Port F control */ | 436 | #define GPFCON (*(volatile unsigned long *)0x56000050) /* Port F control */ |
437 | #define GPFDAT (*(volatile int *)0x56000054) /* Port F data */ | 437 | #define GPFDAT (*(volatile unsigned long *)0x56000054) /* Port F data */ |
438 | #define GPFUP (*(volatile int *)0x56000058) /* Pull-up control F */ | 438 | #define GPFUP (*(volatile unsigned long *)0x56000058) /* Pull-up control F */ |
439 | #define GPGCON (*(volatile int *)0x56000060) /* Port G control */ | 439 | #define GPGCON (*(volatile unsigned long *)0x56000060) /* Port G control */ |
440 | #define GPGDAT (*(volatile int *)0x56000064) /* Port G data */ | 440 | #define GPGDAT (*(volatile unsigned long *)0x56000064) /* Port G data */ |
441 | #define GPGUP (*(volatile int *)0x56000068) /* Pull-up control G */ | 441 | #define GPGUP (*(volatile unsigned long *)0x56000068) /* Pull-up control G */ |
442 | #define GPHCON (*(volatile int *)0x56000070) /* Port H control */ | 442 | #define GPHCON (*(volatile unsigned long *)0x56000070) /* Port H control */ |
443 | #define GPHDAT (*(volatile int *)0x56000074) /* Port H data */ | 443 | #define GPHDAT (*(volatile unsigned long *)0x56000074) /* Port H data */ |
444 | #define GPHUP (*(volatile int *)0x56000078) /* Pull-up control H */ | 444 | #define GPHUP (*(volatile unsigned long *)0x56000078) /* Pull-up control H */ |
445 | #define MISCCR (*(volatile int *)0x56000080) /* Miscellaneous control */ | 445 | #define MISCCR (*(volatile unsigned long *)0x56000080) /* Miscellaneous control */ |
446 | #define DCLKCON (*(volatile int *)0x56000084) /* DCLK0/1 control */ | 446 | #define DCLKCON (*(volatile unsigned long *)0x56000084) /* DCLK0/1 control */ |
447 | #define EXTINT0 (*(volatile int *)0x56000088) /* External interrupt control register 0 */ | 447 | #define EXTINT0 (*(volatile unsigned long *)0x56000088) /* External interrupt control register 0 */ |
448 | #define EXTINT1 (*(volatile int *)0x5600008C) /* External interrupt control register 1 */ | 448 | #define EXTINT1 (*(volatile unsigned long *)0x5600008C) /* External interrupt control register 1 */ |
449 | #define EXTINT2 (*(volatile int *)0x56000090) /* External interrupt control register 2 */ | 449 | #define EXTINT2 (*(volatile unsigned long *)0x56000090) /* External interrupt control register 2 */ |
450 | #define EINTFLT0 (*(volatile int *)0x56000094) /* Reserved */ | 450 | #define EINTFLT0 (*(volatile unsigned long *)0x56000094) /* Reserved */ |
451 | #define EINTFLT1 (*(volatile int *)0x56000098) /* Reserved */ | 451 | #define EINTFLT1 (*(volatile unsigned long *)0x56000098) /* Reserved */ |
452 | #define EINTFLT2 (*(volatile int *)0x5600009C) /* External interrupt filter control register 2 */ | 452 | #define EINTFLT2 (*(volatile unsigned long *)0x5600009C) /* External interrupt filter control register 2 */ |
453 | #define EINTFLT3 (*(volatile int *)0x560000A0) /* External interrupt filter control register 3 */ | 453 | #define EINTFLT3 (*(volatile unsigned long *)0x560000A0) /* External interrupt filter control register 3 */ |
454 | #define EINTMASK (*(volatile int *)0x560000A4) /* External interrupt mask */ | 454 | #define EINTMASK (*(volatile unsigned long *)0x560000A4) /* External interrupt mask */ |
455 | #define EINTPEND (*(volatile int *)0x560000A8) /* External interrupt pending */ | 455 | #define EINTPEND (*(volatile unsigned long *)0x560000A8) /* External interrupt pending */ |
456 | #define GSTATUS0 (*(volatile int *)0x560000AC) /* External pin status */ | 456 | #define GSTATUS0 (*(volatile unsigned long *)0x560000AC) /* External pin status */ |
457 | #define GSTATUS1 (*(volatile int *)0x560000B0) /* Chip ID */ | 457 | #define GSTATUS1 (*(volatile unsigned long *)0x560000B0) /* Chip ID */ |
458 | #define GSTATUS2 (*(volatile int *)0x560000B4) /* Reset status */ | 458 | #define GSTATUS2 (*(volatile unsigned long *)0x560000B4) /* Reset status */ |
459 | #define GSTATUS3 (*(volatile int *)0x560000B8) /* Inform register */ | 459 | #define GSTATUS3 (*(volatile unsigned long *)0x560000B8) /* Inform register */ |
460 | #define GSTATUS4 (*(volatile int *)0x560000BC) /* Inform register */ | 460 | #define GSTATUS4 (*(volatile unsigned long *)0x560000BC) /* Inform register */ |
461 | #define MSLCON (*(volatile int *)0x560000CC) /* Memory sleep control register */ | 461 | #define MSLCON (*(volatile unsigned long *)0x560000CC) /* Memory sleep control register */ |
462 | #define GPJCON (*(volatile int *)0x560000D0) /* Port J control */ | 462 | #define GPJCON (*(volatile unsigned long *)0x560000D0) /* Port J control */ |
463 | #define GPJDAT (*(volatile int *)0x560000D4) /* Port J data */ | 463 | #define GPJDAT (*(volatile unsigned long *)0x560000D4) /* Port J data */ |
464 | #define GPJUP (*(volatile int *)0x560000D8) /* Pull-up control J */ | 464 | #define GPJUP (*(volatile unsigned long *)0x560000D8) /* Pull-up control J */ |
465 | 465 | ||
466 | /* RTC */ | 466 | /* RTC */ |
467 | 467 | ||
468 | #define RTCCON (*(volatile char *)0x57000040) /* RTC control */ | 468 | #define RTCCON (*(volatile unsigned char *)0x57000040) /* RTC control */ |
469 | #define TICNT (*(volatile char *)0x57000044) /* Tick time count */ | 469 | #define TICNT (*(volatile unsigned char *)0x57000044) /* Tick time count */ |
470 | #define RTCALM (*(volatile char *)0x57000050) /* RTC alarm control */ | 470 | #define RTCALM (*(volatile unsigned char *)0x57000050) /* RTC alarm control */ |
471 | #define ALMSEC (*(volatile char *)0x57000054) /* Alarm second */ | 471 | #define ALMSEC (*(volatile unsigned char *)0x57000054) /* Alarm second */ |
472 | #define ALMMIN (*(volatile char *)0x57000058) /* Alarm minute */ | 472 | #define ALMMIN (*(volatile unsigned char *)0x57000058) /* Alarm minute */ |
473 | #define ALMHOUR (*(volatile char *)0x5700005C) /* Alarm hour */ | 473 | #define ALMHOUR (*(volatile unsigned char *)0x5700005C) /* Alarm hour */ |
474 | #define ALMDATE (*(volatile char *)0x57000060) /* alarm day */ | 474 | #define ALMDATE (*(volatile unsigned char *)0x57000060) /* alarm day */ |
475 | #define ALMMON (*(volatile char *)0x57000064) /* Alarm month */ | 475 | #define ALMMON (*(volatile unsigned char *)0x57000064) /* Alarm month */ |
476 | #define ALMYEAR (*(volatile char *)0x57000068) /* Alarm year */ | 476 | #define ALMYEAR (*(volatile unsigned char *)0x57000068) /* Alarm year */ |
477 | #define BCDSEC (*(volatile char *)0x57000070) /* BCD second */ | 477 | #define BCDSEC (*(volatile unsigned char *)0x57000070) /* BCD second */ |
478 | #define BCDMIN (*(volatile char *)0x57000074) /* BCD minute */ | 478 | #define BCDMIN (*(volatile unsigned char *)0x57000074) /* BCD minute */ |
479 | #define BCDHOUR (*(volatile char *)0x57000078) /* BCD hour */ | 479 | #define BCDHOUR (*(volatile unsigned char *)0x57000078) /* BCD hour */ |
480 | #define BCDDATE (*(volatile char *)0x5700007C) /* BCD day */ | 480 | #define BCDDATE (*(volatile unsigned char *)0x5700007C) /* BCD day */ |
481 | #define BCDDAY (*(volatile char *)0x57000080) /* BCD date */ | 481 | #define BCDDAY (*(volatile unsigned char *)0x57000080) /* BCD date */ |
482 | #define BCDMON (*(volatile char *)0x57000084) /* BCD month */ | 482 | #define BCDMON (*(volatile unsigned char *)0x57000084) /* BCD month */ |
483 | #define BCDYEAR (*(volatile char *)0x57000088) /* BCD year */ | 483 | #define BCDYEAR (*(volatile unsigned char *)0x57000088) /* BCD year */ |
484 | 484 | ||
485 | /* A/D Converter */ | 485 | /* A/D Converter */ |
486 | 486 | ||
487 | #define ADCCON (*(volatile int *)0x58000000) /* ADC control */ | 487 | #define ADCCON (*(volatile unsigned long *)0x58000000) /* ADC control */ |
488 | #define ADCTSC (*(volatile int *)0x58000004) /* ADC touch screen control */ | 488 | #define ADCTSC (*(volatile unsigned long *)0x58000004) /* ADC touch screen control */ |
489 | #define ADCDLY (*(volatile int *)0x58000008) /* ADC start or interval delay */ | 489 | #define ADCDLY (*(volatile unsigned long *)0x58000008) /* ADC start or interval delay */ |
490 | #define ADCDAT0 (*(volatile int *)0x5800000C) /* ADC conversion data */ | 490 | #define ADCDAT0 (*(volatile unsigned long *)0x5800000C) /* ADC conversion data */ |
491 | #define ADCDAT1 (*(volatile int *)0x58000010) /* ADC conversion data */ | 491 | #define ADCDAT1 (*(volatile unsigned long *)0x58000010) /* ADC conversion data */ |
492 | #define ADCUPDN (*(volatile int *)0x58000014) /* Stylus up or down interrupt status */ | 492 | #define ADCUPDN (*(volatile unsigned long *)0x58000014) /* Stylus up or down interrupt status */ |
493 | 493 | ||
494 | /* SPI */ | 494 | /* SPI */ |
495 | 495 | ||
496 | #define SPCON0 (*(volatile int *)0x59000000) /* SPI control */ | 496 | #define SPCON0 (*(volatile unsigned long *)0x59000000) /* SPI control */ |
497 | #define SPSTA0 (*(volatile int *)0x59000004) /* SPI status */ | 497 | #define SPSTA0 (*(volatile unsigned long *)0x59000004) /* SPI status */ |
498 | #define SPPIN0 (*(volatile int *)0x59000008) /* SPI pin control */ | 498 | #define SPPIN0 (*(volatile unsigned long *)0x59000008) /* SPI pin control */ |
499 | #define SPPRE0 (*(volatile int *)0x5900000C) /* SPI baud rate prescaler */ | 499 | #define SPPRE0 (*(volatile unsigned long *)0x5900000C) /* SPI baud rate prescaler */ |
500 | #define SPTDAT0 (*(volatile int *)0x59000010) /* SPI Tx data */ | 500 | #define SPTDAT0 (*(volatile unsigned long *)0x59000010) /* SPI Tx data */ |
501 | #define SPRDAT0 (*(volatile int *)0x59000014) /* SPI Rx data */ | 501 | #define SPRDAT0 (*(volatile unsigned long *)0x59000014) /* SPI Rx data */ |
502 | #define SPCON1 (*(volatile int *)0x59000020) /* SPI control */ | 502 | #define SPCON1 (*(volatile unsigned long *)0x59000020) /* SPI control */ |
503 | #define SPSTA1 (*(volatile int *)0x59000024) /* SPI status */ | 503 | #define SPSTA1 (*(volatile unsigned long *)0x59000024) /* SPI status */ |
504 | #define SPPIN1 (*(volatile int *)0x59000028) /* SPI pin control */ | 504 | #define SPPIN1 (*(volatile unsigned long *)0x59000028) /* SPI pin control */ |
505 | #define SPPRE1 (*(volatile int *)0x5900002C) /* SPI baud rate prescaler */ | 505 | #define SPPRE1 (*(volatile unsigned long *)0x5900002C) /* SPI baud rate prescaler */ |
506 | #define SPTDAT1 (*(volatile int *)0x59000030) /* SPI Tx data */ | 506 | #define SPTDAT1 (*(volatile unsigned long *)0x59000030) /* SPI Tx data */ |
507 | #define SPRDAT1 (*(volatile int *)0x59000034) /* SPI Rx data */ | 507 | #define SPRDAT1 (*(volatile unsigned long *)0x59000034) /* SPI Rx data */ |
508 | 508 | ||
509 | /* SD Interface */ | 509 | /* SD Interface */ |
510 | 510 | ||
511 | #define SDICON (*(volatile int *)0x5A000000) /* SDI control */ | 511 | #define SDICON (*(volatile unsigned long *)0x5A000000) /* SDI control */ |
512 | #define SDIPRE (*(volatile int *)0x5A000004) /* SDI baud rate prescaler */ | 512 | #define SDIPRE (*(volatile unsigned long *)0x5A000004) /* SDI baud rate prescaler */ |
513 | #define SDICARG (*(volatile int *)0x5A000008) /* SDI command argument */ | 513 | #define SDICARG (*(volatile unsigned long *)0x5A000008) /* SDI command argument */ |
514 | #define SDICCON (*(volatile int *)0x5A00000C) /* SDI command control */ | 514 | #define SDICCON (*(volatile unsigned long *)0x5A00000C) /* SDI command control */ |
515 | #define SDICSTA (*(volatile int *)0x5A000010) /* SDI command status */ | 515 | #define SDICSTA (*(volatile unsigned long *)0x5A000010) /* SDI command status */ |
516 | #define SDIRSP0 (*(volatile int *)0x5A000014) /* SDI response */ | 516 | #define SDIRSP0 (*(volatile unsigned long *)0x5A000014) /* SDI response */ |
517 | #define SDIRSP1 (*(volatile int *)0x5A000018) /* SDI response */ | 517 | #define SDIRSP1 (*(volatile unsigned long *)0x5A000018) /* SDI response */ |
518 | #define SDIRSP2 (*(volatile int *)0x5A00001C) /* SDI response */ | 518 | #define SDIRSP2 (*(volatile unsigned long *)0x5A00001C) /* SDI response */ |
519 | #define SDIRSP3 (*(volatile int *)0x5A000020) /* SDI response */ | 519 | #define SDIRSP3 (*(volatile unsigned long *)0x5A000020) /* SDI response */ |
520 | #define SDIDTIMER (*(volatile int *)0x5A000024) /* SDI data / busy timer */ | 520 | #define SDIDTIMER (*(volatile unsigned long *)0x5A000024) /* SDI data / busy timer */ |
521 | #define SDIBSIZE (*(volatile int *)0x5A000028) /* SDI block size */ | 521 | #define SDIBSIZE (*(volatile unsigned long *)0x5A000028) /* SDI block size */ |
522 | #define SDIDCON (*(volatile int *)0x5A00002C) /* SDI data control */ | 522 | #define SDIDCON (*(volatile unsigned long *)0x5A00002C) /* SDI data control */ |
523 | #define SDIDCNT (*(volatile int *)0x5A000030) /* SDI data remain counter */ | 523 | #define SDIDCNT (*(volatile unsigned long *)0x5A000030) /* SDI data remain counter */ |
524 | #define SDIDSTA (*(volatile int *)0x5A000034) /* SDI data status */ | 524 | #define SDIDSTA (*(volatile unsigned long *)0x5A000034) /* SDI data status */ |
525 | #define SDIFSTA (*(volatile int *)0x5A000038) /* SDI FIFO status */ | 525 | #define SDIFSTA (*(volatile unsigned long *)0x5A000038) /* SDI FIFO status */ |
526 | #define SDIIMSK (*(volatile int *)0x5A00003C) /* SDI interrupt mask */ | 526 | #define SDIIMSK (*(volatile unsigned long *)0x5A00003C) /* SDI interrupt mask */ |
527 | #define SDIDAT (*(volatile char *)0x5A000040) /* SDI data */ | 527 | #define SDIDAT (*(volatile unsigned char *)0x5A000040) /* SDI data */ |
528 | 528 | ||
529 | /* AC97 Audio-CODEC Interface */ | 529 | /* AC97 Audio-CODEC Interface */ |
530 | 530 | ||
531 | #define AC_GLBCTRL (*(volatile int *)0x5B000000) /* AC97 global control register */ | 531 | #define AC_GLBCTRL (*(volatile unsigned long *)0x5B000000) /* AC97 global control register */ |
532 | #define AC_GLBSTAT (*(volatile int *)0x5B000004) /* AC97 global status register */ | 532 | #define AC_GLBSTAT (*(volatile unsigned long *)0x5B000004) /* AC97 global status register */ |
533 | #define AC_CODEC_CMD (*(volatile int *)0x5B000008) /* AC97 codec command register */ | 533 | #define AC_CODEC_CMD (*(volatile unsigned long *)0x5B000008) /* AC97 codec command register */ |
534 | #define AC_CODEC_STAT (*(volatile int *)0x5B00000C) /* AC97 codec status register */ | 534 | #define AC_CODEC_STAT (*(volatile unsigned long *)0x5B00000C) /* AC97 codec status register */ |
535 | #define AC_PCMADDR (*(volatile int *)0x5B000010) /* AC97 PCM out/in channel FIFO address register */ | 535 | #define AC_PCMADDR (*(volatile unsigned long *)0x5B000010) /* AC97 PCM out/in channel FIFO address register */ |
536 | #define AC_MICADDR (*(volatile int *)0x5B000014) /* AC97 mic in channel FIFO address register */ | 536 | #define AC_MICADDR (*(volatile unsigned long *)0x5B000014) /* AC97 mic in channel FIFO address register */ |
537 | #define AC_PCMDATA (*(volatile int *)0x5B000018) /* AC97 PCM out/in channel FIFO data register */ | 537 | #define AC_PCMDATA (*(volatile unsigned long *)0x5B000018) /* AC97 PCM out/in channel FIFO data register */ |
538 | #define AC_MICDATA (*(volatile int *)0x5B00001C) /* AC97 MIC in channel FIFO data register */ | 538 | #define AC_MICDATA (*(volatile unsigned long *)0x5B00001C) /* AC97 MIC in channel FIFO data register */ |
539 | 539 | ||
540 | /* Memory banks */ | 540 | /* Memory banks */ |
541 | 541 | ||
diff --git a/firmware/target/arm/mmu-arm.c b/firmware/target/arm/mmu-arm.c index fff201cbfc..d86cd430b5 100644 --- a/firmware/target/arm/mmu-arm.c +++ b/firmware/target/arm/mmu-arm.c | |||
@@ -56,7 +56,7 @@ void __attribute__((naked)) map_section(unsigned int pa, unsigned int va, int mb | |||
56 | : | 56 | : |
57 | ); | 57 | ); |
58 | 58 | ||
59 | register int *ttb_base asm ("r3") = TTB_BASE; /* force in r3 */ | 59 | register unsigned long *ttb_base asm ("r3") = TTB_BASE; /* force in r3 */ |
60 | 60 | ||
61 | asm volatile | 61 | asm volatile |
62 | ( | 62 | ( |
diff --git a/firmware/target/arm/s3c2440/debug-s3c2440.c b/firmware/target/arm/s3c2440/debug-s3c2440.c index 97b7123a43..6c01f8bc1a 100644 --- a/firmware/target/arm/s3c2440/debug-s3c2440.c +++ b/firmware/target/arm/s3c2440/debug-s3c2440.c | |||
@@ -46,39 +46,40 @@ bool __dbg_ports(void) | |||
46 | while(1) | 46 | while(1) |
47 | { | 47 | { |
48 | line = 0; | 48 | line = 0; |
49 | snprintf(buf, sizeof(buf), "[Ports and Registers]"); lcd_puts(0, line++, buf); | 49 | snprintf(buf, sizeof(buf), "[Ports and Registers]"); |
50 | lcd_puts(0, line++, buf); | ||
50 | 51 | ||
51 | snprintf(buf, sizeof(buf), "GPACON: %08x GPBCON: %08x", GPACON, GPBCON); lcd_puts(0, line++, buf); | 52 | snprintf(buf, sizeof(buf), "GPACON: %08lx GPBCON: %08lx", GPACON, GPBCON); lcd_puts(0, line++, buf); |
52 | snprintf(buf, sizeof(buf), "GPADAT: %08x GPBDAT: %08x", GPADAT, GPBDAT); lcd_puts(0, line++, buf); | 53 | snprintf(buf, sizeof(buf), "GPADAT: %08lx GPBDAT: %08lx", GPADAT, GPBDAT); lcd_puts(0, line++, buf); |
53 | snprintf(buf, sizeof(buf), "GPAUP: %08x GPBUP: %08x", 0, GPBUP); lcd_puts(0, line++, buf); | 54 | snprintf(buf, sizeof(buf), "GPAUP: %08lx GPBUP: %08lx", 0ul, GPBUP); lcd_puts(0, line++, buf); |
54 | snprintf(buf, sizeof(buf), "GPCCON: %08x GPDCON: %08x", GPCCON, GPDCON); lcd_puts(0, line++, buf); | 55 | snprintf(buf, sizeof(buf), "GPCCON: %08lx GPDCON: %08lx", GPCCON, GPDCON); lcd_puts(0, line++, buf); |
55 | snprintf(buf, sizeof(buf), "GPCDAT: %08x GPDDAT: %08x", GPCDAT, GPDDAT); lcd_puts(0, line++, buf); | 56 | snprintf(buf, sizeof(buf), "GPCDAT: %08lx GPDDAT: %08lx", GPCDAT, GPDDAT); lcd_puts(0, line++, buf); |
56 | snprintf(buf, sizeof(buf), "GPCUP: %08x GPDUP: %08x", GPCUP, GPDUP); lcd_puts(0, line++, buf); | 57 | snprintf(buf, sizeof(buf), "GPCUP: %08lx GPDUP: %08lx", GPCUP, GPDUP); lcd_puts(0, line++, buf); |
57 | 58 | ||
58 | snprintf(buf, sizeof(buf), "GPCCON: %08x GPDCON: %08x", GPCCON, GPDCON); lcd_puts(0, line++, buf); | 59 | snprintf(buf, sizeof(buf), "GPCCON: %08lx GPDCON: %08lx", GPCCON, GPDCON); lcd_puts(0, line++, buf); |
59 | snprintf(buf, sizeof(buf), "GPCDAT: %08x GPDDAT: %08x", GPCDAT, GPDDAT); lcd_puts(0, line++, buf); | 60 | snprintf(buf, sizeof(buf), "GPCDAT: %08lx GPDDAT: %08lx", GPCDAT, GPDDAT); lcd_puts(0, line++, buf); |
60 | snprintf(buf, sizeof(buf), "GPCUP: %08x GPDUP: %08x", GPCUP, GPDUP); lcd_puts(0, line++, buf); | 61 | snprintf(buf, sizeof(buf), "GPCUP: %08lx GPDUP: %08lx", GPCUP, GPDUP); lcd_puts(0, line++, buf); |
61 | 62 | ||
62 | snprintf(buf, sizeof(buf), "GPECON: %08x GPFCON: %08x", GPECON, GPFCON); lcd_puts(0, line++, buf); | 63 | snprintf(buf, sizeof(buf), "GPECON: %08lx GPFCON: %08lx", GPECON, GPFCON); lcd_puts(0, line++, buf); |
63 | snprintf(buf, sizeof(buf), "GPEDAT: %08x GPFDAT: %08x", GPEDAT, GPFDAT); lcd_puts(0, line++, buf); | 64 | snprintf(buf, sizeof(buf), "GPEDAT: %08lx GPFDAT: %08lx", GPEDAT, GPFDAT); lcd_puts(0, line++, buf); |
64 | snprintf(buf, sizeof(buf), "GPEUP: %08x GPFUP: %08x", GPEUP, GPFUP); lcd_puts(0, line++, buf); | 65 | snprintf(buf, sizeof(buf), "GPEUP: %08lx GPFUP: %08lx", GPEUP, GPFUP); lcd_puts(0, line++, buf); |
65 | 66 | ||
66 | snprintf(buf, sizeof(buf), "GPGCON: %08x GPHCON: %08x", GPGCON, GPHCON); lcd_puts(0, line++, buf); | 67 | snprintf(buf, sizeof(buf), "GPGCON: %08lx GPHCON: %08lx", GPGCON, GPHCON); lcd_puts(0, line++, buf); |
67 | snprintf(buf, sizeof(buf), "GPGDAT: %08x GPHDAT: %08x", GPGDAT, GPHDAT); lcd_puts(0, line++, buf); | 68 | snprintf(buf, sizeof(buf), "GPGDAT: %08lx GPHDAT: %08lx", GPGDAT, GPHDAT); lcd_puts(0, line++, buf); |
68 | snprintf(buf, sizeof(buf), "GPGUP: %08x GPHUP: %08x", GPGUP, GPHUP); lcd_puts(0, line++, buf); | 69 | snprintf(buf, sizeof(buf), "GPGUP: %08lx GPHUP: %08lx", GPGUP, GPHUP); lcd_puts(0, line++, buf); |
69 | 70 | ||
70 | snprintf(buf, sizeof(buf), "GPJCON: %08x", GPJCON); lcd_puts(0, line++, buf); | 71 | snprintf(buf, sizeof(buf), "GPJCON: %08lx", GPJCON); lcd_puts(0, line++, buf); |
71 | snprintf(buf, sizeof(buf), "GPJDAT: %08x", GPJDAT); lcd_puts(0, line++, buf); | 72 | snprintf(buf, sizeof(buf), "GPJDAT: %08lx", GPJDAT); lcd_puts(0, line++, buf); |
72 | snprintf(buf, sizeof(buf), "GPJUP: %08x", GPJUP); lcd_puts(0, line++, buf); | 73 | snprintf(buf, sizeof(buf), "GPJUP: %08lx", GPJUP); lcd_puts(0, line++, buf); |
73 | 74 | ||
74 | line++; | 75 | line++; |
75 | 76 | ||
76 | snprintf(buf, sizeof(buf), "SRCPND: %08x INTMOD: %08x", SRCPND, INTMOD); lcd_puts(0, line++, buf); | 77 | snprintf(buf, sizeof(buf), "SRCPND: %08lx INTMOD: %08lx", SRCPND, INTMOD); lcd_puts(0, line++, buf); |
77 | snprintf(buf, sizeof(buf), "INTMSK: %08x INTPND: %08x", INTMSK, INTPND); lcd_puts(0, line++, buf); | 78 | snprintf(buf, sizeof(buf), "INTMSK: %08lx INTPND: %08lx", INTMSK, INTPND); lcd_puts(0, line++, buf); |
78 | snprintf(buf, sizeof(buf), "CLKCON: %08x CLKSLOW: %08x", CLKCON, CLKSLOW); lcd_puts(0, line++, buf); | 79 | snprintf(buf, sizeof(buf), "CLKCON: %08lx CLKSLOW: %08lx", CLKCON, CLKSLOW); lcd_puts(0, line++, buf); |
79 | snprintf(buf, sizeof(buf), "MPLLCON: %08x UPLLCON: %08x", MPLLCON, UPLLCON); lcd_puts(0, line++, buf); | 80 | snprintf(buf, sizeof(buf), "MPLLCON: %08lx UPLLCON: %08lx", MPLLCON, UPLLCON); lcd_puts(0, line++, buf); |
80 | snprintf(buf, sizeof(buf), "CLKDIVN: %08x CAMDIVN: %08x", CLKDIVN, CAMDIVN); lcd_puts(0, line++, buf); | 81 | snprintf(buf, sizeof(buf), "CLKDIVN: %08lx CAMDIVN: %08lx", CLKDIVN, CAMDIVN); lcd_puts(0, line++, buf); |
81 | snprintf(buf, sizeof(buf), "BWSCON: %08x TCONSEL: %08x", BWSCON, TCONSEL); lcd_puts(0, line++, buf); | 82 | snprintf(buf, sizeof(buf), "BWSCON: %08lx TCONSEL: %08lx", BWSCON, TCONSEL); lcd_puts(0, line++, buf); |
82 | 83 | ||
83 | lcd_update(); | 84 | lcd_update(); |
84 | if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) | 85 | if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c index d821de4a30..fd5151a3bf 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c | |||
@@ -35,7 +35,7 @@ void adc_init(void) | |||
35 | int i; | 35 | int i; |
36 | 36 | ||
37 | /* Turn on the ADC PCLK */ | 37 | /* Turn on the ADC PCLK */ |
38 | s3c_regset(&CLKCON, 1<<15); | 38 | s3c_regset32(&CLKCON, 1<<15); |
39 | 39 | ||
40 | /* Set channel 0, normal mode, disable "start by read" */ | 40 | /* Set channel 0, normal mode, disable "start by read" */ |
41 | ADCCON &= ~(0x3F); | 41 | ADCCON &= ~(0x3F); |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c index 8300944243..836dedd462 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c | |||
@@ -43,7 +43,7 @@ void i2c_write(int addr, const unsigned char *buf, int count) | |||
43 | mutex_lock(&i2c_mtx); | 43 | mutex_lock(&i2c_mtx); |
44 | 44 | ||
45 | /* Turn on I2C clock */ | 45 | /* Turn on I2C clock */ |
46 | s3c_regset(&CLKCON, 1 << 16); | 46 | s3c_regset32(&CLKCON, 1 << 16); |
47 | 47 | ||
48 | /* Set mode to master transmitter and enable lines */ | 48 | /* Set mode to master transmitter and enable lines */ |
49 | IICSTAT = I2C_MODE_MASTER | I2C_MODE_TX | I2C_RXTX_ENB; | 49 | IICSTAT = I2C_MODE_MASTER | I2C_MODE_TX | I2C_RXTX_ENB; |
@@ -76,7 +76,7 @@ void i2c_write(int addr, const unsigned char *buf, int count) | |||
76 | IICSTAT = 0; | 76 | IICSTAT = 0; |
77 | 77 | ||
78 | /* Turn off I2C clock */ | 78 | /* Turn off I2C clock */ |
79 | s3c_regclr(&CLKCON, 1 << 16); | 79 | s3c_regclr32(&CLKCON, 1 << 16); |
80 | 80 | ||
81 | mutex_unlock(&i2c_mtx); | 81 | mutex_unlock(&i2c_mtx); |
82 | } | 82 | } |
@@ -92,11 +92,11 @@ void i2c_init(void) | |||
92 | INTPND = IIC_MASK; | 92 | INTPND = IIC_MASK; |
93 | 93 | ||
94 | /* Enable i2c interrupt in controller */ | 94 | /* Enable i2c interrupt in controller */ |
95 | s3c_regclr(&INTMOD, IIC_MASK); | 95 | s3c_regclr32(&INTMOD, IIC_MASK); |
96 | s3c_regclr(&INTMSK, IIC_MASK); | 96 | s3c_regclr32(&INTMSK, IIC_MASK); |
97 | 97 | ||
98 | /* Turn on I2C clock */ | 98 | /* Turn on I2C clock */ |
99 | s3c_regset(&CLKCON, 1 << 16); | 99 | s3c_regset32(&CLKCON, 1 << 16); |
100 | 100 | ||
101 | /* Set GPE15 (IICSDA) and GPE14 (IICSCL) to IIC */ | 101 | /* Set GPE15 (IICSDA) and GPE14 (IICSCL) to IIC */ |
102 | GPECON = (GPECON & ~((3 << 30) | (3 << 28))) | | 102 | GPECON = (GPECON & ~((3 << 30) | (3 << 28))) | |
@@ -110,7 +110,7 @@ void i2c_init(void) | |||
110 | IICLC = (0 << 0); | 110 | IICLC = (0 << 0); |
111 | 111 | ||
112 | /* Turn off I2C clock */ | 112 | /* Turn off I2C clock */ |
113 | s3c_regclr(&CLKCON, 1 << 16); | 113 | s3c_regclr32(&CLKCON, 1 << 16); |
114 | } | 114 | } |
115 | 115 | ||
116 | void IIC(void) | 116 | void IIC(void) |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c index ac8dc380e2..f3461cfe91 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c | |||
@@ -103,7 +103,7 @@ static void LCD_CTRL_clock(bool onoff) | |||
103 | GPDCON |= 0xAAA0AAA0; | 103 | GPDCON |= 0xAAA0AAA0; |
104 | GPDUP |= 0xFCFC; | 104 | GPDUP |= 0xFCFC; |
105 | 105 | ||
106 | s3c_regset(&CLKCON, 0x20); /* enable LCD clock */ | 106 | s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */ |
107 | LCDCON1 |=0x01; | 107 | LCDCON1 |=0x01; |
108 | } | 108 | } |
109 | else | 109 | else |
@@ -115,7 +115,7 @@ static void LCD_CTRL_clock(bool onoff) | |||
115 | GPDUP &= ~0xFCFC; | 115 | GPDUP &= ~0xFCFC; |
116 | 116 | ||
117 | LCDCON1 &= ~1; /* Must diable first or bus may freeze */ | 117 | LCDCON1 &= ~1; /* Must diable first or bus may freeze */ |
118 | s3c_regclr(&CLKCON, 0x20); /* disable LCD clock */ | 118 | s3c_regclr32(&CLKCON, 0x20); /* disable LCD clock */ |
119 | } | 119 | } |
120 | } | 120 | } |
121 | 121 | ||
@@ -162,7 +162,7 @@ static void LCD_SPI_SS(bool select) | |||
162 | 162 | ||
163 | static void LCD_SPI_start(void) | 163 | static void LCD_SPI_start(void) |
164 | { | 164 | { |
165 | s3c_regset(&CLKCON, 0x40000); /* enable SPI clock */ | 165 | s3c_regset32(&CLKCON, 0x40000); /* enable SPI clock */ |
166 | LCD_SPI_SS(false); | 166 | LCD_SPI_SS(false); |
167 | SPCON0=0x3E; | 167 | SPCON0=0x3E; |
168 | SPPRE0=24; | 168 | SPPRE0=24; |
@@ -176,7 +176,7 @@ static void LCD_SPI_stop(void) | |||
176 | LCD_SPI_SS(false); | 176 | LCD_SPI_SS(false); |
177 | 177 | ||
178 | SPCON0 &= ~0x10; | 178 | SPCON0 &= ~0x10; |
179 | s3c_regclr(&CLKCON, 0x40000); /* disable SPI clock */ | 179 | s3c_regclr32(&CLKCON, 0x40000); /* disable SPI clock */ |
180 | } | 180 | } |
181 | 181 | ||
182 | static void LCD_SPI_powerdown(void) | 182 | static void LCD_SPI_powerdown(void) |
@@ -271,7 +271,7 @@ void lcd_init_device(void) | |||
271 | 271 | ||
272 | GPBUP |= 0x181; | 272 | GPBUP |= 0x181; |
273 | 273 | ||
274 | s3c_regset(&CLKCON, 0x20); /* enable LCD clock */ | 274 | s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */ |
275 | 275 | ||
276 | LCD_CTRL_setup(); | 276 | LCD_CTRL_setup(); |
277 | LCD_SPI_init(); | 277 | LCD_SPI_init(); |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c index c219922607..14fbcd5cfe 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c | |||
@@ -77,14 +77,14 @@ void pcm_apply_settings(void) | |||
77 | void pcm_play_lock(void) | 77 | void pcm_play_lock(void) |
78 | { | 78 | { |
79 | if (++dma_play_lock.locked == 1) | 79 | if (++dma_play_lock.locked == 1) |
80 | s3c_regset(&INTMSK, DMA2_MASK); | 80 | s3c_regset32(&INTMSK, DMA2_MASK); |
81 | } | 81 | } |
82 | 82 | ||
83 | /* Unmask the DMA interrupt if enabled */ | 83 | /* Unmask the DMA interrupt if enabled */ |
84 | void pcm_play_unlock(void) | 84 | void pcm_play_unlock(void) |
85 | { | 85 | { |
86 | if (--dma_play_lock.locked == 0) | 86 | if (--dma_play_lock.locked == 0) |
87 | s3c_regclr(&INTMSK, dma_play_lock.state); | 87 | s3c_regclr32(&INTMSK, dma_play_lock.state); |
88 | } | 88 | } |
89 | 89 | ||
90 | void pcm_play_dma_init(void) | 90 | void pcm_play_dma_init(void) |
@@ -94,7 +94,7 @@ void pcm_play_dma_init(void) | |||
94 | /* There seem to be problems when changing the IIS interface configuration | 94 | /* There seem to be problems when changing the IIS interface configuration |
95 | * when a clock is not present. | 95 | * when a clock is not present. |
96 | */ | 96 | */ |
97 | s3c_regset(&CLKCON, 1<<17); | 97 | s3c_regset32(&CLKCON, 1<<17); |
98 | /* slave, transmit mode, 16 bit samples - MCLK 384fs - use 16.9344Mhz - | 98 | /* slave, transmit mode, 16 bit samples - MCLK 384fs - use 16.9344Mhz - |
99 | BCLK 32fs */ | 99 | BCLK 32fs */ |
100 | IISMOD = (1<<9) | (1<<8) | (2<<6) | (1<<3) | (1<<2) | (1<<0); | 100 | IISMOD = (1<<9) | (1<<8) | (2<<6) | (1<<3) | (1<<2) | (1<<0); |
@@ -102,7 +102,7 @@ void pcm_play_dma_init(void) | |||
102 | /* RX,TX off,on */ | 102 | /* RX,TX off,on */ |
103 | IISCON |= (1<<3) | (1<<2); | 103 | IISCON |= (1<<3) | (1<<2); |
104 | 104 | ||
105 | s3c_regclr(&CLKCON, 1<<17); | 105 | s3c_regclr32(&CLKCON, 1<<17); |
106 | 106 | ||
107 | audiohw_init(); | 107 | audiohw_init(); |
108 | 108 | ||
@@ -115,11 +115,11 @@ void pcm_play_dma_init(void) | |||
115 | /* Do not service DMA requests, yet */ | 115 | /* Do not service DMA requests, yet */ |
116 | 116 | ||
117 | /* clear any pending int and mask it */ | 117 | /* clear any pending int and mask it */ |
118 | s3c_regset(&INTMSK, DMA2_MASK); | 118 | s3c_regset32(&INTMSK, DMA2_MASK); |
119 | SRCPND = DMA2_MASK; | 119 | SRCPND = DMA2_MASK; |
120 | 120 | ||
121 | /* connect to FIQ */ | 121 | /* connect to FIQ */ |
122 | s3c_regset(&INTMOD, DMA2_MASK); | 122 | s3c_regset32(&INTMOD, DMA2_MASK); |
123 | } | 123 | } |
124 | 124 | ||
125 | void pcm_postinit(void) | 125 | void pcm_postinit(void) |
@@ -159,7 +159,7 @@ static void play_start_pcm(void) | |||
159 | static void play_stop_pcm(void) | 159 | static void play_stop_pcm(void) |
160 | { | 160 | { |
161 | /* Mask DMA interrupt */ | 161 | /* Mask DMA interrupt */ |
162 | s3c_regset(&INTMSK, DMA2_MASK); | 162 | s3c_regset32(&INTMSK, DMA2_MASK); |
163 | 163 | ||
164 | /* De-Activate the DMA channel */ | 164 | /* De-Activate the DMA channel */ |
165 | DMASKTRIG2 = 0x4; | 165 | DMASKTRIG2 = 0x4; |
@@ -187,7 +187,7 @@ static void play_stop_pcm(void) | |||
187 | void pcm_play_dma_start(const void *addr, size_t size) | 187 | void pcm_play_dma_start(const void *addr, size_t size) |
188 | { | 188 | { |
189 | /* Enable the IIS clock */ | 189 | /* Enable the IIS clock */ |
190 | s3c_regset(&CLKCON, 1<<17); | 190 | s3c_regset32(&CLKCON, 1<<17); |
191 | 191 | ||
192 | /* stop any DMA in progress - idle IIS */ | 192 | /* stop any DMA in progress - idle IIS */ |
193 | play_stop_pcm(); | 193 | play_stop_pcm(); |
@@ -218,7 +218,7 @@ void pcm_play_dma_stop(void) | |||
218 | play_stop_pcm(); | 218 | play_stop_pcm(); |
219 | 219 | ||
220 | /* Disconnect the IIS clock */ | 220 | /* Disconnect the IIS clock */ |
221 | s3c_regclr(&CLKCON, 1<<17); | 221 | s3c_regclr32(&CLKCON, 1<<17); |
222 | } | 222 | } |
223 | 223 | ||
224 | void pcm_play_dma_pause(bool pause) | 224 | void pcm_play_dma_pause(bool pause) |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c index 8065926e28..6d8108be49 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c | |||
@@ -118,34 +118,35 @@ static void set_page_tables(void) | |||
118 | map_section((int)FRAME, (int)FRAME, 1, BUFFERED); /* enable buffered writing for the framebuffer */ | 118 | map_section((int)FRAME, (int)FRAME, 1, BUFFERED); /* enable buffered writing for the framebuffer */ |
119 | } | 119 | } |
120 | 120 | ||
121 | void memory_init(void) { | 121 | void memory_init(void) |
122 | { | ||
122 | ttb_init(); | 123 | ttb_init(); |
123 | set_page_tables(); | 124 | set_page_tables(); |
124 | enable_mmu(); | 125 | enable_mmu(); |
125 | } | 126 | } |
126 | 127 | ||
127 | void s3c_regmod(volatile int *reg, unsigned int set, unsigned int clr) | 128 | void s3c_regmod32(volatile unsigned long *reg, unsigned long bits, |
129 | unsigned long mask) | ||
128 | { | 130 | { |
129 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); | 131 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); |
130 | unsigned int val = *reg; | 132 | *reg = (*reg & ~mask) | (bits & mask); |
131 | *reg = (val | set) & ~clr; | ||
132 | restore_interrupt(oldstatus); | 133 | restore_interrupt(oldstatus); |
133 | } | 134 | } |
134 | 135 | ||
135 | void s3c_regset(volatile int *reg, unsigned int mask) | 136 | void s3c_regset32(volatile unsigned long *reg, unsigned long bits) |
136 | { | 137 | { |
137 | s3c_regmod(reg, mask, 0); | 138 | s3c_regmod32(reg, bits, bits); |
138 | } | 139 | } |
139 | 140 | ||
140 | void s3c_regclr(volatile int *reg, unsigned int mask) | 141 | void s3c_regclr32(volatile unsigned long *reg, unsigned long bits) |
141 | { | 142 | { |
142 | s3c_regmod(reg, 0, mask); | 143 | s3c_regmod32(reg, 0, bits); |
143 | } | 144 | } |
144 | 145 | ||
145 | void system_init(void) | 146 | void system_init(void) |
146 | { | 147 | { |
147 | INTMSK = 0xFFFFFFFF; | 148 | INTMSK = 0xFFFFFFFF; |
148 | INTMOD = 0; | 149 | INTMOD = 0; |
149 | SRCPND = 0xFFFFFFFF; | 150 | SRCPND = 0xFFFFFFFF; |
150 | INTPND = 0xFFFFFFFF; | 151 | INTPND = 0xFFFFFFFF; |
151 | INTSUBMSK = 0xFFFFFFFF; | 152 | INTSUBMSK = 0xFFFFFFFF; |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h index 46b726869b..43758ece08 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h +++ b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h | |||
@@ -31,11 +31,12 @@ | |||
31 | /* Functions to set and clear regiser bits atomically */ | 31 | /* Functions to set and clear regiser bits atomically */ |
32 | 32 | ||
33 | /* Set and clear register bits */ | 33 | /* Set and clear register bits */ |
34 | void s3c_regmod(volatile int *reg, unsigned int set, unsigned int clr); | 34 | void s3c_regmod32(volatile unsigned long *reg, unsigned long bits, |
35 | unsigned long mask); | ||
35 | /* Set register bits */ | 36 | /* Set register bits */ |
36 | void s3c_regset(volatile int *reg, unsigned int mask); | 37 | void s3c_regset32(volatile unsigned long *reg, unsigned long bits); |
37 | /* Clear register bits */ | 38 | /* Clear register bits */ |
38 | void s3c_regclr(volatile int *reg, unsigned int mask); | 39 | void s3c_regclr32(volatile unsigned long *reg, unsigned long bits); |
39 | 40 | ||
40 | #define HAVE_INVALIDATE_ICACHE | 41 | #define HAVE_INVALIDATE_ICACHE |
41 | static inline void invalidate_icache(void) | 42 | static inline void invalidate_icache(void) |