From a1ab7a55ffc768da55e4cb30a87cfb85b1231902 Mon Sep 17 00:00:00 2001 From: Michael Sevakis Date: Thu, 4 Dec 2008 15:06:48 +0000 Subject: Meg-FX: s3c register definitions really should be unsigned. Switch from 'int' to 'unsigned long' like other targets. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19325 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c') diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c index ac8dc380e2..f3461cfe91 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c @@ -103,7 +103,7 @@ static void LCD_CTRL_clock(bool onoff) GPDCON |= 0xAAA0AAA0; GPDUP |= 0xFCFC; - s3c_regset(&CLKCON, 0x20); /* enable LCD clock */ + s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */ LCDCON1 |=0x01; } else @@ -115,7 +115,7 @@ static void LCD_CTRL_clock(bool onoff) GPDUP &= ~0xFCFC; LCDCON1 &= ~1; /* Must diable first or bus may freeze */ - s3c_regclr(&CLKCON, 0x20); /* disable LCD clock */ + s3c_regclr32(&CLKCON, 0x20); /* disable LCD clock */ } } @@ -162,7 +162,7 @@ static void LCD_SPI_SS(bool select) static void LCD_SPI_start(void) { - s3c_regset(&CLKCON, 0x40000); /* enable SPI clock */ + s3c_regset32(&CLKCON, 0x40000); /* enable SPI clock */ LCD_SPI_SS(false); SPCON0=0x3E; SPPRE0=24; @@ -176,7 +176,7 @@ static void LCD_SPI_stop(void) LCD_SPI_SS(false); SPCON0 &= ~0x10; - s3c_regclr(&CLKCON, 0x40000); /* disable SPI clock */ + s3c_regclr32(&CLKCON, 0x40000); /* disable SPI clock */ } static void LCD_SPI_powerdown(void) @@ -271,7 +271,7 @@ void lcd_init_device(void) GPBUP |= 0x181; - s3c_regset(&CLKCON, 0x20); /* enable LCD clock */ + s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */ LCD_CTRL_setup(); LCD_SPI_init(); -- cgit v1.2.3