Make basic cache functions into calls, and get rid of CACHE_FUNCTION_WRAPPERS and CACHE_FUNCTIONS_AS_CALL macros. Rename flush/invalidate_icache to cpucache_flush/invalidate. They're inlined only if an implementation isn't provided by defining HAVE_CPUCACHE_FLUSH/INVALIDATE.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19971 a1c6a512-1295-4272-9138-f99709370657

13 files changed, 100 insertions, 100 deletions

diff --git a/firmware/export/system.h b/firmware/export/system.h
index fb9dfa3003..b44600d2c2 100644
--- a/firmware/export/system.h
+++ b/firmware/export/system.h
@@ -272,12 +272,20 @@ static inline uint32_t swap_odd_even32(uint32_t value)
 #endif
 
 /* Just define these as empty if not declared */
-#ifndef HAVE_INVALIDATE_ICACHE
-#define invalidate_icache()
+#ifdef HAVE_CPUCACHE_INVALIDATE
+void cpucache_invalidate(void);
+#else
+static inline void cpucache_invalidate(void)
+{
+}
 #endif
 
-#ifndef HAVE_FLUSH_ICACHE
-#define flush_icache()
+#ifdef HAVE_CPUCACHE_FLUSH
+void cpucache_flush(void);
+#else
+static inline void cpucache_flush(void)
+{
+}
 #endif
 
 #ifdef PROC_NEEDS_CACHEALIGN
diff --git a/firmware/rolo.c b/firmware/rolo.c
index 6a3fcd2bbb..014f00e2c7 100644
--- a/firmware/rolo.c
+++ b/firmware/rolo.c
@@ -75,7 +75,7 @@ void rolo_restart_cop(void)
     COP_INT_DIS = -1;
 
     /* Invalidate cache */
-    invalidate_icache();
+    cpucache_invalidate();
     
     /* Disable cache */
     CACHE_CTL = CACHE_CTL_DISABLE;
@@ -147,7 +147,7 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
     CPU_INT_DIS = -1;
 
     /* Flush cache */
-    flush_icache();
+    cpucache_flush();
 
     /* Disable cache */
     CACHE_CTL = CACHE_CTL_DISABLE;
@@ -174,7 +174,7 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
 
 #elif defined(CPU_TCC780X) || (CONFIG_CPU == S3C2440)
     /* Flush and invalidate caches */
-    invalidate_icache();
+    cpucache_invalidate();
 
     asm volatile(
         "mov   pc, %0            \n"
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h
index ae50ec4c78..921af0ec8b 100644
--- a/firmware/target/arm/imx31/gigabeat-s/system-target.h
+++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h
@@ -57,34 +57,12 @@ void imx31_regclr32(volatile uint32_t *reg_p, uint32_t mask);
 
 #define KDEV_INIT
 
-#define HAVE_INVALIDATE_ICACHE
-static inline void invalidate_icache(void)
-{
-    asm volatile(
-        /* Clean and invalidate entire data cache */
-        "mcr p15, 0, %0, c7, c14, 0 \n"
-        /* Invalidate entire instruction cache
-         * Also flushes the branch target cache */
-        "mcr p15, 0, %0, c7, c5, 0  \n"
-        /* Data synchronization barrier */
-        "mcr p15, 0, %0, c7, c10, 4 \n"
-        /* Flush prefetch buffer */
-        "mcr p15, 0, %0, c7, c5, 4  \n"
-        : : "r"(0)
-    );
-}
+#define HAVE_CPUCACHE_INVALIDATE
+#define HAVE_CPUCACHE_FLUSH
 
-#define HAVE_FLUSH_ICACHE
-static inline void flush_icache(void)
-{
-    asm volatile (
-        /* Clean entire data cache */
-        "mcr p15, 0, %0, c7, c10, 0 \n"
-        /* Data synchronization barrier */
-        "mcr p15, 0, %0, c7, c10, 4 \n"
-        : : "r"(0)
-    );
-}
+/* Different internal names */
+#define cpucache_flush      clean_dcache
+#define cpucache_invalidate invalidate_idcache
 
 struct ARM_REGS {
         int r0;
diff --git a/firmware/target/arm/mmu-arm.c b/firmware/target/arm/mmu-arm.c
index d86cd430b5..fae7fd0b8f 100644
--- a/firmware/target/arm/mmu-arm.c
+++ b/firmware/target/arm/mmu-arm.c
@@ -265,6 +265,8 @@ void __attribute__((naked)) clean_dcache(void)
         /* Clean entire data cache */
         "mov    r0, #0                 \n"
         "mcr    p15, 0, r0, c7, c10, 0 \n"
+        /* Data synchronization barrier */
+        "mcr    p15, 0, r0, c7, c10, 4 \n"
         "bx     lr                     \n"
     );
 }
@@ -290,3 +292,31 @@ void clean_dcache(void)
 }
 #endif
 
+#if CONFIG_CPU == IMX31L
+void invalidate_idcache(void)
+{
+    asm volatile(
+        /* Clean and invalidate entire data cache */
+        "mcr p15, 0, %0, c7, c14, 0 \n"
+        /* Invalidate entire instruction cache
+         * Also flushes the branch target cache */
+        "mcr p15, 0, %0, c7, c5, 0  \n"
+        /* Data synchronization barrier */
+        "mcr p15, 0, %0, c7, c10, 4 \n"
+        /* Flush prefetch buffer */
+        "mcr p15, 0, %0, c7, c5, 4  \n"
+        : : "r"(0)
+    );
+}
+#else
+void invalidate_idcache(void)
+{
+    clean_dcache();
+    asm volatile(
+        "mov r0, #0 \n"
+        "mcr p15, 0, r0, c7, c5, 0 \n"
+        : : : "r0"
+    );
+}
+#endif
+
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h
index 320c595b99..aa7c0aa50c 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h
@@ -41,15 +41,9 @@ void s3c_regset32(volatile unsigned long *reg, unsigned long bits);
 /* Clear register bits */
 void s3c_regclr32(volatile unsigned long *reg, unsigned long bits);
 
-#define HAVE_INVALIDATE_ICACHE
-static inline void invalidate_icache(void)
-{
-    clean_dcache();
-    asm volatile(
-        "mov r0, #0 \n"
-        "mcr p15, 0, r0, c7, c5, 0 \n"
-        : : : "r0"
-    );
-}
+#define HAVE_CPUCACHE_FLUSH
+#define HAVE_CPUCACHE_INVALIDATE
+#define cpucache_flush      clean_dcache
+#define cpucache_invalidate invalidate_idcache
 
 #endif /* SYSTEM_TARGET_H */
diff --git a/firmware/target/arm/system-pp5002.c b/firmware/target/arm/system-pp5002.c
index a995a5464b..98bf5f21f1 100644
--- a/firmware/target/arm/system-pp5002.c
+++ b/firmware/target/arm/system-pp5002.c
@@ -62,8 +62,7 @@ void __attribute__((interrupt("IRQ"))) irq_handler(void)
    some other CPU frequency scaling. */
 
 #ifndef BOOTLOADER
-void flush_icache(void) ICODE_ATTR;
-void flush_icache(void)
+void ICODE_ATTR cpucache_flush(void)
 {
     intptr_t b, e;
 
@@ -73,8 +72,7 @@ void flush_icache(void)
     }
 }
 
-void invalidate_icache(void) ICODE_ATTR;
-void invalidate_icache(void)
+void ICODE_ATTR cpucache_invalidate(void)
 {
     intptr_t b, e;
 
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c
index b1cef7152a..10a7651f7b 100644
--- a/firmware/target/arm/system-pp502x.c
+++ b/firmware/target/arm/system-pp502x.c
@@ -163,8 +163,7 @@ void __attribute__((interrupt("IRQ"))) irq_handler(void)
    to extend the funtions to do alternate cache configurations. */
 
 #ifndef BOOTLOADER
-void flush_icache(void) ICODE_ATTR;
-void flush_icache(void)
+void ICODE_ATTR cpucache_flush(void)
 {
     if (CACHE_CTL & CACHE_CTL_ENABLE)
     {
@@ -173,8 +172,7 @@ void flush_icache(void)
     }
 }
 
-void invalidate_icache(void) ICODE_ATTR;
-void invalidate_icache(void)
+void ICODE_ATTR cpucache_invalidate(void)
 {
     if (CACHE_CTL & CACHE_CTL_ENABLE)
     {
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h
index 4719b8c971..60844e0b5f 100644
--- a/firmware/target/arm/system-target.h
+++ b/firmware/target/arm/system-target.h
@@ -168,13 +168,8 @@ static inline void wake_core(int core)
 
 /** cache functions **/
 #ifndef BOOTLOADER
-#define CACHE_FUNCTIONS_AS_CALL
-
-#define HAVE_INVALIDATE_ICACHE
-void invalidate_icache(void);
-
-#define HAVE_FLUSH_ICACHE
-void flush_icache(void);
+#define HAVE_CPUCACHE_INVALIDATE
+#define HAVE_CPUCACHE_FLUSH
 #endif
 
 #endif /* CPU_PP */
diff --git a/firmware/target/coldfire/system-coldfire.c b/firmware/target/coldfire/system-coldfire.c
index c4651a3c80..a96cd34441 100644
--- a/firmware/target/coldfire/system-coldfire.c
+++ b/firmware/target/coldfire/system-coldfire.c
@@ -358,3 +358,11 @@ void coldfire_set_dataincontrol(unsigned long value)
     DATAINCONTROL = (DATAINCONTROL & (1 << 9)) | value;
     restore_irq(level);
 }
+
+void cpucache_invalidate(void)
+{
+   asm volatile ("move.l #0x01000000,%d0\n"
+                 "movec.l %d0,%cacr\n"
+                 "move.l #0x80000000,%d0\n"
+                 "movec.l %d0,%cacr");
+}
diff --git a/firmware/target/coldfire/system-target.h b/firmware/target/coldfire/system-target.h
index 9c349b1436..347d8e13dc 100644
--- a/firmware/target/coldfire/system-target.h
+++ b/firmware/target/coldfire/system-target.h
@@ -194,14 +194,7 @@ static inline uint32_t swap_odd_even32(uint32_t value)
     return value;
 }
 
-#define HAVE_INVALIDATE_ICACHE
-static inline void invalidate_icache(void)
-{
-   asm volatile ("move.l #0x01000000,%d0\n"
-                 "movec.l %d0,%cacr\n"
-                 "move.l #0x80000000,%d0\n"
-                 "movec.l %d0,%cacr");
-}
+#define HAVE_CPUCACHE_INVALIDATE
 
 #define DEFAULT_PLLCR_AUDIO_BITS 0x10400000
 void coldfire_set_pllcr_audio_bits(long bits);
diff --git a/firmware/target/sh/system-target.h b/firmware/target/sh/system-target.h
index aaf6c6bb2d..3c225fbb69 100644
--- a/firmware/target/sh/system-target.h
+++ b/firmware/target/sh/system-target.h
@@ -126,6 +126,4 @@ static inline uint32_t swap_odd_even32(uint32_t value)
     return value;
 }
 
-#define invalidate_icache()
-
 #endif /* SYSTEM_TARGET_H */
diff --git a/firmware/thread.c b/firmware/thread.c
index f779ca3ae0..ce78769d11 100644
--- a/firmware/thread.c
+++ b/firmware/thread.c
@@ -179,17 +179,17 @@ static void __attribute__((naked,used)) start_thread(void)
 {
     /* r0 = context */
     asm volatile (
-        "ldr    sp, [r0, #32]          \n" /* Load initial sp */
-        "ldr    r4, [r0, #40]          \n" /* start in r4 since it's non-volatile */
-        "mov    r1, #0                 \n" /* Mark thread as running */
-        "str    r1, [r0, #40]          \n"
+        "ldr    sp, [r0, #32]            \n" /* Load initial sp */
+        "ldr    r4, [r0, #40]            \n" /* start in r4 since it's non-volatile */
+        "mov    r1, #0                   \n" /* Mark thread as running */
+        "str    r1, [r0, #40]            \n"
 #if NUM_CORES > 1
-        "ldr    r0, =invalidate_icache \n" /* Invalidate this core's cache. */
-        "mov    lr, pc                 \n" /* This could be the first entry into */
-        "bx     r0                     \n" /* plugin or codec code for this core. */
+        "ldr    r0, =cpucache_invalidate \n" /* Invalidate this core's cache. */
+        "mov    lr, pc                   \n" /* This could be the first entry into */
+        "bx     r0                       \n" /* plugin or codec code for this core. */
 #endif
-        "mov    lr, pc                 \n" /* Call thread function */
-        "bx     r4                     \n"
+        "mov    lr, pc                   \n" /* Call thread function */
+        "bx     r4                       \n"
     ); /* No clobber list - new thread doesn't care */
     thread_exit();
     //asm volatile (".ltorg"); /* Dump constant pool */
@@ -668,7 +668,7 @@ static inline void switch_to_idle_stack(const unsigned int core)
 static void core_switch_blk_op(unsigned int core, struct thread_entry *thread)
 {
     /* Flush our data to ram */
-    flush_icache();
+    cpucache_flush();
     /* Stash thread in r4 slot */
     thread->context.r[0] = (uint32_t)thread;
     /* Stash restart address in r5 slot */
@@ -696,24 +696,24 @@ static void __attribute__((naked))
      * Stack access also isn't permitted until restoring the original stack and
      * context. */
     asm volatile (
-        "stmfd  sp!, { r4-r12, lr }    \n" /* Stack all non-volatile context on current core */
-        "ldr    r2, =idle_stacks       \n" /* r2 = &idle_stacks[core][IDLE_STACK_WORDS] */
-        "ldr    r2, [r2, r0, lsl #2]   \n"
-        "add    r2, r2, %0*4           \n"
-        "stmfd  r2!, { sp }            \n" /* save original stack pointer on idle stack */
-        "mov    sp, r2                 \n" /* switch stacks */
-        "adr    r2, 1f                 \n" /* r2 = new core restart address */
-        "str    r2, [r1, #40]          \n" /* thread->context.start = r2 */
-        "ldr    pc, =switch_thread     \n" /* r0 = thread after call - see load_context */
-    "1:                                \n"
-        "ldr    sp, [r0, #32]          \n" /* Reload original sp from context structure */
-        "mov    r1, #0                 \n" /* Clear start address */
-        "str    r1, [r0, #40]          \n"
-        "ldr    r0, =invalidate_icache \n" /* Invalidate new core's cache */
-        "mov    lr, pc                 \n"
-        "bx     r0                     \n"
-        "ldmfd  sp!, { r4-r12, pc }    \n" /* Restore non-volatile context to new core and return */
-        ".ltorg                        \n" /* Dump constant pool */
+        "stmfd  sp!, { r4-r12, lr }      \n" /* Stack all non-volatile context on current core */
+        "ldr    r2, =idle_stacks         \n" /* r2 = &idle_stacks[core][IDLE_STACK_WORDS] */
+        "ldr    r2, [r2, r0, lsl #2]     \n"
+        "add    r2, r2, %0*4             \n"
+        "stmfd  r2!, { sp }              \n" /* save original stack pointer on idle stack */
+        "mov    sp, r2                   \n" /* switch stacks */
+        "adr    r2, 1f                   \n" /* r2 = new core restart address */
+        "str    r2, [r1, #40]            \n" /* thread->context.start = r2 */
+        "ldr    pc, =switch_thread       \n" /* r0 = thread after call - see load_context */
+    "1:                                  \n"
+        "ldr    sp, [r0, #32]            \n" /* Reload original sp from context structure */
+        "mov    r1, #0                   \n" /* Clear start address */
+        "str    r1, [r0, #40]            \n"
+        "ldr    r0, =cpucache_invalidate \n" /* Invalidate new core's cache */
+        "mov    lr, pc                   \n"
+        "bx     r0                       \n"
+        "ldmfd  sp!, { r4-r12, pc }      \n" /* Restore non-volatile context to new core and return */
+        ".ltorg                          \n" /* Dump constant pool */
         : : "i"(IDLE_STACK_WORDS)
     );
     (void)core; (void)thread;
@@ -2457,7 +2457,7 @@ unsigned int create_thread(void (*function)(void),
     /* Writeback stack munging or anything else before starting */
     if (core != CURRENT_CORE)
     {
-        flush_icache();
+        cpucache_flush();
     }
 #endif
 
@@ -2597,7 +2597,7 @@ void thread_exit(void)
         switch_to_idle_stack(core);
     }
 
-    flush_icache();
+    cpucache_flush();
 
     /* At this point, this thread isn't using resources allocated for
      * execution except the slot itself. */
diff --git a/firmware/usbstack/usb_storage.c b/firmware/usbstack/usb_storage.c
index 85499c1bbd..86b47cf653 100644
--- a/firmware/usbstack/usb_storage.c
+++ b/firmware/usbstack/usb_storage.c
@@ -415,7 +415,7 @@ void usb_storage_init_connection(void)
     audio_buffer = audio_get_buffer(false,&bufsize);
     tb.transfer_buffer =
         (void *)UNCACHED_ADDR((unsigned int)(audio_buffer + 31) & 0xffffffe0);
-    invalidate_icache();
+    cpucache_invalidate();
 #ifdef USB_USE_RAMDISK
     ramdisk_buffer = tb.transfer_buffer + BUFFER_SIZE*2;
 #endif