Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27188 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 2 insertions, 2 deletions

diff --git a/firmware/target/arm/imx31/mc13783-imx31.c b/firmware/target/arm/imx31/mc13783-imx31.c
index 6e982af3d3..b236dcd2ab 100644
--- a/firmware/target/arm/imx31/mc13783-imx31.c
+++ b/firmware/target/arm/imx31/mc13783-imx31.c
@@ -106,7 +106,7 @@ static void mc13783_interrupt_thread(void)
          * acknowledged. Reenable interrupt and if anything was still
          * pending or became pending again, another signal will be
          * generated. */
-        imx31_regset32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE);
+        bitset32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE);
 
         event = mc13783_events;
         event_last = event + MC13783_NUM_EVENTS;
@@ -138,7 +138,7 @@ static void mc13783_interrupt_thread(void)
 void mc13783_event(void)
 {
     /* Mask the interrupt (unmasked when PMIC thread services it). */
-    imx31_regclr32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE);
+    bitclr32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE);
     MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
     wakeup_signal(&mc13783_svc_wake);
 }