Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27188 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 4 insertions, 4 deletions

diff --git a/firmware/target/arm/imx31/iomuxc-imx31.c b/firmware/target/arm/imx31/iomuxc-imx31.c
index 876b8b2a9c..412693e221 100644
--- a/firmware/target/arm/imx31/iomuxc-imx31.c
+++ b/firmware/target/arm/imx31/iomuxc-imx31.c
@@ -32,8 +32,8 @@ void iomuxc_set_pin_mux(enum IMX31_IOMUXC_PINS pin,
     unsigned long index = pin / 4;
     unsigned int shift = 8*(pin % 4);
 
-    imx31_regmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0xc) + index,
-                   mux << shift, IOMUXC_MUX_MASK << shift);
+    bitmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0xc) + index,
+              mux << shift, IOMUXC_MUX_MASK << shift);
 }
 
 
@@ -45,6 +45,6 @@ void iomuxc_set_pad_config(enum IMX31_IOMUXC_PINS pin,
     unsigned long index = padoffs / 3;
     unsigned int shift = 10*(padoffs % 3);
 
-    imx31_regmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0x154) + index,
-                   config << shift, IOMUXC_PAD_MASK << shift);
+    bitmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0x154) + index,
+             config << shift, IOMUXC_PAD_MASK << shift);
 }