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author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-13 19:03:33 +0200 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-15 22:27:34 +0200 |
commit | 017667c2dc9843eb5082e991f421c773636dcf36 (patch) | |
tree | 60432008dd3bc012ac60cbfa771305f6d894dd84 /firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h | |
parent | 97b9ade63945fd8b8261fb0cf1dd0aa225c1a319 (diff) | |
download | rockbox-017667c2dc9843eb5082e991f421c773636dcf36.tar.gz rockbox-017667c2dc9843eb5082e991f421c773636dcf36.zip |
imx233: generate register headers for stmp3600, stmp3700 and imx233
Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h | 491 |
1 files changed, 491 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h b/firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h new file mode 100644 index 0000000000..9750330d9d --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h | |||
@@ -0,0 +1,491 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__UARTDBG__H__ | ||
24 | #define __HEADERGEN__STMP3600__UARTDBG__H__ | ||
25 | |||
26 | #define REGS_UARTDBG_BASE (0x80070000) | ||
27 | |||
28 | #define REGS_UARTDBG_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_UARTDBG_DR | ||
32 | * Address: 0 | ||
33 | * SCT: no | ||
34 | */ | ||
35 | #define HW_UARTDBG_DR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x0)) | ||
36 | #define BP_UARTDBG_DR_UNAVAILABLE 16 | ||
37 | #define BM_UARTDBG_DR_UNAVAILABLE 0xffff0000 | ||
38 | #define BF_UARTDBG_DR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
39 | #define BP_UARTDBG_DR_RESERVED 12 | ||
40 | #define BM_UARTDBG_DR_RESERVED 0xf000 | ||
41 | #define BF_UARTDBG_DR_RESERVED(v) (((v) << 12) & 0xf000) | ||
42 | #define BP_UARTDBG_DR_OE 11 | ||
43 | #define BM_UARTDBG_DR_OE 0x800 | ||
44 | #define BF_UARTDBG_DR_OE(v) (((v) << 11) & 0x800) | ||
45 | #define BP_UARTDBG_DR_BE 10 | ||
46 | #define BM_UARTDBG_DR_BE 0x400 | ||
47 | #define BF_UARTDBG_DR_BE(v) (((v) << 10) & 0x400) | ||
48 | #define BP_UARTDBG_DR_PE 9 | ||
49 | #define BM_UARTDBG_DR_PE 0x200 | ||
50 | #define BF_UARTDBG_DR_PE(v) (((v) << 9) & 0x200) | ||
51 | #define BP_UARTDBG_DR_FE 8 | ||
52 | #define BM_UARTDBG_DR_FE 0x100 | ||
53 | #define BF_UARTDBG_DR_FE(v) (((v) << 8) & 0x100) | ||
54 | #define BP_UARTDBG_DR_DATA 0 | ||
55 | #define BM_UARTDBG_DR_DATA 0xff | ||
56 | #define BF_UARTDBG_DR_DATA(v) (((v) << 0) & 0xff) | ||
57 | |||
58 | /** | ||
59 | * Register: HW_UARTDBG_RSR_ECR | ||
60 | * Address: 0x4 | ||
61 | * SCT: no | ||
62 | */ | ||
63 | #define HW_UARTDBG_RSR_ECR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x4)) | ||
64 | #define BP_UARTDBG_RSR_ECR_UNAVAILABLE 8 | ||
65 | #define BM_UARTDBG_RSR_ECR_UNAVAILABLE 0xffffff00 | ||
66 | #define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
67 | #define BP_UARTDBG_RSR_ECR_EC 4 | ||
68 | #define BM_UARTDBG_RSR_ECR_EC 0xf0 | ||
69 | #define BF_UARTDBG_RSR_ECR_EC(v) (((v) << 4) & 0xf0) | ||
70 | #define BP_UARTDBG_RSR_ECR_OE 3 | ||
71 | #define BM_UARTDBG_RSR_ECR_OE 0x8 | ||
72 | #define BF_UARTDBG_RSR_ECR_OE(v) (((v) << 3) & 0x8) | ||
73 | #define BP_UARTDBG_RSR_ECR_BE 2 | ||
74 | #define BM_UARTDBG_RSR_ECR_BE 0x4 | ||
75 | #define BF_UARTDBG_RSR_ECR_BE(v) (((v) << 2) & 0x4) | ||
76 | #define BP_UARTDBG_RSR_ECR_PE 1 | ||
77 | #define BM_UARTDBG_RSR_ECR_PE 0x2 | ||
78 | #define BF_UARTDBG_RSR_ECR_PE(v) (((v) << 1) & 0x2) | ||
79 | #define BP_UARTDBG_RSR_ECR_FE 0 | ||
80 | #define BM_UARTDBG_RSR_ECR_FE 0x1 | ||
81 | #define BF_UARTDBG_RSR_ECR_FE(v) (((v) << 0) & 0x1) | ||
82 | |||
83 | /** | ||
84 | * Register: HW_UARTDBG_FR | ||
85 | * Address: 0x18 | ||
86 | * SCT: no | ||
87 | */ | ||
88 | #define HW_UARTDBG_FR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x18)) | ||
89 | #define BP_UARTDBG_FR_UNAVAILABLE 16 | ||
90 | #define BM_UARTDBG_FR_UNAVAILABLE 0xffff0000 | ||
91 | #define BF_UARTDBG_FR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
92 | #define BP_UARTDBG_FR_RESERVED 9 | ||
93 | #define BM_UARTDBG_FR_RESERVED 0xfe00 | ||
94 | #define BF_UARTDBG_FR_RESERVED(v) (((v) << 9) & 0xfe00) | ||
95 | #define BP_UARTDBG_FR_RI 8 | ||
96 | #define BM_UARTDBG_FR_RI 0x100 | ||
97 | #define BF_UARTDBG_FR_RI(v) (((v) << 8) & 0x100) | ||
98 | #define BP_UARTDBG_FR_TXFE 7 | ||
99 | #define BM_UARTDBG_FR_TXFE 0x80 | ||
100 | #define BF_UARTDBG_FR_TXFE(v) (((v) << 7) & 0x80) | ||
101 | #define BP_UARTDBG_FR_RXFF 6 | ||
102 | #define BM_UARTDBG_FR_RXFF 0x40 | ||
103 | #define BF_UARTDBG_FR_RXFF(v) (((v) << 6) & 0x40) | ||
104 | #define BP_UARTDBG_FR_TXFF 5 | ||
105 | #define BM_UARTDBG_FR_TXFF 0x20 | ||
106 | #define BF_UARTDBG_FR_TXFF(v) (((v) << 5) & 0x20) | ||
107 | #define BP_UARTDBG_FR_RXFE 4 | ||
108 | #define BM_UARTDBG_FR_RXFE 0x10 | ||
109 | #define BF_UARTDBG_FR_RXFE(v) (((v) << 4) & 0x10) | ||
110 | #define BP_UARTDBG_FR_BUSY 3 | ||
111 | #define BM_UARTDBG_FR_BUSY 0x8 | ||
112 | #define BF_UARTDBG_FR_BUSY(v) (((v) << 3) & 0x8) | ||
113 | #define BP_UARTDBG_FR_DCD 2 | ||
114 | #define BM_UARTDBG_FR_DCD 0x4 | ||
115 | #define BF_UARTDBG_FR_DCD(v) (((v) << 2) & 0x4) | ||
116 | #define BP_UARTDBG_FR_DSR 1 | ||
117 | #define BM_UARTDBG_FR_DSR 0x2 | ||
118 | #define BF_UARTDBG_FR_DSR(v) (((v) << 1) & 0x2) | ||
119 | #define BP_UARTDBG_FR_CTS 0 | ||
120 | #define BM_UARTDBG_FR_CTS 0x1 | ||
121 | #define BF_UARTDBG_FR_CTS(v) (((v) << 0) & 0x1) | ||
122 | |||
123 | /** | ||
124 | * Register: HW_UARTDBG_ILPR | ||
125 | * Address: 0x20 | ||
126 | * SCT: no | ||
127 | */ | ||
128 | #define HW_UARTDBG_ILPR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x20)) | ||
129 | #define BP_UARTDBG_ILPR_UNAVAILABLE 8 | ||
130 | #define BM_UARTDBG_ILPR_UNAVAILABLE 0xffffff00 | ||
131 | #define BF_UARTDBG_ILPR_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
132 | #define BP_UARTDBG_ILPR_ILPDVSR 0 | ||
133 | #define BM_UARTDBG_ILPR_ILPDVSR 0xff | ||
134 | #define BF_UARTDBG_ILPR_ILPDVSR(v) (((v) << 0) & 0xff) | ||
135 | |||
136 | /** | ||
137 | * Register: HW_UARTDBG_IBRD | ||
138 | * Address: 0x24 | ||
139 | * SCT: no | ||
140 | */ | ||
141 | #define HW_UARTDBG_IBRD (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x24)) | ||
142 | #define BP_UARTDBG_IBRD_UNAVAILABLE 16 | ||
143 | #define BM_UARTDBG_IBRD_UNAVAILABLE 0xffff0000 | ||
144 | #define BF_UARTDBG_IBRD_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
145 | #define BP_UARTDBG_IBRD_BAUD_DIVINT 0 | ||
146 | #define BM_UARTDBG_IBRD_BAUD_DIVINT 0xffff | ||
147 | #define BF_UARTDBG_IBRD_BAUD_DIVINT(v) (((v) << 0) & 0xffff) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_UARTDBG_FBRD | ||
151 | * Address: 0x28 | ||
152 | * SCT: no | ||
153 | */ | ||
154 | #define HW_UARTDBG_FBRD (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x28)) | ||
155 | #define BP_UARTDBG_FBRD_UNAVAILABLE 8 | ||
156 | #define BM_UARTDBG_FBRD_UNAVAILABLE 0xffffff00 | ||
157 | #define BF_UARTDBG_FBRD_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
158 | #define BP_UARTDBG_FBRD_RESERVED 6 | ||
159 | #define BM_UARTDBG_FBRD_RESERVED 0xc0 | ||
160 | #define BF_UARTDBG_FBRD_RESERVED(v) (((v) << 6) & 0xc0) | ||
161 | #define BP_UARTDBG_FBRD_BAUD_DIVFRAC 0 | ||
162 | #define BM_UARTDBG_FBRD_BAUD_DIVFRAC 0x3f | ||
163 | #define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v) (((v) << 0) & 0x3f) | ||
164 | |||
165 | /** | ||
166 | * Register: HW_UARTDBG_LCR_H | ||
167 | * Address: 0x2c | ||
168 | * SCT: no | ||
169 | */ | ||
170 | #define HW_UARTDBG_LCR_H (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x2c)) | ||
171 | #define BP_UARTDBG_LCR_H_UNAVAILABLE 16 | ||
172 | #define BM_UARTDBG_LCR_H_UNAVAILABLE 0xffff0000 | ||
173 | #define BF_UARTDBG_LCR_H_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
174 | #define BP_UARTDBG_LCR_H_RESERVED 8 | ||
175 | #define BM_UARTDBG_LCR_H_RESERVED 0xff00 | ||
176 | #define BF_UARTDBG_LCR_H_RESERVED(v) (((v) << 8) & 0xff00) | ||
177 | #define BP_UARTDBG_LCR_H_SPS 7 | ||
178 | #define BM_UARTDBG_LCR_H_SPS 0x80 | ||
179 | #define BF_UARTDBG_LCR_H_SPS(v) (((v) << 7) & 0x80) | ||
180 | #define BP_UARTDBG_LCR_H_WLEN 5 | ||
181 | #define BM_UARTDBG_LCR_H_WLEN 0x60 | ||
182 | #define BF_UARTDBG_LCR_H_WLEN(v) (((v) << 5) & 0x60) | ||
183 | #define BP_UARTDBG_LCR_H_FEN 4 | ||
184 | #define BM_UARTDBG_LCR_H_FEN 0x10 | ||
185 | #define BF_UARTDBG_LCR_H_FEN(v) (((v) << 4) & 0x10) | ||
186 | #define BP_UARTDBG_LCR_H_STP2 3 | ||
187 | #define BM_UARTDBG_LCR_H_STP2 0x8 | ||
188 | #define BF_UARTDBG_LCR_H_STP2(v) (((v) << 3) & 0x8) | ||
189 | #define BP_UARTDBG_LCR_H_EPS 2 | ||
190 | #define BM_UARTDBG_LCR_H_EPS 0x4 | ||
191 | #define BF_UARTDBG_LCR_H_EPS(v) (((v) << 2) & 0x4) | ||
192 | #define BP_UARTDBG_LCR_H_PEN 1 | ||
193 | #define BM_UARTDBG_LCR_H_PEN 0x2 | ||
194 | #define BF_UARTDBG_LCR_H_PEN(v) (((v) << 1) & 0x2) | ||
195 | #define BP_UARTDBG_LCR_H_BRK 0 | ||
196 | #define BM_UARTDBG_LCR_H_BRK 0x1 | ||
197 | #define BF_UARTDBG_LCR_H_BRK(v) (((v) << 0) & 0x1) | ||
198 | |||
199 | /** | ||
200 | * Register: HW_UARTDBG_CR | ||
201 | * Address: 0x30 | ||
202 | * SCT: no | ||
203 | */ | ||
204 | #define HW_UARTDBG_CR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x30)) | ||
205 | #define BP_UARTDBG_CR_UNAVAILABLE 16 | ||
206 | #define BM_UARTDBG_CR_UNAVAILABLE 0xffff0000 | ||
207 | #define BF_UARTDBG_CR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
208 | #define BP_UARTDBG_CR_CTSEN 15 | ||
209 | #define BM_UARTDBG_CR_CTSEN 0x8000 | ||
210 | #define BF_UARTDBG_CR_CTSEN(v) (((v) << 15) & 0x8000) | ||
211 | #define BP_UARTDBG_CR_RTSEN 14 | ||
212 | #define BM_UARTDBG_CR_RTSEN 0x4000 | ||
213 | #define BF_UARTDBG_CR_RTSEN(v) (((v) << 14) & 0x4000) | ||
214 | #define BP_UARTDBG_CR_OUT2 13 | ||
215 | #define BM_UARTDBG_CR_OUT2 0x2000 | ||
216 | #define BF_UARTDBG_CR_OUT2(v) (((v) << 13) & 0x2000) | ||
217 | #define BP_UARTDBG_CR_OUT1 12 | ||
218 | #define BM_UARTDBG_CR_OUT1 0x1000 | ||
219 | #define BF_UARTDBG_CR_OUT1(v) (((v) << 12) & 0x1000) | ||
220 | #define BP_UARTDBG_CR_RTS 11 | ||
221 | #define BM_UARTDBG_CR_RTS 0x800 | ||
222 | #define BF_UARTDBG_CR_RTS(v) (((v) << 11) & 0x800) | ||
223 | #define BP_UARTDBG_CR_DTR 10 | ||
224 | #define BM_UARTDBG_CR_DTR 0x400 | ||
225 | #define BF_UARTDBG_CR_DTR(v) (((v) << 10) & 0x400) | ||
226 | #define BP_UARTDBG_CR_RXE 9 | ||
227 | #define BM_UARTDBG_CR_RXE 0x200 | ||
228 | #define BF_UARTDBG_CR_RXE(v) (((v) << 9) & 0x200) | ||
229 | #define BP_UARTDBG_CR_TXE 8 | ||
230 | #define BM_UARTDBG_CR_TXE 0x100 | ||
231 | #define BF_UARTDBG_CR_TXE(v) (((v) << 8) & 0x100) | ||
232 | #define BP_UARTDBG_CR_LBE 7 | ||
233 | #define BM_UARTDBG_CR_LBE 0x80 | ||
234 | #define BF_UARTDBG_CR_LBE(v) (((v) << 7) & 0x80) | ||
235 | #define BP_UARTDBG_CR_RESERVED 3 | ||
236 | #define BM_UARTDBG_CR_RESERVED 0x78 | ||
237 | #define BF_UARTDBG_CR_RESERVED(v) (((v) << 3) & 0x78) | ||
238 | #define BP_UARTDBG_CR_SIRLP 2 | ||
239 | #define BM_UARTDBG_CR_SIRLP 0x4 | ||
240 | #define BF_UARTDBG_CR_SIRLP(v) (((v) << 2) & 0x4) | ||
241 | #define BP_UARTDBG_CR_SIREN 1 | ||
242 | #define BM_UARTDBG_CR_SIREN 0x2 | ||
243 | #define BF_UARTDBG_CR_SIREN(v) (((v) << 1) & 0x2) | ||
244 | #define BP_UARTDBG_CR_UARTEN 0 | ||
245 | #define BM_UARTDBG_CR_UARTEN 0x1 | ||
246 | #define BF_UARTDBG_CR_UARTEN(v) (((v) << 0) & 0x1) | ||
247 | |||
248 | /** | ||
249 | * Register: HW_UARTDBG_IFLS | ||
250 | * Address: 0x34 | ||
251 | * SCT: no | ||
252 | */ | ||
253 | #define HW_UARTDBG_IFLS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x34)) | ||
254 | #define BP_UARTDBG_IFLS_UNAVAILABLE 16 | ||
255 | #define BM_UARTDBG_IFLS_UNAVAILABLE 0xffff0000 | ||
256 | #define BF_UARTDBG_IFLS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
257 | #define BP_UARTDBG_IFLS_RESERVED 6 | ||
258 | #define BM_UARTDBG_IFLS_RESERVED 0xffc0 | ||
259 | #define BF_UARTDBG_IFLS_RESERVED(v) (((v) << 6) & 0xffc0) | ||
260 | #define BP_UARTDBG_IFLS_RXIFLSEL 3 | ||
261 | #define BM_UARTDBG_IFLS_RXIFLSEL 0x38 | ||
262 | #define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY 0x0 | ||
263 | #define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER 0x1 | ||
264 | #define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF 0x2 | ||
265 | #define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS 0x3 | ||
266 | #define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
267 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5 0x5 | ||
268 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6 0x6 | ||
269 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7 0x7 | ||
270 | #define BF_UARTDBG_IFLS_RXIFLSEL(v) (((v) << 3) & 0x38) | ||
271 | #define BF_UARTDBG_IFLS_RXIFLSEL_V(v) ((BV_UARTDBG_IFLS_RXIFLSEL__##v << 3) & 0x38) | ||
272 | #define BP_UARTDBG_IFLS_TXIFLSEL 0 | ||
273 | #define BM_UARTDBG_IFLS_TXIFLSEL 0x7 | ||
274 | #define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY 0x0 | ||
275 | #define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER 0x1 | ||
276 | #define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF 0x2 | ||
277 | #define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS 0x3 | ||
278 | #define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
279 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5 0x5 | ||
280 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6 0x6 | ||
281 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7 0x7 | ||
282 | #define BF_UARTDBG_IFLS_TXIFLSEL(v) (((v) << 0) & 0x7) | ||
283 | #define BF_UARTDBG_IFLS_TXIFLSEL_V(v) ((BV_UARTDBG_IFLS_TXIFLSEL__##v << 0) & 0x7) | ||
284 | |||
285 | /** | ||
286 | * Register: HW_UARTDBG_IMSC | ||
287 | * Address: 0x38 | ||
288 | * SCT: no | ||
289 | */ | ||
290 | #define HW_UARTDBG_IMSC (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x38)) | ||
291 | #define BP_UARTDBG_IMSC_UNAVAILABLE 16 | ||
292 | #define BM_UARTDBG_IMSC_UNAVAILABLE 0xffff0000 | ||
293 | #define BF_UARTDBG_IMSC_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
294 | #define BP_UARTDBG_IMSC_RESERVED 11 | ||
295 | #define BM_UARTDBG_IMSC_RESERVED 0xf800 | ||
296 | #define BF_UARTDBG_IMSC_RESERVED(v) (((v) << 11) & 0xf800) | ||
297 | #define BP_UARTDBG_IMSC_OEIM 10 | ||
298 | #define BM_UARTDBG_IMSC_OEIM 0x400 | ||
299 | #define BF_UARTDBG_IMSC_OEIM(v) (((v) << 10) & 0x400) | ||
300 | #define BP_UARTDBG_IMSC_BEIM 9 | ||
301 | #define BM_UARTDBG_IMSC_BEIM 0x200 | ||
302 | #define BF_UARTDBG_IMSC_BEIM(v) (((v) << 9) & 0x200) | ||
303 | #define BP_UARTDBG_IMSC_PEIM 8 | ||
304 | #define BM_UARTDBG_IMSC_PEIM 0x100 | ||
305 | #define BF_UARTDBG_IMSC_PEIM(v) (((v) << 8) & 0x100) | ||
306 | #define BP_UARTDBG_IMSC_FEIM 7 | ||
307 | #define BM_UARTDBG_IMSC_FEIM 0x80 | ||
308 | #define BF_UARTDBG_IMSC_FEIM(v) (((v) << 7) & 0x80) | ||
309 | #define BP_UARTDBG_IMSC_RTIM 6 | ||
310 | #define BM_UARTDBG_IMSC_RTIM 0x40 | ||
311 | #define BF_UARTDBG_IMSC_RTIM(v) (((v) << 6) & 0x40) | ||
312 | #define BP_UARTDBG_IMSC_TXIM 5 | ||
313 | #define BM_UARTDBG_IMSC_TXIM 0x20 | ||
314 | #define BF_UARTDBG_IMSC_TXIM(v) (((v) << 5) & 0x20) | ||
315 | #define BP_UARTDBG_IMSC_RXIM 4 | ||
316 | #define BM_UARTDBG_IMSC_RXIM 0x10 | ||
317 | #define BF_UARTDBG_IMSC_RXIM(v) (((v) << 4) & 0x10) | ||
318 | #define BP_UARTDBG_IMSC_DSRMIM 3 | ||
319 | #define BM_UARTDBG_IMSC_DSRMIM 0x8 | ||
320 | #define BF_UARTDBG_IMSC_DSRMIM(v) (((v) << 3) & 0x8) | ||
321 | #define BP_UARTDBG_IMSC_DCDMIM 2 | ||
322 | #define BM_UARTDBG_IMSC_DCDMIM 0x4 | ||
323 | #define BF_UARTDBG_IMSC_DCDMIM(v) (((v) << 2) & 0x4) | ||
324 | #define BP_UARTDBG_IMSC_CTSMIM 1 | ||
325 | #define BM_UARTDBG_IMSC_CTSMIM 0x2 | ||
326 | #define BF_UARTDBG_IMSC_CTSMIM(v) (((v) << 1) & 0x2) | ||
327 | #define BP_UARTDBG_IMSC_RIMIM 0 | ||
328 | #define BM_UARTDBG_IMSC_RIMIM 0x1 | ||
329 | #define BF_UARTDBG_IMSC_RIMIM(v) (((v) << 0) & 0x1) | ||
330 | |||
331 | /** | ||
332 | * Register: HW_UARTDBG_RIS | ||
333 | * Address: 0x3c | ||
334 | * SCT: no | ||
335 | */ | ||
336 | #define HW_UARTDBG_RIS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x3c)) | ||
337 | #define BP_UARTDBG_RIS_UNAVAILABLE 16 | ||
338 | #define BM_UARTDBG_RIS_UNAVAILABLE 0xffff0000 | ||
339 | #define BF_UARTDBG_RIS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
340 | #define BP_UARTDBG_RIS_RESERVED 11 | ||
341 | #define BM_UARTDBG_RIS_RESERVED 0xf800 | ||
342 | #define BF_UARTDBG_RIS_RESERVED(v) (((v) << 11) & 0xf800) | ||
343 | #define BP_UARTDBG_RIS_OERIS 10 | ||
344 | #define BM_UARTDBG_RIS_OERIS 0x400 | ||
345 | #define BF_UARTDBG_RIS_OERIS(v) (((v) << 10) & 0x400) | ||
346 | #define BP_UARTDBG_RIS_BERIS 9 | ||
347 | #define BM_UARTDBG_RIS_BERIS 0x200 | ||
348 | #define BF_UARTDBG_RIS_BERIS(v) (((v) << 9) & 0x200) | ||
349 | #define BP_UARTDBG_RIS_PERIS 8 | ||
350 | #define BM_UARTDBG_RIS_PERIS 0x100 | ||
351 | #define BF_UARTDBG_RIS_PERIS(v) (((v) << 8) & 0x100) | ||
352 | #define BP_UARTDBG_RIS_FERIS 7 | ||
353 | #define BM_UARTDBG_RIS_FERIS 0x80 | ||
354 | #define BF_UARTDBG_RIS_FERIS(v) (((v) << 7) & 0x80) | ||
355 | #define BP_UARTDBG_RIS_RTRIS 6 | ||
356 | #define BM_UARTDBG_RIS_RTRIS 0x40 | ||
357 | #define BF_UARTDBG_RIS_RTRIS(v) (((v) << 6) & 0x40) | ||
358 | #define BP_UARTDBG_RIS_TXRIS 5 | ||
359 | #define BM_UARTDBG_RIS_TXRIS 0x20 | ||
360 | #define BF_UARTDBG_RIS_TXRIS(v) (((v) << 5) & 0x20) | ||
361 | #define BP_UARTDBG_RIS_RXRIS 4 | ||
362 | #define BM_UARTDBG_RIS_RXRIS 0x10 | ||
363 | #define BF_UARTDBG_RIS_RXRIS(v) (((v) << 4) & 0x10) | ||
364 | #define BP_UARTDBG_RIS_DSRRMIS 3 | ||
365 | #define BM_UARTDBG_RIS_DSRRMIS 0x8 | ||
366 | #define BF_UARTDBG_RIS_DSRRMIS(v) (((v) << 3) & 0x8) | ||
367 | #define BP_UARTDBG_RIS_DCDRMIS 2 | ||
368 | #define BM_UARTDBG_RIS_DCDRMIS 0x4 | ||
369 | #define BF_UARTDBG_RIS_DCDRMIS(v) (((v) << 2) & 0x4) | ||
370 | #define BP_UARTDBG_RIS_CTSRMIS 1 | ||
371 | #define BM_UARTDBG_RIS_CTSRMIS 0x2 | ||
372 | #define BF_UARTDBG_RIS_CTSRMIS(v) (((v) << 1) & 0x2) | ||
373 | #define BP_UARTDBG_RIS_RIRMIS 0 | ||
374 | #define BM_UARTDBG_RIS_RIRMIS 0x1 | ||
375 | #define BF_UARTDBG_RIS_RIRMIS(v) (((v) << 0) & 0x1) | ||
376 | |||
377 | /** | ||
378 | * Register: HW_UARTDBG_MIS | ||
379 | * Address: 0x40 | ||
380 | * SCT: no | ||
381 | */ | ||
382 | #define HW_UARTDBG_MIS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x40)) | ||
383 | #define BP_UARTDBG_MIS_UNAVAILABLE 16 | ||
384 | #define BM_UARTDBG_MIS_UNAVAILABLE 0xffff0000 | ||
385 | #define BF_UARTDBG_MIS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
386 | #define BP_UARTDBG_MIS_RESERVED 11 | ||
387 | #define BM_UARTDBG_MIS_RESERVED 0xf800 | ||
388 | #define BF_UARTDBG_MIS_RESERVED(v) (((v) << 11) & 0xf800) | ||
389 | #define BP_UARTDBG_MIS_OEMIS 10 | ||
390 | #define BM_UARTDBG_MIS_OEMIS 0x400 | ||
391 | #define BF_UARTDBG_MIS_OEMIS(v) (((v) << 10) & 0x400) | ||
392 | #define BP_UARTDBG_MIS_BEMIS 9 | ||
393 | #define BM_UARTDBG_MIS_BEMIS 0x200 | ||
394 | #define BF_UARTDBG_MIS_BEMIS(v) (((v) << 9) & 0x200) | ||
395 | #define BP_UARTDBG_MIS_PEMIS 8 | ||
396 | #define BM_UARTDBG_MIS_PEMIS 0x100 | ||
397 | #define BF_UARTDBG_MIS_PEMIS(v) (((v) << 8) & 0x100) | ||
398 | #define BP_UARTDBG_MIS_FEMIS 7 | ||
399 | #define BM_UARTDBG_MIS_FEMIS 0x80 | ||
400 | #define BF_UARTDBG_MIS_FEMIS(v) (((v) << 7) & 0x80) | ||
401 | #define BP_UARTDBG_MIS_RTMIS 6 | ||
402 | #define BM_UARTDBG_MIS_RTMIS 0x40 | ||
403 | #define BF_UARTDBG_MIS_RTMIS(v) (((v) << 6) & 0x40) | ||
404 | #define BP_UARTDBG_MIS_TXMIS 5 | ||
405 | #define BM_UARTDBG_MIS_TXMIS 0x20 | ||
406 | #define BF_UARTDBG_MIS_TXMIS(v) (((v) << 5) & 0x20) | ||
407 | #define BP_UARTDBG_MIS_RXMIS 4 | ||
408 | #define BM_UARTDBG_MIS_RXMIS 0x10 | ||
409 | #define BF_UARTDBG_MIS_RXMIS(v) (((v) << 4) & 0x10) | ||
410 | #define BP_UARTDBG_MIS_DSRMMIS 3 | ||
411 | #define BM_UARTDBG_MIS_DSRMMIS 0x8 | ||
412 | #define BF_UARTDBG_MIS_DSRMMIS(v) (((v) << 3) & 0x8) | ||
413 | #define BP_UARTDBG_MIS_DCDMMIS 2 | ||
414 | #define BM_UARTDBG_MIS_DCDMMIS 0x4 | ||
415 | #define BF_UARTDBG_MIS_DCDMMIS(v) (((v) << 2) & 0x4) | ||
416 | #define BP_UARTDBG_MIS_CTSMMIS 1 | ||
417 | #define BM_UARTDBG_MIS_CTSMMIS 0x2 | ||
418 | #define BF_UARTDBG_MIS_CTSMMIS(v) (((v) << 1) & 0x2) | ||
419 | #define BP_UARTDBG_MIS_RIMMIS 0 | ||
420 | #define BM_UARTDBG_MIS_RIMMIS 0x1 | ||
421 | #define BF_UARTDBG_MIS_RIMMIS(v) (((v) << 0) & 0x1) | ||
422 | |||
423 | /** | ||
424 | * Register: HW_UARTDBG_ICR | ||
425 | * Address: 0x44 | ||
426 | * SCT: no | ||
427 | */ | ||
428 | #define HW_UARTDBG_ICR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x44)) | ||
429 | #define BP_UARTDBG_ICR_UNAVAILABLE 16 | ||
430 | #define BM_UARTDBG_ICR_UNAVAILABLE 0xffff0000 | ||
431 | #define BF_UARTDBG_ICR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
432 | #define BP_UARTDBG_ICR_RESERVED 11 | ||
433 | #define BM_UARTDBG_ICR_RESERVED 0xf800 | ||
434 | #define BF_UARTDBG_ICR_RESERVED(v) (((v) << 11) & 0xf800) | ||
435 | #define BP_UARTDBG_ICR_OEIC 10 | ||
436 | #define BM_UARTDBG_ICR_OEIC 0x400 | ||
437 | #define BF_UARTDBG_ICR_OEIC(v) (((v) << 10) & 0x400) | ||
438 | #define BP_UARTDBG_ICR_BEIC 9 | ||
439 | #define BM_UARTDBG_ICR_BEIC 0x200 | ||
440 | #define BF_UARTDBG_ICR_BEIC(v) (((v) << 9) & 0x200) | ||
441 | #define BP_UARTDBG_ICR_PEIC 8 | ||
442 | #define BM_UARTDBG_ICR_PEIC 0x100 | ||
443 | #define BF_UARTDBG_ICR_PEIC(v) (((v) << 8) & 0x100) | ||
444 | #define BP_UARTDBG_ICR_FEIC 7 | ||
445 | #define BM_UARTDBG_ICR_FEIC 0x80 | ||
446 | #define BF_UARTDBG_ICR_FEIC(v) (((v) << 7) & 0x80) | ||
447 | #define BP_UARTDBG_ICR_RTIC 6 | ||
448 | #define BM_UARTDBG_ICR_RTIC 0x40 | ||
449 | #define BF_UARTDBG_ICR_RTIC(v) (((v) << 6) & 0x40) | ||
450 | #define BP_UARTDBG_ICR_TXIC 5 | ||
451 | #define BM_UARTDBG_ICR_TXIC 0x20 | ||
452 | #define BF_UARTDBG_ICR_TXIC(v) (((v) << 5) & 0x20) | ||
453 | #define BP_UARTDBG_ICR_RXIC 4 | ||
454 | #define BM_UARTDBG_ICR_RXIC 0x10 | ||
455 | #define BF_UARTDBG_ICR_RXIC(v) (((v) << 4) & 0x10) | ||
456 | #define BP_UARTDBG_ICR_DSRMIC 3 | ||
457 | #define BM_UARTDBG_ICR_DSRMIC 0x8 | ||
458 | #define BF_UARTDBG_ICR_DSRMIC(v) (((v) << 3) & 0x8) | ||
459 | #define BP_UARTDBG_ICR_DCDMIC 2 | ||
460 | #define BM_UARTDBG_ICR_DCDMIC 0x4 | ||
461 | #define BF_UARTDBG_ICR_DCDMIC(v) (((v) << 2) & 0x4) | ||
462 | #define BP_UARTDBG_ICR_CTSMIC 1 | ||
463 | #define BM_UARTDBG_ICR_CTSMIC 0x2 | ||
464 | #define BF_UARTDBG_ICR_CTSMIC(v) (((v) << 1) & 0x2) | ||
465 | #define BP_UARTDBG_ICR_RIMIC 0 | ||
466 | #define BM_UARTDBG_ICR_RIMIC 0x1 | ||
467 | #define BF_UARTDBG_ICR_RIMIC(v) (((v) << 0) & 0x1) | ||
468 | |||
469 | /** | ||
470 | * Register: HW_UARTDBG_DMACR | ||
471 | * Address: 0x48 | ||
472 | * SCT: no | ||
473 | */ | ||
474 | #define HW_UARTDBG_DMACR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x48)) | ||
475 | #define BP_UARTDBG_DMACR_UNAVAILABLE 16 | ||
476 | #define BM_UARTDBG_DMACR_UNAVAILABLE 0xffff0000 | ||
477 | #define BF_UARTDBG_DMACR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
478 | #define BP_UARTDBG_DMACR_RESERVED 3 | ||
479 | #define BM_UARTDBG_DMACR_RESERVED 0xfff8 | ||
480 | #define BF_UARTDBG_DMACR_RESERVED(v) (((v) << 3) & 0xfff8) | ||
481 | #define BP_UARTDBG_DMACR_DMAONERR 2 | ||
482 | #define BM_UARTDBG_DMACR_DMAONERR 0x4 | ||
483 | #define BF_UARTDBG_DMACR_DMAONERR(v) (((v) << 2) & 0x4) | ||
484 | #define BP_UARTDBG_DMACR_TXDMAE 1 | ||
485 | #define BM_UARTDBG_DMACR_TXDMAE 0x2 | ||
486 | #define BF_UARTDBG_DMACR_TXDMAE(v) (((v) << 1) & 0x2) | ||
487 | #define BP_UARTDBG_DMACR_RXDMAE 0 | ||
488 | #define BM_UARTDBG_DMACR_RXDMAE 0x1 | ||
489 | #define BF_UARTDBG_DMACR_RXDMAE(v) (((v) << 0) & 0x1) | ||
490 | |||
491 | #endif /* __HEADERGEN__STMP3600__UARTDBG__H__ */ | ||