imx233: generate register headers for stmp3600, stmp3700 and imx233

Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934

1 files changed, 484 insertions, 0 deletions

diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-power.h b/firmware/target/arm/imx233/regs/stmp3600/regs-power.h
new file mode 100644
index 0000000000..577a1c6415
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-power.h
@@ -0,0 +1,484 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__POWER__H__
+#define __HEADERGEN__STMP3600__POWER__H__
+
+#define REGS_POWER_BASE (0x80044000)
+
+#define REGS_POWER_VERSION "2.3.0"
+
+/**
+ * Register: HW_POWER_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_POWER_CTRL                               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x0))
+#define HW_POWER_CTRL_SET                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x4))
+#define HW_POWER_CTRL_CLR                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x8))
+#define HW_POWER_CTRL_TOG                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0xc))
+#define BP_POWER_CTRL_CLKGATE                       30
+#define BM_POWER_CTRL_CLKGATE                       0x40000000
+#define BF_POWER_CTRL_CLKGATE(v)                    (((v) << 30) & 0x40000000)
+#define BP_POWER_CTRL_BATT_BO_IRQ                   8
+#define BM_POWER_CTRL_BATT_BO_IRQ                   0x100
+#define BF_POWER_CTRL_BATT_BO_IRQ(v)                (((v) << 8) & 0x100)
+#define BP_POWER_CTRL_ENIRQBATT_BO                  7
+#define BM_POWER_CTRL_ENIRQBATT_BO                  0x80
+#define BF_POWER_CTRL_ENIRQBATT_BO(v)               (((v) << 7) & 0x80)
+#define BP_POWER_CTRL_VDDIO_BO_IRQ                  6
+#define BM_POWER_CTRL_VDDIO_BO_IRQ                  0x40
+#define BF_POWER_CTRL_VDDIO_BO_IRQ(v)               (((v) << 6) & 0x40)
+#define BP_POWER_CTRL_ENIRQVDDIO_BO                 5
+#define BM_POWER_CTRL_ENIRQVDDIO_BO                 0x20
+#define BF_POWER_CTRL_ENIRQVDDIO_BO(v)              (((v) << 5) & 0x20)
+#define BP_POWER_CTRL_VDDD_BO_IRQ                   4
+#define BM_POWER_CTRL_VDDD_BO_IRQ                   0x10
+#define BF_POWER_CTRL_VDDD_BO_IRQ(v)                (((v) << 4) & 0x10)
+#define BP_POWER_CTRL_ENIRQVDDD_BO                  3
+#define BM_POWER_CTRL_ENIRQVDDD_BO                  0x8
+#define BF_POWER_CTRL_ENIRQVDDD_BO(v)               (((v) << 3) & 0x8)
+#define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       2
+#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       0x4
+#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)    (((v) << 2) & 0x4)
+#define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            1
+#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            0x2
+#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)         (((v) << 1) & 0x2)
+#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0
+#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0x1
+#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_5VCTRL
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_POWER_5VCTRL                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x0))
+#define HW_POWER_5VCTRL_SET                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x4))
+#define HW_POWER_5VCTRL_CLR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x8))
+#define HW_POWER_5VCTRL_TOG                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0xc))
+#define BP_POWER_5VCTRL_PWDN_5VBRNOUT           21
+#define BM_POWER_5VCTRL_PWDN_5VBRNOUT           0x200000
+#define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v)        (((v) << 21) & 0x200000)
+#define BP_POWER_5VCTRL_PWDN_IOBRNOUT           20
+#define BM_POWER_5VCTRL_PWDN_IOBRNOUT           0x100000
+#define BF_POWER_5VCTRL_PWDN_IOBRNOUT(v)        (((v) << 20) & 0x100000)
+#define BP_POWER_5VCTRL_DISABLE_ILIMIT          19
+#define BM_POWER_5VCTRL_DISABLE_ILIMIT          0x80000
+#define BF_POWER_5VCTRL_DISABLE_ILIMIT(v)       (((v) << 19) & 0x80000)
+#define BP_POWER_5VCTRL_DCDC_XFER               18
+#define BM_POWER_5VCTRL_DCDC_XFER               0x40000
+#define BF_POWER_5VCTRL_DCDC_XFER(v)            (((v) << 18) & 0x40000)
+#define BP_POWER_5VCTRL_EN_BATT_PULLDN          17
+#define BM_POWER_5VCTRL_EN_BATT_PULLDN          0x20000
+#define BF_POWER_5VCTRL_EN_BATT_PULLDN(v)       (((v) << 17) & 0x20000)
+#define BP_POWER_5VCTRL_VBUSVALID_5VDETECT      16
+#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT      0x10000
+#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v)   (((v) << 16) & 0x10000)
+#define BP_POWER_5VCTRL_VBUSVALID_TRSH          8
+#define BM_POWER_5VCTRL_VBUSVALID_TRSH          0x300
+#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v)       (((v) << 8) & 0x300)
+#define BP_POWER_5VCTRL_USB_SUSPEND_I           7
+#define BM_POWER_5VCTRL_USB_SUSPEND_I           0x80
+#define BF_POWER_5VCTRL_USB_SUSPEND_I(v)        (((v) << 7) & 0x80)
+#define BP_POWER_5VCTRL_VBUSVALID_TO_B          6
+#define BM_POWER_5VCTRL_VBUSVALID_TO_B          0x40
+#define BF_POWER_5VCTRL_VBUSVALID_TO_B(v)       (((v) << 6) & 0x40)
+#define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO          5
+#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO          0x20
+#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)       (((v) << 5) & 0x20)
+#define BP_POWER_5VCTRL_OTG_PWRUP_CMPS          4
+#define BM_POWER_5VCTRL_OTG_PWRUP_CMPS          0x10
+#define BF_POWER_5VCTRL_OTG_PWRUP_CMPS(v)       (((v) << 4) & 0x10)
+#define BP_POWER_5VCTRL_EN_DCDC2                3
+#define BM_POWER_5VCTRL_EN_DCDC2                0x8
+#define BF_POWER_5VCTRL_EN_DCDC2(v)             (((v) << 3) & 0x8)
+#define BP_POWER_5VCTRL_PWD_VDDD_LINREG         2
+#define BM_POWER_5VCTRL_PWD_VDDD_LINREG         0x4
+#define BF_POWER_5VCTRL_PWD_VDDD_LINREG(v)      (((v) << 2) & 0x4)
+#define BP_POWER_5VCTRL_EN_DCDC1                1
+#define BM_POWER_5VCTRL_EN_DCDC1                0x2
+#define BF_POWER_5VCTRL_EN_DCDC1(v)             (((v) << 1) & 0x2)
+#define BP_POWER_5VCTRL_LINREG_OFFSET           0
+#define BM_POWER_5VCTRL_LINREG_OFFSET           0x1
+#define BF_POWER_5VCTRL_LINREG_OFFSET(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_MINPWR
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_POWER_MINPWR                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x0))
+#define HW_POWER_MINPWR_SET                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x4))
+#define HW_POWER_MINPWR_CLR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x8))
+#define HW_POWER_MINPWR_TOG                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0xc))
+#define BP_POWER_MINPWR_TEST_DISCHRG_VBUS       23
+#define BM_POWER_MINPWR_TEST_DISCHRG_VBUS       0x800000
+#define BF_POWER_MINPWR_TEST_DISCHRG_VBUS(v)    (((v) << 23) & 0x800000)
+#define BP_POWER_MINPWR_TEST_CHRG_VBUS          22
+#define BM_POWER_MINPWR_TEST_CHRG_VBUS          0x400000
+#define BF_POWER_MINPWR_TEST_CHRG_VBUS(v)       (((v) << 22) & 0x400000)
+#define BP_POWER_MINPWR_DC2_TST                 21
+#define BM_POWER_MINPWR_DC2_TST                 0x200000
+#define BF_POWER_MINPWR_DC2_TST(v)              (((v) << 21) & 0x200000)
+#define BP_POWER_MINPWR_DC1_TST                 20
+#define BM_POWER_MINPWR_DC1_TST                 0x100000
+#define BF_POWER_MINPWR_DC1_TST(v)              (((v) << 20) & 0x100000)
+#define BP_POWER_MINPWR_PERIPHERALSWOFF         19
+#define BM_POWER_MINPWR_PERIPHERALSWOFF         0x80000
+#define BF_POWER_MINPWR_PERIPHERALSWOFF(v)      (((v) << 19) & 0x80000)
+#define BP_POWER_MINPWR_TOGGLE_DIF              18
+#define BM_POWER_MINPWR_TOGGLE_DIF              0x40000
+#define BF_POWER_MINPWR_TOGGLE_DIF(v)           (((v) << 18) & 0x40000)
+#define BP_POWER_MINPWR_DISABLE_VDDIOSTEP       17
+#define BM_POWER_MINPWR_DISABLE_VDDIOSTEP       0x20000
+#define BF_POWER_MINPWR_DISABLE_VDDIOSTEP(v)    (((v) << 17) & 0x20000)
+#define BP_POWER_MINPWR_DISABLE_VDDSTEP         16
+#define BM_POWER_MINPWR_DISABLE_VDDSTEP         0x10000
+#define BF_POWER_MINPWR_DISABLE_VDDSTEP(v)      (((v) << 16) & 0x10000)
+#define BP_POWER_MINPWR_SEL_PLLDIV16CLK         9
+#define BM_POWER_MINPWR_SEL_PLLDIV16CLK         0x200
+#define BF_POWER_MINPWR_SEL_PLLDIV16CLK(v)      (((v) << 9) & 0x200)
+#define BP_POWER_MINPWR_PWD_VDDIOBO             8
+#define BM_POWER_MINPWR_PWD_VDDIOBO             0x100
+#define BF_POWER_MINPWR_PWD_VDDIOBO(v)          (((v) << 8) & 0x100)
+#define BP_POWER_MINPWR_LESSANA_I               7
+#define BM_POWER_MINPWR_LESSANA_I               0x80
+#define BF_POWER_MINPWR_LESSANA_I(v)            (((v) << 7) & 0x80)
+#define BP_POWER_MINPWR_DC1_HALFFETS            6
+#define BM_POWER_MINPWR_DC1_HALFFETS            0x40
+#define BF_POWER_MINPWR_DC1_HALFFETS(v)         (((v) << 6) & 0x40)
+#define BP_POWER_MINPWR_DC2_STOPCLK             5
+#define BM_POWER_MINPWR_DC2_STOPCLK             0x20
+#define BF_POWER_MINPWR_DC2_STOPCLK(v)          (((v) << 5) & 0x20)
+#define BP_POWER_MINPWR_DC1_STOPCLK             4
+#define BM_POWER_MINPWR_DC1_STOPCLK             0x10
+#define BF_POWER_MINPWR_DC1_STOPCLK(v)          (((v) << 4) & 0x10)
+#define BP_POWER_MINPWR_EN_DC2_PFM              3
+#define BM_POWER_MINPWR_EN_DC2_PFM              0x8
+#define BF_POWER_MINPWR_EN_DC2_PFM(v)           (((v) << 3) & 0x8)
+#define BP_POWER_MINPWR_EN_DC1_PFM              2
+#define BM_POWER_MINPWR_EN_DC1_PFM              0x4
+#define BF_POWER_MINPWR_EN_DC1_PFM(v)           (((v) << 2) & 0x4)
+#define BP_POWER_MINPWR_DC2_HALFCLK             1
+#define BM_POWER_MINPWR_DC2_HALFCLK             0x2
+#define BF_POWER_MINPWR_DC2_HALFCLK(v)          (((v) << 1) & 0x2)
+#define BP_POWER_MINPWR_DC1_HALFCLK             0
+#define BM_POWER_MINPWR_DC1_HALFCLK             0x1
+#define BF_POWER_MINPWR_DC1_HALFCLK(v)          (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_BATTCHRG
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_POWER_BATTCHRG                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x0))
+#define HW_POWER_BATTCHRG_SET               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x4))
+#define HW_POWER_BATTCHRG_CLR               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x8))
+#define HW_POWER_BATTCHRG_TOG               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0xc))
+#define BP_POWER_BATTCHRG_CHRG_STS_OFF      19
+#define BM_POWER_BATTCHRG_CHRG_STS_OFF      0x80000
+#define BF_POWER_BATTCHRG_CHRG_STS_OFF(v)   (((v) << 19) & 0x80000)
+#define BP_POWER_BATTCHRG_LIION_4P1         18
+#define BM_POWER_BATTCHRG_LIION_4P1         0x40000
+#define BF_POWER_BATTCHRG_LIION_4P1(v)      (((v) << 18) & 0x40000)
+#define BP_POWER_BATTCHRG_USE_EXTERN_R      17
+#define BM_POWER_BATTCHRG_USE_EXTERN_R      0x20000
+#define BF_POWER_BATTCHRG_USE_EXTERN_R(v)   (((v) << 17) & 0x20000)
+#define BP_POWER_BATTCHRG_PWD_BATTCHRG      16
+#define BM_POWER_BATTCHRG_PWD_BATTCHRG      0x10000
+#define BF_POWER_BATTCHRG_PWD_BATTCHRG(v)   (((v) << 16) & 0x10000)
+#define BP_POWER_BATTCHRG_STOP_ILIMIT       8
+#define BM_POWER_BATTCHRG_STOP_ILIMIT       0xf00
+#define BF_POWER_BATTCHRG_STOP_ILIMIT(v)    (((v) << 8) & 0xf00)
+#define BP_POWER_BATTCHRG_BATTCHRG_I        0
+#define BM_POWER_BATTCHRG_BATTCHRG_I        0x3f
+#define BF_POWER_BATTCHRG_BATTCHRG_I(v)     (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_POWER_VDDCTRL
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_POWER_VDDCTRL                (*(volatile unsigned long *)(REGS_POWER_BASE + 0x40))
+#define BP_POWER_VDDCTRL_VDDIO_BO       24
+#define BM_POWER_VDDCTRL_VDDIO_BO       0x1f000000
+#define BF_POWER_VDDCTRL_VDDIO_BO(v)    (((v) << 24) & 0x1f000000)
+#define BP_POWER_VDDCTRL_VDDIO_TRG      16
+#define BM_POWER_VDDCTRL_VDDIO_TRG      0x1f0000
+#define BF_POWER_VDDCTRL_VDDIO_TRG(v)   (((v) << 16) & 0x1f0000)
+#define BP_POWER_VDDCTRL_VDDD_BO        8
+#define BM_POWER_VDDCTRL_VDDD_BO        0x1f00
+#define BF_POWER_VDDCTRL_VDDD_BO(v)     (((v) << 8) & 0x1f00)
+#define BP_POWER_VDDCTRL_VDDD_TRG       0
+#define BM_POWER_VDDCTRL_VDDD_TRG       0x1f
+#define BF_POWER_VDDCTRL_VDDD_TRG(v)    (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_POWER_DC1MULTOUT
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_POWER_DC1MULTOUT                 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x50))
+#define BP_POWER_DC1MULTOUT_FUNCV           16
+#define BM_POWER_DC1MULTOUT_FUNCV           0x1ff0000
+#define BF_POWER_DC1MULTOUT_FUNCV(v)        (((v) << 16) & 0x1ff0000)
+#define BP_POWER_DC1MULTOUT_EN_BATADJ       8
+#define BM_POWER_DC1MULTOUT_EN_BATADJ       0x100
+#define BF_POWER_DC1MULTOUT_EN_BATADJ(v)    (((v) << 8) & 0x100)
+#define BP_POWER_DC1MULTOUT_ADJTN           0
+#define BM_POWER_DC1MULTOUT_ADJTN           0xf
+#define BF_POWER_DC1MULTOUT_ADJTN(v)        (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_POWER_DC1LIMITS
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_POWER_DC1LIMITS                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0x60))
+#define BP_POWER_DC1LIMITS_EN_PFETOFF           24
+#define BM_POWER_DC1LIMITS_EN_PFETOFF           0x1000000
+#define BF_POWER_DC1LIMITS_EN_PFETOFF(v)        (((v) << 24) & 0x1000000)
+#define BP_POWER_DC1LIMITS_POSLIMIT_BOOST       16
+#define BM_POWER_DC1LIMITS_POSLIMIT_BOOST       0x7f0000
+#define BF_POWER_DC1LIMITS_POSLIMIT_BOOST(v)    (((v) << 16) & 0x7f0000)
+#define BP_POWER_DC1LIMITS_POSLIMIT_BUCK        8
+#define BM_POWER_DC1LIMITS_POSLIMIT_BUCK        0x7f00
+#define BF_POWER_DC1LIMITS_POSLIMIT_BUCK(v)     (((v) << 8) & 0x7f00)
+#define BP_POWER_DC1LIMITS_NEGLIMIT             0
+#define BM_POWER_DC1LIMITS_NEGLIMIT             0x7f
+#define BF_POWER_DC1LIMITS_NEGLIMIT(v)          (((v) << 0) & 0x7f)
+
+/**
+ * Register: HW_POWER_DC2LIMITS
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_POWER_DC2LIMITS                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0x70))
+#define BP_POWER_DC2LIMITS_EN_BOOST             24
+#define BM_POWER_DC2LIMITS_EN_BOOST             0x1000000
+#define BF_POWER_DC2LIMITS_EN_BOOST(v)          (((v) << 24) & 0x1000000)
+#define BP_POWER_DC2LIMITS_POSLIMIT_BOOST       16
+#define BM_POWER_DC2LIMITS_POSLIMIT_BOOST       0x7f0000
+#define BF_POWER_DC2LIMITS_POSLIMIT_BOOST(v)    (((v) << 16) & 0x7f0000)
+#define BP_POWER_DC2LIMITS_POSLIMIT_BUCK        8
+#define BM_POWER_DC2LIMITS_POSLIMIT_BUCK        0x7f00
+#define BF_POWER_DC2LIMITS_POSLIMIT_BUCK(v)     (((v) << 8) & 0x7f00)
+#define BP_POWER_DC2LIMITS_NEGLIMIT             0
+#define BM_POWER_DC2LIMITS_NEGLIMIT             0x7f
+#define BF_POWER_DC2LIMITS_NEGLIMIT(v)          (((v) << 0) & 0x7f)
+
+/**
+ * Register: HW_POWER_LOOPCTRL
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_POWER_LOOPCTRL                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0x0))
+#define HW_POWER_LOOPCTRL_SET               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0x4))
+#define HW_POWER_LOOPCTRL_CLR               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0x8))
+#define HW_POWER_LOOPCTRL_TOG               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0xc))
+#define BP_POWER_LOOPCTRL_TRAN_NOHYST       30
+#define BM_POWER_LOOPCTRL_TRAN_NOHYST       0x40000000
+#define BF_POWER_LOOPCTRL_TRAN_NOHYST(v)    (((v) << 30) & 0x40000000)
+#define BP_POWER_LOOPCTRL_HYST_SIGN         29
+#define BM_POWER_LOOPCTRL_HYST_SIGN         0x20000000
+#define BF_POWER_LOOPCTRL_HYST_SIGN(v)      (((v) << 29) & 0x20000000)
+#define BP_POWER_LOOPCTRL_EN_CMP_HYST       28
+#define BM_POWER_LOOPCTRL_EN_CMP_HYST       0x10000000
+#define BF_POWER_LOOPCTRL_EN_CMP_HYST(v)    (((v) << 28) & 0x10000000)
+#define BP_POWER_LOOPCTRL_EN_DC2_RCSCALE    27
+#define BM_POWER_LOOPCTRL_EN_DC2_RCSCALE    0x8000000
+#define BF_POWER_LOOPCTRL_EN_DC2_RCSCALE(v) (((v) << 27) & 0x8000000)
+#define BP_POWER_LOOPCTRL_EN_DC1_RCSCALE    26
+#define BM_POWER_LOOPCTRL_EN_DC1_RCSCALE    0x4000000
+#define BF_POWER_LOOPCTRL_EN_DC1_RCSCALE(v) (((v) << 26) & 0x4000000)
+#define BP_POWER_LOOPCTRL_RC_SIGN           25
+#define BM_POWER_LOOPCTRL_RC_SIGN           0x2000000
+#define BF_POWER_LOOPCTRL_RC_SIGN(v)        (((v) << 25) & 0x2000000)
+#define BP_POWER_LOOPCTRL_EN_RCSCALE        24
+#define BM_POWER_LOOPCTRL_EN_RCSCALE        0x1000000
+#define BF_POWER_LOOPCTRL_EN_RCSCALE(v)     (((v) << 24) & 0x1000000)
+#define BP_POWER_LOOPCTRL_DC2_FF            20
+#define BM_POWER_LOOPCTRL_DC2_FF            0x700000
+#define BF_POWER_LOOPCTRL_DC2_FF(v)         (((v) << 20) & 0x700000)
+#define BP_POWER_LOOPCTRL_DC2_R             16
+#define BM_POWER_LOOPCTRL_DC2_R             0xf0000
+#define BF_POWER_LOOPCTRL_DC2_R(v)          (((v) << 16) & 0xf0000)
+#define BP_POWER_LOOPCTRL_DC2_C             12
+#define BM_POWER_LOOPCTRL_DC2_C             0x3000
+#define BF_POWER_LOOPCTRL_DC2_C(v)          (((v) << 12) & 0x3000)
+#define BP_POWER_LOOPCTRL_DC1_FF            8
+#define BM_POWER_LOOPCTRL_DC1_FF            0x700
+#define BF_POWER_LOOPCTRL_DC1_FF(v)         (((v) << 8) & 0x700)
+#define BP_POWER_LOOPCTRL_DC1_R             4
+#define BM_POWER_LOOPCTRL_DC1_R             0xf0
+#define BF_POWER_LOOPCTRL_DC1_R(v)          (((v) << 4) & 0xf0)
+#define BP_POWER_LOOPCTRL_DC1_C             0
+#define BM_POWER_LOOPCTRL_DC1_C             0x3
+#define BF_POWER_LOOPCTRL_DC1_C(v)          (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_POWER_STS
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_POWER_STS                        (*(volatile unsigned long *)(REGS_POWER_BASE + 0x90))
+#define BP_POWER_STS_BATT_CHRG_PRESENT      31
+#define BM_POWER_STS_BATT_CHRG_PRESENT      0x80000000
+#define BF_POWER_STS_BATT_CHRG_PRESENT(v)   (((v) << 31) & 0x80000000)
+#define BP_POWER_STS_MODE                   20
+#define BM_POWER_STS_MODE                   0x300000
+#define BF_POWER_STS_MODE(v)                (((v) << 20) & 0x300000)
+#define BP_POWER_STS_BATT_BO                16
+#define BM_POWER_STS_BATT_BO                0x10000
+#define BF_POWER_STS_BATT_BO(v)             (((v) << 16) & 0x10000)
+#define BP_POWER_STS_CHRGSTS                14
+#define BM_POWER_STS_CHRGSTS                0x4000
+#define BF_POWER_STS_CHRGSTS(v)             (((v) << 14) & 0x4000)
+#define BP_POWER_STS_DC2_OK                 13
+#define BM_POWER_STS_DC2_OK                 0x2000
+#define BF_POWER_STS_DC2_OK(v)              (((v) << 13) & 0x2000)
+#define BP_POWER_STS_DC1_OK                 12
+#define BM_POWER_STS_DC1_OK                 0x1000
+#define BF_POWER_STS_DC1_OK(v)              (((v) << 12) & 0x1000)
+#define BP_POWER_STS_VDDIO_BO               9
+#define BM_POWER_STS_VDDIO_BO               0x200
+#define BF_POWER_STS_VDDIO_BO(v)            (((v) << 9) & 0x200)
+#define BP_POWER_STS_VDDD_BO                8
+#define BM_POWER_STS_VDDD_BO                0x100
+#define BF_POWER_STS_VDDD_BO(v)             (((v) << 8) & 0x100)
+#define BP_POWER_STS_VDD5V_GT_VDDIO         4
+#define BM_POWER_STS_VDD5V_GT_VDDIO         0x10
+#define BF_POWER_STS_VDD5V_GT_VDDIO(v)      (((v) << 4) & 0x10)
+#define BP_POWER_STS_AVALID                 3
+#define BM_POWER_STS_AVALID                 0x8
+#define BF_POWER_STS_AVALID(v)              (((v) << 3) & 0x8)
+#define BP_POWER_STS_BVALID                 2
+#define BM_POWER_STS_BVALID                 0x4
+#define BF_POWER_STS_BVALID(v)              (((v) << 2) & 0x4)
+#define BP_POWER_STS_VBUSVALID              1
+#define BM_POWER_STS_VBUSVALID              0x2
+#define BF_POWER_STS_VBUSVALID(v)           (((v) << 1) & 0x2)
+#define BP_POWER_STS_SESSEND                0
+#define BM_POWER_STS_SESSEND                0x1
+#define BF_POWER_STS_SESSEND(v)             (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_SPEEDTEMP
+ * Address: 0xa0
+ * SCT: yes
+*/
+#define HW_POWER_SPEEDTEMP                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x0))
+#define HW_POWER_SPEEDTEMP_SET              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x4))
+#define HW_POWER_SPEEDTEMP_CLR              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x8))
+#define HW_POWER_SPEEDTEMP_TOG              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0xc))
+#define BP_POWER_SPEEDTEMP_SPEED_STS1       24
+#define BM_POWER_SPEEDTEMP_SPEED_STS1       0xff000000
+#define BF_POWER_SPEEDTEMP_SPEED_STS1(v)    (((v) << 24) & 0xff000000)
+#define BP_POWER_SPEEDTEMP_SPEED_STS2       16
+#define BM_POWER_SPEEDTEMP_SPEED_STS2       0xff0000
+#define BF_POWER_SPEEDTEMP_SPEED_STS2(v)    (((v) << 16) & 0xff0000)
+#define BP_POWER_SPEEDTEMP_TEMP_STS         8
+#define BM_POWER_SPEEDTEMP_TEMP_STS         0xf00
+#define BF_POWER_SPEEDTEMP_TEMP_STS(v)      (((v) << 8) & 0xf00)
+#define BP_POWER_SPEEDTEMP_SPEED_CTRL       4
+#define BM_POWER_SPEEDTEMP_SPEED_CTRL       0x30
+#define BF_POWER_SPEEDTEMP_SPEED_CTRL(v)    (((v) << 4) & 0x30)
+#define BP_POWER_SPEEDTEMP_TEMP_CTRL        0
+#define BM_POWER_SPEEDTEMP_TEMP_CTRL        0xf
+#define BF_POWER_SPEEDTEMP_TEMP_CTRL(v)     (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_POWER_BATTMONITOR
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_POWER_BATTMONITOR                    (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0))
+#define BP_POWER_BATTMONITOR_BATT_VAL           16
+#define BM_POWER_BATTMONITOR_BATT_VAL           0x3ff0000
+#define BF_POWER_BATTMONITOR_BATT_VAL(v)        (((v) << 16) & 0x3ff0000)
+#define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT    9
+#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT    0x200
+#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v) (((v) << 9) & 0x200)
+#define BP_POWER_BATTMONITOR_BRWNOUT_PWD        8
+#define BM_POWER_BATTMONITOR_BRWNOUT_PWD        0x100
+#define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v)     (((v) << 8) & 0x100)
+#define BP_POWER_BATTMONITOR_BRWNOUT_LVL        0
+#define BM_POWER_BATTMONITOR_BRWNOUT_LVL        0xf
+#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v)     (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_POWER_RESET
+ * Address: 0xc0
+ * SCT: yes
+*/
+#define HW_POWER_RESET              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x0))
+#define HW_POWER_RESET_SET          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x4))
+#define HW_POWER_RESET_CLR          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x8))
+#define HW_POWER_RESET_TOG          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0xc))
+#define BP_POWER_RESET_UNLOCK       16
+#define BM_POWER_RESET_UNLOCK       0xffff0000
+#define BV_POWER_RESET_UNLOCK__KEY  0x3e77
+#define BF_POWER_RESET_UNLOCK(v)    (((v) << 16) & 0xffff0000)
+#define BF_POWER_RESET_UNLOCK_V(v)  ((BV_POWER_RESET_UNLOCK__##v << 16) & 0xffff0000)
+#define BP_POWER_RESET_PWD_OFF      4
+#define BM_POWER_RESET_PWD_OFF      0x10
+#define BF_POWER_RESET_PWD_OFF(v)   (((v) << 4) & 0x10)
+#define BP_POWER_RESET_POR          3
+#define BM_POWER_RESET_POR          0x8
+#define BF_POWER_RESET_POR(v)       (((v) << 3) & 0x8)
+#define BP_POWER_RESET_PWD          2
+#define BM_POWER_RESET_PWD          0x4
+#define BF_POWER_RESET_PWD(v)       (((v) << 2) & 0x4)
+#define BP_POWER_RESET_RST_DIG      1
+#define BM_POWER_RESET_RST_DIG      0x2
+#define BF_POWER_RESET_RST_DIG(v)   (((v) << 1) & 0x2)
+#define BP_POWER_RESET_RST_ALL      0
+#define BM_POWER_RESET_RST_ALL      0x1
+#define BF_POWER_RESET_RST_ALL(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_DEBUG
+ * Address: 0xd0
+ * SCT: yes
+*/
+#define HW_POWER_DEBUG                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x0))
+#define HW_POWER_DEBUG_SET                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x4))
+#define HW_POWER_DEBUG_CLR                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x8))
+#define HW_POWER_DEBUG_TOG                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0xc))
+#define BP_POWER_DEBUG_ENCTRLVBUS           4
+#define BM_POWER_DEBUG_ENCTRLVBUS           0x10
+#define BF_POWER_DEBUG_ENCTRLVBUS(v)        (((v) << 4) & 0x10)
+#define BP_POWER_DEBUG_VBUSVALIDPIOLOCK     3
+#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK     0x8
+#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v)  (((v) << 3) & 0x8)
+#define BP_POWER_DEBUG_AVALIDPIOLOCK        2
+#define BM_POWER_DEBUG_AVALIDPIOLOCK        0x4
+#define BF_POWER_DEBUG_AVALIDPIOLOCK(v)     (((v) << 2) & 0x4)
+#define BP_POWER_DEBUG_BVALIDPIOLOCK        1
+#define BM_POWER_DEBUG_BVALIDPIOLOCK        0x2
+#define BF_POWER_DEBUG_BVALIDPIOLOCK(v)     (((v) << 1) & 0x2)
+#define BP_POWER_DEBUG_SESSENDPIOLOCK       0
+#define BM_POWER_DEBUG_SESSENDPIOLOCK       0x1
+#define BF_POWER_DEBUG_SESSENDPIOLOCK(v)    (((v) << 0) & 0x1)
+
+#endif /* __HEADERGEN__STMP3600__POWER__H__ */