imx233: generate register headers for stmp3600, stmp3700 and imx233

Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934

1 files changed, 105 insertions, 0 deletions

diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h b/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h
new file mode 100644
index 0000000000..3ba723eab3
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h
@@ -0,0 +1,105 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__MEMCPY__H__
+#define __HEADERGEN__STMP3600__MEMCPY__H__
+
+#define REGS_MEMCPY_BASE (0x80014000)
+
+#define REGS_MEMCPY_VERSION "2.3.0"
+
+/**
+ * Register: HW_MEMCPY_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_MEMCPY_CTRL                      (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x0))
+#define HW_MEMCPY_CTRL_SET                  (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x4))
+#define HW_MEMCPY_CTRL_CLR                  (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x8))
+#define HW_MEMCPY_CTRL_TOG                  (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0xc))
+#define BP_MEMCPY_CTRL_SFTRST               31
+#define BM_MEMCPY_CTRL_SFTRST               0x80000000
+#define BV_MEMCPY_CTRL_SFTRST__RUN          0x0
+#define BV_MEMCPY_CTRL_SFTRST__RESET        0x1
+#define BF_MEMCPY_CTRL_SFTRST(v)            (((v) << 31) & 0x80000000)
+#define BF_MEMCPY_CTRL_SFTRST_V(v)          ((BV_MEMCPY_CTRL_SFTRST__##v << 31) & 0x80000000)
+#define BP_MEMCPY_CTRL_CLKGATE              30
+#define BM_MEMCPY_CTRL_CLKGATE              0x40000000
+#define BV_MEMCPY_CTRL_CLKGATE__RUN         0x0
+#define BV_MEMCPY_CTRL_CLKGATE__NO_CLKS     0x1
+#define BF_MEMCPY_CTRL_CLKGATE(v)           (((v) << 30) & 0x40000000)
+#define BF_MEMCPY_CTRL_CLKGATE_V(v)         ((BV_MEMCPY_CTRL_CLKGATE__##v << 30) & 0x40000000)
+#define BP_MEMCPY_CTRL_PRESENT              29
+#define BM_MEMCPY_CTRL_PRESENT              0x20000000
+#define BV_MEMCPY_CTRL_PRESENT__UNAVAILABLE 0x0
+#define BV_MEMCPY_CTRL_PRESENT__AVAILABLE   0x1
+#define BF_MEMCPY_CTRL_PRESENT(v)           (((v) << 29) & 0x20000000)
+#define BF_MEMCPY_CTRL_PRESENT_V(v)         ((BV_MEMCPY_CTRL_PRESENT__##v << 29) & 0x20000000)
+#define BP_MEMCPY_CTRL_BURST                16
+#define BM_MEMCPY_CTRL_BURST                0x10000
+#define BF_MEMCPY_CTRL_BURST(v)             (((v) << 16) & 0x10000)
+#define BP_MEMCPY_CTRL_XFER_SIZE            0
+#define BM_MEMCPY_CTRL_XFER_SIZE            0xffff
+#define BF_MEMCPY_CTRL_XFER_SIZE(v)         (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_MEMCPY_DATA
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_MEMCPY_DATA          (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x0))
+#define HW_MEMCPY_DATA_SET      (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x4))
+#define HW_MEMCPY_DATA_CLR      (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x8))
+#define HW_MEMCPY_DATA_TOG      (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0xc))
+#define BP_MEMCPY_DATA_DATA     0
+#define BM_MEMCPY_DATA_DATA     0xffffffff
+#define BF_MEMCPY_DATA_DATA(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_MEMCPY_DEBUG
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_MEMCPY_DEBUG                 (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x20))
+#define BP_MEMCPY_DEBUG_DST_END_CMD     30
+#define BM_MEMCPY_DEBUG_DST_END_CMD     0x40000000
+#define BF_MEMCPY_DEBUG_DST_END_CMD(v)  (((v) << 30) & 0x40000000)
+#define BP_MEMCPY_DEBUG_DST_KICK        29
+#define BM_MEMCPY_DEBUG_DST_KICK        0x20000000
+#define BF_MEMCPY_DEBUG_DST_KICK(v)     (((v) << 29) & 0x20000000)
+#define BP_MEMCPY_DEBUG_DST_DMA_REQ     28
+#define BM_MEMCPY_DEBUG_DST_DMA_REQ     0x10000000
+#define BF_MEMCPY_DEBUG_DST_DMA_REQ(v)  (((v) << 28) & 0x10000000)
+#define BP_MEMCPY_DEBUG_SRC_KICK        25
+#define BM_MEMCPY_DEBUG_SRC_KICK        0x2000000
+#define BF_MEMCPY_DEBUG_SRC_KICK(v)     (((v) << 25) & 0x2000000)
+#define BP_MEMCPY_DEBUG_SRC_DMA_REQ     24
+#define BM_MEMCPY_DEBUG_SRC_DMA_REQ     0x1000000
+#define BF_MEMCPY_DEBUG_SRC_DMA_REQ(v)  (((v) << 24) & 0x1000000)
+#define BP_MEMCPY_DEBUG_WRITE_STATE     2
+#define BM_MEMCPY_DEBUG_WRITE_STATE     0xc
+#define BF_MEMCPY_DEBUG_WRITE_STATE(v)  (((v) << 2) & 0xc)
+#define BP_MEMCPY_DEBUG_READ_STATE      0
+#define BM_MEMCPY_DEBUG_READ_STATE      0x3
+#define BF_MEMCPY_DEBUG_READ_STATE(v)   (((v) << 0) & 0x3)
+
+#endif /* __HEADERGEN__STMP3600__MEMCPY__H__ */