diff options
author | Rafaël Carré <rafael.carre@gmail.com> | 2008-12-04 20:04:31 +0000 |
---|---|---|
committer | Rafaël Carré <rafael.carre@gmail.com> | 2008-12-04 20:04:31 +0000 |
commit | 45711ac2869f955c40be96d8dcbc7201c718dba4 (patch) | |
tree | ef022bec4b6e8bcc11005de34d300e073c60770d /firmware/target/arm/as3525/sansa-fuze | |
parent | 7ea9e31658da4fce9c4a3e30838b82fda8eda287 (diff) | |
download | rockbox-45711ac2869f955c40be96d8dcbc7201c718dba4.tar.gz rockbox-45711ac2869f955c40be96d8dcbc7201c718dba4.zip |
Sansa AMS: centralize clock settings in clock-target.h
Reorder system_init() to initialize peripherals not only in bootloader
Use a 65MHz PCLK (and memclk) which will be needed for realtime decoding
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19330 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/sansa-fuze')
-rw-r--r-- | firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c b/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c index cc61a82c6f..76b74b7c3e 100644 --- a/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c +++ b/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c | |||
@@ -24,6 +24,7 @@ | |||
24 | 24 | ||
25 | #include "cpu.h" | 25 | #include "cpu.h" |
26 | #include "lcd.h" | 26 | #include "lcd.h" |
27 | #include "clock-target.h" | ||
27 | 28 | ||
28 | /* The controller is unknown, but some registers appear to be the same as the | 29 | /* The controller is unknown, but some registers appear to be the same as the |
29 | HD66789R */ | 30 | HD66789R */ |
@@ -49,7 +50,8 @@ static void lcd_delay(int x) | |||
49 | 50 | ||
50 | static void as3525_dbop_init(void) | 51 | static void as3525_dbop_init(void) |
51 | { | 52 | { |
52 | CGU_DBOP = (1<<3); | 53 | CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); |
54 | |||
53 | DBOP_TIMPOL_01 = 0xe167e167; | 55 | DBOP_TIMPOL_01 = 0xe167e167; |
54 | DBOP_TIMPOL_23 = 0xe167006e; | 56 | DBOP_TIMPOL_23 = 0xe167006e; |
55 | DBOP_CTRL = 0x41008; | 57 | DBOP_CTRL = 0x41008; |